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IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 1, JANUARY 2008
Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire Maesoon Im, Jin-Woo Han, Hyunjin Lee, Lee-Eun Yu, Sungho Kim, Chang-Hoon Kim, Sang Cheol Jeon, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Yun Chang Park, Hee Mok Lee, and Yang-Kyu Choi
Abstract—An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire. Index Terms—CMOS, multiple gate, nanoscale, nanowire, thinfilm transistor (TFT), vertical integration.
I. I NTRODUCTION
W
ITH EMERGING various consumer electronics which require huge data storage, higher memory device density is greatly demanded. In addition to shrinkage of a device itself, several approaches have been reported to increase the device density. Multiple active layers that comprised of iteratively stacked polysilicon (poly-Si) can significantly enhance the device packing density, which results in a reduction of interconnection delay, power consumption, and cost [1], [2] as well as the capacitive and resistive loading effects in chip- or package-level stacking [3]. In practical applications, Samsung has used the stacked single crystal thin-film transistors (TFTs) as the peripheral CMOS transistors as well as the cell transistors to save area in SRAM products [4] and NAND flash memories [3]. When the poly-Si TFT size is small enough to be enclosed in a single grain, vertical integration using multiple poly-Si active layers becomes more attractive, particularly in the terabit memory era. In general, TFT performance has been improved by increasing the grain size of the poly-Si thin film, as this leads to a reduced defect density [5]. Various methods to control the size and direction of the poly-Si grain have been reported, including excimer laser annealing (ELA) [5]–[7], metal-induced lateral
Manuscript received October 10, 2007. This work was supported in part by the National Research Program for 0.1-Terabit Nonvolatile Memory Development sponsored by the Ministry of Commerce, Industry, and Energy (MOCIE) and the Ministry of Science and Technology (MOST) through the CavendishKAIST Corporation Research Program. The review of this letter was arranged by Editor J. Sin. M. Im, J.-W. Han, H. Lee, L.-E. Yu, S. Kim, C.-H. Kim, and Y.-K. Choi are with the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail:
[email protected]). S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, and H. M. Lee are with the Korea National NanoFab Center, Daejeon 305-806, Korea. Digital Object Identifier 10.1109/LED.2007.911982
Fig. 1. (a) Schematic of the poly-Si nanowire channel TFT. (b) Crosssectional view in the AA direction. The initial buried-oxide thickness is 145 nm, and a thermal oxide layer of 1.7 nm is used as a gate dielectric.
crystallization [8], and ELA with different channel structures [9]. However, poly-Si TFTs with smaller sizes have also been fabricated in efforts to reduce the effects of grain boundaries [10]–[12]. In these studies, the TFT characteristics were improved remarkably by decreasing the channel dimensions to be comparable to, or even smaller than, the grain size. Additionally, specific gate and channel structures have been studied to enhance performance, including a self-aligned double gate [13], gate-all-around TFTs [14], finlike channels [15], and nanowire channels [16]. In comparison with the traditional planar TFT, these approaches show higher performances due to improved channel controllability through the multiple-gate structure, although they have process complexity. In this letter, novel poly-Si TFTs with poly-Si nanowire channels have been successfully fabricated and characterized. The gate length (LG ) ranges from 20 to 100 nm, and the width of the silicon nanowire (WSN ) is 14 nm, which are the smallest TFT device dimensions reported to date. Such small device dimensions can reduce the effects of poly-Si grain boundary defects without additional crystallization processes. In order to suppress the short-channel effects, a 3-D poly-Si nanowire channel is used; it is surrounded by a gate dielectric and an omega-shaped poly-Si gate. II. N ANOWIRE C HANNEL TFT F ABRICATION Schematic diagrams of the poly-Si nanowire channel and its gate are shown in Fig. 1(a) and (b). The process flow of the nanowire channel TFTs is similar to that of a sub-5-nm all-around gate FinFET [17]. An 8-in (100) bulk silicon wafer
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was used as a starting material. After a 145-nm-thick silicon dioxide (SiO2 ) was thermally grown as a buried oxide, a 20-nm-thick undoped poly-Si film was deposited using lowpressure chemical vapor deposition. After an n-well mask process, phosphorous (4 × 1012 cm−2 , 8 keV) was implanted. Boron difluoride (BF2 , 4 × 1012 cm−2 , 8 keV) implantation was then performed after a p-well mask process to construct twin-well formations for CMOS. To delineate the ultrafine sizes and maximize throughput, a dual-photoresist process (e-beam lithography for nanometer-scaled nanowires and gates, and KrF optical lithography for noncritical interconnection and probing pad areas) was developed. After the silicon nanowire etching, a sacrificial oxidation (3 nm in wet ambient) was performed to taper the rectangular nanowire to make rounded corner shapes. While etching the sacrificial oxide, the buried oxide was overetched, and an undercut beneath the poly-Si nanowire channel was formed, as shown in Fig. 2(b); the dimensions of the poly-Si nanowire were reduced from 20 to 14 nm in width and from 20 to 17 nm in height. The omega-shaped gate structure originates from the undercut profile of the buried oxide. A gate dielectric of 1.7-nm SiO2 was thermally grown. A 30-nmthick undoped poly-Si layer was deposited for the gate material. Next, it was doped by arsenic (4 × 1014 cm−2 , 2 keV) and BF2 (4 × 1014 cm−2 , 2 keV) implantations for NMOS and PMOS TFTs, respectively. The gate poly-Si was patterned using the aforementioned dual-photoresist process with anisotropic etching. Fig. 2(a) shows a top-view scanning-electron-microscopy (SEM) image of a poly-Si nanowire crossed with a patterned poly-Si gate (LG = 30 nm; WSN = 14 nm). Fig. 2(b) shows a transmission-electron-microscopy (TEM) image taken in the AA direction shown in Fig. 1(a). The gate sidewall spacers were conventionally formed with a 60-nm-thick tetraethylorthosilicate oxide. Arsenic (5 × 1015 cm−2 , 2 keV) and BF2 (5 × 1015 cm−2 , 2 keV) were subsequently implanted for the source and drain of NMOS and PMOS, respectively. Finally, a spike annealing for dopant activation was performed at 1000 ◦ C for 3 s, and a forming gas annealing was performed at 450 ◦ C for 30 min. The high temperature of the dopant activation can be lowered by using plasma immersion ion implantation [18]. III. D EVICE C HARACTERISTICS AND D ISCUSSION The fabricated multiple-gate CMOS TFTs with poly-Si nanowires have an LG of 20–200 nm and a WSN of 14 nm. Fig. 3(a) shows the transfer curves of the CMOS TFTs with an LG of 100 nm and a WSN of 14 nm. As shown in Fig. 3(d), the devices have subthreshold slopes of 79 and 87 mV/dec for NMOS and PMOS, respectively. A comparison of device characteristics with the reported TFTs is summarized in Table I. It is worthwhile to note very steep subthreshold slopes compared with the state-of-the-art TFTs. The drain-induced barrier lowering (DIBL) was measured to be 78 mV/V for NMOS and 53 mV/V for PMOS. As predicted for a 100-nm dimension, the multiple-gate nanowire FET effectively suppresses the OFFstate leakage current by increased electrostatic gate controllability over the channel potential. The ratios of ION /IOFF are approximately 1.8 × 104 for NMOS and 5.1 × 104 for PMOS. The OFF-state leakage current was read at |VDS | = 1.0 V. From
Fig. 2. (a) SEM image of a 30-nm-long gate with a 14-nm-wide poly-Si nanowire before the gate spacer formation. (b) Cross-sectional TEM image of a 14-nm-wide and 17-nm-thick poly-Si nanowire and a 30-nm-thick poly-Si gate. Inset: TEM image of low magnification.
various TEM images of the fabricated devices, the average size of the poly-Si grains is 41.8 nm, and their standard deviation is 6.6 nm. The output characteristics are shown in Fig. 3(b). Generally, in planar devices, the NMOS exhibits higher drain currents than the PMOS due to the electron mobility which is higher than the mobility of the hole. Fig. 3(b), however, shows a comparable or smaller ON-state current in the NMOS than in the PMOS. Low series resistances in the source/drain (S/D) result in a higher ON-state drain current in the PMOS than in the NMOS because the boron in the p+ S/D diffuses faster
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Fig. 3. (a) Transfer characteristics (ID –VG curves) of the CMOS poly-Si nanowire channel TFTs, where LG = 100 nm, WSN = 14 nm, and TOX = 1.7 nm. (b) Drain currents of the devices in (a) as a function of drain voltage for various gate overdrive voltages (VG –VT ). (c) Transfer characteristics (ID –VG curves) of the CMOS poly-Si nanowire channel TFTs, where LG = 20 nm, WSN = 14 nm, and TOX = 1.7 nm. (d) Subthreshold slope versus gate length of the poly-Si nanowire channel TFTs, where WSN = 14 nm, and TOX = 1.7 nm. TABLE I COMPARISON OF DEVICE CHARACTERISTICS WITH THE REPORTED TFTS. OUR DEVICE SHOWS A VERY STEEP SUBTHRESHOLD SLOPE COMPARED WITH THE STATE-OF-THE-ART TFTS
than the arsenic in the n+ S/D. In addition, more dopants are activated in the S/D under the same spike-annealing conditions. In addition to the series-resistance effect, the effect of
crystal orientation can be another factor contributing to the ON -state drain-current difference between the PMOS and the NMOS [19].
IM et al.: MULTIPLE-GATE CMOS THIN-FILM TRANSISTOR WITH POLYSILICON NANOWIRE
The transfer curves of extremely small TFTs are shown in Fig. 3(c). The minimum LG of the CMOS is 20 nm, and WSN is 14 nm. Resulting from the shorter gate lengths, the DIBL is increased to 605 mV/V for NMOS and 503 mV/V for PMOS. The subthreshold slope of NMOS is increased to 166 mV/V and that of PMOS is increased to 207 mV/dec. These show the feasibility of the multiple-gate technology with a poly-Si nanowire TFT and indicate that it can contribute to open the terabit memory era further. Asymmetric I–V characteristics and relatively high OFF-state NMOS current in a regime of 20-nm gate length can be improved by further process optimization. IV. C ONCLUSION Ultimately scaled CMOS TFTs were demonstrated using a multiple-gate structure and a poly-Si nanowire. The fabricated TFTs showed good switching characteristics without extra crystallization processes. The high-performance characteristics originated from an omega-shaped gate that is used to electrostatically control the channel potential and nanometerscale features. Given these high-performance characteristics, it is expected that this technology can be used to stack multiple active layers vertically in order to increase the device packing density and reduce the interconnection delay and the power consumption.
[5] [6]
[7] [8] [9]
[10]
[11] [12] [13] [14]
ACKNOWLEDGMENT The authors would like to thank Dr. H. C. Lee from the Korea National NanoFab Center for the managerial support.
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