Multiple SiGe well - IEEE Xplore

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Ph: +33 4 76 92 68 29, Fax: +33 4 76 92 68 14, e-mail: jerome.alieu@st.com. ' INSA Lyon, UMR CNRS 51 I , 20 av. A. Einstein, 69621 Villeurbanne France.
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Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances J. Alieu', T. Skotnicki', E. Josse',J.-L. Regolini' and G. Bremond2

' Centre Commun CNETIST Microelectronics, 850 rue J. Monnet, BP 16, 38926 Crolles Cedex France Ph: +33 4 76 92 68 29, Fax: +33 4 76 92 68 14, e-mail: [email protected]

' INSA Lyon, UMR CNRS 51 I , 20 av. A. Einstein, 69621 Villeurbanne France Abstract: We present, for the first time, multiple SiGe quantum wells as a new channel architecture allowing increased performances for both NMOS and PMOS short channel transistors. We show that interleaved Si layers are strained as well as SiGe layers which strongly increases both electron and hole mobilities. Comparing multiple well and pure Si epitaxial channel devices, we demonstrate the ability of our structure to better control SCE for both NMOS and PMOS.

gain is maintained even if the current is normalized to constant (Vg-Vth). In addition, the Id gain (with respect to the EpiSi control devices), is correlated with the Ge fraction in the upper-most well, where the inversion occurs. This gain when the upper well has reaches approximately 45% (S%) 30% of Ge and is negligible when Ge fraction is 10 or 0%. The role of the deeper wells is thus to strengthen the structure and to prevent relaxation, rather than improving the mobility.

Introduction: In order to boost PMOS performances, by hole mobility improvement, it has been proposed to use single strained SiGe epitaxial layer [ l ] which creates a valence band offset. This structure, however, degrades the NMOS operation, in contradiction with common expectations, as it has been shown in [2], due to local layer relaxation by Arsenic LDD implant. In order to conserve the hole mobility gain and to reduce the relaxation probability, multiple SiGe layer architecture has been proposed [3]. Similar structure was previously studied for optical applications [4] but never for CMOS short channel devices. We present, for the first time, the successful integration of multiple SiGe well structure for both PMOS and NMOS short transistors.

NMOS performances: Fig. 6 also shows, for the first time, the gain obtained at the NMOS side using multiple SiGe wells structure. Transconductance measurements at low Vd, Fig. 7, demonstrate that the current gain is due to higher electron mobility since oxide thickness and average dopant concentration are identical in both cases as can be inferred from Fig. 8. This improvement is attributed to the electron conduction within strained Si layers. We believe that Coulomb, phonon and surface roughness scatterings are identical comparing with pure Si epitaxy and that electron mobility gain results from lower electron effective mass due to strain. We believe that with the single SiGe layer the SiGe is strained and adjusts its lattice to that of Si. Therefore the Si cap layer is not strained. In the case of multiple wells, the strain is shared between the SiGe and Si interleaved layers and thus the Si layer as well as the underlaying SiGe layer are both strained. The best structure, with regard to the drain current gain, is 30/30/30, but this structure leads to a bad short channel operation. The best I o d o f f trade-off is obtained with the 10/20/30 structure. Finally, the drain current in short channel devices, measured at Vg = Vd = ISV, is increased from 616pA/pm to 653pMpm when using 10/20/30 multiple SiGe wells with respect to the EpiSi channel, whereas the Vth and Ioff are unchanged, Fig. 9 and Tab. 1. Fig. 10 shows output characteristics for 10/20/30 and EpiSi structures. Fig. 1 1 and Tab. 1 demonstrate slightly improved SCE obtained with multiple SiGe wells structure in comparison with the EpiSi one. Fig. 12 shows a quite good operation for a very short, L = 0.1 pm, NMOS transistor with multiple SiGe well structure. Note that Tox=3 nm is inadapted for such short devices.

Process results: Fig. 1 summaries the process flow and the targeted structure. Fig. 2 shows the result of a SIMS analysis of a preliminary test structure with a double SiGe well targeting a 4 nm thick SiGe layers (30% of Ge) interleaved by 4 nm thick Si layers. In our transistor experimental batch, in order to find the best architecture, various Ge fractions (A, B or C equal to IO%, 20% or 30% respectively) are used. The corresponding name is A/B/C where A is the Ge fraction of the deepest well and C the Ge fraction of the upper-most one. The Si buffer and the Si cap layers are 20 and 8 nm thick, respectively. The total undoped epitaxial stack is 48 nm thick. As a reference we have fabricated transistors with a pure Si epitaxial layer, 48 nm thick referred to as EpiSi.

PMOS Performances: As demonstrated in Fig. 3, transconductance is improved due to higher hole mobility when using multiple SiGe layers. This improvement is due to the hole confinement, leading to a lower hole scattering on surface roughness and on ionized impurities, and to a lower hole effective mass linked to the strain. Even higher hole mobility gain can be achieved using a single SiGe well, but as we have demonstrated in [3] this single SiGe layer relaxes after the LDD implantation whereas the multiple SiGe wells form a much more robust structure, immune to relaxation. In this experiment, we obtain a very good mobility gain, around 50%, and layer relaxation, usually characterized by a high leakage level, is not observed in transfer characteristics, Fig. 4, even for very short PMOS transistor. Indeed, Tab. 1 shows that subthreshold slope is improved and the DIBL conserved using 10/20/30 multiple SiGe well structure with respect to the EpiSi one. The threshold voltage I S shifted due to valence band offset by 268 mV, accordingly to the theory which gives 259 mV [ 5 ] . The drain current gain, shown in Fig. 5, is linked to the threshold voltage shift. However, Fig. 6 shows that the current

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Conclusion: We have shown that multiple SiGe wells are a very promising channel architecture for O.lpm NMOS and PMOS devices. This structure leads to electron and hole effective mobility improvement due to the strain in Si and SiGe layers. Finally, we have demonstrated the improved SCE control obtained with multiple SiGe wells structure. We have demonstrated the compatibility with bulk CMOS process (at the price of adding a selective epitaxy), especially for high performance applications (low Vth) Acknowledgment: this work has been carried out within the CRESS1 consortium (between CEA-LET1 and France Telecom). ( I ) V.P. Kesan e t a / ,IEDM91, pp. 25 - 28 (2) J. Alieu et a / , ESSDERC98, pp. 144 - 147 (3) J. Alieu et a/,ESSDERC99,pp.292-295 (4) R. People, IEEE J.Q.E., vol. 22, n o 9. pp. 1696, 1986 2000 Symposium on VLSl Technology Digest of Technical Papers

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