Nanowire Phase Change Memory with Carbon ... - IEEE Xplore

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Illinois, Urbana-Champaign, IL 61801, USA. E-mail: [email protected] 2Dept. of Electrical & Computer Engineering, Univ. Illinois, Urbana-Champaign, IL 61801 ...

Nanowire Phase Change Memory with Carbon Nanotube Electrodes Feng Xiong1,2,3, Myung-Ho Bae1,2 , Yuan Dai1,2, Albert D. Liao1,2, Ashkan Behnam1,2, Enrique Carrion1,2, Sungduk Hong1,2, Daniele Ielmini4 and Eric Pop1,2,3 1

Micro & Nanotechnology Lab, Univ. Illinois, Urbana‐Champaign, IL 61801, USA. E‐mail: [email protected]   2 Dept. of Electrical & Computer Engineering, Univ. Illinois, Urbana‐Champaign, IL 61801, USA  3 Beckman Institute, Univ. Illinois, Urbana‐Champaign, IL 61801, USA  4 Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano 20133, Italy 

Data storage based on phase change materials (PCMs) encodes information as the crystalline or amorphous state of the material bit, which have a resistivity ratio >103. PCM resistive storage is thought to be more scalable [1] than charge-based devices like Flash, which are prone to leakage at nanoscale dimensions. However, PCM technology has historically suffered from relatively high (~0.5 mA) programming currents [2] needed to change the phase of the material bit through Joule heating. Here, we describe PCM nanowires (NWs) that are self-aligned with carbon nanotube (CNT) electrodes, achieving switching currents of the order ~1 μA, over two orders of magnitude below industrial state of the art. Such devices confine the PCM bit in three-dimensions, unlike previous efforts with CNT electrodes [3-5], and approach the fundamental scaling limits of this technology. To self-align NWs with CNTs without complex lithography, we first cover CNT devices with a thin (~50 nm) layer of PMMA (Figs. 1a-c). We flow current in the CNT such that its Joule heating [3] causes the PMMA covering it to evaporate [5], leaving behind a nanotrench (Figs. 1d-e). We create nanogaps in the exposed CNT by electrical breakdown (Fig. 1f) [4], sputter ~10 nm of Ge2Sb2Te5 (GST) then lift-off the remaining PMMA; this leaves behind a PCM NW perfectly aligned with the two CNT electrodes (Figs. 1g-i). Figure 2a shows current-voltage (I-V) characteristics of a typical device under dc current sweep, demonstrating SET switching from the high resistance amorphous phase of the bit (ROFF ~ 2.5 GΩ) to the low-resistance crystalline state (RON ~ 1.3 MΩ). The SET switching is initiated at a threshold voltage (VT) through a field-induced transition of the amorphous phase; Joule heating then heats up and crystallizes the bit (at ~150 ºC) into the conductive state. The VT of our devices decreases by 20-30% after the first few switching cycles, such “burn-in” being consistent with previous reports [5]. Reversible memory switching is achieved with pulsed operation (Fig. 2b). The bit is re-amorphized (RESET) with a ~100 ns current pulse which heats up the crystalline GST to its melting point (~620 ºC) then quenches it back to a disordered amorphous GST state during the short falling edge of the pulse. A memory endurance test (Fig. 2c) shows that the device can be reversibly programmed for nearly 1500 cycles. We note that such devices are capped by a thin (~10 nm) layer of SiO2, which protects the GST from oxidation; however, the capping and passivation of such devices are not yet optimized and could be improved. We plot the RON and ROFF of 102 self-aligned PCM NW devices against their respective VT in Fig. 3. The mean ratio ROFF/RON is ~ 900 for all measured devices. A few devices have off/on ratio ~2000, approaching the intrinsic switching limits of the GST material resistance. Such a high off/on ratio has not been previously achieved, and it is very promising for multilevel memory applications even at the most reduced bit dimensions. Figure 4 shows that the RESET and SET currents of our devices scale approximately with the electrode tip area, estimated as πd2/4 where d is the CNT diameter. Here, the small diameter of the CNT electrodes and their high conductivity are essential for the ultra-low power operation. In conclusion, we presented a novel technique to fabricate self-aligned PCM NW devices with CNT electrodes. The programming currents (~0.1 μA SET, ~1.6 μA RESET) and power dissipation of these devices are among the lowest reported to date. Such devices also offer outstanding ROFF/RON ratio (~103), approaching the intrinsic limits of the GST material. The powerful yet simple nanopatterning method could also be used to probe other nanomaterials by automatically aligning them with CNT electrodes. [1] M. Wuttig et al, Nat. Mat. 6, 824 (2007) [2] G. Servalli et al, IEEE IEDM Tech. Dig. 113 (2009) [3] F. Xiong et al, Appl. Phys. Lett. 95, 243103 (2009) [4] F. Xiong et al, Science 332, 568 (2011) [5] J. Liang et al, IEEE Symp. VLSI Tech. Dig. 100 (2011) [6] C.Y. Jin et al, Nano. Lett. 11, 4818 (2011)

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  Fig. 2. Device electrical characteristics. (a) Electrical characteristics of the 1st, 10th and 100th SET switch of a typical self-aligned PCM NW device, showing VT stabilizes at 3.2 V. (b) Resistance switching after a series of current pulses with increasing amplitude. SET (RESET) pulses have 300 ns (100 ns) width and rising (falling) edges of 50 ns (2 ns). The SET (RESET) current of this device is ~0.4 μA (~1.9 μA). The ratio ROFF/RON is ~2000×. (c) Endurance test over nearly 1500 cycles of operation. 8

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Fig. 1. Schematics and AFM imaging of self-aligned device. (a) CNT between two Pd electrodes. (b) AFM of a CNT with length L ~ 3.1 µm and diameter d ~ 2.2 nm. (c) The CNT device is covered with a thin layer (~50 nm) of PMMA. (d) Current flow in the CNT leads to Joule heating and nanotrench formation along it as the PMMA evaporates (in vacuum). (e) AFM imaging of nanotrench (~90 nm wide) in PMMA. Inset shows nanotrench is visible under the optical microscope, enabling quick detection. (f) CNT nanogap is formed by electrical cutting under Ar/O2 flow. (g), PCM deposition covers the device and fills the nanogap and nanotrench. (h-i) AFM imaging and schematic of self-aligned NW with CNT electrodes obtained after PMMA lift-off. Some devices were further encapsulated with a ~10-nm layer of evaporated SiO2.

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Fig. 3. Device statistics. On and off-state resistance of 102 self-aligned PCM NW devices, plotted against their threshold voltages VT. The solid and dashed fits suggest approximately linear scaling between R and VT, both governed by the bit size within the CNT nanogap. The average ROFF/RON is ~ 900. The right panel shows a histogram of the same data set.

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Fig. 4. Current scaling. SET and RESET programming currents of 13 self-aligned devices suggest pseudo-linear scaling as a function of CNT electrode tip area. The solid (dashed) line is a linear fit with a slope of 0.17 μA/nm2 (0.64 μA/nm2).

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