Jul 22, 1974 - Crenshaw Boulevard, Hawthorne, California 90250. [5]. Lilley, R.W., et.al., "Flight Evaluation", NASA TM-13, Avionics. Engineering Center ...
NASA CR-144956
OU TM-19 (NASA)
(NAs-cR-144956)
DGT£.
.
(VS-R145)DIGITAL-CORBELATION DETECTOR FOR LOW-COST OMIEGA NAVIGATION (Ohio Univ.) 55 p HC $4.50 CSCL 17G
.
.
.... _N76- 20115unclas G3/04 21412
DIGITAL CORRELATION DETECTOR
FOR LOW-COST OMEGA NAVIGATION
by Kent A. Chamberlin
Avionics Engineering Center
Department of Electrical Engineering
Ohio University
Athens, Ohio 45701
February, 1976
Supported by
National Aeronautics and Space Administration
Langley Research Center
Langley Field, Virginia
Grant NGR 36-009-017
FOREWORD
This paper was submitted to and approved by the Department of Electrical Engineering and the Graduate College of Ohio University on February 9, 1976 as a master's thesis.
TABLE OF CONTENTS Page" List of Figures
I
BACKGROUND INFORMATION
A.
Statement of the Problem
B.
Description of the Receiver Front-End
2
Antenna and Preamplifier Front-End and Envelope Detector
4
5
1. 2. C.
Preliminary Analysis 1.
II
III
ii
Test Configuration for Phase Averaging
9
9
ANALYSIS OF INCOMING OMEGA SIGNALS
14
A.
Single-Cycle Phase Measurement
14
B.
Analysis of Single-Cycle Data
16
DIGITAL PHASE LOCK LOOP.
25
A.
28
Basic DPLL Operation 1. 2. 3.
Phase Detector Digital Filtering Digital Phase Shifting and Clock Stability
28
31
32
B.
Analysis of Loop Performance
35
C.
Memory-Aiding for Time Multiplexing
41
IV
CONCLUSIONS
43
V
ACKNOWLEDGEMENTS
48
VI
REFERENCES
49
LIST OF FIGURES Page Figure 1.
Block Diagram of Components that Provide Signals to the PLL.
3
Figure 2.
Two Stage Filter.
6
Figure 3.
Envelope Detector Characteristics.
7
Figure 4.
Omega Signal Strengths.
8
Figure 5.
N-Cycle Recording Configuration.
10
Figure 6.
North Dakota (D) Station with Respect to Offset Reference Clock.
12
Figure 7.
Trinidad (B)Station with Respect to Offset Reference Clock.
13
Figure 8.
Single-Cycle Omega Phase Measurement.
15
Figure 9.
Phase of Sampled Noise in One Omega Time Slot.
17
Figure 10.
Phase of Omega B Channel for One Time Slot.
18
Figure 11.
Phase Distribution of the Raw Trinidad Transmission.
20
Figure 12.
Phase Distribution When No Signal is Present.
21
Figure 13.
Differentiated Phase Data from the Trinidad Station.
23
Figure 14.
Differentiated Phase Data from the Clear Channel.
24
Figure 15.
Basic Phase Lock Loop.
26
Figure 16.
Correlator/Phase Lock Loop Block Diagram.
27
Figure 17.
Phase Detector.
29
ii
Page
Figure 18.
Digital Phase Shifter.
33
Figure 19.
Phase Distribution for the Trinidad Station After 3-Bits of Integration.
37
Figure 20.
Phase Distribution of the Trinidad Station After 7-Bits of Integration.
38
Figure 21.
Phase Distribution of the Trinidad Station After 10-Bits of Integration.
39
Figure 22.
Lock-Up Rate Versus Phase Difference.
42
Figure 23.
Memory-Aided Phase-Locked Loop (MAPLL).
44
Figure 24.
MAPLL Timing Sequence.
45
oIII
h.
BACKGROUND INFORMATION
A.
Statement of the Problem.
Omega is a global navigation network
which will, when completed, be comprised of eight ten-kilowatt stations around the world.
[
1,2,3 1 These stations transmit very low-frequency (VLF) sinusoids
in a time-multiplexed format, each transmitting for about one second. out of every ten on each of three frequencies.
Position is determined by measuring the phase
of these signals with respect to each other.
The basic problem with making this
phase measurement is that the signals are often weak and masked by impulse noise. To overcome this problem, Omega receivers typically employ a correlation device, or phase-locked loop (PLL), to recover the phase information from the noisy signal.
The PLL configuration used in an Omega receiver is most critical
to the accuracy and cost of the system since it determines both the quality and format of the inputs to the navigation processor.
A look at presently available
receivers such as the Tracer, Dynell, and Micro models [ 41 reveals a wide variety of PLL designs.
With all of these PLL configurations available to the Omega
designer, a question which arises is whether there is any one optimal PLL design where "optimal" refers to simple configuration, minimal maintenance, good per formance, and convenient interfacing. The purpose of the research' presented in this thesis is to develop techniques to lower the cost of using Omega, specifically in the area of phase-lbcked loops. The design that has been accepted as being "optimal" is called the memory-aided phase-locked loop (MAPLL) since it allows operation on all eight Omega time slots with one PLL through the implementation of a random access memory (RAM).
-I
The first and second chapters of this paper are devoted to a description of the receiver front-end and the signals that it presents to the PLL.
A brief
statistical analysis of these signals in Chapter II allows a rough comparison of the front-end presented in this thesis to a commercially available front-end to be made.
Chapter Ill describes the hardware and theory of operation of the
MAPLL, ending with an analysis of data taken with the MAPLL.
Chapter IV
lists some conclusions about the system as well as recommendations for possible future work. The Omega system operates at three harmonically related frequencies: 10.2, 11.33..., and 13.6 KHz. The 10.2 KHz frequency alone has shown itself to be adequate for navigation during several test flights[ 5 1.; however, it may be desirable to use more than a single frequency to minimize the prob ability of an ambiguity problem.
The PLL to be presented can operate at all
Omega frequencies, although for convenience only the 10.2 KHz case will be described. The Omega sensor processor presented here is working as described and has provided good sensor processor data on several test flights. B.
Description of the Receiver Front-End.
Before anything can be said
about signal processing, some time should be devoted to the equipment that re covers the signals off the air.
This section is devoted to a description of the
components that provide the signals to the PLL. ponents is shown in Figure 1.
A block diagram for these com
The signals from the antenna receive slight
amplification in the preamplifier and are fed into the front-end where they are highly filtered and hard-limited.
The front-end has two outputs: a threshold -2
ENVELOPE FOR SYNCHRONIZATIO
RECEIVER TIMING
~FRONT PREMPLIFIER
E
PHASE LOCK LOOP HARD LIMITED OMEGA SIGNAL
to the PLL. Figure 1. Block Diagram of Components that Provide Signals
detected signal envelope to allow the receiver timing unit to start on the strongest station, and a hard-limited, TTL-compatible signal representing the Omega zero crossings.
The input to the front-end is analog, and its outputs are digital.
Since this thesis deals with the PLL, in-depth descriptions of the front-end equipment will not be given, although complete details have been published by 1 Burhans.[ 6,7 1. Antenna and Preamplifier.
A short whip or wire antenna is by
far the simplest to install but suffers from locally-generated precipitation static in snow or rain, and is non-directional with respect to nearby thundershower spherics and other local interference.
A loop or crossed pair of loops can reduce
local noise in many applications but requires more processing for the phase ambiguity introduced depending upon the bearing of the transmitting source.
Much work has
been done and many methods are proposed for reducing antenna noise problems all of which tend to increase the cost of present receiver systems.
[8]
Since the goal
of this research emphasizes low-cost, a 6 meter wire was used for these tests.
The
effective height of that antenna after the preamplifier as seen by the front-end is one meter. The purpose of the preamplifier is to match the high impedance of the antenna to the low impedance of the front-end input while supplying sufficient gain to over come losses incurred during the impedance transformation.
The high impedance
input to the preamplifier is accomplished by using a MOSFET and the low impedance output by a small audio transformer.
The phase shift through the preamplifier is
neglig bIe.
-4
2.
Front-End and Envelope Detector.
The purpose of the front-end
is to amplify the wideband signal from the preamplifier and pass only the frequency of interest (10.2 KHz) to the PLL.
This is accomplished by feeding the wideband
signals into split-ring ceramic filters, which act like mechanically-tuned tuning forks.
These devices have a very high Q and are potentially available at low
cost, if sufficient demand can be created.
After the first bandwidth reduction
stage, the signal is amplified and low-pass filtered (at 4 to 5 times the center frequency) to remove some of the spurious high-frequency response of the ceramic filter network.
The signal is further reduced in bandwidth by being fed into another
ceramic filter network.
The resulting bandpass curve is shown in Figure 2.
Again,
the phase shift through this network is negligible. The signal is then limited through a commercially available F.M. limiter-detector integrated circuit.
The
limiter is followed by a TTL-compatible hard-limiter and the signal is fed to the PLL.
The overall gain from the antenna input to the limiter output is around
100 dB. The detector output from the limiter-detector integrated circuit is a voltage that represents the envelope strength of the carrier.
The curve showing the relation
ship between front-end input to detector output is shown in Figure 3.
This data
was obtained by inputting a signal of known strength into the front-end and monitor ing the detector output.
Since the preamplifier makes the antenna appear to have
an effective height of one meter, the signal strength of a signal resulting in X microvolts at the output of the preamplifier is X microvolts/meter. Figure 4 shows typical signal strengths for several Omega stations. solid lines represent measurements taken in New York'19 -5
The
with a 30 Hz bandwidth
3dB, 15 Hz
'
-20
RELATIVE RESPONSE dB
-40
100 Hz
-60
1)
12
14
13
Figure 2. Two Stage Filter.
-6
15
KHz
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