Negative Bias Temperature Instability(NBTI) of Bulk FinFETs Sang-Yun Kim 1, Tai-su Park 2, Jae-Sung Lee3, Donggun Park4 , Ki-Nam Kim 4 and Jong-Ho Lee1 1
School of Electrical Engineering and Computer Science, Kyungpook National University,Daegu, Korea Phone : 82-53-950-6561; Fax: 82-53-950-6561; e-mail:
[email protected] 2 School of Materials Science and, Seoul National University, Shillim, Kwanak, Seoul 151-744, Korea 3 Division of Information & Communication Engineering, Uiduk University, San 50, Gyongju, 780-713, Korea,
[email protected] 4 Technology Development, Memory Device Business, Samsung Electronics Co., San #24, Nongseo-Lee, Kiheung-Eup, Yongin-Gun, Kyungki-Do, Korea
ABSTRACT We investigated Negative Bias Temperature Instability (NBTI) of bulk FinFET for the first time. Since the bulk FinFET has body terminal, it is more flexible in studying the NBTI characteristics than SOI FinFET (no body terminal). Dependence of NBTI on the back bias is smaller in 100 nm bulk FinFET with fin width of 30 nm than in conventional planar channel devices. The bulk FinFET with the side surface orientation of (100) showed better NBTI than the device with the orientation of (110). The fin width was shown to have little impact on NBTI in the bulk FinFET. Moreover, the device with longer channel showed less degradation.
gate devices based on SOI wafers is floated, the NBTI may be different to some extent from that of our bulk FinFET. The gate oxide thicknesses of the bulk FinFET are 1.8 nm on the top surface and 5.5 nm on the side surfaces of the fin body, respectively. The p+ poly-Si gate was applied to p-type bulk FinFET. The fin height (Hg) is defined as a height of side channel formed on one of the side surfaces of the fin body. The height is about 85 nm. The total dielectric thickness in STI (shallow trench isolation) is about 350 nm. The SiN thickness is 50 nm. The fin width (Wfin)is varied from 30 nm to 130 nm.
Hg
body
Introduction As the device size is continuously scaled down, novel device structures are needed to suppress so-called Short Channel Effect (SCE). As one of promising candidates for future CMOS technology, bulk FinFETs that are built on bulk Si wafer have been reported by our group [1]-[3]. The bulk FinFETs have the same scalability as SOI FinFET [4], and provide lower wafer cost, lower defect density, and higher heat transfer rate than SOI FinFETs. Additional advantages over conventional MOS devices are better scalability and less back bias effect [3]. In those scaled FinFETs and double/triplegate MOSFETs, the NBTI of PMOS devices is one of serious problems [5], since the NBTI shifts the threshold voltage and degrades the device lifetime. Both interface-trap state and oxidefixed charge are changed during NBTI stress, which causes the threshold voltage shift. The degradation due to the NBTI is more severe in p+ gate PMOSFET than in NMOSFET. The NBTI of triplegate PMOS device built on SOI wafer was characterized [6]. However, the SOI triple-gate device in [6] has no body terminal, so that we cannot observe the body current which shows the extent of the impact ionization and cannot apply any body bias as a manner of stress measurement.
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e trod lec E te Ga SiO 2
Keywords : Negative bias temperature instability, NBTI, Bulk FinFET, back bias
SiO 2 TFOX
xj
Wfin
SiN SiN
te tra ubs S Si
Fig. 1. 3-dimensional schematic view of bulk FinFET for NBTI measurement. We checked the ID-V GS characteristics to guarantee the device operation of p-type bulk FinFET and the results are shown in Fig. 2. The device shows reasonable Ion (~170 µA/µm at VGS=-1.5 V, VDS=1 V, and VBS=0 V) and Ioff (~1 nA/µm at VGS=0 V, VDS=-1 V, and VBS=0 V) currents, and excellent DIBL (drain induced barrier lowering). For negative body biases (VBS=0.5 and 1 V for PMOS), the threshold voltage is shifted only slightly, and this characteristic is one of the advantages of bulk FinFET [1], [3]. -3
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Wfin=30 nm Lg=100 nm
Drain Current(A)
In this paper, we characterize the negative bias temperature instability of bulk FinFETs for the first time. The body of the bulk FinFET is connected directly to the substrate, so that we can utilize the body terminal during measurement. We show the NBTI characteristics with body bias, and its dependence on crystal orientation, fin body width, and channel length.
Hfin=85 nm
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TEMP = 27 C VBS=0.5 V@V DS =-0.05 V
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VBS= -0.5 V@VDS=-0.05 V VBS= -1 V@V DS =-0.05 V VBS=0.5 V@V DS =-1 V
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Device Structure and I-V Characteristics
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Fig. 1 shows 3-dimensional schematic view of bulk FinFET. Process steps for the fabrication of the device are given in [2]. In the bulk FinFET, current flows on the top surface and both side surfaces of the fin body wrapped around by gate electrode. The fin body is directly connected to the substrate. Since the body in double/triple-
0-7803-8803-8/05/$20.00 ©2005 IEEE
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Fig. 2. The V GS-ID curve of bulk FinFET with different body biases. It is shown that the drain current is independent of negative body biases (V BS=0.5 and 1 V for PMOS).
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IEEE 05CH37616 43rd Annual International Reliability Physics Symposium, San Jose, 2005
To determine stress voltage, we measured the I-V characteristics for the bulk FinFET. The minus gate voltage was applied to the bulk FinFET while source, drain, and substrate electrodes are grounded. The I-V data are shown in Fig. 3. For gate bias higher than around – 1.5 V, the substrate current which can be identified with electron current rapidly increases. To avoid the impact ionization effect due to the electron current, the gate bias of –2 V is selected as a reasonable stressing condition for our bulk FinFET.
fin body has (100) of top surface and (110) of side surfaces as shown in figure (a). The figure (b) shows the cross section of 45° rotated fin body in which the top and the side surfaces have all (100) orientation. Gate
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Fig. 3. Carrier separation curves for p-type bulk FinFET with the gate length of 100 nm. The Wfinis about 50 nm.
Fig. 6 shows ∆VTH for the two types of the side orientation (a) and the impact of crystal orientation on the interface-trap density (△Nit) generated due to the NBTI (b). So far, it has been reported that the NBTI degradation of (110) surface is worse than that of (100) surface because (110) surface has more dangling bonds than (100) surface[6, 9]. In our bulk FinFETs, the crystal orientation of the side channel has been found to affect both the degradation rate and the time evolution. This result corresponds to the previous reports [6, 9]. The △Nit with (110) side surface is higher than that with (100) side surface.
NBTI Results and Discussion
50 45 40 35 30 25
∆VTH (mV)
Fig. 4 shows the threshold voltage shift (∆VTH) of bulk FinFET (Wfin=30 nm and Lg=100 nm) along with those of conventional planar MOSFETs with W/L of 10/0.15. The bulk FinFET shows larger ∆VTH and smaller ∆V TH slope with stress time. It is well known that the ∆VTH increases with decreasing device size [5]. It was reported that the NBTI degradation is worse at high VBS because the hot hole injection from substrate under high reverse body bias gives rise to faster generation of interface traps and positive oxide charges [7]. As mentioned in ID-V GS data shown in Fig. 2, the bulk FinFET shows very small back bias effect because the surface potential of the bulk FinFET is not affected remarkably by reverse body bias [8]. As shown in Fig. 4, the bulk FinFET shows less dependence of the NBTI on back bias than the conventional planar PMOSFET. Bulk FinFET W fin =30 nm, L g=100 nm T ox_top=1.8 nm,T ox_side=5.5 nm
Bulk FinFET Bulk FinFET(PMOS) top (100), side (100) top (100), side (110)
20 15 W fin=50 nm, L g=100 nm
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∆Nit 45 (100) side surface
Stress condition VG=-2 V o
∆NIT(cm )
H fin =85 nm
∆ VTH (mV)
Oxide Si substrate
(b) Fig. 5. The cross sectional schematics along the gate electrode of bulk FinFET with (a) 0° and (b) 45° rotations.
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Oxide
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H fin=85 nm
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Oxide Si substrate
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{100}
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V GS=-2 V @100 C(Bulk FinFET)
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PMOSFET Wfin=50 nm Lg=100 nm
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V GS=-2 V, V BS=2 V @100 C(Bulk FinFET)
Tox_top=1.8 nm Tox_side=5.5 nm
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V GS=-2.5 V @125 C(Planar) o
V GS=-2.5 V, VBS=3 V @125 C(Planar)
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Fig. 5 shows the cross-sectional schematics along the gate electrode of bulk FinFET: 0° and 45° rotated fin body. The 0° rotated
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Stress Time (sec)
Stress Time (sec)
Fig. 4. The NBTI characteristics with the reverse body bias. Stress conditions are VGS=-2 V, V BS =+2 V at 100 °C for bulk FinFET (T oxtop=1.8 nm and T ox-side=5.5 nm) and VGS=-2.3, VBS =+3 V at 125 °C in planar MOSFET (T ox=2.6 nm), respectively.
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(b) Fig. 6. The threshold voltage shift with different surface directions (a) and change of interface-trap density due to the NBTI with different crystal orientation (b). The △Nit was extracted from the measured data with crystal orientation. The stress condition of NBTI was V GS=-2 V at 100 °C.
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Fig. 7 shows threshold voltage shift by the NBTI with different gate width at a fixed Lg of 100 nm and a fixed Hfin of 85 nm. We can calculate effective channel width of the bulk FinFET as 2×Hfin+Wfin.
L g =100 nm T ox_top =1.8 nm, T ox_side=5.5 nm
∆ VTH (mV)
H fin=85 nm
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PMOSFET
W fin=50 nm
Stress condition V GS=-2 V
W fin=90 nm
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Acknowledgement
o
TEMP=100 C
W fin=110 nm
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This work was supported by Tera Level Nanodevices Project of MOST in 2004.
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Stress Time (sec)
Fig. 7. NBTI characteristics of bulk FinFET with different fin widths. The gate fin widths are 30 nm, 50 nm, 90 nm, 110 at a fixed gate length of 100 nm. The stress voltage was -2V at 100 °C. With the increase of Wfin from 30 nm to 110 nm, the effective channel width increases from 200 nm to 280 nm. It was reported that the NBTI degradation becomes more serious as gate width increases [10]. However, the bulk FinFETs with different effective channel widths show similar ∆V TH over the stress time. All devices in this measurement have the top surface of (100) face and the side surfaces of (110) face. As the WFin decreases, we can expect the (100) portion in the effective channel width becomes small and resultant NBTI degradation becomes small. However, we cannot observe the expected trend. It seems that there may be a factor dominated by channel structure, and further study is required. Fig. 8 shows the threshold voltage shift with different gate lengths. In principle, the NBTI is independent of gate length because the lateral electric field has no effect on the NBTI degradation. However, as shown Fig. 8, it was observed that the ∆VTH for short channel is more severe than for long channel PMOSFETs. The same trend was found in [5] where it was discussed that the end of damaged channel plays a role as leakage paths. 100 Lg
∆ VTH (mV)
100 nm 180 nm 500 nm
10 Bulk FinFET(PMOS) Wfin=50 nm Tox_top=1.8 nm, Tox_side=5.5 nm Stress condition o VGS=-2 V @100 C
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100
is smaller in bulk FinFETs than in conventional planar channel devices. We have also shown that the NBTI of the bulk FinFET with the side surface crystal orientation of (110) is worse than that in the device with (100) side surface orientation. The fin width was shown to have little impact on NBTI in the bulk FinFET, although conventional planar devices showed large degradation with increasing channel width. Long channel bulk FinFET shows lower NBTI, which corresponds to the reported results on the conventional planar channel PMOSFET.
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Stress Time (sec)
Fig. 8. NBTI degradation of bulk FinFET with different gate lengths. The gate lengths are 100 nm, 180 nm and 500 nm at a fixed Wfin of
50 nm.
Conclusion
References [1] T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, “Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafer”, Symp.on VLSI Technology. Tech. Dig., T10A3, 2003, pp. 135-136 [2] T.Park, H, J, Cho, J. K. Choe, S. Y. Han, S.-M. Jung, J. H. Jeong, B. Y. Nam, O. I. Kwon, J. N. Han, H. S. Kang, M. C. Chae, D. Y. Lee, D. Park, K. Kim, E. Yoon, and J. H. Lee “Static Noise Margin of the Full DG-CMOS SRAM Cell Using Bulk FinFETs(Omega MOSFETs)”, Proc. Of 2003 International Electron Device Meeting [3] J. H. Lee, T. Park, E. Yoon, and Y. J. Park, “Simulation Study of a New Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers,” Si Nanoelectronics Tech. Dig., 2003, pp.102-103 [4] Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Device Letters, vol.23, 2002, pp.25-27 [5] Dieter K. Schroder, Jeff A. Babcock, “Negative bias temperature Instability : Road to cross in deep submicron silicon semiconductor Manufacturing”, J. Appl. Phys. Vol. 94, Num. 1, July 2003 [6] Shigenobu Maeda, Jung-A Choi, Jeong-Hwan Yang, You-Seung Jin, Su-Kon Bae, Young-Wug Kim, and Kwang-Pyuk Suh, Negative Bias Temperature Instability in Triple Gate Transistors”, IEEE 04CH37533 43nd International Reliability Physics Symposium, Phoenix, 2004, pp. 8-12 [7] Main -Gwo Chen, Jih-San Li, Charles Jiang, Chuan H. Liu, KuanCheng Su, Yih-Jau Chang, “NBTI Mechanism Explored on the Back Gate Bias for pMOSFETs” 2003 IRW FINAL REPORT, pp.131-132 [8] Nam-Kyun Tak and Jong-Ho Lee, “RF Small Signal Modeling of Tri-Gate(Omega MOSFETs) Implemented on Bulk Si Wafers”, 2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2004, pp. 17-18 [9] Hisayo Sasaki Momose, Tatsuya Ohguro Kenji Kojima, Shin-ichi Nakamura and Yoshiaki Toyoshima, “110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on (110) surface-oriented Si substrate”, tech., dig., Symp. On. VLSI Tech., (2002), pp. 156-157 [10] G. Gellere, M. G. Valentim, and A. Paccagnella “Effect of channel width, length, and latent damage on NBTI”, 2004 IEEE International Conference on Integrated Circuit Design and Technology, pp. 303-306
We have investigated negative bias temperature instability in bulk FinFET for the first time. Dependence of the NBTI on the back bias
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