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Neural Network Simulation and Evolutionary Synthesis of QCA Circuits Omar Paranaiba Vilela Neto, Marco Aure´lio C. Pacheco, and Carlos R. Hall Barbosa Abstract—CMOS technology miniaturization limits have promoted research on new alternatives which can keep the technologically advanced level of the last decades. Quantum-dot Cellular Automata (QCA) is a new technology in the nanometer scale that has been considered as one of these alternatives. QCA have a large potential in the development of circuits with high space density and low heat dissipation and allow the development of faster computers with lower power consumption. Differently from conventional technologies, QCA do not codify information by means of electric current flow, but rather by the configuration of electrical charges in the interior of the cells. The Coulomb interaction between cells is responsible for the flow of information. This paper proposes the use of computational intelligence techniques in the simulation and in the automatic synthesis of QCA circuits. The first results show that these techniques may play an important role in this research area since they are capable of simulating efficiently and fast, synthesizing optimized circuits with a reduced number of cells. Such optimization reduces the possibility of failures and guarantees higher speed. Index Terms—Evolvable hardware, genetic algorithm, artificial neural networks, quantum-dot cellular automata, nanotechnology, nanoelectronics.

Ç 1

INTRODUCTION

T

HE

integration of two distinct areas, Quantum-dot Cellular Automata and Computational Intelligence, aimed at improving the development of nanometric computational systems, is the focus of this paper. Due to the miniaturization of transistors, the basic building unit of digital circuits in VLSI technology such as CMOS, the performance of computer chips has shown outstanding development in the last decades. CMOS technology represents binary information by switching the electric current. However, this paradigm has serious drawbacks as device sizes are reduced. The interconnection of devices and signals is one of these problems. Another problem is with regard to the quantization of charge, which becomes significant as transistors become smaller. Finally, current switching results in huge energy dissipation. Recent studies show that the spatial limits of conventional electronics will be reached in the next few years and, as a consequence, this continuing development of VLSI technology is threatened [1]. Thus, new computational paradigms that leverage the quantum effects present in the nanometric scale will have to be approached in order to develop new technologies that overcome the barrier imposed by physical laws. The paradigm of Quantum-Dot Cellular Automata (QCA) is one of the most promising alternatives to the CMOS-VLSI technologies, according to ITRS [1]. Differently from traditional computers, which use the flow of electrical . The authors are with the ICA—Research Center of Applied Computational Intelligence, Department of Engenharia Ele´trica, Pontifı´cia Universidade Cato´lica do Rio de Janeiro- PUC-Rio, Rua Marques de Sa˜o Vicente 225Ga´vea, Pre´dio Cardeal Leme, sala 401-L, CEP 22451-041, Rio de Janeiro,Brazil. E-mail: {omar, marco, hall}@ele.puc-rio.br. Manuscript received 31 Oct. 2005; revised 14 Apr. 2006; accepted 27 July 2006; published online 20 Dec. 2006. For information on obtaining reprints of this article, please send e-mail to: [email protected], and reference IEEECS Log Number TCSI-0383-1005. 0018-9340/07/$25.00 ß 2007 IEEE

current to transfer information, the QCA technology transfers information by means of the polarization state of various cells [2], [3], [4]. However, QCA is also based on binary coding due to the configuration of charges in the quantum dot cells, as will be explained later. All of the computational power is provided by the Coulomb interaction between cells, and there is no electrical current flow between cells. QCA cells and some simple devices have already been successfully developed [5], [6], [7]. However, since QCA is a new technology, much work is yet to be done. Even though the physical implementation of such devices is still being developed, it is necessary to perform studies about the architecture of QCA circuits in order to anticipate the design of complex computational systems. The functionality of QCA circuits is extremely dependent on the cell positioning, turning the design of new logical devices into a nontrivial task and also leading to a topology which is quite different from the traditional circuits. In order to implement a circuit that works correctly, each cell must be placed in such a way that it leverages the interaction with its neighboring cells, thus creating the logical behavior that is necessary to the global functioning of the circuit. However, the evaluation of QCA circuits demands the use of simulators because the physical implementation of such devices is still difficult to accomplish. Computational intelligence provides a number of techniques inspired by nature such as Genetic Algorithms and Artificial Neural Networks, which attempt the development of intelligent systems. Evolvable Hardware (EHW) refers to circuit design and optimization, using reconfigurable systems by means of Genetic Algorithms. The synthesis and optimization process considers all possible circuits that can be implemented with the available components defined in the search space. In the so-called extrinsic synthesis, circuits are continuously simulated and evaluated in order Published by the IEEE Computer Society

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Fig. 1. QCA cells with four quantum dots in two possible cell polarizations due to the Coulomb interaction between the electrons.

to find the optimized circuit that shows the desired behavior. EHW has already been applied successfully in the design of conventional and unconventional circuits [8], in different applications (digital, analog, VLSI CMOS, etc.). Artificial Neural Networks, on the other hand, are inspired by the structure and behavior of the human brain and have been used for a variety of problems. However, these techniques have not yet been thoroughly explored to help the design of nanoscale circuits and devices. The expectation is that they can provide highly useful tools, allowing faster development of this novel research area. This paper presents both the simulation and the extrinsic synthesis and optimization of Quantum-Dot Cellular Automata circuits using computational intelligence techniques. The main objective is to demonstrate the potential of the computational intelligence techniques in the design of optimized QCA circuits, thus reducing the risk of malfunction. The remainder of this paper is structured as follows: Section 2 introduces the QCA paradigm, presenting its basic concepts and the logical circuits which have already been defined. Section 3 presents the Neural-Network-based simulator. Section 4 describes the evolutionary synthesis of QCA circuits, defining representation, codification, and decodification of evolved circuits. Section 5 presents case studies and Section 6 concludes the work and suggests future works.

2

QUANTUM-DOT CELLULAR AUTOMATA (QCA)

The Quantum-Dot Cellular Automata (QCA) paradigm is presented in this section by depicting how QCA cells work and interact with one another and also the role of the clock in the functionality of the circuits. In addition, the basic QCA devices are explained in detail and the logical circuits previously developed are presented. It is important to note that this work assumes that all fabrication issues related to QCA circuits will eventually be solved in the future, so it will be possible to leverage the capacity and potential of this new technology.

2.1 The Basic QCA Devices The basic units of QCA circuits are cells made of quantum dots. A dot, in this context, is just a region where an electric charge can be located or not. The basic diagram of a cell is shown in Fig. 1, consisting of four quantum dots located at the corners of the cell. Each cell has two electrons that are free and mobile and which are able to tunnel between the quantum dots. The positive charge that compensates for the cell energy is fixed. It is assumed that tunneling to the outside of the cell is not allowed due to a high potential barrier. Considering the possibility of keeping control of the tunneling process between the cell dots and supposing that, at a given instant t, such tunneling is not allowed, thus, at

Fig 2. Nonlinear interaction between QCA cells. The polarization of cell 2 is fixed and has a strong influence on the polarization of cell 1.

the same instant, the electrons will have a well-defined position. It is because the Coulomb interaction between the electrons tends to locate the electrons at opposing diagonals, as shown in Fig. 1, rather than an isolated cell which may be in one of two equivalent energy states. These states are called cell polarizations, P ¼ þ1 and P ¼ 1. So, it is possible to codify binary information by considering that P ¼ þ1 represents the value 1 and that P ¼ 1 represents the value 0. The two possible polarization states for a cell will not be equivalent in terms of energy if another cell, with a fixed polarization, is placed in its proximity. Consider the example shown in Fig. 2, where it is assumed that cell 2 has its polarization fixed at P2 ¼ 1. The distribution of charges in cell 2 influences the distribution of charges in cell 1, which is then responsible for the polarization of cell 1 (P1). So, cell 1 tends to have the same polarization as cell 2, reducing the Coulomb interaction between all the electrons involved. It is essential to observe, in Fig. 2, the highly nonlinear interaction between the cells. A small asymmetry of charges in cell 2 is already enough to have a strong influence on the polarization of cell 1.

2.2 Simple QCA Devices In order to create QCA devices with the desired logic, the cells must be placed in a way that leverages the interaction between them. Next, two basic QCA devices are presented and explained in detail. When cells are placed diagonally to each other, they tend to have reverse polarizations due to the repulsion between electrons. This characteristic is used to implement an inverter, such as the one shown in Fig. 3a. The basic QCA logic device is called the majority gate (Fig. 3b). The device cell at the center of the gate has its lowest energy when it assumes the polarization of the

VILELA NETO ET AL.: NEURAL NETWORK SIMULATION AND EVOLUTIONARY SYNTHESIS OF QCA CIRCUITS

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Fig. 5. (a) Coulomb interaction between a rotated cell and a conventional cell. (b) Crossover of two wires with independent information at the same plane. Fig. 3. Two simple QCA devices. (a) Inverter. (b) Majority gate.

majority of the three input cells because this is the configuration where the repulsion between the electrons in the three inputs cells and the electrons in the device cell is the smallest. Observe in Fig. 3b that, even though input cell A has the polarization that represents binary 0, the device cell has the same polarization as cells B and C, which are the majority in this case. Observe also in Fig. 3b that, if input cell A is fixed at binary 0, an AND gate with two inputs (B and C) is defined. Also, if the same cell A is fixed at binary 1, an OR gate is realized.

2.3 QCA Wires in the Plane The QCA paradigm allows the possibility of implementing circuits by crossing wires on a single plane. To do so, it is necessary to introduce the concept of rotated cells. The major difference between these cells and the conventional cells shown earlier is the fact that the former have the quantum dots rotated by 45 in relation to the quantum dots of the latter. Differently from the conventional cells, the rotated cells tend to inverse their polarizations when placed side by side. Fig. 4 shows a QCA wire using rotated cells. When two cells are placed side by side, one conventional and the other rotated, there is a null electrostatic interaction between them. Thus, in both cells, the two possible energy states are equivalent, as shown in Fig. 5a. So, if a wire made by rotated cells crosses a wire made by conventional cells, there will be no interference between them, so the

Fig. 4. QCA wires made of rotated cells.

information will be transmitted independently by both wires, as shown in Fig. 5b.

2.4 QCA Clock In QCA circuits, the clock, in contrast to traditional circuits, is seen as an electrical field which controls the tunneling barriers within a cell, thus keeping control when a cell might or might not be polarized. Thus, in this case, the clock is used to synchronize the information, avoiding having a signal reach a logic gate and propagate before the other inputs reach the gate. This characteristic is extremely important in QCA circuits, guaranteeing its correct operation. Lent and Tougaw [4] defined the QCA clock as having four phases, as shown in Fig. 6. It is considered that the lag between adjacent phases is 90 . At the first phase, called switch, the QCA cells start depolarized with the tunneling potential barriers low. During this phase, the barriers are progressively increased and the cells start to polarize according to the state of their drivers (that is, their input cells). It is in this phase that the actual computation is made. At the end of this phase, the barriers are high enough to avoid the tunneling of any electron, so the states of the cells are fixed. During the second clock phase, known as hold, the barriers are kept high, so the cells in this phase have fixed states and can be used as inputs to the next stage. In the third clock phase, called release, the barriers are lowered and the cells are allowed to relax to a depolarized state. Finally,

Fig. 6. QCA cells with four quantum dots in two possible cell polarizations due to the Coulomb interaction between the electrons.

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during the last clock phase, the relax phase, the barriers are kept low and the cells remain depolarized. A QCA circuit can be divided into zones, which allows the clock to be applied to groups of cells. In each zone, a single potential can modulate the barriers between the dots. The scheme of clock zones permits a cluster of QCA cells to make a certain calculation and then have its states frozen, and, finally, have its outputs used as inputs to the next clock zone.

2.5 Previous Work on QCA Circuits Several successful demonstrations of QCA devices have been reported using metal tunnel-junctions in the Coulomb blockade regime [5], [6], [7]. These metal dot tunneljunction cells operate at 80 mK, but it is clear that, as sizes of dots and junctions shrink, operating temperatures increase. Molecular scales are predicted to allow roomtemperature QCA operation. Implementing QCA cells with single molecules is a new area with considerable promise [9]. Candidate QCA molecules use redox centers in the molecule to play the role of “dots.” Appropriate bridging ligands provide a path for tunneling from one dot to another within the molecule. Cell sizes in these systems range from 1 nm to 5 nm. There is a lot of research focused on creating these molecular circuits [10], [11]. Research on QCA architecture has already been done. The first results focused on creating basic logic devices and an Adder as an example of a QCA circuit [4]. The effect that the QCA paradigm has on architecture and system design was first studied by Niemier [12], who focused on the design of a simple processor in QCA, identifying key issues in the design of QCA logic circuits and systems. In other works, the design of implementable FPGAs was explored [13]. Another key work explored the layout parameters and layout rules that will govern the layout of QCA circuits [14]. Other research projects attempt to build models of QCA faults in order to build fault-tolerant circuits and CAD tools to facilitate the design and testing of circuits [15]. Kim et al. attempted to show several critical vulnerabilities in the structures of primitive QCA gates and QCA interconnects and proposed a disciplinary guideline to prevent any additional plausible but malfunctioning QCA designs [16]. They also presented a new design for a processor, as an alternative to the one considered by Niemier. In addition, Frost et al.’s work proposed a QCA memory architecture based on the H-memory architecture [17].

3

NEURAL NETWORK-BASED QCA SIMULATOR

The automatic synthesis of QCA circuits by means of evolutionary algorithm requires an efficient (fast) QCA simulator with an easy interface with the algorithm in order to evaluate the synthesized circuits. The few simulators already presently available [18] provide a user interface but not a software interface to allow the exchange of information with the genetic algorithm. Thus, in this paper, we propose a new QCA simulator based on Artificial Neural Networks that, by design, is fast and includes the desired characteristics needed to be used as the evaluation function of a Genetic Algorithm.

Fig. 7. Hopfield neural network with connections between all neurons.

3.1 Hopfield Neural Network The new simulator is based on Hopfield neural networks [19], [20], [21], shown in Fig. 7, which are highly interconnected and successfully used in optimization and energy minimization problems. The network structure and the synaptic weights depend on the specification of each problem. Each neuron just adds the signals sent by the other neurons, multiplied by the synaptic weights, and then generates an output signal. The weighted sum of the input signals, U, and the output signal, V(U), are called input and output potentials, respectively. The energy function for the network is defined as E ¼ 1=2

m X m X

Tij Vi Vj ;

ð1Þ

I¼1 j¼1

where Tij ði; j ¼ 1; . . . ; mÞ is the synaptic weight between neurons j and i. The set of values Tij ð¼ TjiÞ forms a symmetric matrix that contains the synaptic weights. Each Tij can be positive or negative or zero when there is no connection between neurons j and i. In order to minimize the energy of the network, the input potential Ui of neuron i is defined by Ui ¼ @E=@Vi

ði ¼ 1; . . . ; mÞ;

ð2Þ

From the above equations, it is possible to find Ui ¼

m X

Tij Vj

ði ¼ 1; . . . ; mÞ;

ð3Þ

j¼1

The above equations are better explained in [19], [20], 21] and determine the evolution of the network to a local minimum of energy, which is a metastable state of the network. These equations, plus a heuristic that controls the interaction between neurons, are enough to implement the simulator.

3.2 Simulation Rules In order to implement a QCA simulator based on Hopfield neural networks, some assumptions must be made. First, each neuron represents one cell of a QCA circuit, and might have a value between 1 and 1. So, the neural network that represents a majority gate with 20 cells, shown in Fig. 8a, has 20 neurons, as can be seen in Fig. 8b. The neuron marked with the number 1 in the neural network topology represents the cell marked with the number 1 in the circuit and so on.


195

Fig. 9. Neighborhood radius of a QCA cell considered by the simulator.

Fig. 8. (a) Majority Gate circuit (the different gray levels represent the clocking zones). (b) The topology of the Hopfield Neural Network that represents it.

The simulator receives as input a matrix that defines the circuit topology, that is, it defines where a cell exists and the type of each cell (conventional or rotated). Also, the simulator receives another matrix that defines the clock zone of each cell. Finally, it is necessary to inform the positions of the input cells and their polarizations. In the current version of the neural network-based QCA simulator, the maximum neighborhood of each cell has been defined as a circle with a radius of two cells, as depicted in Fig. 9. This neighborhood radius is enough for the correct work of the simulator, allowing the crossover of information within a plane, as explained earlier. Based on this information, it is possible to calculate the energy due to the interaction between all neighboring cells. This energy is known as kink energy and actually is the cost of two neighboring cells having different polarizations. To find the kink energy, we first compute the electrostatic energy when the cells have opposite polarization, then again when the cells have the same polarization, and then subtract the two values. This electrostatic energy also depends on the potential energy between the quantum dots. This kink energy is used as the synaptic weight T ij between two neurons that represent two cells in the circuit. Therefore, as an example, the synaptic weight between neuron 1 and neuron 2 ðT 12 ¼ T 21Þ in Fig. 8b is the value of the kink energy between cell 1 and cell 2 in Fig. 8a. After all these values are calculated, the energy function of the network, E, can be determined. The derivative of this function is the input potential of neuron i, Ui , as defined earlier. In order to simulate QCA circuits, the neural network is executed several times, according to the four possible clock phases. Only the neurons that represent cells in a switch phase can be changed. The neurons corresponding to cells that are at the previous clock phase (hold) are frozen and used as inputs to the current clock phase. The neurons corresponding to cells in the release and relax phases are set to zero. Thus, the circuits are simulated in the following way: The simulator receives as input a matrix that defines the topology, the types of cells, and the clock zones of the

circuit to be simulated. Next, the matrix that contains the synaptic weights is created. The full simulation of the circuit is comprised of two main loops. The outermost loop is responsible for controlling the global simulation and for switching of the clock zones. This loop terminates only when the stop condition defined by the user is reached. This stop condition can be, for example, the total number of clock zones. The second loop runs within each clock zone and executes until there is no further variation on the polarization of the cells contained in the present clock zone. Actually, this loop is divided in subloops as explained in the following: A very important aspect for the correct work of the circuit is the choice of the function that represents the output potential of the neuron, V ðUÞ. As discussed earlier, the interaction between QCA cells has a strong nonlinear behavior. By coincidence, the activation function of a neuron of an Artificial Neural Network also has a nonlinear characteristic, and one of the mathematical functions most frequently used is the hyperbolic tangent (tanh) [21]. Thus, for the simulator to work properly, we used a scale factor to multiply the kink energy. This scale factor increases gradually until it reaches a limit and is used to simulate the variation on the potential energy between the quantum dots of a clocking zone. Compared to previous simulators developed [18], this simulation calculates the time-independent state of the cells, like the Bistable and the Nonlinear Approximations models. Various complex circuits have been simulated in order to evaluate the simulator efficiency. The achieved results demonstrate that the neural network is able to reproduce the effects of information flow along the cells in a QCA circuit. The simulator also proved to be quite fast (the simulation of the majority gate shown in Fig. 8 took less than half a second on a Pentium 4 2.2 GHz) and provides an adequate software interface to the genetic algorithm, necessary for the evolutionary synthesis of QCA circuits.

4

EVOLUTIONARY SYNTHESIS

OF

QCA CIRCUITS

Evolvable Hardware (EHW) provides the automatic synthesis and optimization of electronic systems in reality. By genetically manipulating the representation of a circuit, EHW often finds optimized solutions which are considered unthinkable when contrasted with traditional human designs.

196

Fig. 10. Genetic cooperative coevolutionary model.

The basic component of genetic algorithms is the chromosome, which represents one individual (solution) on the search space in a certain problem. In order to synthesize optimized QCA circuits with the desired logic, the genetic algorithm must be able to evolve not only the circuit topology but also the type of cells and their respective clock zones. Thus, the evolutionary system used in this work actually has three distinct populations, representing different species in a cooperative coevolutionary model, as will be detailed later. In this model, two or more different species form an ecosystem. As in nature, the species are genetically isolated, that is, each individual can only reproduce with individuals from the same species. This is accomplished simply by isolating each species in a separate population. The different species only interact (cooperate) with one another through a shared domain, which is responsible for forming a complete solution. The generic cooperative coevolutionary model is depicted in Fig. 10. Even though Fig. 10 shows only two species, the model can have any number of distinct species. In order to calculate the fitness of the individuals from a certain species, each individual must be submitted to the domain model (which contains the evaluation function) together with one or more collaborators from each one of the remaining species (so as to form a complete solution to the problem at hand).

4.1 Representation of the Problem The simulator described in Section 3 receives as input a matrix that represents the topology of the circuit to be simulated. This matrix can be seen as a grid, as in the example shown in Fig. 11, which has 7 7 elements. Each crossing point of the grid represents the center of a cell so that each cell in the QCA is defined by four elements of the grid. This example has two input cells (gray) and one output cell (black). All other n positions (internal points) of the grid which are available for a QCA cell are numbered from 1 to n. Observe that all the borders of the input and output cells are not numbered because new QCA cells cannot be positioned in this positions as they would occupy the same position as part of the existing QCA cell. As can be seen in the grid shown in Fig. 11, the resolution of the QCA circuits design considered in this work corresponds to half of a cell, which actually has been enough for almost all QCA circuits developed so far. Anyway, the model used for the evolutionary synthesis of QCA circuits, as well as the simulator presented herein, can


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Fig. 11. Grid for a circuit with two inputs (gray) and one output (black).The numbers indicate the positions (the left-bottom point of the numbered cell) where new QCA cells can be positioned.

be easily extended to allow the synthesis of QCA circuits with smaller or larger resolutions. The representation used to create a circuit topology will guarantee that no illegal (unfeasible) solutions are generated during the evolutionary process. Legal solutions imply that the topology allows the output cells to be reached starting from the input cells. Also, the representation must guarantee that the path between each input and each output is unique, that is, it does not pass through any other input or output. This last restriction increases the chance that all inputs have influence in all outputs. A criterion that encompasses both restrictions is checking if, starting from each output, it is possible to reach each input through a distinct path. To guarantee these restrictions, we have proposed a model inspired by a former one which has been applied to the traveling salesman and other combinatorial problems with restrictions of precedence [22]. In this method, a solution is built by enforcing the restrictions as each element of an ordered list (chromosome) is considered. In the circuit topology, the main restriction imposed is that a new QCA cell can be positioned in the grid if, and only if, there is a neighboring cell to this position that is not an output cell. To do so, the topology chromosome is an array with n elements in which a unique number between 1 and n encodes the order of priority to place a QCA cell in its corresponding position. For instance, according to the chromosome shown below, the order of priority for placing a QCA cell in the first grid position is 24, while it is 3 to the last (35th). Topology Chromosome ¼ ð24 33 13 8 31 37 9 15 21 14 27 36 11 7 25 18 32 1 4 17 22 29 6 19 35 23 12 5 16 34 30 20 26 10 2 28 3Þ: The second chromosome, which represents the type of cells to be placed on the circuit, is also an array with the same dimension (n elements), but, in this case, with bits encoding the two types of cells. Thus, if there is a QCA cell in position k of the grid, the type of cell is determined by the binary value of element k of this chromosome. The value zero means a conventional QCA cell, while the value one means a rotated cell. Type ¼ ð0 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 1 0Þ:


Fig. 12. Topology of the circuit generated by the building procedure.

In a similar way, the third chromosome, which represents the clock zone to which each QCA cell pertains, also uses binary values. In this case, the binary value zero means that the cell is on the same clock zone as its neighbors and the binary value one means that this cell is leading its neighbors by one clock zone. Clock ¼ ð0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1Þ: These three arrays are examples of a possible solution when considering the grid shown in Fig. 11. The algorithm in charge of creating a valid QCA circuit topology has as inputs the grid with the location of the fixed cells (input, outputs, and cells with fixed polarizations) and the chromosomes presented above. The procedure to achieve a valid circuit employs two steps: First, the topology vector is parsed until a position where a new QCA cell is allowed is found. Next, the type of the QCA and its clock zone is defined by the other two chromosomes. The following steps would be taken for the example shown in Fig. 12, considering the three chromosome arrays seen before: The first position where a new cell can be placed, considering the priorities defined on the topology chromosome and the restriction that the position must have a nonoutput cell as a neighbor, is number 13. The other two chromosomes indicate that this cell is a conventional one and is on the same clock zone as the input cell. After that, a rotated cell, at the same clock zone, is placed at position 8. The next cell to be placed on the circuit, at position 24, is also rotated and is one clock zone ahead of the cell at position 8. Note that, at this moment, the output has already been reached. However, starting from the output, it is possible to reach only the upper left input, but not the lower left input, so the stop condition has not been reached. Finally, a conventional QCA cell is placed at position 27, one clock zone ahead of the cell at position 13. Now, the stop condition is satisfied as both inputs can be reached from the output through distinct paths. Fig. 12 shows the circuit which results from this building procedure applied to the triple chromosome.

4.2 Circuit Evaluation The number of correct outputs (hits) in comparison with a predefined truth table is used by the evaluation function to measure the circuit performance. In case the circuit has n inputs, the goal is to evolve a circuit with 2n correct answers. Thus, the evaluation function is given by: Fitness ¼ Hits;

0 Hits 2n :

ð4Þ

197

Whenever a digital circuit is being evolved, the goal is to find a circuit that is fully compliant with the specifications. Thus, the evolution of circuits that present 99 percent correct answers is not desired. However, Genetic Algorithms are easily attracted to such local minima. In order to avoid such a problem, it is necessary to include other terms in the evaluation function [8]. Such modifications on the evaluation function are somewhat dependent on the specific problem at hand, so they will be presented separately for each case study in the next section. Another important objective is to reduce the number of QCA cells in a circuit. To achieve that, a new term in the evaluation function gives fully correct logic designs a bonus which is inversely proportional to the number of cells in the circuit, so the lower the number of cells the better the evaluation. The idea of just giving a bonus to fully correct logic designs is to avoid small circuits with a low number of hits having a good evaluation, which would hinder the evolution of correct circuits. This bonus is also specific to each case study.

5

CASE STUDIES

In order to evaluate the performance of the evolutionary synthesis of QCA circuits, various circuits have been generated (and, or, multiplexer, xor, and flip-flop) and bigger and more complex circuits (full-adder and a logic unit). Three such experiments are presented herein: multiplexer, or, and xor gates. The first two were tested using the bistable engine of the QCADesigner [18] and have worked in the same way.

5.1 Experiment 1 This experiment aims to synthesize a two-input logic multiplexer. The third input is the multiplexer selector. The objective is to find a gate that functions correctly, presenting the smallest number of cells possible. This experiment uses conventional cells only, so just two populations are necessary: topology and clocking zone. A grid of three Pentium 4 2.2 GHz running in parallel was used for the automatic synthesis of the multiplexer. One of these PCs also controls the GA and distributes the simulation to the other computers. The distribution attempts to optimize execution time (faster computers receive more individuals). Ten complete runs of the GA were used to evaluate its average performance. The time necessary for the 10 executions was less than seven hours and, in this case, more than 80,000 solutions were evaluated. The evaluation function for this circuit was based on the number of hits of the logical gate, for all eight possible input configurations. However, in this case, a penalty is applied to individuals (solutions) that commit errors when the desired output is zero, in order to avoid the GA being stuck in local minima, as explained in [8]. Whenever a circuit reaches the maximum score, it is awarded a bonus. As, in this case, the grid allows a maximum number of 35 cells, the bonus was defined as 30 divided by the number of cells in the circuit, so the lower the number of cells, the better the evaluation. The value of the bonus was based on the previous tests. We observed that most of the fully correct logic circuits created have less than 30 cells.

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TABLE 1 GA and Random Search Comparison Data for 10 Experiments

The evolved circuit has four input cells (two of them are used by the selector), one output cell, and two fixed cells (one at binary 0 and the other at binary 1). The I/O cells positioning was based on known circuit configurations and on previous tests. The GA parameters are as follows: . Generations: 200. . Population: 100. . Initial Crossover Rate: 0.9. . Final Crossover Rate: 0.75. . Initial Mutation Rate: 0.2. . Final Mutation Rate: 0.5. . GAP: 20 percent. The GA parameters defined above indicate that a population of 100 individuals (solutions) is used, the stop condition being determined by the number of generations, equal to 200. The parameter GAP indicates that the 20 percent worst individuals of each generation are substituted by new individuals created by the genetic operators. The remaining parameters indicate the rates of execution of the genetic operators. In this case, the genetic algorithm has shown good results when compared with a random search approach. Table 1 contrasts both approaches by showing the number of experiments that generated a correct logic, the average number of cells in the correct circuits, and the number of cells in the best circuit found during 10 runs. The evolution can be observed by the graph in Fig. 13a, which shows the average fitness of the best individual at each generation in a total of 10 experiments with 200 generations. The random algorithm is executed in a similar way to the GA, but, in this case, the new individuals which will replace the worst individuals of each generation are randomly generated. As the best individuals are kept between consecutive generations, the random search presents a small evolution along generations. The minimal fitness value for an individual with the fully correct logic is eight. Observe that the GA found the correct logic in the 50th generation. On the other hand, the random search, on average, did not reach the correct logic. Fig. 13b shows the topology of the best circuit found by the GA, containing only 14 cells. For comparison purposes, Fig. 13c shows the topology proposed by Niemier [12] with 21 cells. Clearly, the circuit synthesized by the GA is smaller and more compact. These features are important in the development of QCA circuits. Smaller circuits have the advantage of being faster. Moreover, more compact circuits allow the creation of denser circuits, using less space to create the logical designs.

Fig. 13. (a) Average fitness of the best individuals at each generation, in 10 runs. (b) Topology of the best multiplexer found by the GA. The gray tones represent the different clock zones. (c) Topology of the multiplexer proposed by Niemier [12].

In order to increase the problem complexity, the search space was increased by using a 13 13 grid. In this case, the random search found no valid circuits. On the other hand, the GA kept successfully synthesizing the desired circuits on 60 percent of the experiments.

5.2 Experiment 2 This experiment is similar to the previous one, but now the objective is to find an OR gate with four inputs that works correctly and has the smallest number of cells possible. The evaluation function for this circuit was based on the number of hits of the logical gate for the 16 possible input configurations. Since it is a logic OR gate, the desired output is equal to binary 0 only once for all input sets. So, this output was given a weight of 2 in order to help the evolution. Adding this to all the other possible outputs, the total evaluation of a correct circuit is equal to 17. Whenever a circuit reaches this score, it is awarded a bonus, just like in the previous experiment. The evolved circuit by the GA has four input cells, one output cell, and one cell fixed at binary 1. The positioning of these cells was based on known circuit configurations or on previous tests. The GA parameters are the same as in the previous experiment, except for the population size, which, in this case, is equal to 50. Since it is a simple circuit on a small grid (13 9), the evolution is not too hard. Nevertheless, even for this circuit, the genetic algorithm has shown good results if compared with random search. Table 2 shows the number of


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TABLE 2 Comparison Data for a Total of 10 Experiments

experiments that generated a correct logic, the average number of cells in the correct circuits, and the number of cells in the best circuit found. A total of 10 experiments have been executed. This experiment was processed in the same way as the previous one and took more than three hours. Observe that the GA finds the correct logic in all experiments and also optimizes the circuit. Fig. 14a shows the topology of the 12-cell circuit found in the experiments and Fig. 14b shows the OR gate presented in [23], with 18 cells. So, the GA was able to find a circuit 33 percent smaller. The circuits in Fig. 14 have quite different designs. The circuit presented in [23] was created by a specialist that exploited the availability of the 2-input OR gate design to achieve a 4-input OR gate design. In contrast, the information available for the evolutionary synthesis was only the position of the four inputs cells, the output cell, and one fixed cell. To a specialist, it is easier to design circuits using Majority Gates while the genetic design is free to create new unrelated designs.

5.3 Experiment 3 This experiment aims to synthesize an xor circuit. The xor is a function not linearly divisible, thus its synthesis is not trivial. Differently from the other experiments, in this case, the GA needs three populations (topology, type, and clock), using rotated cells to develop the logical circuits. The GA parameters used in this experiment were: . . . .

Generations: 200. Population: 50. Initial Crossover Rate: 0.8. Final Crossover Rate: 0.65.

Fig. 14. (a) Topology of the best evolved OR gate. The different gray tones represent the clock zones. (b) The best or gate in the literature [23].

Fig. 15. Topology of the best xor found. The gray levels represent the different clock zones.

. Initial Mutation Rate: 0.08. . Final Mutation Rate: 0.4. . Steady State: 20 percent. Fig. 15 shows the topology of the best circuit synthesized. The evolved circuit has four fixed cells defined by the user: two input cells, one output cell, and one cell with the polarization fixed at binary 0. The position of these cells was also based on previous tests. The GA has found the correct logic in all experiments, while the random search has obtained success in only one experiment out of six. This new xor topology synthesized by the GA has only 27 cells, in contrast to the xor circuit proposed in the literature, which has 64 cells [3] and does not define the clocking zones. Normally, QCA specialists use rotated cells to form “wires” to deliver the information, seldom to create logic. The automatic synthesis proposed in this paper can freely explore rotated cells, using them mixed with conventional cells. The consequence of that is the large variability of circuits synthesized. This problem is due to the inherent quantum variability on the interaction between rotated cells, in some particular situations, which can randomly occur in evolved circuits such as the xor gate. This is the main reason that prevents the use of rotated cells in logic by the specialists. One of the goals of this research work is to evolve robust circuits by building topologies that avoid cell arrangements in which rotated cells may cause variability. As can be noticed in the three case studies, the objective of the work presented herein was to synthesize QCA circuits that present a correct logical behavior, with the smallest number of cells possible. The results have been quite satisfactory and have opened the possibility of a large number of new applications. One modification that is being introduced is varying the size of the grid during evolution, inspired in the work presented in [8]. This allows the synthesis of even smaller circuits by starting from small grids that would be gradually increased until circuits with the correct logic are archived. Also, multiobjective techniques [24] can be applied to separately optimize other aspects of the circuits, such as maximizing cell to cell interaction,

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which would reduce susceptibility to errors due to thermal noise, creating more robust circuits. Beyond the experiments presented in this paper, others circuits, such as a flip-flop and a full-adder, have been synthesized successfully.

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(which uses the cell as a basic unit) presents an impact in the synthesis of larger and more complex circuits, due to the large search space that is involved. An alternative would be to use this technique to synthesize only basic building blocks and then apply them as components of another evolvable hardware systems.

FUTURE WORKS

In this paper, the use of computational intelligence techniques in the simulation, automatic synthesis, and optimization of QCA circuits has been proposed and tested. Logic circuits have been successfully simulated and evolved, with correct functionality and optimized designs. As it is a new technology, the QCA circuit’s architecture is not clearly established yet. Neural Networks and Genetic Algorithms can play an important role, as shown in this paper, by aiding in the development of correct circuits and avoiding noise (introduced by the undesired polarization of other cells in the circuit) and other undesired interferences that could lead to malfunction. The use of simulators and the creation of methodologies for circuit design make it possible for researchers to understand how future circuits will function and then to assist the progress of the technology. The successful application of the EHW techniques on the synthesis of analog and digital CMOS circuits, QCA circuits, and the other applications indicates that these can be extended to develop and to enhance other nanometric devices and systems. Fifty-eight years ago, a silicon-based microstructure called a transistor was created, leading to the huge technological and scientific advances now observed in the 21st century. Contrastingly, science now has all of the technical computing resources to master nanotechnology in a much shorter period, to a degree that will allow significant advances. In this sense, Computational Intelligence offers models and algorithms inspired by nature as tools that will aid the development of nanotechnology. In this paper, the application of Computational Intelligence techniques allowed the simulation and the synthesis of optimized QCA circuits. The first results show that this design approach is able to find efficient, novel designs, leading to faster development of QCA circuit architecture. We believe that much physical space and working time can be saved in the development of complex circuits, such as a complete processor, by using evolutionary design. The simulator presented herein was able to simulate the QCA circuits in a fast and efficient way. Also, the automatic synthesis of QCA circuits has found innovative topologies, significantly reducing the number of cells in the circuits. New features to improve simulation and synthesis performance are already on the way. In one of them, the restriction of a limited neighborhood for each cell can be discarded. This can be easily achieved through a simple modification on the neural network simulator. The only impact would be a larger, but not critical, computational cost for the simulation. The synthesis of circuits on a cell by cell basis, as done in this paper, gives the user, expert or not in the field, the possibility of exploring a large variety of topologies that are hardly considered by experts. However, this approach

ACKNOWLEDGMENTS This work was supported in part by CNPq.

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[23] N. Gergel et al., “Modeling QCA for Area Minimization in Logic Synthesis,” Proc. Great Lakes Symp. VLSI (GLSVLSI ’03), Apr. 2003. [24] C.A.C. Coelho and G.B. Lamont, Applications of Multi-Objective Evolutionary Algorithms, p. 792. World Scientific, Dec. 2004. Omar Paranaiba Vilela Neto received the BE degree in computer engineering and the MSc degree in electrical engineering from the Catholic University of Rio de Janeiro (PUCRio) in 2003 and 2006, respectively. He is currently pursuing the PhD degree in the Department of Electrical Engineering, PUCRio, Brazil. His research interests include evolutionary computation, evolvable hardware, computational nanotechnology, applied computational intelligence, and nanoelectronics.

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Marco Aure´lio C. Pacheco received the PhD degree in computer science from University College London in 1991, and the master’s and electronics engineering degrees from the Catholic University of Rio de Janeiro (PUC-Rio) in 1980 and 1976, respectively. He is currently a professor in the Department of Electrical Engineering, PUC-Rio, Brazil, where he coordinates the ICA: Applied Computational Intelligence Laboratory. His research interests include evolutionary computation, evolvable hardware, computational nanotechnology, neural networks, fuzzy systems, applied computational intelligence, and data mining. Carlos R. Hall Barbosa received the bachelor’s degree in electronics and telecommunication engineering from the Catholic University of Rio de Janeiro (PUC-Rio), Brazil, in 1992 and the DSc degree in computer science (computational intelligence) from the same university in 1999. His research interests include applied computational intelligence, digital signal processing, biomedical engineering, and applied metrology.

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