© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Conference: IEEE MWSCAS 2012 - Boise, ID, USA 5-8 Aug 2012 | DOI: 10.1109/MWSCAS.2012.6291969 | URL: http://ieeexplore.ieee.org/document/6291969/
New Operational Transconductance Amplifiers Using Current Boosting Mehdi Noormohammadi, Vahid Khojasteh Lazarjan, Khosrow HajSadeghi Department of Electrical Engineering Sharif University of Technology Tehran, Iran Email:
[email protected],
[email protected] Abstract— New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in classAB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18µm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method.
I
I.
INTRODUCTION
ncreasing demand for battery operated portable equipments and power saving emphasizes the importance of low power circuit design. Lowering total power consumption, while maintaining the output signal level, is one of the fundamental challenges of designing low voltage integrated circuits. With new technology and decreasing feature size, the available supply voltage decreases but noise level is usually unchanged, hence, in order to maintain the signal to noise ratio, more total power must be consumed [1]. Operational transconductance amplifier (OTA) is a versatile building block that has been extensively employed in switched capacitor circuits such as filters and analog to digital converters [2]. The two stage OTA structure is usually utilized in which the first stage is a folded cascode and is suitable for low voltage applications [3]. The second stage of the OTA can be designed either as a class-A or class-AB amplifier. However, the OTA designed with class-A amplifier in the second stage cannot reach high gain-bandwidth (GBW) and slew rate (SR) without consuming large amount of power, due to the general characteristics of the class-A amplifiers. In order to achieve large values of gain-bandwidth and slew rate, the class-AB amplifier must be employed. The OTA with class-AB in the second stage is usually named as class-AB OTA. In this paper two current boosting methods are proposed which result in a reduction of total power consumption for high speed and low voltage OTAs compared to the conventional designs. The rest of this paper is organized as follows. Section II introduces the proposed topologies and
978-1-4673-2527-1/12/$31.00 ©2012 IEEE
presents a brief analysis of their operation, section III summarizes the results of the performed circuit simulations, and finally section IV concludes the presented paper. II.
NEW FAMILY OF TWO STAGE CLASS-AB OTAS
Fig. 1 shows a conventional OTA with second stage operating as class-AB. The M14 transistor in the second stage functions as a constant current source. It means that the maximum output current from one side of this differential structure is limited to the bias current source provided by the M13 and M14 transistors. This limits the slew rate. To increase the slew rate, increasing the bias current and in turn consuming more power is inevitable. The proposed solutions in this paper utilize circuit modifications based on nonlinear current mirrors that boost the output current in the second stage. Two topologies for two stage OTAs with nonlinear current mirror based on flipped voltage follower current sensor (FVFCS) and flipped voltage follower (FVF) are discussed in parts A and B, respectively [5],[6]. For a better description of the operation of the proposed circuits, first the following equations should be considered which show the drain current of transistors in triode and saturation regions, respectively.
k 2 2 VGS Vth VDS VDS 2 k 2 I D VGS Vth 1 VDS 2 ID
(1) (2)
When transistors operate in the linear region and their DrainSource voltage is relatively small, the quadratic term of the equation (1) can be ignored. So equation (1) can be simplified as (3).
ID
k 2 VGS Vth VDS 2
(3)
These equations are referred to the following subsections for a better analysis of the operation of the circuits.
109
VDD = 1.5V
Vb5
M12
M10
CMFB
Vi-
Vb4
CC
Vout
Vb3
VDD = 1.5V M9
I tail
Vb5
M12
M11
M8
M7
Vi
A
B
M5
M6
Vb4
Vb4
Vb3
Vb3
CC
CL
CL
CL
CC
Vout
+ Vout
CMFB
Vb
M3
M4
Vb
M13
A. Two stage OTAs with nonlinear current mirror based on FVFCS Class-AB OTAs can be implemented with FVFCS [4], [5] and [6]. Fig. 2 shows the schematic of the proposed circuit. If Vin+ is larger than Vin- , the current through M1 is reduced and the current through M5 is increased. As a result the voltage of node B decreases and that in turn increases the current of transistor Mb1 (I1). Because of existing shunt feedback with transistor Mb5 and low impedance at the source of Mb3 node, the changes of the I1 current cannot induce large changes in voltage of this node. So this node can sink large currents resulted by the changes of I1. FVFCS uses these current changes in order to change the drain voltage of Mb3 which is the gate voltage of Mb5 and Mb7. This voltage can be used for boosted current of I1 with Mb7. Fig. 3 is the DC response that shows the ratio of the Mb7 current to Mb5 current. The Mb5 is biased near triode region while Mb7 is biased to operate in saturation region in order to get an amplified version of I1 changes on the drain of Mb7. A voltage increase on the gates of Mb5 and Mb7 drives the Mb5 in to triode region, while Mb7 remains in saturation. From (2) and (3) and ignoring the channel length modulation, the current of Mb7 can be derived as equation (4).
kMb 7 I1 I B 2 kMb 5VDSMb 5
2
Noting that VDS Vb1 Mb 5
M6
M5
Vb4
B
CC
Mb10
Mb2
Mb1
Vb3
CL
Vb
Mb4
Vb1
MC2
M3
Vb2
Mb5
+ Vout
Mb6
CMFB
Mb8
Figure 2. Schematic of a two stage OTA with nonlinear current mirror based on flipped voltage follower current sensor (FVFCS)
Figure 1. Schematic of conventional two stages OTA
I Mb 7
M11
+
M7
M4
Mb7
Vi
M1
M2
Mb3
MC1
Vb2
-
Vb5
I1
Vb1
M14
M9
I tail
M8 A
Mb9 Vb
CMFB
M10
Vi+
M1
M2
Vb5
If RB is selected as resistance of node B, the voltage of this node can be expressed as equation (5).
VB g m1
Vid RB 2
(5)
The I1, ignoring channel length modulation, is:
I1
kMb1 2 VDD VB Vth 2
(6)
VB is assumed large enough so for a large signal using (4), (5) and (6), the current trough Mb7 can be expressed as equation (7). 2
2 k kMb1 Vid IB I Mb 7 Mb 7 V V g R (7) DD th m1 B 2 2kMb5VDSMb 5 2 kMb5VDSMb 5
For a large Vid the current due to input voltage is much larger than IB, so the equation (7) can be simplified as (8).
(4)
I Mb 7
2I B Vth one can adjust kMb 3
VDSMb 5 by changing IB and Vb1. IB is the current of Mb9. At equation (4) the quadratic ratio between I1 and IMb7 is clear.
kMb 7 kMb1 2 2kMb5VDSMb 5
2
2 Vid RB (8) VDD Vth g m1 2
Considering equation (8) one can observe that for large values of Vid, the output current is proportional to Vid4. This can improve gain bandwidth and slew rate considerably.
110
VDD = 1.5V
-4
8
x 10
Fig.2 Fig.4
7
Vb5
M12
M10
6
Vi-
Vb4
5 IMb7,A
CMFB
4 3
CC
Vout
Vb3
M11
Vi+
M1
M2
Vb5
M9
I tail
M8
M7
A
B
M6
M5
Vb4
Vb3
CC
+ Vout
2
CL
1 0
0
0.1
0.2
0.3
0.4
0.5 I1,A
0.6
0.7
0.8
0.9
Vb1
1 x 10
CMFB
B. Two Stage OTA with Nonlinear Current Mirror Based on FVFs. The second proposed circuit in Fig. 4 shows a two stage class-AB OTA which is combined with a nonlinear current mirror based on FVF [6], [7]. As previous circuit, transistors Mb5 and Mb6 must be biased near triode region, with their VDS to be a little more than VDSsat. Increasing Vid results in an increase in the voltage of the node A and a decrease of the voltage of the node B. The decreasing voltage of node B increases the current of Mb1 (I1), which in turn increases the gate source voltage of Mb5 and also decreases the drain source voltage of Mb5 and eventually drives Mb5 in to the triode region. Fig. 3 is the DC response that shows the ratio of the Mb7 current to Mb5 current. Considering (2) and (3) the current of Mb7, ignoring channel length modulation, can be expressed by (9).
I Mb 7
where VDS Vb1 Mb 5
2
(9)
MC1
Vb1
Mb4
Vb2
Mb5
CMFB
Mc2
M3
M4
Mb7
CL
Mb2 Mb3
-4
Figure 3. The DC response for comparison the current of M b7 and I1
k I1 Mb 7 2 kMb 5VDSMb 5
I1 M b1
Mb6
Mb8
Figure 4. Schematic of a two stage OTA with nonlinear current mirror based on flipped voltage follower (FVF)
I Mb 7
kMb 7 kMb1 2 2kMb5VDSMb 5
2
2 Vid (12) V V g R m1 B DD th 2
Considering equation (12) one can observe that for large values of Vid, the output current is proportional to Vid4. This can improve gain bandwidth and slew rate considerably. III.
SIMULATION RESULTS
In order to prove the advantages of the proposed circuits, simulation results are presented using a 0.18µm CMOS technology. All body terminals of the PMOS and NMOS are connected to the maximum and minimum voltages respectively and the load capacitance is assumed 4pF in all simulations. The power consumption has been intentionally adjusted to remain constant in order to have a fair comparison. Fig. 5 shows the step response simulations that prove the benefit of these circuit level modifications. The settling time is reduced by almost the half in both proposed circuits.
2 I1 Vth . As can be seen, VDSMb 5 kMb3
1.5
depends on I1 such that by increasing I1 the VDSMb 5 will decrease which finally results in an increase of IMb7. Ignoring channel length modulation, one can express I1 as equation (10).
kMb1 2 VDD VB Vth 2
Fig.1 Fig.2 Fig.4
0.5 Vout, V
I1
1
(10)
0
where VB is the voltage of node B and can express as (11).
VB g m1
Vid RB 2
-0.5
(11)
RB is assumed as resistance of node B. The current of Mb7, can be derived from (9), (10) and (11) and simplified into equation (12).
111
-1 0
0.5
1
1.5
2
2.5 Time,sec
3
3.5
Figure 5. Transient Response
4
4.5 -8
x 10
TABLE I.
80 Fig.1 Fig.2 Fig.4
70 60
Gain,dB
50 40 30 20 10 0 -10 -20 0 10
2
4
10
10
6
10 Frequency, Hz
8
10
0
Figure 2
Figure 4
Conventional
Gain Phase Margin GBW Slew Rate Settling Time CMRR Power Consumption Power Supply Technology
72dB 64º 200MHz 320V/µs 20ns 90 dB 1.5mW 1.5V 0.18µmCMOS
70.15dB 63 º 136MHz 236V/µs 19ns 100 dB 1.5mW 1.5V 0.18µmCMOS
60.72dB 66 º 78MHz 60V/µs 46ns 83 dB 1.5mW 1.5V 0.18µmCMOS
10
Two current boosting techniques have been employed and applied to a conventional OTA for low voltage and low power applications. Simulation results of proposed circuits in 0.18µm CMOS technology shows considerable improvement in gain, GBW, CMRR, slew rate, and settling time against conventional design as summarize in table I. These circuit level modifications considerably improve the performance of the OTAs to be used in switched capacitor circuits such as high resolution and low power analog to digital converters.
Fig.1 Fig.2 Fig.4
-40 -60 Phase,Degree
Parameters
10
(a)
-20
-80
-100 -120
REFERENCES
-140
[1]
-160 -180 -200 0 10
SIMULATION RESULTS SUMMARY
2
4
10
10
6
10 Frequency,Hz
8
10
[2]
10
10
(b) Figure 6. Frequency Response (a) DC Gain and (b) Phase Margin
[3]
Fig. 6 shows the open loop frequency responses for both proposed circuits and conventional one. Fig. 6 indicates 10 dB increment in Gain and also an improvement in the gain bandwidth of both proposed circuits against the conventional design (Fig.1). Obtained gain bandwidth shows an improvement of about two times for both proposed circuits against conventional OTA. The measured CMRR and slew rate also indicates considerable improvement as shown in table I.
[4]
IV.
[5]
[6]
CONCLUSION
Two proposed class-AB OTAs have been presented and compared with conventional design using simulation results.
[7]
112
M. Abo, P. R. Gray. "A 1.5-V 10-bit. IJ.3MSls CMOS Pipeline Analog-to-Digital Converter." in IEEE J. Solid State Circuits, vo1.34. pp.599-606. May 1999. Chang, P., Rofougaran, A., and Abidi, A.: „A CMOS channel-select filter for a direct-conversion wireless receiver‟, IEEE J. Solid State Circuits,1997, 32, (5), pp. 722–729. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2000. R. G. Carvajal, J. Ramírez-Angulo, A. J. Lopez-Martin, A. Torralba, J. A. Galan, A. Carlosena, and F. Muñoz, “The flipped voltage follower: A useful cell for low-voltage, low-power circuit design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1276–1291, Jul. 2005. Juan A. Galan, Antonio J. López-Martín, Member, IEEE, Ramón G. Carvajal, Senior Member, IEEE, Jaime Ramírez-Angulo, Fellow, IEEE, and Carlos Rubia-Marcos,” Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling”, IEEE Transactions on Circuits and Systems-I: Regular Papares, vol. 54, no. 3, pp.449-457 march 2007. V. Peluso, P. Vancorenland, M. Steyaert, and W. Sansen, “900 mV differential Class-ABOTAfor switched opamp applications,” Electron. Lett., vol. 33, no. 17, pp. 1455–1456, Aug. 1997. F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, “Low-voltage Class-AB buffers with quiescent current control,” IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 915–920, Jun. 1998.
