New Power Factor Correction AC-DC Converter With ... - IEEE Xplore

384

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 1, FEBRUARY 2007

New Power Factor Correction AC-DC Converter With Reduced Storage Capacitor Voltage Antonio Lázaro, Member, IEEE, Andrés Barrado, Member, IEEE, Marina Sanz, Member, IEEE, Vicente Salas, Member, IEEE, and Emilio Olías

Abstract—Most of single-stage power factor correction (PFC) ac-dc converters usually present a high voltage swing on the storage capacitor. That means, high size and cost of the storage capacitor is obtained. The Series Inductance Interval (SII) PFC converters allow reducing cost and size of the storage capacitor since the capacitor voltage is lower than the output voltage and, therefore, the voltage swing is significantly reduced. In this paper, the novel single-stage SII-B-2D PFC converter is presented. In addition, this topology provides input current harmonics under EN61000-3-2 Class D limits and advantageous component count. Index Terms—AC-DC power conversion, capacitive energy storage, power conversion harmonics, power electronics, power supplies, pulse width modulated power converters.

I. INTRODUCTION INGLE-STAGE power factor correction (PFC) ac-dc converters become interesting in low power applications since they present lower cost and complexity in comparison to classical two-stage approach. However, several aspects must be considered from the point of view of the single-stage PFC solutions performance. Assuming universal line voltage operation and fast output voltage regulation these aspects are the following:

S

A. Input Current The input current of the two-stage approach is potentially sinusoidal. However, the regulations allow a harmonic content in line current. The EN61000-3-2:2000 (mandatory in January 2004) and the new version EN61000-3-2: 2005-11 Third Edition [1], forces power supplies of “high impact products” as computers, PC monitors and television sets to comply with Class D limits. Therefore, the compliance of the Class D limits would be an added value of single-stage PFC solutions. B. Storage-Capacitor Voltage Swing and Storage-Capacitor Size and Cost Since input energy is pulsating, any power factor correction (PFC) ac-dc converter, requires a storage element to provide Manuscript received October 1, 2004; revised July 28, 2006. Abstract published on the Internet November 30, 2006. This work was supported in part by the Ministry of Science and Technology (Spain) through research project ARDID (Code of PN: ENE2005-08674). This paper (Best paper award) was presented at the IEEE Industrial Electronics Society Conference (IECON) in 2002, Sevilla, Spain. The authors are with the Universidad Carlos III de Madrid, Departamento de Tecnología Electrónica, Grupo de Sistemas Electrónicos de Potencia, Madrid 28911, Spain (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2006.888795

constant power to the load. In two-stage approach, the control loop of the PFC front-end regulates the storage-capacitor voltage, however, in single-stage PFC there is not any control loop in charge of storage-capacitor voltage regulation. Therefore, in single-stage converters, the storage capacitor voltage can vary with both, the load power and the input ac voltage. The input voltage, when universal range voltage is considered, presents a voltage swing from 1 to 3 approximately (85 to 265 ). In single-stage converters this voltage swing could appear also in the storage-capacitor voltage, since this is not a regulated voltage. In this case, the storage capacitor requires both, a large capacitance value (to meet the hold-up time requirement at low line ac voltage) and a high voltage rating ) at high line ac voltage. Therefore, the size and cost ( of the storage-capacitor will increase a lot in comparison to the two-stage approach. Taking into account the prior art of single-stage PFC converters (two interesting surveys are provided in [2] and [3]), the different solutions could be classified into several groups according to the storage-capacitor voltage. The interesting group of solutions [4]–[6] obtains a storage capacitor voltage clamped to the peak value of input voltage. Therefore, in this case, the input line voltage variation (1 to 3) is still produced and the rated voltage of the needed capacitors is 400 V (the same value than in a Boost PFC front end of a two-stage approach). Other important groups of single-stage solutions [7]–[10], is named as “current shaper.” In these converters, the voltage on storage capacitor varies with both, input voltage and output power, therefore, the voltage swing is higher than in the previous group, and the size and cost of the storage capacitor is even more penalized. In the simple solution proposed in [11], the voltage values on storage capacitor are lower than the peak of the input voltage. As it can be seen, in the more detailed analysis of this topology carried out in [12], this converter can be designed in order to reduce the storage capacitor voltage swing and, therefore, in order to reduce the size and cost of the storage capacitor. In this paper, is proposed a new topology which obtains an important reduction of the voltage swing on storage capacitor. C. Simplicity and Component Count The raison d’être of single-stage PFC ac-dc converters has been to reduce the complexity and cost of the two-stage approach for low power applications. According to this, a solution holds a better position in the ranking if the following hold. • Only a simple feedback loop is needed to obtain a well regulated output voltage.

0278-0046/$25.00 © 2007 IEEE

LÁZARO et al.: NEW PFC AC-DC CONVERTER WITH REDUCED STORAGE CAPACITOR VOLTAGE

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Fig. 1. Power stage and control loop of the SII-B-2D converter.

• Complex transformers are not required in order to avoid high manufacturing cost. Furthermore, some solutions can also be less attractive if the magnetic components are bigger and more complex than those of the equivalent two-stage approach. • No extra components in the power stage are added to the two-stage approach. Much better if some of the converter components present lower size and cost. In the “current shaper” group of solutions [7]–[10], just a few components are added to a conventional dc-dc converter. Therefore, from the point of view of simplicity, these converters can be considered as an advantageous solution.

D. Energy Processing and Efficiency At first, the poorest performance falls on the two-stage approach because the total power is processed twice and also falls on those converters which operate in discontinuous conduction mode (DCM) due to the higher rms currents. New MOSFET technologies, together with an energy-processing lower than two, could provide to DCM low power single-stage converters an efficiency similar to the two-stage approach efficiency. However, when the power value is increased the way in which the power is processed becomes more important than the number of times power is processed [13]. Then, the two-stage approach obtains the best results. If a revision of the prior art of low power PFC converters is done, it can be concluded that there is not a topology which optimizes the four PFC requirements at the same time. Most interesting solutions achieve good results in two or three aspects, and the rest of the aspects are good enough so they do not force the solution to be rejected. Therefore, the concrete application would define which is the best solution. In this context, a new family of PFC converters has been recently proposed in [14]. These converters present an overall good performance, taking into account the four aspects aforementioned. In this paper, a new topology of the Series Inductance Interval (SII) family of PFC converters is analyzed and experimentally verified.

II. PROPOSED AC-DC CONVERTER The proposed ac-dc converter is shown in Fig. 1. On one hand, ( if it is the magnetizing inductance of the transformer viewed at the primary winding and if it is referred to the and secondary winding), the MOSFET , the diodes can be seen as a Flyback converter. On other hand, the and the diode can be inductance , the MOSFET seen as a Boost converter. Both inductances ( and ) operate in DCM to achieve automatic power factor correction. Finally, this topology requires two diodes in the secondary side of instead of three as other SII converters proposed in [14]. This is the reason for the name SII-B-2D. The main advantages of the proposed converter can be summarized as follows: • Storage capacitor size and cost: Due to the topology, the voltage on the storage capacitor is always lower than output voltage. Therefore, the voltage swing on storage capacitor, due to the input voltage variation, can be significantly reduced. This is an important advantage that makes the proposed converter to be a competitive solution in comparison to some other single-stage converters. • EN61000-3-2 compliance: The input current complies with the Class D limits regardless of the load power because of the DCM operation. The margin to comply with Class D limits can be selected by design as will be detailed in the paper. • The component count is also favourable. In comparison to a typical two-stage approach (Boost front-end plus Flyback dc-dc converter), the same number of power components are used. However, the SII-B-2D converter presents a branch ( , , ) which handles just a of the input power, moreover they have a lower voltage rating. Additionally, just a single control loop is required to obtain a tightly regulated output voltage. This control loop generates a common duty cycle which is applied to both MOSFET. Two different aspects are related with the reduction of the cost of the control stage. On the one hand, the proposed converter eliminates the use of one of the two control IC present in a two-stage approach. On the other

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Fig. 3. Switching modes along the line cycle.

Fig. 2. Application field of proposed converter in comparison with passive, singe-stage and two-stage PFC ac-dc converter. (a) For Class-A compliance. (b) For Class-D compliance.

hand, the DCM operation of this topology provides automatic PFC, so a “multiplier IC” is not required to shape input current. • Energy processing and efficiency: By means of a suitable design, up to a 70% of the input power can be processed only once. That means, the penalty in the converter efficiency due to DCM operation is reduced. Therefore, for low power applications, the proposed converter allows obtaining a competitive efficiency, similar to the obtained by means of a two-stage approach. Taking into account the abovementioned four aspects and the study of the prior art [2]–[15], the field of application for each type of ac-dc converter can be distributed as it is shown in Fig. 2. In this figure, passive solutions, single-stage converters and twostage approach, have been distributed as a function of the output power for two input-voltage ranges and for Class A or Class D compliance. We wish to highlight that each area does not present hard boundaries, but most of the time overlapping is produced. Technical aspects make two-stage approach the most suitable solution, mainly for medium-high power applications. However for low power applications some other could also be attractive. In [15] it is shown, how passive components could shape line current to comply with Class A limits up to 300–400 W, when a range selector is used together with voltage doubler topologies. Single-stage converters seem to have a wider application field under European input-voltage range, for Class A applications.

Universal input voltage range penalises the use of single- stage converters due to the required bulk and expensive storage capacitor and also due to the lower efficiency associated to those converters which operate in DCM. The most suitable field of application, of the proposed converter, have been pointed out in Fig. 2(b). As it will be demonstrated in Section VI, the proposed PFC could be interesting for applications up to 200 W, with European voltage range ( ), and for applications up to 100–120 W, for universal input-voltage range ( ). Therefore, potential applications of the proposed ac-dc converter could be as follows. • PC monitors and ac-dc adapters for laptops: Universal input voltage range and output power about 100 W. • Small television sets: European input voltage range and output power about 200 W. III. SWITCHING PROCESS The converter has two operation modes depending on the instantaneous magnitude of the input line voltage as it is illustrated in Fig. 3. Since the principal switching mode is Mode 2, its corresponding switching process will be described in more detail. A. Mode 2 The main switching frequency waveforms together with the equivalent circuit of each stage are represented in Fig. 4. The switching process can be summarized as follows: and are switched on. is magnetized with 1) Stage 1: the voltage on storage capacitor and is magnetized with the input voltage. The duration of this stage normalized with the switching period is . 2) Stage 2: delivers energy through . resets through and via and connected in series. Therefore, each switching cycle, single processing energy and double processing energy flow through as it can be also seen in Fig. 5(a). The normalized duration of this stage is . 3) Stage 3: is recharged with the current. During current has been decreasing because the output Stage 2, the voltage minus the storage capacitor voltage has been applied on it. When this current reaches the zero value, Stage 2 finishes. Furthermore, this current begins to flow in the opposite sense.


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Fig. 4. Mode 2 switching frequency theoretical waveforms. Equivalent circuit of each stage of the switching cycle.

Therefore, is recharged since the current is flowing into it [see Fig. 5(b)]. When the value of the current through is equal to the reset current of , switches off and the Stage 3 ends. The duration of the third stage is . 4) Stage 4: “The Series Inductance Interval.” Once has switched off, and result connected in series and they reset together. This stage is common to all the SII converters and gives them its name. Stages 3 and 4 allow the recharge of as it can be seen in Fig. 5(b). The normalized duration of the series inductance interval is . After this stage, as in any converter working in DCM, a dead time is produced. The duration is .

reset before . Therefore, taneous input voltage make never inverts its current and is not recharged. The currents of both inductances are shown in Fig. 6. The boundary line angle, , between the operation modes 1 and 2 is given by (1). This value of the line angle is reached when the reset time of , , and the reset time of , , become equal

B. Mode 1 In this switching mode, output is also feed from the input and from the storage capacitor. However, low value of the instan-

where is the turns ratio of (1: ), is the peak value of the line voltage, is the output voltage and is the storage capacitor voltage.

(1)

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Fig. 5. (a) Single and double processing energy and current through DS1–2. (b) Energy delivered to C1 and current through DS1 AUX.

IV. ENERGY PROCESSING

A simple method to explain the energy transference among the three main ports of PFC converters (input source, storage element and load) is proposed in [16]. According to this method, SII converters can be analyzed by means of the block diagram shown in Fig. 7(b). This block diagram and energy flow among the input source ( ), the storage element (C1) and the load ( ) is classified as I-IIIB type [I-IIIB is just the name given in [16] to those converters which block diagram is identical to the one represented in Fig. 7(b)]. In the proposed topology [Fig. 7(a)], the inner Flyback converter placed in the position 2 takes the power from the line [branch 1 in Fig. 7(b)]. A portion of this energy [trace in Fig. 7(a) and branch in Fig. 7(b)] is directly delivered to the output through the series connection of and , so, this energy is processed once. The other portion of the input energy is stored in the capacitor C1 also through the diode [branch in Fig. 7(b)]. The components , and can be seen as a Boost converter which holds the position 1 of the block diagram. Along the whole line half-cycle, and complementarily to the single processing energy, the Boost converter feeds the output via [trace in Fig. 7(b) and branch in Fig. 7(b)] with the energy stored in capacitor . This energy is processed twice and its value equals the output power when input voltage reaches zero Volts. In Appendix A, the derivation of the main line frequency theoretical waveforms for the proposed ac-dc converter is given. As an example, Fig. 8 shows these theoretical waveforms for a single processing power of 68% of the output power. Fig. 8(a) shows how the duty cycle must vary with the line angle to keep the output voltage constant. The output voltage

presents a fast dynamic response since the addition of the avand is constant along the erage currents through whole line half-cycle, see Fig. 8(d). The single processing power, is given by the product of the output voltage, , and the average value of (see Figs. 5 and 6). The regulation EN61000-3-2 allows some distortion in the line current (in Fig. 8(b), a line current which complies with Class D limits is shown). This fact allows increasing the single processing power and, therefore, an improvement in the converter efficiency is obtained. In Fig. 8(c), the evolution of the input power with the line angle is represented. The dashed line is the input power if sinusoidal input current is obtained while the bold black line is the input power of the proposed converter. As a consequence of the input current distortion, a higher percentage of the input power (68%) is processed once. This value is higher that the maximum single processing power obtained when the line current is sinusoidal. In this case, just the 50% of the output power can be processed once. It can be seen, how the single level) is higher that the processing power (area below the double processing power [line-filled area in Fig. 8(c) and (d)]. Therefore, the inner converter 1 have to transfer a low power level and the low overall efficiency, due to DCM operation, can be improved. As it will be seen in the next paragraph, it is very useful to , as the proportion between define the single processing ratio, the single processing power and the output power. Taking into is given by (2). For example of Fig. 8, account Figs. 5 and 6, the value of is 0.68

(2) It should be noticed that the equation of is different for each mode of operation as it is detailed in Appendix A. V. DESIGN GUIDELINES A. Design Parameters The degrees of freedom to design the converter SII-B-2D are three, the turns ratio of and the value of the inductances and . However, normalizing the values of the inductances and has been considered a more useful way to describe the design guidelines. The normalized design parameters are the following. • turns ratio

(3) • Dimensionless load parameter

(4)


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Fig. 6. Mode 1 switching frequency theoretical waveforms of the current through the inductance L12 and L2 and diode DS1-AUX. Equivalent circuit of each stage of the switching cycle and single energy processing.

where is the load resistor and riod. • Inductance ratio

is the switching pe-

(5) Since the equation which connects the storage capacitor voltage ( ) with the other circuit parameters is transcendental, mathematical software such as MathCAD® must be used and only numerical solutions can be obtained for each design and operating conditions. The structure and main analytical equations of the calculus program are shown in Appendix A. These equations have been programmed in a MathCAD®-developed calculus program which provides the corresponding numerical values of , are obtained, as well as the evolution of the input current, duty cycle, etc, with the line angle. An example of the output of the program is shown in Fig. 8. In addition, the evaluation repeatedly of the MathCAD® program allows analysing the effect of each dimensionless design

parameter on the performance of the converter. The main results of this analysis are shown in Figs. 9 and 10. , has a close reThe ratio of the single processing power, lation with the efficiency and also gives information about the size of the inner converter 1. Therefore, this parameter has been preferred to describe the performance of the design better than the use of theoretical efficiency models. Also the storage capacitor voltage and input current harmonic content have been taken into account. B. Design Process Fig. 9(a) shows the waveform and harmonic content of the input current for designs with a different single processing ratio, . The harmonic content of the input current for each value compared to the Class D limits are represented in Fig. 9(b). In order to get the highest efficiency, the best design corresponds to the highest value of , while Class D limits are complied. The influence of each design parameter is represented in Fig. 10 and can be summarized as follows:

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Fig. 7. Block diagram and energy flow (a) in SII-B-2D converter according to I-IIIB PFC type (b).

•

turns ratio ( ): decreases slightly with , see Fig. 10(c). However, the storage capacitor voltage depends strongly of as it can bee seen in Fig. 10(a) and (b). The higher is, the higher the storage capacitor voltage is obtained. • Dimensionless load parameter ( ): has no influence on either the input current waveform or on the storage capacitor voltage since the converter operates in DCM. This parameter has to be selected low enough to assure the DCM operation for full load and the lower input voltage, 84 . • Inductance ratio ( ): As it can be seen in Figs. 9(a) and 10(c), the input current waveform and depend strongly on . A better input current waveform and, therefore, a wider margin with respect to the regulation limits are obtained for higher values of . However, high values of imply low values of and, therefore, worse efficiencies.

C. Optimized Design The storage capacitor is determined by its voltage value at high and low line. • Storage capacitor voltage at low line, (84 ). This value defines the required capacitance to meet the

hold-up time requirement and is given by (6) (considering full storage capacitor discharge by constant power load)

(6) is the output where HUT is the hold-up time, and power. • Storage capacitor voltage at high line, (265 ): This value defines the voltage rating of the storage capacitor. In order to obtain the lower storage capacitor size, the design must obtain the following. • A value of (84 ) as high as possible. This way a lower value of capacitance is needed. • A value of (265 as close as possible to the upper commercial rated value. An example of good-performance design is shown in Table I. In this design, has been chosen lower enough to obtain a about 70% and high enough to comply Class D limits. The value of has been selected to obtain a storage capacitor voltage at high line (265 ) lower than the commercial rated voltage of 35 V. Besides, this value has been selected to hold the


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Fig. 8. Line frequency theoretical waveforms.

storage capacitor voltage in a value of 18.8 V at low line (84 ). 1) Storage-Capacitor Voltage Comparison Between the Converter SII-B-2D and a Two-Stage Approach: As it can be seen in Table I, the voltage swing on storage capacitor goes from 1 to 1.8 times (18.8 to 34 V) when input voltage varies from 1 to 3 (84–265 Vrms) with universal input voltage range. Therefore, the storage capacitor size is bigger in SII-B-2D converter than in two-stage approach since, in these converters, the voltage swing of the storage capacitor is null. However, it is important to highlight that just the 30% of the input power is handled by the storage capacitor. Hence, the rms value of the storage capacitor current (low-frequency ripple) is reduced in comparison with the rms current value of the capacitor in two-stage approach. 2) Storage-Capacitor Voltage Comparison Between the Converter SII-B-2D and Other Single-Stage Converters: The storage capacitor size of the proposed converter has been compared to the capacitor size required in a single-stage converter which storage-capacitor voltage was clamped to the peak value of line voltage “clamped converters.” It can be seen in Table II how the selected design of the proposed SII-B-2D converter provides a lower size than the “clamped converters” considering universal input line voltage. The required capacitance has been obtained using (6) and miniature size series of com-

mercial cap-acitors. Therefore, the SII-B-2D converter takes advantage in terms of size over the “clamped converters” since the variation of the storage capacitor voltage is lower in the SII-B-2D converter under universal input voltage range. The SII-B-2D converter requires just 1.8 times capacitor voltage swing against the 3 times of the clamped converters.

VI. EXPERIMENTAL RESULTS A SII-B-2D converter for European input range has been developed and experimentally checked in order to validate the features of the proposed topology, because as mentioned before, the proposed converter becomes more interesting under European voltage range. The prototype specifications are as follows: • output power: 100 W; • output voltage: 56 VDC; • ac line voltage: 187–265 VRMS, “European range.” The design parameters selected for the proposed converter are detailed in Table III. These parameters are similar to the optimized design which has been described in Section V. In addition, the output capacitor ( ) is 47 /63 V. It is important to highlight that the output capacitance value is not

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Fig. 9. Influence of inductance ratio, , on single processing power ratio, KP, and on the input current waveform and harmonic content by varying n1.

very high since this capacitor only must reduce the high-frequency ripple of the output voltage. Low-frequency ripple (100-120 Hz) is not produced, since the output is fed by a constant power during the whole line cycle.

A. EN61000-3-2 Compliance The measured line current of the SII-B-2D converter is shown in Fig. 11(a). According to the design parameters of Table III,

the converter presents a value around 0.65 and the input current waveform complies with the Class D limits with a wide enough margin, as it can be seen in Fig. 11(b). We wish to highlight that the harmonic compliance test has been carried out with distorted input voltage due to limitations in the laboratory setup. If sinusoidal line voltage had been used, the margin to the regulation limits would be increased. Experimental results Fig. 11(b) also validate the relationship between and the harmonic content of the line current. It has been theoretically determined that, values lower than 0.7 (in this particular case 0.65) bring the


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TABLE I SELECTED PARAMETER VALUES OF AN OPTIMIZED DESIGN FOR UNIVERSAL INPUT VOLTAGE RANGE AND P = 100 W

TABLE II STORAGE CAPACITOR VOLTAGE SIZE COMPARISON BETWEEN A “CLAMPED CONVERTER” AND THE PROPOSED SII-B-2D CONVERTER. HUT = 10 MS AND

P

= 100 W

TABLE III SELECTED DESIGN PARAMETERS FOR THE PROTOTYPE

Appendix A). Since Class D limits are expressed in mA/W, it can be seen than output power does not affect the regulation compliance. B. Storage Capacitor

Fig. 10. Influence of design parameters n1 and .

input current to comply with Class D limits (see Figs. 9 and 10). A wider margin of compliance can be obtained by increasing , however a penalty in the converter efficiency is produced. The input current harmonics have been measured at full load and 230 as it is specified in the regulation [1]. Regarding to the load conditions, it is important to highlight that input current is proportional to output power due to DCM operation (see also

The measured variation of the storage capacitor voltage as a function of the load power and the input ac voltage has been represented in Fig. 12(a). The storage capacitor voltage is held for 187 V and 34 for 253 V ac line voltage, around 28 just a variation of 1.2 times. Since the converter operates in DCM, the voltage on storage capacitor ( ) does not vary with the load power (see [17] for a theoretical explanation). The measured variation with load power has been lower than a 2%. This low variation is due to the DCM operation of the converter. It should be noticed that the proposed converter can not operate at null load condition since any Flyback converter requires a minimum load. In Table IV, a storage capacitor size comparison between “clamped converters” and the prototype for European range has been shown. Also in this table it is shown the rated ripple current at low and high frequency. In the case of the prototype, the rms current values at both frequencies are lower than the rated / 35 V Nichicon PJ values for the selected capacitor (3300 series). According to high-frequency current ripple, only at the zero crossing of input voltage, when storage capacitor is providing most of the output power, their high-frequency current ripple is high. However, during the rest of the half line cycle, highfrequency ripple is reduced significantly because most of power

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Fig. 11. (a) v , rectified line voltage (100 V/div). i , line current (0.5 A/div). Error amplifier output (duty cycle) (0.5 V/div, ac coupling). Time base 5 ms. (b) Harmonic content and Class D limits. Fig. 12. (a) Storage capacitor voltage variation. (b) Hold up time measurement.

is transferred directly from the input. If an average value (in the half-line cycle) is considered to be under the rated current, ripple value can be easily obtained. In Table IV, it can be seen how similar size of storage capacitor is obtained for two very different storage capacitor voltages: 35 V for the prototype and 400 V for “clamped converters.” Therefore, no penalty is paid by using a low-voltage capacitor. This fact could be explained as follows. On the one hand, although more micro Farads must be used at low voltage to store the same energy, low-voltage capacitors present a lower size. On the other hand, a bigger number of capacitance values as well as a bigger number of rated voltage values are available in commercial low-voltage series ( ). Therefore, low voltage capacitors could result better exploited, so, the size and cost can be reduced. As conclusion, above a nominal voltage about 35–50 V, there is not a capacitance value which drastically reduces the size of the storage capacitor, see [18] and [19] for detailed explanation. Finally, the measured hold-up time is shown in Fig. 12(b). C. Efficiency The efficiency of the proposed converter is shown in Fig. 13. The use of Coolmos technology for the switch , as well as the value of , allows obtaining these competitive efficiency values. Since the conduction losses of the MOSFETS increase in DCM operation, if universal input voltage range is considered, the efficiency of the prototype is expected to be reduced. In order

to guarantee the DCM operation, under universal range, the inductance must be significantly reduced, therefore, the rms currents will increase. In this case, the efficiency could be reduced up to a margin between 0.78 and 0.81. Therefore, under universal range, this solution may be only attractive for very low power applications, about 100 W. D. Dynamic Response Fig. 14 shows the line current, the duty cycle, and the output voltage variation under a load step of 55% of amplitude. From these measurements, it can be concluded that fast dynamic and tightly regulated output voltage is obtained. • As seen in Fig. 14(a), the duty cycle and the line current are adapted to the new load conditions instantaneously. Hence, the converter does not require several line cycles to reach the new steady-state conditions. • When a negative step in the load current is produced, just a small overshoot appears in the output voltage as it is shown in Fig. 14(b). • Although, the proposed converter should not present low-frequency ripple, since the output is fed by a constant power during the whole line cycle, the output voltage shows a small output voltage variation of 100 Hz [see Fig. 14(b)]. This effect is due to the fact that DCM operation reduces the loop gain at 100 Hz, thus, a small part of input voltage ripple is transferred to the output.


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TABLE IV STORAGE CAPACITOR SIZE & CURRENT RIPPLE COMPARISON BETWEEN “CLAMPED CONVERTERS” AND THE PROTOTYPE FOR EUROPEAN RANGE. AND

P = 100 W

HUT = 10 MS

creases. Hence, an overall bandwidth lower than 1.5 kHz produces extra distortion in the line current. As seen in Fig. 14(a) and (b), the value of the line current is always higher at the beginning of the half line cycle. [20] can be seen for further information. To obtain the shown fast dynamic of the converter, a single control loop (based on a low cost IC controller) has been used. Furthermore, the same duty cycle is applied to both MOSFET. It is important to highlight that the maximum ac voltage in the measurements (253 Vrms) is lower than the specified value (265 Vrms) due to limitations of the ac source available in the experimental setup. However, this value does not significantly affect the results since the difference between the experimental and specified ac voltage is only 5%.

Fig. 13. Efficiency measured in the prototype.

VII. CONCLUSION

Fig. 14. Dynamical response. (a) Positive load step. (b) Negative load step. , rectified line voltage (100 V/div). , line current (0.5 A/div). Duty , output voltage cycle (0.5 V/div, ac coupling). , output current (1 A/div). ripple (0.5 V/div, ac coupling).

v

I

i

1v

• A 1.5 kHz loop bandwidth is obtained for the peak value of the input voltage. However, the loop gain and the bandwidth diminish when the instantaneous input voltage de-

In this paper, a new SII single-stage ac-dc PFC converter has been presented together with the main design guidelines and experimental results. The main advantages of the novel topology are the following. • EN61000-3-2 Class D compliance. • The prototype has obtained an experimental voltage value around 29 VDC on storage capacitor, for an output voltage of 56 VDC. The reduced variation with line voltage ( ) and load power ( ), together with the low rated voltage of storage capacitor voltage allow reducing the size of the storage capacitor. • A tightly regulated output voltage with fast dynamic response is achieved by means of a single control loop operating on both MOSFET. • The components count also results advantageous because the converter uses the same power components than a Boost–Flyback two-stage approach. However, in the proposed topology, the inner converter 1 transfers just 30% of the total power and its components have a low rated voltage. The energy processing (lower than twice, ) allows overcoming the potential low efficiency of the DCM operation since it keeps high enough the converter efficiency. The measured efficiency in the prototype is above the 80% for European input voltage range. Therefore, the proposed converter presents an overall good performance in the main parameters of single-stage PFC converters. APPENDIX No direct analytical expressions can be obtained for the mean magnitudes of the SII-B-2D converter. Therefore, the

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(7)

(10)

analysis of the converter (e.g., Figs. 8 and 9) and their design (e.g., Fig. 10) must be made by means of a Mathcad® calculus program. This appendix shows the main equations and structure of this calculus program. Input Data: • The operating conditions and the converter specifications: , peak value of the input voltage, , output voltage, output power, , and switching frequency

is

2) Power balance at line frequency: The value of obtained as numerical solution of (9)

(9) • Normalized design parameters: , transformer T1 turns ratio, , inductances ratio and dimensionless load parameter, , Output: • The storage capacitor voltage, , and the single pro. cessing ratio, • The line frequency law of variation for the duty cycle, , input current, , single processing power , double processing power , etc. • Rms currents and losses. STEPS for the Calculation of Main Converter Magnitudes:

3) Main magnitudes determination: Once numerical value of is obtained, the expression of becomes . The single processing energy ratio, , is given by (2). By , shown in Figs. 4 and averaging the current waveform 5 for Mode 2 and Mode 1, respectively, the average value of can be obtained [see (10) at the top of the page]. Taking into account the “volts second balance” of the inductances and , the normalized durations of each switching stage and (the normalized can be determined. Thus, duration of stages 2 and 3 in operating Mode 2, see Fig. 4), are given by (11) and (12). The normalized duration of Stage 2 of , is given by operating Mode 1,

1) Power balance at switching frequency: The analytical expression (7), shown at the top of the page, of the duty cycle variation with the line angle is obtained. It is important to highlight that the storage capacitor voltage ( ) has not yet been determined, so this value appears as a parameter. In addition, the input current ( ) can be determined as a function of the line angle and . This current is the average value of the switch current of the Flyback converter

(11)

(12) (13) REFERENCES

(8)

[1] IEC 61000-3-2: 2005-11 Third Edition, EMC Part 3-2: “Limits for Har16 A per monic Current Emissions (Equipment input current Phase)”.


[2] O. García, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Power factor correction: A survey,” in Proc IEEE Power Electronics Specialists Conf. (PESC 01),, Vancouver, BC, Canada, 2001, pp. 8–13. [3] C. Qiao and K. M. Smedley, “A topology survey of single-stage power factor corrector with a Boost type input-current-shaper,” IEEE Trans. Power Electron., vol. 16, no. 3, pp. 360–368, May 2001. [4] O. García, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Simple AC/DC converters to meet IEC 1000-3-2,” in Proc. IEEE Applied Power Electronics Conf. (APEC 00), New Orleans, LA, 2000, pp. 487–493. [5] N. Vázquez, C. Hernández, R. Cano, J. Antonio, E. Rodriguez, and J. Arau, “An efficient single-switch voltage regulator,” in Proc. IEEE Power Electronics Specialists Conf. (PESC 00), Galway, Ireland, 2000, pp. 811–816. [6] Q. Zhao, J. Qian, and F. C. Lee, “Single-stage parallel power factor correction AC/DC converters with inherent load current feedback,” in Proc. IEEE Applied Power Electronics Conf. (APEC 02), Dallas, TX, 2002, pp. 270–276. [7] J. Sebastián, M. M. Hernando, P. Villegas, J. Díaz, and A. Fontán, “Input current shaper based on the series connection of a voltage source and a loss free resistor,” in Proc. IEEE Applied Power Electronics Conf. (APEC 98), Anaheim, CA, 1998, pp. 461–467. [8] L. Huber and M. M. Jovanovic, “Single-stage, single switch, isolated power supply technique with input current shaping and fast outputvoltage regulation for universal input-voltage-range applications,” in Proc. IEEE Applied Power Electronics Conf. (APEC 97), Atlanta, GA, 1997, pp. 272–280. [9] M. Daniele, P. Jain, and G. Jóos, “A single stage single switch power factor corrected AC/DC converter,” in Proc. IEEE International Telecommunications Energy Conf. (INTELEC 96), Boston, MA, 1996, pp. 216–222. [10] F. Tsai, P. Markowski, and E. Whitcomb, “Off-line Flyback converter with input harmonic correction,” in Proc. IEEE International Telecommunications Energy Conf. (INTELEC 96), Boston, MA, 1996, pp. 120–124. [11] J. J. Spangler, “A power factor corrected, MOSFET, multiple output, Flyback switching supply,” in Proc. 10th Int. Power Conversion International Conf. (PCI), Chicago, IL, 1985, pp. 19–32 . [12] A. Lázaro, A. Barrado, M. Sanz, V. Salas, and E. Olías, “500 W class-D single-stage power supply,” in Proc. IEEE Power Electronics Specialists Conf., Recife, Brazil, Jun. 12, 2005, pp. 554–559. [13] J. Zhang, M. M. Jovanovic, and F. C. Lee, “Comparison between CCM single-stage and two-stage Boost PFC converters,” in Proc. IEEE Applied Power Electronics Conf. (APEC 99), Dallas, TX, 1999, pp. 335–341. [14] A. Lázaro, A. Barrado, J. Pleite, R. Vázquez, and E. Olías, “New family of single-stage PFC converters with series inductance interval,” in Proc. IEEE Power Electronics Specialists Conf. (PESC 02), Cairns, Australia, 2002, pp. 1357–1362. [15] M. M. Jovanovic and D. E. Crow, “Merits and limitations of full-bridge rectifier with LC filter in meeting IEC 1000-3-2 harmonic-limit specifications,” IEEE Trans. Ind. Appl., vol. 33, no. 2, pp. 551–557, Mar.-Apr. 1997. [16] C. K. Tse and M. H. Chow, “A theoretical examination of the circuit requirements of power factor correction,” in Proc. IEEE Power Electronics Specialists Conf. (PESC 98), Fukuoka, Japan, 1998, pp. 1415–1421. [17] R. Redl and L. Balogh, “Design considerations for single-stage power factor corrected power supplies with fast regulation of the output voltage,” in Proceedings of IEEE Applied Power Electronics Conf. (APEC 95), Dallas, TX, 1995, pp. 454–458. [18] A. Lázaro, A. Barrado, J. Pleite, R. Vazquez, J. Vázquez, and E. Olías, “Size and cost reduction of the storage capacitor in AC/DC converters under hold-up time requirements,” in Proc. Electronics Specialists Conf. (PESC 03), Acapulco, México, 2003, pp. 1959–1964. [19] A. Lázaro, A. Barrado, J. Pleite, J. Vázquez, and E. Olías, “Size and cost reduction of the energy-storage capacitors,” in Proc. IEEE Applied Power Electronics Conf. (APEC 04), Anaheim, CA, 2004, pp. 723–729. [20] ——, “New approach of average modeling and control for AC/DC power supplies which operates with variable duty cycle,” in Proc. IEEE Power Electronics Specialists Conf. (PESC 04), Aachen, Germany, Jun. 2004, pp. 652–658.

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Antonio Lázaro (A’97–M’03) was born in Madrid, Spain, in 1968. He received the M.Sc. degree in electrical engineering from the Universidad Politécnica de Madrid, in 1995. He received the Ph.D. degree in electronic engineering from the Universidad Carlos III de Madrid in 2003. He has been an Assistant Professor of the Universidad Carlos III de Madrid since 1995. He has been involved in power electronics since 1994, participating in more than ten research and development projects and he has published nearly 40 papers in IEEE conferences. His research interest is switching mode power supplies, power factor correction, modeling of dc-dc and ac-dc converters, and low-voltage fast transient response dc/dc converters.

Andrés Barrado (M’02) was born in Badajoz, Spain, in 1968. He received the M.Sc. degree in electrical engineering from the Universidad Politécnica de Madrid, Madrid, Spain, in 1994 and the Ph.D. degree from the University Carlos III of Madrid in 2000. Since 1994, he has been an Associate Professor at the University Carlos III of Madrid. His research interests is focus in switching-mode power supplies, multiple output DC-DC converters, modeling of dc-dc and ac-dc converters, low-voltage fast transient response dc-dc converters, EMC, ballasts, and high power factor rectifiers.

Marina Sanz (M’05) was born in Burgos, Spain, in 1973. She received the M.Sc. and Ph.D. degrees in electrical engineering from the Universidad Politécnica de Madrid, Madrid, Spain, in 1997 and 2004, respectively. Since 2001, she has been an Assistant Professor with the Electronic Department, Universidad Carlos III de Madrid. Her main research interests include switching-mode power supplies, modeling and design of piezoelectric transformers, and engineering education. Dr. Sanz is member of the IEEE Power Electronics Society.

Vicente Salas (S’01–A’04–M’06) received the M.Sc. degree in physics from the Complutense University of Madrid, Madrid, Spain, in 1996 and Ph.D. degree in electrical, electronic, and automatic engineering from the University Carlos III of Madrid in 2005. Since 1999, he is with the Power Electronics Systems Group, University Carlos III of Madrid. His research interests are maximum power point trackers, hybrid power systems, photovoltaic energy, and switching-mode power supply.

Emilio Olías received the M.D. and Ph.D degrees in industrial engineering from Universidad Politécnica de Madrid, Madrid, Spain, in 1981 and 1983, respectively. Since 1996, he is Professor in the Department of Electronic Technology in the Universidad Carlos III de Madrid, heading the Power Electronics Systems Group and collaborating with power electronics companies in different subjects around research projects, financed by private and public founds. He is working on power electronics (dc-dc converters with new topologies, control strategies, and power factor correction), alternative energy systems (photovoltaic and hybrid systems), and electromagnetic compatibility. At the Universidad Carlos III de Madrid, he is Staff Member of the EPS (“Escuela Politécnica Superior,” High Polytechnic School). Dr. Olías was named First Vice-Dean in 2000. He is interested in computer-aided design tools applied to the design and analysis of power systems operating in low and medium frequency