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Nonplanar InGaAs Gate Wrapped Around Field-Effect Transistors Fei Xue, Member, IEEE, Aiting Jiang, Yen-Ting Chen, Yanzhen Wang, Fei Zhou, Yao-Feng Chang, and Jack Lee, Fellow, IEEE Abstract— Nonplanar In0.53 Ga0.47 As gate wrap around fieldeffect transistors (GWAFETs) with atomic-layer deposited high-k dielectric and metal gate have been demonstrated in this paper. By applying novel device structure and optimizing fabrication process, In0.53 Ga0.47 As GWAFETs exhibit significant performance improvements over planar MOSFETs on both current drive capability and electrostatics control. In0.53 Ga0.47 As GWAFETs with fin width (W fin ) 40–200 nm have been fabricated. Devices with narrower W fin exhibit higher drive current, transconductance, and better short channel effect control, which demonstrates the scalability of nonplanar In0.53 Ga0.47 As GWAFETs. Subthreshold swing of 80 mV/decade and draininduced barrier lowering of 20 mV/V have been achieved by 40-nm W fin and 140-nm L g In0.53 Ga0.47 As GWAFETs. Index Terms— Gate wrapped around (GWA), InGaAs, MOSFETs, nanowire, nonplanar, scalability.
I. I NTRODUCTION
A
S MOSFETS continue scaling down for low-power logic applications, nonplanar multigated field-effect transistors (FETs) have been brought out to overcome the electrostatics control issues [1], [2]. To achieve the ultimate gate electrode control, great efforts have been devoted to investigate nanowire and gate wrap around FETs (GWAFETs) or gate all around FETs devices [3]–[7]. Nanowires can be constructed using bottom-up synthesis method where various materials can be used, however, with huge manufacture challenges [8], [9], or they can be built using top-down machining approach. Here, we fabricated the lateral In0.53 Ga0.47 As GWAFETs using the top-down method, that is, the devices were patterned by e-beam lithography and nanowires were constructed using dry and wet etching process. The GWA structure was applied to higher electron mobility III–V material to achieve a combination of improved subthreshold characteristics and higher current drive capability [10]. Many works on III–V multigated FETs and GWAFETs have shown promising results, including better short channel effect (SCE) control and increased integration density [11]–[15]. However, several challenges remain, such as current degradation from quantum
Manuscript received August 6, 2013; revised April 24, 2014; accepted April 25, 2014. Date of publication May 8, 2014; date of current version June 17, 2014. This work was supported by the National Science Foundation. The review of this paper was arranged by Editor K. J. Chen. The authors are with the Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX 78758 USA (e-mail:
[email protected];
[email protected];
[email protected];
[email protected]; essenonvidare@ gmail.com;
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2320946
effect, leakage current, high-k/III–V interface quality, external contact resistance, and fabrication difficulties. In this paper, In0.53Ga0.47 As GWAFETs with atomic-layer deposited (ALD) Al2 O3 and TiN metal gate have been demonstrated to outperform trigate and planar devices. High performance was achieved by: 1) improved device layout design, which limits undercut during wet etch process of the underlying InP layer; 2) optimized fin etching process by applying digital wet etch to achieve smooth sidewalls of the In0.53Ga0.47 As channels; and 3) high-quality Al2 O3 /TiN gatestack results from in situ plasma enhanced ALD process. The ON -state and OFF -state device performances of In0.53 Ga0.47 As GWAFETs were compared with planar InGaAs channel devices with 10- and 5-nm-thick channel. Improvement on electrostatic control was clearly observed. Major degradation components include quantum confinement effect, interface traps at high-k/InGaAs, and contact resistance. II. E XPERIMENT A. Device Structure The layer structure of In0.53 Ga0.47 As GWAFET device, grown by MBE on the semi-insulating InP substrate, consists of 500-nm InP buffer layer, 50-nm In0.53Ga0.47 As channel layer, 1-nm InP barrier layer, and 20-nm In0.53Ga0.47 As cap layer. All these layers were designed to be undoped, except for the top In0.53 Ga0.47 As layer, which is a heavily N-doped (Si 3e19 cm−3 ) layer intended for source/drain (S/D) contact. Fig. 1 shows the device layer structure of In0.53Ga0.47 As GWAFET with the channel wrapped around by ALD Al2 O3 /TiN gate. InP was chosen as the buffer layer to enable selective wet etch between In0.53Ga0.47 As and InP for releasing the In0.53Ga0.47 As fin structure. The addition of 1-nm InP barrier layer performs as a wet etch stop layer at gate recess and it also separates the high-k dielectric/III–V interface from In0.53Ga0.47 As channel, therefore, the effective channel mobility is improved due to reduced carrier scattering. B. Fabrication Process The key fabrication steps are shown in Fig. 2. The III–V substrate was first cleaned by diluted HF and protected by a 10-nm ALD Al2 O3 cap layer, followed by mesa isolation etching. Gate recess was done using citric acid-based wet etch to remove the n+ layer. Wet etch stopped at InP barrier layer. Fins were then patterned by e-beam lithography using diluted ZEP520A as photo resist. Fin dry etching was done by CH4 /H2 inductively coupled plasma (ICP) using SiO2 as
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XUE et al.: NONPLANAR InGaAs GWAFETs
Fig. 1. Layer structure and top view of In0.53 Ga0.47 As GWAFETs with ALD Al2 O3 /TiN GWA.
Fig. 2.
Key processes of In0.53 Ga0.47 As GWAFETs fabrication.
hard mask, which is one of the key processes of nanowire channel construction. Here, the dry etch was done in cycles to reduce surface roughness and to better control etching rate. A digital wet etch of In0.53 Ga0.47 As was carried out by soaking samples in H2 O2 and H2 SO4 separately for a certain time to enable fully chemical reaction [16]. Three cycles was used and around 5-nm In0.53 Ga0.47 As was removed on each side. This step is believed to reduce the surface roughness significantly after dry etch. InP buffer layer underneath channel was then removed by diluted HCl solution. InP wet etching is highly anisotropic; it etches fast along [010] direction, but stops along [110] direction. If pattern the fins along [110] direction, InP underneath can hardly be removed. While pattern the fins along [010] direction, both InP underneath the fins and InP under S/D region would be etched away quickly. This would leave a large undercut at S/D. Thus, here fins were designed to be 45° aligned with S/D edge (Fig. 3). Fins are patterned in such a way that InP buffer underneath fins was
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Fig. 3. Improved In0.53 Ga0.47 As GWAFETs device layout design to enable fast etch under the fin and limit undercut in S/D region. (a) Fins pattern along [110] direction: InP buffer wet etch stopped under the fins. (b) Fins pattern along [010] direction: InP buffer layer both underneath fins and at S/D was etched fast. (c) Fins patterned 45° to [110]: InP buffer was etched under the fins but stopped at S/D edge. (d) Top view of In0.53 Ga0.47 As GWAFETs with fins wrapped around by ALD of Al2 O3 and TiN.
etched in a fast rate without creating a large undercut in S/D area. In this way, precise time control of wet etching can be eased. In practice, the 45° alignment might not be needed if a new etching chemistry with high selectivity can be developed. Alternatively, the etching can be performed using time control. By using this approach, leakage current from broken fins is reduced, fins are more robust and the device yield is improved. After fin construction, SiO2 hard mask was removed by buffered oxide etch (BOE) and the sample was dipped in (NH4 )2 S for surface passivation. The 7-nm ALD Al2 O3 with equivalent oxide thickness of 3.6 nm was deposited, followed by 60-nm plasma enhanced ALD TiN in the same chamber to wrap around the channel. TaN was then reactively sputtered on top to reduce the gate resistance. Gate was then defined by CF4 RIE using Ni as the hard mask. Fig. 3(d) shows the SEM image of InGaAs GWAFETs with fins wrapped around by ALD of Al2 O3 and TiN. Finally, S/D contacts were formed by removing gate oxide by BOE dip and e-beam evaporation of Pd/Ge/Ti/Pd 20-nm/40-nm/10-nm/ 40-nm metal stack. Rapid thermal annealing at 320 °C for 90 s was carried out to form the alloy. The S/D metal to gate distance is 1 μm. Devices with Wfin from 40 to 200 nm, the gate length of 140 and 280 nm, and various numbers of parallel channels were fabricated. III. R ESULTS AND D ISCUSSION Fig. 4 shows the transfer characteristics of a typical In0.53Ga0.47 As GWAFET with Wfin = 40 nm, L g = 140 nm, and seven parallel channels. Drive currents are normalized to the perimeter of InGaAs channels Wtot = (2Wfin + 2Hfin ) × (No. of channels). The gate leakage is lower than 10−5 μA/μm in the voltage range. The ON / OFF current ratio of this device is around 4 × 104 at Vd = 1 V. The OFF-current is at 2 × 10−3 μA/μm level at Vg = −0.2 V and Vds = 0.5 V. The OFF-current is limited by the bulk leakage current. The threshold voltage of L g = 140 nm and Wfin = 40 nm device
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Fig. 6. Log(Id ) versus Vg of In0.53 Ga0.47 As GWAFET with fin width 40 nm, 60 nm, 100 nm and gate length 140 nm at Vds = 0.05 V. Fig. 4. Transfer characteristics of In0.53 Ga0.47 As GWAFET with fin width 40 nm and gate length 140 nm at Vds = 0.05 V and 0.5 V.
Fig. 7. Extrinsic transconductance of In0.53 Ga0.47 As GWAFET with fin width 40, 60, and 100 nm and gate length 140 nm at Vds = 0.5 V.
Fig. 5. Output characteristics of In0.53 Ga0.47 As GWAFET with fin width 40 nm and gate length 140 nm at Vgs from 0 V to 1.4 V at 0.2 V step.
is 0.23 V, which is extracted by the linear extrapolation of the maximum transconductance. When increase the drain voltage from 0.5 to 1 V, the drive current increase around 22.5% at Vg = 1 V. This indicates that external resistance is a strong factor that limits the drive current. The output characteristics of the same device are shown in Fig. 5 and this device delivers Id of 613 μA/μm at Vd = 1 V and Vg –Vth = 1 V. The contact resistance was extracted using gate length dependence to be ∼930 · μm. This high contact resistance may be due to the InP barrier layer at S/D regions and spreading resistance from S/D to channel. The metal contact to n+ InGaAs layer resistance is ∼200 ·μm. The sheet resistance of n+ InGaAs is low (
