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Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric Hyun-Seop Kim, Sang-Woo Han, Won-Ho Jang, Chun-Hyung Cho, Kwang-Seok Seo, Jungwoo Oh, and Ho-Young Cha, Member, IEEE Abstract — We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal–insulator–semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12 MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ∼2 V, an ON-resistance of 7.85 m · cm2 , and a breakdown voltage of ∼640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1 × 1012 cm−2 · eV−1 at Ec − Et = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics. Index Terms — Gallium nitride (GaN), normally-off, plasma enhanced chemical vapor deposition (PECVD), silicon oxynitride (SiON).
I. I NTRODUCTION ALLIUM nitride (GaN) has been widely studied as a next-generation material for high-power and highfrequency applications due to wide bandgap, high breakdown field, and high electron mobility [1], [2]. AlGaN/GaN heterostructure field-effect transistors (HFETs) have a high concentration 2-dimensional electron gas (2DEG) channel without any intentional doping because of their strong polarization effects [3]. Such high channel carrier concentration, however, makes it difficult to deplete the channel with zero gate bias to achieve ‘normally-off’ operation. A typical device configuration to achieve the normally-off operation is a recessed metal-insulator-semiconductor FET (MISFET) where great care must be taken of the MIS gate process. Various gate dielectric materials have been studied for GaN MISFETs, such as SiO2 [4], [5], SiNx [6], [7], Al2 O3 [8]–[12], HfO2 [13], ZrO2 [14], etc. Each material has advantages and disadvantages. For examples, SiO2 is an attractive gate
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Manuscript received June 14, 2017; accepted June 24, 2017. Date of publication June 27, 2017; date of current version July 24, 2017. This work was supported by NRF of Korea under Grant 2015R1A6A1A03031833, Grant 2012M3A7B4035274, and Grant 2016R1D1A1B03935445. The review of this letter was arranged by Editor T. Palacios. (Corresponding author: Ho-Young Cha.) H.-S. Kim, S.-W. Han, W.-H. Jang, and H.-Y. Cha are with the School of Electronic and Electrical Engineering, Hongik University, Seoul 04066, South Korea (e-mail:
[email protected]). C.-H. Cho is with the Department of Electronic and Electrical Engineering, Hongik University, Sejong 30016, South Korea. K.-S. Seo is with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea. J. Oh is with the School of Integrated Technology, Yonsei University, Incheon 21983, South Korea. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2017.2720719
dielectric material for GaN because of its large bandgap energy and conduction band offset (Ec ∼3.6 eV) [4], [15] but has a relatively lower dielectric constant (εr = 3.9) and weak durability. On the other hand, SiNx that has been widely used as a passivation layer for GaN electronic devices has a higher dielectric constant (εr ∼7) but a lower conduction band offset from GaN (Ec ∼2.4 eV) [15]. As a tradeoff approach, silicon oxynitride (SiON) would be an alternative candidate to take good properties from both SiO2 and SiNx . In addition, it was reported that SiON can prevent impurity penetration, enhance reliability, and reduce hot electron induced degradation in comparison with SiO2 [16]. The feasibility of SiON has been proven for the passivation layer of AlGaN/GaN HEMTs and the gate dielectric for AlInN/AlN/GaN HFETs [17]–[19]. However, there is no report on SiON as a gate dielectric for AlGaN/GaN recessed MISFET. In this work, we have optimized a SiON deposition process using a plasma enhanced chemical vapor deposition system (PECVD) for use in normally-off AlGaN/GaN-on-Si recessed MISFET fabrication. II. O PTIMIZATION OF S ILICON OXYNITRIDE SiON films were deposited on Si wafers using a PECVD system with SiH4 (5%)/N2 , N2 O, and NH3 mixtures as reactant gases to optimize the film quality. The chuck temperature during film deposition process was fixed at 350°C. The reactant gas flow rate, RF power, and chamber pressure were varied to optimize the deposition conditions where the breakdown field and refractive index were monitored. As summarized in Table I, the refractive index increased with SiH4 (5%) and NH3 flow rates and decreased with N2 O flow rate. A breakdown field of 12 MV/cm with a refractive index of 1.58 was achieved with an RF power of 100 W, a chamber pressure of 500 mTorr, and gas flow rates of SiH4 (5%)/N2 O/NH3 (= 50/25/25 sccm). The relative dielectric constant was 5.3. III. D EVICE FABRICATION AND C HARACTERISTICS The epitaxial structure consisted of a 9.9 nm in-situ SiNx passivation layer, a 3.7 nm GaN cap, a 22 nm Al0.25 Ga0.75 N barrier, a 490 nm i-GaN layer, and a 4.4 μm GaN buffer on a Si (111) substrate. The 2DEG mobility and sheet carrier concentration extracted by the van der Pauw hall measurements were 1470 cm2 /V·s and 9 × 1012 cm−2 , respectively. The device fabrication started with solvent cleaning. The ohmic contact regions were patterned and partially recessed using Cl2 /BCl3 plasma etching prior to Ti/Al/Ni/Au (= 20/120/25/50 nm) evaporation [20]. A rapid thermal
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KIM et al.: NORMALLY-OFF GaN-ON-Si MISFET USING PECVD SiON GATE DIELECTRIC
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TABLE I SiON P ROPERTIES AS F UNCTIONS OF D EPOSITION C ONDITIONS
annealing was carried out at 820°C for 30 sec in nitrogen ambient. A Cl2 /BCl3 -based inductively coupled plasma reactive ion etch (ICP-RIE) was used for MESA isolation. The contact and sheet resistances were 1.4 · mm and 465 /sq, respectively. The gate recess was performed carefully using a low-damage Cl2 /BCl3 -based ICP-RIE process [4] during which the AlGaN barrier layer was completely removed to ensure normallyoff operation. The recess depth was 36 nm from GaN cap surface. A 33 nm PECVD SiON film was deposited as a gate dielectric layer using the optimized process conditions. The surface cleaning prior to SiON deposition was performed using diluted HF (10:1) for 1 min, which rarely attacked the in-situ SiNx layer. The gate with an overhang length of 1 μm was formed by Mo/Au (= 20/200 nm) evaporation. Finally, post-metallization annealing was carried out at 400°C for 10 min in forming gas (N2 :H2 = 95:5) ambient in order to improve the interface condition. The source-to-gate distance, gate length, gate-to-drain distance, and gate width were 3, 2, 12, and 100 μm, respectively. Fig. 1(a) shows the crosssectional schematic of a fabricated AlGaN/GaN-on-Si recessed MISFET. The forward and reverse leakage characteristics of the SiON-on-recessed GaN MIS gate are shown in Fig. 1(b). The forward breakdown field was ∼8 MV/cm and the reverse leakage current density was < 10−9 A/mm at a reverse bias voltage of 100 V. It is suggested that the relatively lower forward breakdown field of SiON-on-GaN compared to the optimized SiON-on-Si was mainly attributed to the smaller conduction band offset from GaN. The transfer and output characteristics of the fabricated device are shown in Fig. 1(c) and (d), respectively. Negligible hysteresis was observed with very low gate leakage current (∼10−9 A/mm). It is suggested that the relatively higher off-state drain leakage current in Fig. 1(c) was associated with the leakage components through buffer and mesa isolation surface. The specific on-resistance extracted at
Fig. 1. (a) Cross-sectional schematic of GaN-on-Si MISFET, (b) forward and reverse leakage characteristics of MIS gate, (c) transfer characteristics, (d) output characteristics, (e) off-state breakdown characteristics, and (f) field-effect mobility of MIS channel as a function of transverse electric field.
Vds = 1 V was 7.85 m · cm2 taking account of the intrinsic channel region between source and drain. The portion of the contact resistances in the specific on-resistance was ∼6% and thus the specific on-resistance can be further improved by optimizing the ohmic contact process. The threshold voltage was ∼2 V, which was extracted by linear extrapolation of the transfer characteristics measured with Vds = 0.1 V. Typical breakdown characteristics are shown in Fig. 1(e), which were measured with Vgs = 0 V using Tektronix 370A curve tracer. The looping characteristics are typically observed in curve tracer measurements. The breakdown voltages defined at 1 μA/mm and 100 μA/mm were ∼640 V and ∼900 V, respectively. The field-effect mobility was extracted using a long channel FET with a gate length of 100 μm [21]. The maximum mobility value was 124 cm2 /V·s, as shown in Fig. 1(f). In Table II, the DC characteristics are compared with those reported recently with various gate dielectrics of fullyrecessed GaN MISFETs. Although this prototype device does not exhibit the state-of-the-art characteristics, the feasibility of SiON has been clearly validated. The capacitance-voltage (C-V) characteristics were measured for a recessed circular MIS device illustrated in Fig. 2(a) where the diameter of the inner recessed region was 30 μm and the outer overhang length was 10 μm. The C-V characteristics measured at 1 MHz are shown in Fig. 2(b) in which the higher level corresponds to the overall recessed MIS capacitance whereas the lower level corresponds to the overhang region capacitance. The overhang region capacitance was confirmed by C-V measurement for a non-recessed MIS pattern. The flatband voltage extracted by a second derivative method [26] was 1.1 V (see Fig. 2(c)) from which the derived interface
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TABLE II P ERFORMANCE C OMPARISON W ITH VARIOUS G ATE D IELECTRICS
Fig. 3. (a) Pulsed output characteristics, (b) dynamic on-resistance characteristics, (c) gate bias step stress sequence, and (d) threshold voltage changes during gate bias stress tests.
Fig. 2. (a) Cross-sectional schematic of a recessed MIS device, (b) capacitance-voltage (C-V) characteristics at 1 MHz, (c) flat-band voltage extracted by a second derivative method, (d) frequency dependent conductance and (e) parallel conductance characteristics, and (f) extracted interface trap density characteristics.
charge density was −5.3 × 1011 cm−2 . The interface trap density was extracted by a conductance method [27] where the frequency dependent conductance characteristics were derived from the C-V characteristics measured at a frequency range from 1 kHz to 1 MHz (see Fig. 2(d) and (e)). The extracted interface trap density characteristics are plotted in Fig. 2(f). The overhang region capacitance was excluded for more accurate estimation although it did not make significant difference. The interface trap density was 1 × 1012 cm−2 · eV−1 at Ec – Et = 0.442 eV. Various electrical measurements were carried out to investigate the trapping effects. Firstly, the current collapse phenomenon was examined by pulsed measurements with different quiescent drain bias voltages. The pulse width was 200 ns with a period of 1 ms. As shown in Fig. 3(a), excellent pulse characteristics were achieved even without an additional field plate. Secondly, the dynamic switching characteristics were investigated up to Vdd = 200 V under hard switching
operation [28]. The measurement frequency was 10 kHz with a 50% duty cycle. As plotted in Fig. 3(b), the dynamic on-resistance was increased by (Ron /Static Ron ) = 1.43 at 200 V operation, which validated the feasibility of SiON as an alternative gate dielectric for GaN MISFET although further improvement must be made in the future by careful process optimization. Lastly, high temperature gate bias stress tests [29] were performed to investigate the threshold voltage instability. The stress tests were carried out at room temperature, 100°C, and 150°C. The step stress sequence is shown in Fig. 3(c) and the measured threshold voltage changes are plotted in Fig. 3(d). Although the initial threshold voltage was negatively shifted at 150°C, the threshold voltage change as a function of stress voltage and time was independent of stress temperature conditions, suggesting that the threshold voltage drift was not accelerated by increasing temperature. A threshold voltage change of ∼0.5 V was observed after 10 V gate bias stress regardless of temperature conditions. Since the electron channel is formed right at the MIS interface without AlGaN barrier, the electron trapping at the MIS interface and SiON bulk region during stress cannot be suppressed and thus is responsible for the threshold voltage instability. It is suggested that such an instability issue can be mitigated by careful process optimization to further reduce the interface trap density and/or employing a partially-recessed MIS structure in which a thin AlGaN barrier exists between SiON and GaN. IV. C ONCLUSION We have developed a SiON deposition process using a PECVD system for the gate dielectric of normally-off GaN-on-Si MISFET. The fabricated device with the gate-todrain distance of 12 μm exhibited a threshold voltage of ∼2 V, a gate leakage current density of the order of 10−9 A/mm, a specific on-resistance of 7.85 m · cm2 , and an off-state breakdown voltage of ∼640 V at the off-state current density of 1 μA/mm. It is suggested that PECVD SiON is a great candidate for the gate dielectric of GaN based MISFETs although the dynamic on-resistance and reliability issues must be improved further in the future.
KIM et al.: NORMALLY-OFF GaN-ON-Si MISFET USING PECVD SiON GATE DIELECTRIC
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