Novel GAA Si Nanowire p-MOSFETs with Excellent ... - IEEE Xplore

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2018.2807389, IEEE Electron Device Letters

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Novel GAA Si Nanowire p-MOSFETs with Excellent Short Channel Effect Immunity via an Advanced Forming Process Qingzhu Zhang, Huaxiang Yin, Lingkuan Meng, Jiaxin Yao, Junjie Li, Guilei Wang, Yudong li, Zhenhua Wu, Wenjuan Xiong, Hong Yang, Hailing Tu, Junfeng Li, Chao Zhao, Wenwu Wang and Tianchun Ye.  Abstract—In this paper, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional HKMG FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels such as circular and inverted droplet were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with Lg = 16 nm demonstrate superb SCE immunity characteristics, with SS = 61.86 mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than circular NWs of similar geometric size. Index Terms—Gate-All-Around (GAA), Silicon NW, short channel effects (SCEs), drain induced barrier lowing (DIBL), sub-threshold swing (SS), Oxidation, H2 baking. I.

INTRODUCTION

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ecently, to develop advanced CMOS technology beyond the 5nm node, GAA NWs or stack NWs MOSFETs have attracted increasing interest because of their exceptional channel control ability and their excellent process compatibility with the existing high-k/metal gate (HKMG) FinFET technology in mass production [1-4]. The reported approaches to fabricate single or stack NWs based on mainstream FinFET process includes two key steps, i.e., first forming fins on multi-layer Si/SiGe epitaxy substrate; second, releasing nanowire channels in RMG by selective removing SiGe stacks [2,5]. The latest report on nano-sheet transistors also presented a similar method forming its channels [6]. However, these This work was supported by “02 National Key Project of Science and Technology” (2017ZX02315001) and “National Key Research and Development Program of China” (2016YFA0202304, 2016YFA0301701). Q. Zhang is with the Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China, and also with State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 100088, China. H. Yin, J. Yao, Yu. Li, C. Zhao and T. Ye are with the Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China, and also with University of Chinese Academy of Sciences, 100049 Beijing, China. L. Meng, J. Li, Z. Wu, H. Yang, W. Xiong are with the Institute of Microelectronics, ChineseAcademy of Sciences, Beijing 100029, China. H. Tu is with State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 100088, China. (e-mail: [email protected]; [email protected]; ).

Fig. 1. (a) Process flow of GAA NW p-MOSFETs with totally isolated channels in RMG, (b) the schematic of isolated GAA device, (c) and (d) TEM images of GAA NW device cut across AA’ and BB’ directions.

methods commonly require an extremely sophisticated multi-layer Si/SiGe epitaxy process with nearly defect-free film quality. In addition, this process also should be integrated with a low-temp (~700 ºC) STI & source drain (SD) annealing process to suppress the process or contamination issues of Ge-atom out-diffusions. Therefore, the optimizations to large process windows and good device performance are challenging for manufacture technologies. In this paper, the p-type GAA NW MOSFETs with a channel epitaxy-free approach to fabricate the totally isolated channel in RMG process was reported for the first time. The process was fundamentally based on the previously reported FOI FinFET [7]. On bulk-Si, the polygonal fins isolated to the substrate were formed with advanced etch technology, and then the fins were transformed into the NWs in the RMG module using two special forming approaches. Both the etch process of fin notch technology and the NW channel forming processes were explored in detail. Two profiles of NWs with circlar and inverted droplet shape were produced, and the devices with Lg = 16 nm demonstrate strong SCE immunity abilities. II. EXPERIMENTAL PROCEDURE The p-type fully isolated GAA NW MOSFETs using popular RMG process were fabricated on 200-mm bulk-Si (100) wafers; the process integration flow was schematically shown in Fig. 1(a). A schematic of the isolated GAA device is shown in Fig. 1(b). The NW was formed only in the gate, and the fin at SD remains in original profile, which is helpful for the reduction in SD series and contact resistances. The size of the NW in the channel is smaller than fins at the SD area, and the device is totally isolated to substrate by a thick bottom oxide.

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2 III. RESULTS AND DISCUSSION

Fig. 2. (a) Round GAA NW formation by H2 baking, (b) inverted droplet NW formation by oxidation, (c) NBD results for NW channel and (d) ID-VG curves of 16nm-Lg fully isolated GAA NW p-MOSFETs.

The proposed fabrication process flow of the GAA NW devices was evolved from conventional bulk FinFET. Therefore, it shows excellent process compatibility with advanced FinFET mass production. First, the small fin structures were patterned using self-aligned spacer image transfer (SIT) technology, followed by special fin notches formed on both sides via advanced etch technologies [8-10]. A linear oxidation process was conducted to totally isolate the upper fins from the bottom substrate. Because of the isolated structure, a punch through stop (PTS) doping process necessary in bulk FinFET was omitted. The processes for the fin STI and amorphous-Si dummy gate formation are similar to those of a conventional FinFET. After the formation of 20 nm spacers, the SD was formed by implantation (BF2+, 5keV, 30°and 2E15) and activation (1050 ºC spike) without an SD epitaxy process. The dummy gate planarization and removal processes were performed after deposition of a Si3N4 protective film by LPCVD. In the opened gate trenches, two methods, namely, oxidation and H2 baking processes for NWs diameter-shrinking and channel-rounding, were performed after releasing fin tails using dilute HF solution. In the oxidation method, a 5 nm rapid thermal oxidation (RTO) process was performed by mixed O2/H2 vapor at 950 ºC for 30s and the formed oxide requires another removal process. In another method, H2 baking was conducted in a reduced pressure ASME 2000 plus RPCVD chamber (20 mT, 850 ºC) for 120 s. These high-temperature processes also recover and improve the quality of interface greatly for the formed NW channels. Multi-layer HKMGs via an all ALD process and SD metal-contact processes for device formation were performed in subsequent steps. The FOI FinFETs were fabricated for devices comparison. The electrical characterization was performed using an Agilent 4156C semiconductor parameter analyzer. In addition to the experiment, simulations using physics-based quantum mechanical models and traditional Sentarus TCAD ware also conducted [11].

The cross-sectional TEM image along the NW channel is shown in Fig. 1(c) (cut across AA’). A small Si NW is formed only in the gate, and the fin at SD remains in original profile. The minimum physical Lgs of 16.2 nm for the fabricated GAA devices are obtained, matching the requirements of the future scaled devices. Fig. 1(d) shows the final TEM image of the GAA NW profile in the channel (cut across BB’). The NW is well surrounded by conformal ALD multi-layer HKMG stacks, and the geometric size of Si NW in channel is greatly reduced. In addition, the isolation thickness of the NW channels from the sub-fin parasitic channel is more than 20 nm, which is also useful for suppressing channel leakage and restraining the parasitic conductance of device under sub-threshold region. The final fabricated NWs profiles by these two methods are shown in Figs. 2 (a) and (b). Both of the isolated Si NWs have smooth surfaces, and the total areas of two NWs are similar. The NWs are well surrounded by multi-layer HKMG stacks. However, the formed NW channel via H2 baking is close to the ideal circular profile, whereas via oxidation is similar to an inverted droplet. Compared with the TEM results of the reported FOI FinFET [7], there is only approximately 12.3% reduction in the effective width for the GAA devices, but the effective area of GAA NWs for gate control is only half of that of the fin in the FOI FinFET. In other words, the formed GAA device has a stronger gate control capability compared with the FOI FinFET. Fig. 2 (c) shows a nanobeam diffraction (NBD) pattern of NW channel, revealing the clear orthorhombic phase of the Si lattice. The results indicate the perfect Si crystal remaining in the channel after a series etch and rounding processes. The optimal transfer curves of 16-nm-Lg p-type NW devices formed by oxidation and H2 baking are shown in Fig. 2 (d). The data is normalized according to the measured size from the TEM images in Figs. 2 (a) and (b). Superb sub-threshold parameters, such as DIBL = 6.5mV/V, SS = 61.86 mV/dec for the oxidation-proposed NW transistor and DIBL = 3.5mV/V, SS= 62.5mV/dec for the H2-baking proposed NW transistor are achieved. These results are approaching the limits (0mV/V and 60mV/dec) of ideal devices, indicating that the novel fully isolated GAA NW transistors via the demonstrated process have very strong gate control ability on the channel electrostatic potential. It also achieves a >108 ION/IOFF ratio (IOFF is defined as drain current at Vg = Vt + 0.4V) for the droplet NW. The achieved excellent SCE characteristics are due to the totally isolated GAA structure on the NW-shaped channel offoring the best gate control. The suppression of parasitic sub-fin leakage beneath the isolated NW channel and the perfect Si crystal quality in NW channel, as well as the improved interface around released NW channel due to the novel integration flow, are the other reasons for these excellent characteristics. Alternatively, without any silicide process and with long SD contact distances, the fabricated GAA NW devices demonstrate large SD parasitic resistance resulting in the poor driving current (ION~106 μA/μm while at VG = VDD = 0.8 V), which may also contribute to the obtained superb SCE characteristics. The mean values of Vts, DIBLs and SSs vs. different Lgs for a number of droplet, round profile NWs and FOI FinFETs are



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Fig. 3. Variation of Vts, DIBLs and SSs as a function of Lgs for a number of devices with droplet, round shape NWs and FOI FinFETs.

shown in Fig.3. Compared with the FOI FinFET, great values reductions in values for Vt roll-offs, DIBLs and SSs were obtained for two kinds of NW devices indicating superior short channel effect immunity for the novel fabricated GAA devices. The droplet NW device exhibits a reduced Vt-sat roll-off from the values of Vt-sat roll-off from 90 mV to 10 mV compared with the values of the round NW devices, and the values is over 160 mV for FOI FinFET (shown in Fig. 3 (a)). Similar slightly smaller degradations of DIBLs and SSs were also achieved for the droplet NW compared with those of the round NW device, and this trend is more obvious as Lgs decreases. It indicates that both of the formed NW devices have great advantages for improved SCE immunities, and with the droplet NW having slightly better SCEs control than that of the round NW device at similar geometric size. The achieved excellent SCE characteristics are attributed to the totally isolated structure on the GAA NW-shaped channel. The suppression of parasitic sub-fin leakage beneath the isolated NW channel and the perfect Si crystal quality in NW channel, as well as the improved interface around released NW channel due to the novel integration flow, are the other reasons for the excellent characteristics. Moreover, the designed underlapped structure for the SDE doping process and a large SD parasitic resistance may also contribute to the excellent characteristics. Fig. 4 (a) shows the experimental and simulated results of the transfer curves for a 16-nm-Lg NW formed via oxidation, where the corresponding profile (cut across AA’) after RTO process is shown in the insert. The results demonstrate the RTO process cause ~10 nm diffusion lengths in channel direction compared with the original SDE. Fig. 4 (b) shows the calculated results of the charge density distribution maps for droplet and round profile NWs via a physics-based quantum mechanical model [11-12]; and geometric sizes of NWs are defined according to the fabricated NWs devices. The larger charge density distribution at the on-state forms a uniform torus for circular NW, and that in a droplet NW is also distributed at sharp corner, besides a torus area. For both NW devices, the charge density mapping area at the off-state is primarily

Fig. 4. (a) simulated and experimental ID-VG curves, (b) calculated on-states and off-states charge density by quantum physical model, (c) simulated SS vs. RTA time for different profiles of NW devices and (d) schematic of the doping redistribution during the RTO process.

distributed at the center of the channel. However, the charge density in the droplet NW is apparently slightly smaller than that in a conventional circle NW channel; this result is caused by stronger gate control at the bottom sides for the droplet NW. For further illustration of two different profiles of NWs, the simulated variations of SS and the moving distance of diffused B and P atoms vs. different annealing times are shown Fig. 4 (c). The values of SSs for the droplet NW are slightly smaller than those of the circular NW, implying a slightly better gate control for the droplet NW device. The diffused distance for P atoms is a little longer than B atoms, which exhibits some limitations and needs optimization for advanced technology node. Conversely, the sharp corners at bottom sides of droplet NWs perhaps lead to the degradations of HKMG TDDB leakage characteristics. In addition to the NW shape effect, the process advantage of the RTO process is also illustrated in Fig. 4 (d). As P atoms are squeezed into the Si NW and B atoms are pushed into the oxide during oxidation process, the NW channel would achieve a higher P atoms concentration. Most of the diffused B atoms in channel direction are removed after the removal of the formed oxide, containing a massive amount of diffused B atoms. Therefore, this behavior may restrain SCEs and achieve better DIBL and SS parameters for p-type GAA NW devices compared with NW devices formed via H2 baking. IV. CONCLUSION In conclusion, two new approaches to fabricate totally isolated GAA NW p-MOSFETs fully compatible with conventional HKMG FinFET flow were reported. The new process provides not only a high-quality NW channel profile but also high quality charge conductance. The fabricated devices demonstrate super SCE immunity approaching the ideal limit. The proposed approaches would provide useful methods for CMOS scaling beyond FinFET technology.



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