NP-hard Module Rotation Problems - Semantic Scholar

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Yamada and Lin [YAMA88], Libeskind-Hadas and Liu [LIBE89], and Chong and ... Chong and Sahni [CHON92] show that ETLF is linearly solvable for the case ...
NP-hard Module Rotation Problems

Keumog Ahn University of Minnesota

and

Sartaj Sahni* University of Florida

University of Florida TR 92-24 Abstract

Preplaced circuit modules may be rotated to improve performance and/or routability. We show that several simple versions of the module rotation problem are NP-hard.

Keywords and Phrases

Module rotation, circuit performance, routability

__________________ * Research supported, in part, by the National Science Foundation under grant MIP-9103379 and in part by an award from AT&T Bell Laboratories.

1

2 1 Introduction

The performance and routability of a circuit are affected by flipping and/or rotating the circuit modules while keeping the placement fixed. One may formulate several performance and/or routability measures that are based on estimates of wire length. In these estimates, the length of a wire is estimated either by the Euclidean distance between the wire end points or by the Manhattan distance. The developments of this chapter use the Manhattan Metric. Let ETL denote the estimated total wire length and let MEL denote the maximum estimated wire length (i.e., length of the longest wire).

The problems of minimizing ETL and MEL by flipping modules have been studied by Yamada and Lin [YAMA88], Libeskind-Hadas and Liu [LIBE89], and Chong and Sahni [CHON91 and 92]. All of these start with a preplaced circuit. It is assumed that modules may be flipped about their horizontal and/or vertical axes. Hence, there are four possible orientations of a module under flipping (Figure 1). The initial or reference orientation is denoted by φ, h, v, and b, respectively, denote the orientation that results from flipping about the horizontal axis, vertical axis, and both axes. For rotation, rotations of 0, 90, 180, and 270 degrees are permitted and it is assumed that these rotations do not result in module overlaps.

_______________________________________________________________________________

vertical axis

v (x,y)

(x,y) (xc ,yc )

b (x,y)

horizontal axis h (x,y)

______________________________________________________________________________________

Figure 1 φ, h, v, b

3 Let ETLF (ETLR) denote the problem of flipping (rotating) modules so as to minimize the estimated total wire length. In both [YAMA88] and [LIBE89], the Euclidean distance between wire end points is used to estimate wire length. Both ETLF and ETLR are shown to be NP-hard in [LIBE89]. The proofs of [LIBE89] are easily modified for the case when wire length is estimated using the Manhattan distance between the wire end points. Further, the proof for ETLF holds even if flips are restricted to be made along only the vertical (horizontal) axis. Yamada and Liu [YAMA88] propose an analytical method to obtain suboptimal solutions for ETLF. This algorithm is shown (experimentally) to be competitive with hill-climbing and simulated annealing algorithms for ETLF. In [LIBE89], Libeskind-Hadas and Liu propose neural network formulations for ETLF and ETLR.

Chong and Sahni [CHON92] show that ETLF is linearly solvable for the case when the modules are arranged as a matrix in which wires connect only pairs of modules that are in adjacent columns. They also show that ETLF is polynomially solvable for standard cell designs in which wires connect modules in adjacent columns and either the number of module columns is two or the number of modules dependent on any other module is bounded by some constant. Chong and Sahni [CHON92] also evaluate a simple greedy heuristic that attempts to minimize ETL by flipping modules. Experimental results reported by them indicate this heuristic is superior to the neural network approach of [LIBE89].

The problem of minimizing the maximum estimated wire length was studied by Chong and Sahni [CHON91]. They considered two versions of the problem MEL4 and MEL2. In MEL4 each module is permitted four orientations as in Figure 1. In MEL2, only two these four orientations are permitted. Chong and Sahni showed that MEL4 is NP-hard even for a single row or column of modules. They developed polynomial time algorithms for restricted versions of MEL4 and obtained an O (nlogn) algorithm for MEL2.

In [AHN92], we obtained the following results for module orientation problems: 1. The MaxDelay problem is that of reorienting the modules so that the length of the longest signal flow path is minimized. We showed that MaxDelay is NP-hard when only horizontal flips, only vertical flips, both horizontal and vertical flips, are permitted. This is so even for single column or single row instances with equal size modules.

4 2. The ETLF problem is NP-hard for a single column of equal size modules even when only vertical flips are permitted. Note that he ETLF proof of [LIBE89] uses modules of two different sizes. While most of these are placed in a single row arrangement, two modules are stacked into a column. So, their construction does not apply to the case of single row instances with equal size modules and flips restricted to horizontal ones (this would be symmetric to single column, equal size modules, vertical flips only). So, our ETLF proof applies to even simpler module layouts than does the proof of [LIBE89]. 3. Single column ETLF can be solved in linear time when only horizontal flips are permitted. 4. For the ETLF problem, algorithms to obtain optimal solutions for layouts that follow a module matrix model as well as for standard cell layouts are developed. 5. A heuristic for the MaxDelay problem is proposed and evaluated experimentally.

In this paper we consider only module rotations. The following NP-hard results are obtained: 1. The MaxDelay problem is NP-hard for single column and single row instances with equal size modules even when only rotations are permitted. 2. The ETLR problem is NP-hard for a single column or row of equal size modules even when only 0° and 90° rotations are permitted. Note that the ETLR proof of [LIBE89] comes close to having three rows of modules. However, modules of different size are used. Our proof applies to the simpler layout of equal size modules into a single row or single column.

2 NP-hard Results

To prove our NP-hard results, we use the following problem that is known to be NP-hard: NE3SAT problem [GARE79] Input: A Boolean function I = C 1 , C 2 , ..., Cm in n variables x 1 , x 2 , ..., xn . Each clause Ci is the disjunction of exactly three literals. Output: "Yes" iff there is a truth assignment for the n variables such that in each clause Ci at least one literal evaluates to true and at least one to false (i.e., all three literals do not have the same truth value). "No" otherwise.

5 Theorem 1: MaxDelay is NP-hard for a single column of equal sized modules when modules may be rotated but not flipped. Proof: Let I be an m clause n variable instance of NE3SAT. We shall construct a 2n module sigle column instance, R, of MaxDelay such that R has an orientation with maximum delay at most d iff I has answer ’yes’. Each module of R has dimensions s × s where s=2m +4n (Figure 2). Each ___ ___ module has 2m +1 pins on each of its four corners. The 2m modules are labeled M 1 , M 1 , M 2 , M 2 , ...

and are stacked one on top of the other as in Figure 3. There are 2n input pins to the circuit and 2n output pins. The input pins are the top of the circuit and the output pins at the bottom. Some of the 8m +4 pins on a module are input pins, some are output pins, and some are not used. No pin will have more than one wire connected to it. The vertical distance between the circuit input and output pins is L. We assume that the signal delay along a wire equals the Manhattan distance between its two end points and the delay between an input and output pin of a module is s regardless of the distance between these two pins.

_______________________________________________________________________________ 12

m

12

m

1´ 2´

1´ 2´





1 2 m

1 2 m 1´2´ m´

1´2´ m´

______________________________________________________________________________________

Figure 2 A module for Theorem 1

__

__

Module Mi denotes literal xi while Mi denotes xi . As drawn in Figure 3, each module represents the condition when its corresponding literal is true. If a module Mi is rotated counterclockwise 90°, then its corresponding literal is interpreted to be false. A counterclockwise rota__

tion of 180° or 270° corresponds to an invalid truth assignment for xi . Similarly, if Mi is rotated __

__

clockwise by 90°, xi is false. If it is rotated 180° or 270°, xi has an invalid truth assignment.

6

_______________________________________________________________________________ 1 2 m +n +1/2

input pins

2n

2n −1

m +n +1/2

M1

__ M1 L M2

__ Mn

1 2

output pins

2n

______________________________________________________________________________________

Figure 3 Single column module stack

When the modules of Figure 3 and the circuit input/output pins are connected by wires, paths between the input and output pins of the circuit will be defined. The signal delay along these paths will depend on the orientation of the modules on the paths. An optimal orientation is one which results in the maximum input pin to output pin delay being minimum. The wires we shall now define will have the property that an optimal orientation of the modules will have maximum delay < L +3s −2n +2 iff the answer to I is ’yes’. First, input pin 2i −1 is connected to the top right corner pin of Mi and input pin 2i is con__

nected to the top left corner pin of Mi , 1≤i≤n. Also the bottom left corner pin of Mi is connected to __

the output pin 2i −1 and the bottom right output pin of Mi connected to output pin 2i, 1≤i≤n (Figure 4(a)). The wires are drawn as directed edges so as to define the direction of signal flow. Signal enters a module through an input pin and leaves through an output pin. As remarked earlier, the signal delay in going from a module input pin to a module output pin is s. We assume that each

7 input pin (defined so far) of a module is connected to each of its output pins. There are two circuit input-to-output paths in Figure 4(a). One is from input pin 2i −1 to output pin 2i −1; the other between

input

and

output

pins

2i.

The

delay

of

the

first

is

L +(m +n +1/2+2n −(2i −1))+(m +n +1/2+(2i −2)) = L +s. The delay of the second path is also L +s.

_______________________________________________________________________________ 2i −1 2i

2i −1 2i

A

B Mi

Mi

D a

C b

__ Mi

__ Mi

d

c

2i −1 2i

2i −1 2i

(a)

(b) Consistency wires included

______________________________________________________________________________________

Figure 4 Input output pin connections

__

In Figure 4(b), we have added two wires between modules Mi and Mi . This has been done to __

__

ensure a consistent truth assignment to xi and xi (i.e., one in which exactly one of xi and xi is true and the other is false). As can be seen, these wires also use corner pins. In the module orientation __

of Figure 4(b), both xi and xi are true. The path (2i −1), B, A, d, c, 2i has delay L +(m +n +1/2+2n −(2i −1))+s +s +(m +n +1/2+2n −2i) = L +3s +2n −4i +2 ≥ L +3s −2n +2. One may

verify that the remaining paths in Figure 4(b) have a delay no more than that of this path. __

The maximum delay can be reduced by rotating either Mi counterclockwise 90° or Mi __

clockwise 90°. In the first case (Figure 5(a)) we have xi false and xi true while in the second, we __

have xi true and xi false. In Figure 5(a), the paths with maximum delay are (2i −1), B, C, b, c, 2i and (2i −1), B, A, d, c, 2i. Both have delay L +(m +n +1/2+2i −2)+s +(m +n +1/2+2n −2i) = L +2s +1.

8 In Figure 5(b), the paths (2i −1), B, A, d, c, 2i and (2i −1), B, C, b, c, 2i have maximum delay. This delay is also L +(m +n +1/2+2n −(2i −1))+s +(m +n +1/2+2i −1) = L +2s +1. One may verify that any __

other orientation of Mi or Mi results in a maximum delay ≥ L +3s −2n +2. (Note that L +3s −2n +2 = L +2s +1+(2m +4n −2n +1) > L +2s +1.)

_______________________________________________________________________________

B A

Mi

a

C

A

D

D

b

d

__ Mi

d

B Mi

C a

__ Mi

c

c

b

__

(a) Mi rotated 90° counterclockwise

(b) Mi rotated 90° clockwise

______________________________________________________________________________________

Figure 5 Rotating a module

Next, we introduce three wires for each of the clauses of I. Consider clause Ci . Suppose that Ci = (xu +xv +xw ) and u