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Optimized Pad Design for Millimeter-Wave. Applications with a 65nm CMOS RF Technology. Sofiane Aloui1, Eric Kerhervé1, Jean Baptiste Bégueret1, Robert ...
Proceedings of the 39th European Microwave Conference

Optimized Pad Design for Millimeter-Wave Applications with a 65nm CMOS RF Technology Sofiane Aloui 1, Eric Kerhervé 1, Jean Baptiste Bégueret 1, Robert Plana 2, Didier Bélot 3 1

IMS laboratory, UMR CNRS 5218, University of Bordeaux 33405 Talence Cedex, France [email protected] [email protected] 2

LAAS-CNRS, University of Toulouse, France [email protected]

3

STMicroelectronics, Central R&D 1, Crolles, France [email protected]

Abstract— Millimeter-wave pads based on a 65nm CMOS technology from STMicroelectronics have been designed and measured. A pad was optimized to minimize losses caused by a ground shield and by the conductive substrate. Modelling techniques and special cares to design a millimeter pad with a minimum of effects are highlighted. The goal is to integrate this pad in active devices such as a power amplifier (PA) or a low noise amplifier (LNA). The frequency response shows that the intrinsic capacitance of an optimum pad does not exceed 17fF at 60GHz. The aimed application is the unlicensed band around 60GHz suitable for Wireless Personal Area Network application (WPAN).

Most of today’s pads realizations try to minimize the intrinsic capacitance, usually composed by the top metals (M6/M7/Alucap) and the bottom metals (M1/M2) [3]. The main motivation of this design is the reduction of the conductive substrate coupling and the improvement of the quality factor. This technique is still inefficient. It suffers from capacitive coupling losses, because of the low thickness of the Back End of Line (BAEL) in the emerging CMOS technology process. The second method is the realization of a deep trench, which consists of etching a deep groove in a silicon substrate corresponding substantially to the shape of the desired groove. The deep is inversely proportional to the capacitance value. I. INTRODUCTION Other approach consists in adding a shunt transmission line Moore’s law became known as a limit of integration, it stub to resonate with the pad capacitance, is presented in [4]. trends to reduce the exploitation’s time of a typical technology. Design trade-offs in millimeter wave are discussed in this Indeed, the transit time from a 0.35m to 65nm CMOS paper. Indeed, the capacitance of the pad is not the only technology is no more than 13 years. This fast development in parameter to be controlled at high frequencies and we propose semiconductor technologies gives new outlooks towards a simple modelling of the pad and interconnects, based on the higher frequencies. Millimeter-wave applications are Y-Z matrix equations. To validate this new modelling numerous with radar system automotive at 77GHz, and approach, pad simulations and measurements are compared up WPAN system operating at 60GHz. The requirement of the to 110GHz. Finally, an optimized Coplanar Wave Guide microelectronics designer is striving to reduce both die cost (CPW) pad is detailed. and die area. The main challenge is to maintain the RF II. HIGH FREQUENCIES PAD DESIGN performances .The 7GHz unlicensed band around 60GHz is dedicated to WPAN, in order to establish a wireless kioskA. Pad’s geometry download communication link with a high data rate (3 GB/s) All integrated circuits are immunized against all external [1]. The pad is one of the most important elements. It must be radiation by a nitride passivation layer. It reduces the field characterized since it represents the direct access to any circuit. leakage thanks to its high permittivity. However, a good Its behavior is critical especially at high frequencies. contact with circuit’s pad must be ensured, in order to retain Therefore, an effort of modelling and characterization is the RF probe. For this reason, a Copper Bondpad (CB2) which define an opening (mask) in final nitride passivation, is necessary. The technology associated to this work is the 65nmCMOS included in the process. The minimum opening of CB2 bulk (=20.cm) [2] from STMicroelectronics. This imposed by the founder is (44 m x 77 m). This constraint technology (7M-Alu) has a low relative permittivity (r~4) fixes the minimum pad’s size. Fig. 1 depicts an octagonal typical contact pad on different and a thickness of BAEL under 5m. It is important to note view. The top plate of the pad capacitance is formed by (M6that these characteristic parameters influence the capacitance M7-Alucap), the bottom plate, representing the solid metal of the pad. This dependence is less important in the emerging shield, is formed by (M1, M2). The pad pitch is 100 m. SiGe technologies because of their high back-end compared with CMOS technology.

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1 (1) ) /( 2S ˜ f ) y11 The capacitance remains constant if the ground pad accesses are not taken into account. In fact, the intrinsic inductors of the accesses are added to the effective capacitance of the pad. As a result, its value drops from 70fF to 30fF (more than 50%) in the 10 to 80 GHz range. C

(a)

(b)

im (

(c) Fig. 1.

Pad’s structure: sectional view (a) Top view (b) Bottom view (c)

B. ESD protection It is extremely important to pay off the ElectroStatic Discharge (ESD) protection circuit design. Hence, an ESD protection device is integrated in the pad to protect the internal circuit against ESD damages. The analog ESD circuit is drawn in Fig. 2. It is mounted as a power clamping device between VDD and the pad [4]. It forms a low impedance current discharging path during an ESD event. It has a transparent behavior during the normal operation of the circuit as a high impedance parallel circuit to the pad.

Fig. 2.

Fig. 3. Simulated pad’s capacitance, with and without accesses.

A LC model of the pad is more realistic. In order to take into account the dielectric and metallic losses, (Rs_pad) and (Rp_pad) are added, as shown in the Fig. 4. The substrate capacitance and conductance are supposed stronger than the capacitance and resistance of the pad. Consequently, they are neglected.

Schematic of the clamping ESD protection

Typical ESD induces parasitic, especially at high frequency. It includes a RC delay and substrate noise coupling due to ESD capacitance. The total capacitance caused by the ESD routing is about 15fF. A parasitic and protection performances trade-off must be done. C. Pad’s model The previous pad is often used at low frequencies. Its own capacitance is easily characterized. Furthermore, growing in frequency induces other parameters that must be included in the design flow. The most critical parameter is the intrinsic inductive effect. Indeed, the inductive effect is present in almost all components: transmission lines return path current, interconnections and also in pads. Fig. 3 exhibits the capacitance simulation results extracted from (1):

Fig. 4.

Pad’s lumped LC model.

This model has the same behavior of a low pass filter with a resonance frequency f = 1/ (2. LC ). The goal of this work is to understand how each lumped element influences the frequency response of the pad. D. Pad design and measurements According to the pad model; both the intrinsic capacitance and inductance contribute to the resonance. In order to control separately the effect of each one, several pads were designed and measured. An Agilent E83612 vector network analyzer is used to measure S-parameters up to 110 GHz.

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1) Control of series elements: Two first pads were designed and measured with different pitches (100m and 150m). Different grounded-metal pad designs are also tested.

Pad's capacitance

150

Pad M6/M2(pitch = 150) Pad M6/M2(pitch = 100)

100 50

Traditionally, CPW lines are chosen due to higher obtainable characteristic impedance because of the additional degree of freedom which is the gap [6]. Microstrip topology is sometimes adopted to immunize face to the substrate losses. Nevertheless, it suffers from conductor losses in the return signal path. The choice depends on the desired application. In the case of the pad design, a CPW line respecting the pad dimensions (Fig. 6), i.e. (Wide, Gap) = (45um, 23um), was simulated with Ansoft HFSS electromagnetic simulator.

0 -50 20

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Frequency (GHz] Fig. 5. Pad resonance caused by series elements

Fig. 5 shows the resonance when the capacitance of the pads is null. The pad with 150m pitch resonates at 80 GHz, the second with 100m pitch shows a resonance at 100GHz. The resonance is directly related to the length of the access. The total reactance of the pad is still capacitive up to the resonance frequency. Beyond this frequency, the pad behaves as an inductor. 2) Control of the parallel elements The capacitance of the pad is directly related to its geometry and effective permittivity (eq. (2): S (2) C ] 0 .] r . e where:

]r

]  ]

]   j.

V

2.S . f .] 0

Fig. 6. shows that the coplanar mode is established. Indeed, the RF signal spreads over the M7 layer and the return current spreads over the adjacent ground plane. Hence, most of the electromagnetic fields are retrieved in the adjacent plane and just a small part of electromagnetic field penetrates the substrate. Consequently, the pad ground plane, usually used in the pad structure, will be taken out. III. OPTIMIZED PAD DESIGN In view of the aforementioned comments, a pad has been fabricated. The top metals consist in (M7, Alucap) exposed to the silicon substrate. There is no ESD protection. It can be substituted in the circuit by adding a stub in parallel connected to the ground. The contact between the two ground plots is ensured by the M2. The pitch adopted is 100 m. Fig.7 depicts the layout view of the realized pad.

(3)

and

]0 (

Fig. 6. Electric field distribution of a CPW pad

1 ).1010 : permittivity of free space, 36.S

] r : relative static permittivity, ]  : real part of ] r related to the stored energy, ] : imaginary part of ] r related to the dissipated energy. The capacitance value is proportional to the variation of the permittivity. This variation reflects the leakage current [5] in the substrate which is generally modeled by a conductance proportional to f. To obtain the minimum capacitance, the M7 layer is used as a top plate. However, it is more delicate concerning the bottom plate. We investigate if it is better to shield the substrate by a metal in a pad design. Thus, a transmission line theory is reminded. In fact, at high frequency, the design of CPW and MicroStrip (MS) lines are the two independent alternatives solutions. It is not possible to assert that MS/CPW is better than CPW/MS. Both exhibit pro and cons.

(a)

(b)

Fig. 7. Structure of the optimized pad : Sectional view(a) Top view (b)

A. Optimized Pad measurement The pad was measured and Fig. 8 demonstrates that the pad’s parasitic are dominated by the reactance and not by the conductance. The ratio between the reactance and the conductance, considered as the quality factor, can reach 17 at

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Im (Y11)

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Im, Re (Y11) [Ohm]

low frequencies. At higher frequencies, substrate losses increase more rapidly than the conductor losses, it explains how this ratio tends towards zero near the resonance (not seen in Fig.8). Thanks to this design, the pad keeps almost the same behaviour, from 20GHz to 100GHz.

ACKNOWLEDGMENT The authors would like to acknowledge the fabrication support provided by STMicroelectronics. The technical support for testing was provided by M. De Matos. The authors would also thank Conseil Régional Aquitaine for the support of NANOCOM test bench. REFERENCES [1]

[2]

0 100

[3]

Frequency [GHz] [4]

Fig. 8. Optimized pad capacitance, conductance, and quality factor.

Pad's capacitance [fF]

Fig. 9 shows the capacitance of the optimized pad. Its value is slightly lower than 20fF from 20GHz to 100 GHz. This low value does not mismatch the input/output. As an example, for the 60GHz application, the input is deviated from 50Ohm to (42-j*9): because of the pad. With the pad previously illustrated in Fig. 1, the input is drastically deviated to (15j*13) :, as a result the input and output matching becomes not convenient.

[5] [6]

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Frequency [GHz] Fig. 9. Optimized pad capacitance

IV. CONCLUSION Design techniques and modelling for millimeter-wave applications of a RF pad were discussed. Both traditional and optimized pads have been presented and measured. They have been fabricated using 65nm CMOS technology from STMicroelectronics. ESD protection is presented and trade-off between parasitic and protection performances is discussed. This work clearly demonstrates that the solid metal shield, usually present at radio frequency applications, reduces significantly the pad’s performances at high frequencies. For that, an optimized pad with a top plate exposed to the substrate is realised. Its capacitance is less than 20fF. This pad can be used in narrowband and distributed circuits due to the wide band frequency response.

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U.Pfeiffer, J. Grryb, D. Liu, B. Gaucher, T. Beukema, B. Floyd, and S.Reynolds, “A 60GHz Radio Chipset Fully-integrated in a Low-cost Packaging Technology”, Proceeding of ECTC, pp. 1343-1346, June 2006. F. Gianesello, D.Gloria, S. Montusclat, C. Raynaud, S. Boret, C. Clement, G. Dambrine, S. Lepilliet, F. Saguin, P.Scheer, Ph. Benech, J. M. Fournier,”65nm RFCMOS technologies with bulk and HG SOI substrate wave passives and circuits characterized up to 220 GHZ”, MTT Microwave Symposium, 2006, pp. 1927-1930 Low loss contact pad with tuned impedance for operation at millimeter wave frequencies. Pfeifer; T.J Watson, Signal propagation on interconnects2005; Mai2005; pp61-64 Ming-Dou Ker, Hsin-Chin Jiang, and Chyh-Yih Chang,“Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits,” IEEE, ASIC/SOC, pp. 293,296, 2000. Z. Albert, Z.H. Wang, On Chip ESD Protection For Integrated Circuits, Kluwer Academic Publishers, Boston/Dordrecht/London, 2002. S. Pruvost, Etude de faisabilité de circuits pour systemes de communication en bande millemetrique, en technologie BiCMOS SiGeC 0.13um” M. Eng. thesis, University of Lille 1, France, 2005. C.H.Doan, S. Emami, A.M. Niknejad, and R. W Brodersen, “Design of CMOS for 60GHz application,” ISSCC Digest of Technical Papers, , pp. 440-538, 2004