Optimizing performance of Dual Metal Gate Modified Source FDSOI using Symmetric and Asymmetric Oxide Spacers Abhishek Kumar Malviya, Student Member, IEEE
R. K. Chauhan, Associate Professor
Department of Electronics and Communication Engineering Madan Mohan Malaviya University of Technology Gorakhpur (Uttar Pradesh)-273010
[email protected]
Department of Electronics and Communication Engineering Madan Mohan Malaviya University of Technology Gorakhpur (Uttar Pradesh)-273010
[email protected]
Abstract—This Paper is focused on improving the ON current and reducing the OFF current with the use of different types of the high-k spacer. Some spacers provide better ON current and some provide lower OFF current (leakage current). Lowering of leakage current can also be controlled by use of high-K BOX (buried oxide layer). In this paper, we used Tio2, Hfo2, Si3N4 and Sio2 at 50 nm gate length Modified Source DMG FDSOI structure. All simulation part has been done on Silvaco tool.
oxide spacer structure [11]. His paper introduced a new way to tackle the problems. Vimal et al. described MS FDSOI in detail [12]-[13]. Sandeep et al. explained different device parameters variation with work function [14]-[16]. By looking over these papers we tried to replace the gate oxide with two different dielectrics in symmetric and asymmetric manner. In this paper, we have used 50 nm gate length MS DMG FDSOI device. It helped in improving the On-state and Off-State current ratio in comparison to previous MS DMG FDSOI [14]. The device structure is discussed in section 2 and comparative study will be in section 3, followed by the conclusion, result, and references.
Keywords—ON current, OFF leakage current, DMG FDSOI, High-k, silvaco.
I. INTRODUCTION By looking at ITRS roadmap [1] we can comprehend how much device scaling has been done and with the help of Moore's low, we can foresee the upcoming node technologies [2]-[3]. Because of day by day scaling in the channel length, short channel effects(SCEs) like DIBL, GIBL, hot electron effect, Off-state leakage current, threshold voltage roll-off come into the picture. For proper operation of MOSFET current should be controlled properly and current is controlled by voltage. For better control over current, gate voltage should have good control over the channel. It is possible only when there is no SCEs like DIBL (Drain induced barrier lowering). To overcome these problems SOI technology came into the picture. Silicon on insulator (SOI) CMOS technology helped us a lot in improving the Off-state leakage currents and short channel effects [4]-[6]. As we reduce the size of the device, the width of dielectric become a critical feature. Due to scaling below 65nm fringing electric filed to become a more important factor for short channel effect [7]-[9]. Using high-k materials we can get less series resistance because of the fringing electric field and it kicks in the good On-state driving current. Some papers have a good idea to overcome with the SCEs. Ming-Wen Ma et al. discussed the effect of high-k dielectrics on 65-nm length SOI device [10]. His paper provides an idea of using the high-k spacer. S. C. Lin et al. proposed modeling of FDSOI on the Vth of with the sidewall
II. DEVICE STRUCTURE AND SPECIFICATION DMG MS FDSOI provides better control over the channel that results in a larger velocity of the electron in the channel. DMG also provide flattened electric field, due to this short channel effects reduces and transconductance improves. DMG Modified Source FDSOI proposed in 50 nm gate length with following device specifications as shown in Table 1: TABLE I. DEVICE SPECIFICATIONS OF DMG FD SOI N-MOSFET
Parameters
DMG MS FD-SOI
Gate length
50nm
Tox
1nm
Substrate doping
1e16 cm-3
Source region doping n+
1e20 cm-3
Source region doping n-
1e17 cm-3
Drain region doping
1e20 cm-3
Work function of Gate
4.77eV(M1)-4.1eV(M2)
Insulator thickness (BOX)
5nm
Gate voltage
1.1 volts
Silicon film thickness
12nm
Silicon Substrate
5nm
permittivity 50 and Hfo2 with permittivity 30. Different combinations are given below: • Oxide1=Hfo2 Oxide2=Hfo2 • Oxide1=Hfo2 Oxide2=Sio2 • Oxide1=Zro2 Oxide2=Zro2 • Oxide1=Hfo2 Oxide2=Sio2 Fig. 3 compare the On-state driving current on these different combinations of dielectric.
Fig. 1. DMG MS FDSOI with symmetric spacers
Here we can see the clear difference in the On-state driving current. In the first combination when we use the hfo2 as a total dielectric the ON current becomes significantly large enough at Vgs 1.1v. On another hand when we use Zro2 and Sio2 as a dielectric then the On-state current is quite similar to some extent. And other tow combinations give a less On-state drive current. But when we talk about the off-state leakage current then it is found that the Zro2 as dielectric gives lowest leakage current. It is due to the fringing electric field that reduces short channel effect and improves the device performance to a decent level. Ion to Ioff ratio was 0.43x1010. B. Asymmetrical oxide division In asymmetric distribution, we mainly tried to improve the Ion to Ioff current ratio to an acceptable value. And it happened when we used asymmetric dielectric combinations. We have listed two high-k dielectrics below: • Oxide1=Zro2 Oxide2=Hfo2 • Oxide1=Tio2 Oxide2=Hfo2
Apart from this we used spacers Tio2 (ɛ = 80), Zro2 (ɛ = 50), Hfo2 (ɛ = 30), Si3N4 (ɛ = 7.5), Sio2 (ɛ = 1.5) with few combinations of two at a time. In this way, we have used 10 combinations of the spacer. In one structure, we have replaced the BOX material with the Si3N4 dielectric material. This structure helps in reducing the leakage current by a large amount. Fig.1 shows the structural geometry of device with symmetrical spacers. In this oxide layer is separated from the mid of the device and in the Fig.2 oxide is separated from the contact of the drain. All simulation work has been done on Atlas Silvaco device simulator at 300K temperature [17].
1) 2) 3) 4)
0.002
Id(amp)
Fig. 2. DMG MS FDSOI with asymmetric spacers
As mentioned above permittivity of Tio2 is taken 80 and permittivity of Hfo2 is 30. Fig. 4 gives the clear picture that there is a huge improvement in the on-state current and it reaches to 2.3mA with the combination of Tio2 and Hfo2 high-k dielectrics. And it with the Zro2 and Hfo2 it was 2.2mA. If we look at the leakage current then it comes again with the same combination. And it reduces to the 55pA. Also, it helps in the increment of Ion to Ioff ratio. With this combination, Ion/Ioff ratio become 0.418x1010. With the Zro2 and Hfo2 pair it was 0.3x1010
Oxide1=Hfo2 Oxide2=Hfo2 Oxide1=Hfo2 Oxide2=Sio2 Oxide1=Zro2 Oxide2=Zro2 Oxide1=Hfo2 Oxide2=Sio2
0.001
III. RESULTS AND DISCUSSION A. Symmetrical oxide division In the symmetric division of spacer, we have compared the performance of device on drive current and on Off-state leakage current by two high-k dielectric Zro2 with
0.000
0.0
0.5
1.0
VGS(volt)
Fig. 3. Drain Current vs Gate Voltage Curve with different spacers.
C. Si3N4 as a BOX material This is an experiment towards enlarging On-state current and reducing the short channel effect as well reducing the off-state leakage current. In this direction, we have introduced Si3N4 as a BOX layer in the DMG MS FDSOI at the place of the conventional Sio2 oxide layer as shown in the Fig. 5. And it gives us 2.1mA as an on-state current and much reduced Off-state subthreshold current 24.6pA. This results in a comparatively very high Ion to Ioff ratio 0.88x1010. Subthreshold slope and threshold voltage for this structure is 65.8mV/decade, 0.49V respectively.
Fig. 4. Drain Current vs Gate Voltage Curve with Asymmetric
For the validation of result, we have used the result of previously published work [14]. In Fig. 6 comparisons is shown with the previous device drain current to our device drain current using Tio2 and Hfo2 as a dielectric and Si3N4 as a BOX drain current. Ion for Tio2 and Hfo2 is larger than the single oxide layer. As well as the Off-state current for Si3N4 as a BOX is 24pA that is lower than the conventional BOX current. IV. CONCLUSION With this comparative study, we found that the controllability of gate to the channel can be significantly enhanced by high-k gate spacers for short channel devices. Devices with the combination of dielectrics can improve Onstate current and Off-state leakage current. And we get a large Ion/Ioff current ratio with the high-k spacer as a BOX in compare to conventional SOI devices. So, the combination of high-k dielectric could be a better option for reducing short channel effects and improving Ion/Ioff ratio.
V. REFERENCES [1] [2] Fig. 5. Structure of DMG MS FDSOI with Si3N4 BOX Dielectrics
[3] [4]
[5]
[6] [7]
[8] Fig. 6. Comparison of Dain Current with Single Oxide Spacer, Double Oxide Spacer, and Si3N4 BOX Layer
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