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Optimum Design Considerations for a High Efficiency ZVS Full Bridge DC-DC Converter Xinke Wu, J.M Zhang, Zhaoming Qian College of Electrical Engineering, Zhejiang University, Hangzhou, China
[email protected],edu.cn Abstract: This paper focuses on the ZVS operation and design Considerations for a ZVS DC-DC full bridge converter. With the proposed circuit diagram the emciency can be improved comparing with a conventional phase shift lull bridge (PSFB),and tbe voltage ringing across the rectifler diodes can be reduced signiflcantly by clamp circuits. A I.ZkW(50V/24A) prototype with a efliciency of 95% is made to verify the theoretical analysis.
converters mentioned above. An improved PSFB converter as shown in Fig.1 was proposed in [12], which can solve these problems mentioned above by adding two auxiliary coupled inductors Llkl,Lur2and two clamp diodes Dcl ,Dc2, but the ZVS condition and the designing of the key parameter weren't given in [12]. This paper discusses the ZVS operation condition and the optimal design considerations to achieve high efficiency and full load range ZVS. The operation principle of the proposed converter will he given in the next section. The design consideration will be given in the third section.
I INTRODUCTION The phase shift ZVS full hridge(FB) converter is widely used in high power applications because of it's high power density, low E M , and simply control strategy''21. In a conventional PSFB converter, the leakage inductance or series inductance must be large enough to ensure the ZVS for the lagging leg switches"-". However a large series inductance will bring out large duty cycle loss and voltage ringing across the rectifier diodes. Some improvements have been proposed to reduce the duty cycle loss and suppress the diodes and a series inductor voltage r i n g i ~ ~ g " Two ~ ' ~ ~clamp . are added to extend ZVS range and relax the voltage ringing across the rectifier diodes".". But the duty loss is still large because of the large series inductor and it still can't achieve ZVS at very light load. Some converters utilizing the magnetizing current of transformePJor paralleled inductor, and other assistant current murcelg1to improvement ZVS for the switches of the lagging leg. With the assistant current source it can achieve ZVS without increasing duty loss if the leakage inductance of the transformer is small, and ZVS is independent of the input voltage. However if the series inductance or leakage inductance is very small, during the passive to active transition period, the reflected load current opposes the magnetizing current in the transformer and sinks the current from the assistant current source before the parasitic capacitor of MOSFET fully discharged or charged["]. Hence ZVS fails if the assistant current is not larger than the reflected load current at full load condition. To achieve ZVS at heavy load the magnitude of assistant current source must be higher than the reflected full load current, which results in high conduction loss especially in high power level. A family of FB converters, which can achieve ZVS from full load to no load by adding a series coupled inductor were proposed in [9,10]. However these converters suffer from the same drawbacks as of other current source assistant
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11 OPERATION PRWCIPLE OF THE PROPOSED CONVERTER
A . The Circuit Diagram of the Improved Converter AS shown in Fig.] the circuit consists of two half bridges with coupled primary windings. The two inductors Lrl, Lr2 I L, are coupled and two small auxiliary inductors L ~ and
Fig. I The circuit diagram ofthe improved ZVS PSFB D€-DC converter
Trp~ and Trp2 are the primary windings of the transformer with same turn count, and Trsl, Trs2 are =nl. L,, and Lr2 are coupled secondary windings. NTrpl:NTmI inductors with the same turns. Lkl and L, are small inductors in series of the transformer winding and LLLI=Lur2. To relax the voltage ringings across the output rectifier diodes two clamp diodes Dcl, Dc2 are added as shown in Fig.1. Because the inductor Lrl and Lr2 are coupled, the needed clamp diodes can be reduced to two. The two primary windings of the transformer are connected in opposite manner as shown in Fig.1. Therefore the current through the midpoint of transformer is the sum of two winding currents, and the primary side peak current control method can be employed. To simplify the analysis a large block capacitor is neglected, which is in series with the
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transformer winding in the experimental circuit to block the DC bias of the transformer. Due to the large inductance of Lo, the inductor Lo can be seen as a current souse Io.
input voltage during this interval by input voltage.
B. The Operation Stages in a HarfSwitching Cycle To simplify the analysis the parasitic capacitance of the transformer is replaced by the junction capacitor Col and CD2shownin Fig.1. Because the detailed analysis of every operation stages of half switching cycle has been discussed in [12], the stages are explained simply in this paper. Fig.2 is the key waveforms in one switching cycle and Fig.3 is the equivalent circuits of the corresponding stages.
1x2
0-
r,I ‘0
1 7 tl ‘2
‘3
‘4
tS
‘6
tl
I (d) Mode qt3-14)
Fig.2 The key waveforms ofthe converter in one switching cycle
Model(t&): Before the time bthe switches MI, M4 are on. The voltages across TTI and Tmzare both half of input voltage V i , the energy is transferred to the load. At to M4 turns off, due to the junction capacitance of M4 the voltage across M4 is almost clamped at zero, therefore switching off loss is reduced. During this interval the capacitors C,,, Cd are discharged and charged respectively until the voltage across Cd reaches V,. Mode2(1,-fz): During this interval the current l p 2 flows through the anti-paralleled diode of M3 when the voltage across C,, reaches zero. M3 is switched on when the anti-paralleled diode is on. The voltage across transformer is clamp at zero because the rectifier diodes both D1 and D2 are on. The coupled inductors L1and Lr2are charged by the
I
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I
I (0 Mode S(t4-6)
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I
The next half switching cycle is similar to the analysis mentioned above except the opposite polarity of the currents through the transformer windings and voltages across the transformer windings.
111 ANALYSIS AND OPTIMAL DESIGN CONSIDERATIONS
Trsl
A. The ZVS Range The leading leg ZVS range: To achieve the ZVS operation in overall load range of all switches the coupled inductors should be designed appropriately. The simplified equivalent circuits of the leading leg (M3,M4) and the lagging leg transitions(MI,M2) are shown in Fig.4 and Fig.5 respectively.
iFcdlD
TrsiI
(g) Mode 7(t6-17)
Fig.3 The swen equivalent circuits ofopention modes in half switching cycle
Made3(tTt3): At t2 MI is switched off, then the storage energy in Lnl,Lmand L,I,L,~will charge and discharge the capacitors C,I and Cs2respectively. This period ends when the capacitor C,I is charged fully until the drain to source voltage of M I reaches Vin. Mode4(13-14): At t3 the anti-paralleled diode of M2 is on because the voltage across Ce is discharged to zero. After t3, the M2 switches on and ZVS is achieved. Because the DI and D2 are still conducting and the voltage across the series and Lm are V d 2 . coupled inductors 41 ModeS(t4-15): When the current IDI of primary reaches the value -(lo/nl-Im) at t4, the diode DI cuts off. Then the capacitor CDlwill interact with the inductance Lrl and Lm. This period ends when the voltage across the capacitor Col reaches at 2Vin/(nl) while the voltages across the primary winding Trpl and Trp2 of the transformer reach Vin/2 respectively. Mode6(tS-t6): At tl the clamp diode Dc? conducts &er the voltage across the transformer winding reaches Vin/2. The transition of lagging leg switches is ffished. The current difference between the inductance Llkl and the current of the winding Trpl flows through the clamp diode. Owing to the clamping diode Dcl the voltage across diode Dlwill he clamped at 2Vidnl. This period ends when the clamping diode cuts off because the difference current decreases to zero. During this interval the energy is transferred tn the load. Mode7fl6-17): AAer the clamp diode cuts off, the current of the inductance Lrl will be equal to the current of the winding Trpl. During this interval the energy is still transferred to the load. This period ends at t7, when the switch M3 switches off.Then the next operation mode will be similar to mode 1.
I I I Fig.4 The leading leg Wansition equivalent circuit
Before the transition of the leading leg, the magnetizing current Im of the coupled inductor Lrl, and the currents Ipl and Ip2 can be described as equations (1)-(3). The current ripple of the filter inductor is considered in the current Ipl and lp2. Due to the large inductance of the inductor Lrl, the current Im can he seen as a current source during the transition periods of the leading leg and the lagging leg. 1 Vin.x(1 - D l I , =(1) 2 4 L r l x 2 x fs
+ ( I o l n l ) + AI042 *nl) I p l ( t o )= ( I o i n l )+ AIoI(2 * nl) - I,, I p l ( t O=) I ,
(2)
(3)
where D is the operation duty cycle of the converter, N o is the current ripple of the output current, and fs is the switching frequency, Io is the load current. ZVS switching for the leading leg switches is achieved easily because of the large filter inductance of Lo. At heavy load condition, it can he seen as a current source and the capacitor Cs is charged easily by this current source. Even at very light load, lo is almost zero and the current source Im still flows through the leading leg switches because of the large inductance of Lrl and Lr2. Therefore the parasitic capacitors of the MOSFETs will he fully charged linearly by the current source Im during the dead time between the leg switches. In fact when the load current is null the duty cycle will be very small, and the current source Im described in ( I ) will be much larger than the reflected load current. Therefore the most difficult ZVS condition is at critical continuous condition because the duty is still larger while the reflected load current is small. Hence to achieve ZVS for the leading leg switches at full load range, the inductance Lrl must match the equation (4).
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tdl Lo.nl where tdl is the dead time between the leading leg switches shown in Fig.2, and Dmax is the maximum duty cycle of the critical continuous mode of the output current. f i e lagging leg ZVS range: The ZVS operation condition of lagging leg switches is critical, and it determines the ZVS operation of the proposed converter. The currents and voltages of the key components during tl and t2 are presented in equations (S)-(8). Fig.5 shows the simplified equivalent circuits of the transition period of the lagging leg.
(b)CCM(lo/nl
