Packed U Cells Multilevel Converter Topology - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Packed U Cells Multilevel Converter Topology: Theoretical Study and Experimental Validation Youssef Ounejjar, Member, IEEE, Kamal Al-Haddad, Fellow, IEEE, and Luc-André Grégoire

Abstract—In this paper, authors propose a new power multilevel converter topology that is very competitive compared to the existing ones. It consists of packed U cells (PUC). Each U cell consists of an arrangement of two power switches and one capacitor. It offers high-energy conversion quality using a small number of capacitors and power devices and consequently, has a very low production cost. An averaged model of the topology is detailed. The operating principle of the transformerless seven-level inverter is analyzed and detailed. The multilevel sinusoidal modulation has been adapted for use with the PUC-based structure. The control strategy has been designed to reduce the harmonic contents of the load voltage. With such converters, filters’ rating is considerably reduced. A comparative study is performed to highlight the advantages of the new packed U cells topology. The operation of the proposed converter topology has been verified through simulation. Experimental validation was performed using DS1103 DSP of dSpace. Index Terms—DSP implementation, harmonics, multilevel converter topologies, power quality, unity power factor operation.

I. I NTRODUCTION

F

OR DECADES, renewable energy resources have been the focus for researchers, and different families of power converters have been designed to ease the integration of these types of systems into the distribution grid [1]. Nowadays, power conversion is a well-studied topic by academics and industries due to the power demand and the integration of power sources in the electrical grid or in stand-alone applications [2]. The domain of power conversion quality is subdivided into two broad classes. The first considers power converters as pollution emitters particularly in terms of harmonics and power factor. In this technology, research has been focused to improve the power quality by using additional hardware like active/hybrid filters [3]–[7]. This affects greatly the efficiency of power exchange and the cost of the installations. The aim of the second is to provide a low-cost nonpolluant converter with high energy efficiency. Multilevel converters belong to this technology. Multilevel power conversion technology is a very rapidly growing area of power electronics Manuscript received June 15, 2009; revised October 30, 2009, February 6, 2010, and March 19, 2010; accepted April 27, 2010. Date of publication June 1, 2010; date of current version March 11, 2011. This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC), by the Canada Research Chair in Electric Energy Conversion and Power Electronics, and by FQRNT of Quebec. The authors are with the Department of Electrical Engineering, École De Technologie Supérieure, Montréal, QC H3C 1K3, Canada (e-mail: [email protected]; [email protected]; luc-andre.gregoire.1@ ens.etsmtl.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2010.2050412

with high potential for further development. The most attractive applications of this technology are in the medium–high voltage ranges, and include the following: 1) motor drives; 2) photovoltaic systems; 3) power distribution; 4) power quality; and 5) power conditioning applications. Due to their ability to synthesize waveforms with a controlled harmonic spectrum and to attain higher voltages, and to overcome the limited semiconductor voltage and current ratings, multilevel inverters have been receiving increasing attention for the past few years [8]. By generating high voltage with low harmonic contents, while reducing switches’ stress, multilevel converters allow an effective high power exchange between multiple sources. Traditional multilevel converters like the following: 1) neutral point-clamped converters (NPC) proposed by Nabae et al. [9]; 2) flying capacitors converters (FCC) proposed by Meynard et al. [10]; 3) and classic cascaded H-bridges proposed by Peng et al. [11], present many drawbacks if the number of voltage levels is increased. In fact, the number of switches, diodes and capacitors grows excessively, resulting in prohibitive cost and their implementation becomes very complicated. Hybrid cascaded H-bridges topology [12] presents many advantages and typically, they use a small number of active and passive components. In the last few years, many propositions have been presented to improve their efficiency [13]–[27]. In this paper, the authors propose a novel multilevel competitive topology which offers high power quality using a small number of passive and active components. It can be classified as a compromise between the flying capacitor and the cascaded H-bridges topologies. A detailed comparative study of these converters is given to show the advantages and the effectiveness of the proposed schemes. The novel topology can be seen as asymmetric flying capacitors or packed U cells. Each U cell consists of two power switches and one capacitor as shown in Fig. 1(a). Simulation results and experimental validation are presented to confirm the advantages of the proposed concept. II. P RESENTATION OF THE P ROPOSED M ULTILEVEL T OPOLOGY The proposed topology is subdivided into many multilevel converters. Each one is characterized by the number of attainable voltage levels. Fig. 1(b) shows the transformerless single-phase seven-level inverter, Fig. 1(c) shows the sevenlevel rectifier, Fig. 1(d) shows the topology in the case of 31-level single-phase converter, whereas Fig. 1(e) presents the three- phase seven-level converter. The number of voltage levels across the line-to-line load voltage is 13. Moreover, the number

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OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY

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Fig. 1. Different converter schemes. (a) Single U cell. (b) Single-phase seven-level inverter. (c) Single-phase seven-level rectifier. (d) Single-phase 30 one-level inverter. (e) Three-phase seven-level inverter. TABLE I VOLTAGES VALUES OF DIFFERENT MULTILEVEL CONVERTERS OF THE PROPOSED TOPOLOGY

of voltage levels depends on the value of the voltage across the capacitors. To determine the values of voltages V2 , V3 , and V4 [of Fig. 1(d)], one can carry out a comparative analysis which is illustrated in Table I. In case of using two capacitors, the output voltage is therefore obtained from the following seven levels (V dc, 2.V dc/3, V dc/3, 0, −V dc/3, −2.V dc/3, −V dc). In or-

der to obtain these levels, the second capacitor voltage (V2 ) must be regulated to V 1/3. Classic multilevel converters, such as the Cascaded H-Bridge Converter, require many dc sources which may result in the use of an excessive number of transformers. In order to reduce these, a transformerless inverter configuration is proposed. However, like other transformerless inverters, it suffers from a common drawback manifested at low

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at medium frequency. The combination of two GTOs and four IGBTs in the seven-level PUC topology permits to achieve optimally designed and efficient high power conversion unit. III. O PERATION OF THE S EVEN -L EVEL PACKED U C ELLS C ONVERTER

Fig. 2. Output voltage and holding voltage of different Ti switches.

modulation indices, where auxiliary capacitors are not charged because they are never connected to the main dc bus. The number of the voltage levels of the proposed PUC topology is governed by a geometric progression of the following form: un = a.u(n−1) + b u0 = U.

(1)

The nth term can be written as follows: un = an U + b

1 − an . 1−a

(2)

Thus, Ni = 2N ci +1 − 1

(3)

where N ci is the number of used capacitors, Ni is the number of voltage levels, and i is an integer. By the same, the number of produced voltage levels Ni according to the number of power switches N swi is given by the following equation: Ni = 2

N swi 2

− 1.

(4)

When using four capacitors, the number of voltage levels will be N4 = 31. In this case, only ten power switches are required. Fig. 2 shows the holding voltage of T1 , T2 , and T3 switches for a seven-level converter with V 1 = 150 V and V 2 = 50 V, operating under sinusoidal modulation. The total converter ac voltage Vab is given by the following equation: Vab = Vaa1 − Va2a1 − Vba2 .

(5)

By observing Vaa1 , Va2a1 , and Vba2 , one can notice the potential of using a combination of two types of semiconductor devices technologies (GTO and IGBT) in this highpower conversion scheme. In fact, the major drawback of the GTO technology is its limited switching frequency; whereas, IGBT technology cannot sustain high power, while operating

Fig. 3 shows the scheme of the converter under study which makes use of two capacitors. The first one is the dc source V 1 which is generated from the ac supply network, and the second is V 2 which is regulated by the converter control circuit to the desired voltage level that is required to produce the exact number of voltage levels across the load. The proposed topology makes use of six semiconductor devices T1,2,3 and T1,2,3 . Each switch consists of a MOSFET with its antiparallel diode and has only two operating states. Since only three switches form one leg, then eight possible state combinations can be identified (Fig. 3). Two of the states are redundant and represent the zero voltage and the other six active states apply the appropriate voltage level across the load as seen in Table II. The sequence of the operation of the converter describing the eight possible states is therefore given in Fig. 3. As shown in this figure, the ac load is fed by seven-level V1 , V1 − V2 , V2 , 0, −V2 , V2 − V1 , and −V1 , single-phase topology. Moreover, for other applications, if required, a dc load can be placed across the capacitor. By subdividing the desired sinusoidal waveform into three positive and three negative zones as shown in Fig. 4, and using seven-level sinusoidal modulation, one can produce four rectangular signals with two values two or one for the three positive zones and −2 or −1 for the three negative ones; also, two rectangular signals with two values one or zero for the positive zone and zero or −1 for the negative zone. Summing these signals leads to a unique signal S having eight levels as shown in Fig. 5. The later shows the signal which synthesizes the desired output voltage. In this signal, the redundant states, which correspond to the null voltage, are identified for a better use of the switching devices. If the modulating frequency is not equal to a multiple of the fundamental frequency (60 Hz), then, there is an asymmetry in the resulting signal. Figs. 7 and 9 are obtained with a modulating frequency equal to 960 Hz. These levels correspond to the desired seven-level output voltages with the redundant null one. Thus, the use of a lookup switching table (Table II) allows the generation of the synthesized sevenlevel voltages as shown in Fig. 13(a). IV. C OMPARATIVE S TUDY OF THE P ROPOSED T OPOLOGY W ITH OTHER C OMPETITIVE M ULTILEVEL T OPOLOGIES A. Comparison Toward Neutral Point Diode Clamped NPC and Flying Capacitors Topologies This section of the paper presents a comparative study of the proposed topology with two other topologies that make use of NPC and flying capacitors configurations. However, one must take into account the additional drawback of NPC which uses additional clamping diodes that characterize the NPC topology.


Fig. 3.

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One cycle operating states of the proposed packed U cells seven-level topology.

TABLE II SWITCHING TABLE OF THE PROPOSED SEVEN-LEVEL CONVERTER

Fig. 5. Signal S waveform.

Fig. 4.

Seven-level sinusoidal modulation.

In a flying capacitor converter [e.g., the three-level shown in Fig. 6(a) and the four-level shown in Fig. 6(c)], the zero voltage is produced by the subtraction of the flying capacitor and the half of the dc bus voltages, because it cannot be produced otherwise. Based on the architecture of the three-level flying capacitors converter [Fig. 6(a)], two switching devices have been added in order to produce the zero-voltage level and to remove the dependence between the flying and the dc bus capacitors voltages resulting in the proposed seven-level converter topology

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Fig. 6. Converters schemes of the (a) three-level flying capacitors, (b) proposed seven-level, and (c) four-level flying capacitors.

as shown in Fig. 6(b). FC topology requires 12 switches and six capacitors; whereas, the proposed one generates the same voltage levels with 200% of cost reduction in terms of passive components and 100% in terms of active components. That is to say the number of semiconductors has been reduced from 12 to six, and the number of capacitors is reduced from six to two. Consequently, when compared with an FC converter, the U-cell topology might achieve smaller physical size thereby resulting in a very compact power conversion unit. The cost saving, in terms of the capacitors, depending on the desired number of levels in the output voltage is given by the following equation: gc = (N − log2 (N + 1)) × pc

(6)

where, “pc” is the price of one capacitor and N is the desired number of levels in the output voltage (e.g., N = 7 means seven-level converter). gc is the number of saved capacitors log2 (x) =

log(x) . log(2)

(7)

This cost can be expressed in percent by gc (in%) = 100 ×

N − log2 (N + 1) . log2 (N + 1) − 1

(8)

Fig. 7(a) shows the evolution of the cost saving in terms of the capacitors in percent depending on the desired number of voltage levels. The power semiconductor devices saving depending on the desired number of levels in the output voltage is given by equation gsw = (2 × (N − 1 − log2 (N + 1))) .

(9)

The number of voltage levels according to the number of capacitors of a flying capacitors converter is given by N = Nc + 1.

(10)

From equations (3) and (10), we deduce the power quality gain in terms of voltage level surplus which is given by gq = 2N c+1 − Nc − 2.

(11)

Fig. 7. Benefits of the PUC compared to FC topology. (a) Cost saving in (%) in terms of capacitors according to the number of voltage levels. (b) Power quality gain in (%) in terms of voltage levels according to the number of capacitors.

For the same number of capacitors, the use of the proposed topology against flying capacitors one improves the number of levels in the output voltage by g1 = 100 ×

2N c+1 − Nc − 2 %. Nc + 1

(12)

The evolution of this gain is shown in Fig. 7(b). For three capacitors (Nc = 3), the use of the proposed topology against flying capacitors gives eleeven additional voltage levels.


Fig. 8.

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Seven-level converters. (a) Classic cascaded H-bridges. (b) Hybrid cascaded H-bridges (E2 equals the third of E1). (c) Proposed topology. TABLE III NUMBER OF VOLTAGE LEVELS SURPLUS ACCORDING TO THE N UMBER OF C APACITORS

B. Comparison Toward Cascaded H-Bridges Topology Fig. 8(a) shows a classic seven-level cascaded H-bridges converter. To produce the same voltage levels, a hybrid cascaded converter uses less number of active and passive components as shown in Fig. 8(b), where E2 equals the third of E1. The proposed U-cell converter topology can be seen as a hybrid cascaded H-bridges converter using less number of semiconductor devices as depicted in Fig. 8(c). For the classic cascaded H-bridges converter, the number of the generated voltage levels according to the number of capacitors is given by the following relation: N = 2Nc + 1

(13)

where Nc is the number of capacitors, (e.g., if Nc = 2, the classic cascaded H-bridges converter is N = 5 level). For a given number of capacitors, the gain in terms of voltage level surplus is gqh = 2N c+1 − 2Nc − 2.

(14)

Fig. 9. Benefits of the PUC compared to cascaded H-bridges topology. (a) Gain in (%) of voltage levels according to the number of capacitors. (b) Gain in (%) of voltage levels according to the number of power switches.

In percent, this gain becomes g2 = 100 ×

2N c+1 − 2Nc − 2 %. 2Nc + 1

(15)

Table III depicts the gain gqh . Fig. 9(a) shows the evolution of the gain g2 . Conversely, for a desired number of voltage levels, the cost saving in terms of capacitors is given by N +1 − log2 (N + 1) × pc (16) gch = 2 where, “pc” is the price of one capacitor.

If one chooses the classic cascaded H-bridges converter to generate 31 voltage levels, eleven capacitors will be lost, which represent a surplus of 275% compared to the proposed topology. In the case of hybrid cascaded H-bridges converter, the number of the generated voltage levels according to the number of power switches is given by the following relation: N =2

Nsw 4

+1

−1

where Nsw is the number of power switches.

(17)

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TABLE IV COMPARISON OF SEVEN LEVELS CLASSIC TOPOLOGIES AND THE P ROPOSED O NE

TABLE V COMPARISON OF FIFTEEN LEVELS CLASSIC TOPOLOGIES AND THE P ROPOSED O NE

Fig. 10. Averaged control strategy of the seven-level PUC operating in rectifier mode.

For a given number of power switches, the gain in terms of the number of voltage levels is given by gqhh = 2

N sw 2

−2

N sw 4 +1

.

(18)

This gain can be expressed in percent by g3 = 100 ×

2

N sw 2

2

−2

N sw 4 +1

N sw 4 +1

−1

Fig. 11.

.

(19)

The evolution of g3 is shown in Fig. 9(b). For example, for eight power switches (Nsw = 8), the use of the proposed topology against hybrid cascaded H-bridges gives eight additional voltage levels (gqhh = 8). A comparison of the proposed topology in case of seven- and 15-level converters toward classic ones is given in Tables IV and V. One can notice the considerable reduction of the semiconductor components in the proposed topology. V. AVERAGED M ODEL OF A S EVEN -L EVEL PACKED U-C ELL ACTIVE R ECTIFIER According to Fig. 1(c), Ti and Ti switches operate complementarily. Let Si be a switching function of Ti switch where i = (1, 2, 3). Si is defined by Si =

1, 0,

if Ti is ON if Ti is OFF.

From Fig. 1(b), one can write ⎧ ⎨ Vaa1 = −(1 − S1) × V 1 Va1a2 = (1 − S2)(V 1 − V 2) ⎩ Va2b = (1 − S3) × V 2.

Seven-level PUC rectifier output voltages.

Also,

i1 = S1 × is i2 = S2 × is i3 = S3 × is .

(22)

where is and es are, respectively the line current and the supply voltage. Then, es − Rs is − (S2 − S1) × V 1 − (S3 − S2) × V 2 dis = . dt Ls (23) Let ui be duty cycle of switch Ti . Then, assuming that 1) Line current is constant in a switching period 2)

u1 + u2 + u3 = 1.5.

(24)

Let x1 , x2 , x3 , and x4 be the state variables of the source–converter–load system defined by

(20) x1 = is ,

x2 = V 1 and x3 = V 2.

(25)

The averaged model of the source–converter–load system can be given by the following matrix equation: (21)

dX = F (X) + G(X) × U + C dt

(26)


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Fig. 12. Source voltage and line current of the seven-level PUC rectifier.

Fig. 14. Output voltage Vab, load current iL , principal V 1 and auxiliary dc bus V 2 voltages.

where ⎡

⎤ ⎡ −Rs x1 ⎤ x1 Ls X = ⎣ x2 ⎦ , F (X) = ⎣ 0 ⎦ , x3 0 ⎡ ⎤ u1 U = ⎣ u2 ⎦ u3 ⎡ x2 x3 −x2 −x3 ⎤ Ls

Fig. 13. (a) Proposed modulation scheme. (b) Scheme of the proposed transformerless seven-level converter with block diagram of the control circuit. TABLE VI SIMULATION PARAMETERS

x1 G(X) = ⎣ C1 0

Ls −x1 C1 x1 C2

⎡ C=⎣

es Ls −I1 C1 −I2 C2

⎤ ⎦

(27)

Ls

0 ⎦.

(28)

−x1 C2

The input vector can then be obtained by the following equation: ⎤ ⎡ x2 +x3 3x1 x3 u1 x−2x3 ⎣ u2 ⎦ = ⎢ ⎣ 3x1 x2 u3 −2x2 −x3 ⎡

3x1 x2

−1 3x2 2 3x2 −1 3x2

1 3 1 3 1 3

⎤⎡ ⎥⎣ ⎦

Rs x1 −es Ls I2 u31 + C2

u11 +

1.5

⎤ ⎦

(29)

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Fig. 15. Harmonic contents of output voltage.

Fig. 17. (a) Block diagram of the seven-level converter feeding ac and dc loads. (b) Output voltage and holding voltage of different Ti switches.

Fig. 16. (a) Waveforms of the output voltage V ab, load current iL , principal and auxiliary DC buses voltages V 1 and V 2, respectively. (b)Loop effects on transient.

where

u11 = −(x1ref u21 = −(x2ref u31 = −(x3ref

Ki11 − x1 ) Kp11 + s Ki21 − x2 ) Kp21 + s Ki31 − x3 ) Kp31 + . s

(30)

The proposed control strategy used for the seven-level PUC active rectifier is depicted in Fig. 10. The system parameters are the following: Switching frequency f s = 600 Hz; Line inductance Ls = 3 mH; √ Source voltage es = 120 2 sin(120πt). Simulation was performed in Matlab Simulink environment using the SimPowerSystem toolbox. In order to verify the system dynamics, a dc link voltage reference variation is applied from 200 V to 250 V at time t = 4 s. A sudden load change is applied, at time t = 2 s, the upper capacitor load changes from 25 Ω to 15 Ω, whereas the lower capacitor remains uncharged until time t = 6 s when its load becomes 25 Ω. Fig. 11 shows the output voltages’ good dynamic response. Output voltages ripples are kept below 4% at full power.


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Fig. 18. Output voltage Vab , load current iL , principal and auxiliary dc bus voltages current. (b) Harmonic contents of load voltage.

Fig. 12 shows the source voltage and line current under unbalanced loads, hence confirming the unity power factor operation after disturbances.

VI. C ONTROL OF THE S EVEN -L EVEL T RANSFORMERLESS PACKED U C ELLS C ONVERTER The principal dc-bus (V 1) is the source voltage, which is generated from the ac supply network using a diode bridge rectifier. In order to generate seven levels of output voltage, one must control the capacitor voltage set point equal to V 1/3. Thus, the seven-level voltages are therefore obtained as given in Table IV. The modulator stage produces the signal S, which pass through a switching table to generate finally the gate pulses (Fig. 13).

VII. S IMULATION AND E XPERIENTIAL VALIDATION OF THE P ROPOSED M ULTILEVEL P OWER C ONVERTER T OPOLOGY A. Simulation Results The system parameters are given in Table VI. The auxiliary dc bus of Fig. 13(a), which is loaded by 40 Ω, is controlled to the third of the principal dc bus voltage V 1, which is maintained at 150 V. The ac load is constituted by a 20 Ω resistor and an inductor of 12 mH. The switching frequency of the sinusoidal PWM modulator is set at 1 kHz. The simulation was performed using SimPowerSystems in Matlab Simulink environment. Fig. 14 shows the principal and auxiliary dc bus voltages, the ac load current, and voltage waveforms evolution. A loop effect shows the steady-state operation. The ac load voltage has seven levels and its harmonic contents are centered on multiples of the PWM frequency as shown in Fig. 15. The computed output voltage THD is 24.32%. Moreover, as depicted in Fig. 15, the amplitude of the load voltage fundamental component, which has the frequency of 60 Hz, is equal to 115.6 V.

Finally, load current is near sinusoidal as shown in Fig. 14. Fig. 16 shows the waveforms when a reduced capacitor size of 680μ is considered. One can notice that at time t = 4 s, a sudden change of the ac load resistor from 40 Ω to 20 Ω occurs. Moreover, Fig. 16(b) shows a loop effects on transient of load voltage and current, and also the dc buses voltages. One can notice the good dynamic response of the proposed concept even during sudden load variations.

B. Experimental Validation The Matlab Real-Time Workshop (RTW) is used to automatically generate C code from Simulink block diagrams [Fig. 17(a)]. The code used to implement the converter control is optimized for real-time application. Afterwards, the interface between Simulink and DS1103 of dSpace [28]–[30] allows the control algorithm to run the hardware, which is a MPC8240 processor. Three analog-to-digital converters (ADC) are used to acquire load current iL , principal and auxiliary dc-bus voltages V 1 and V 2, respectively. An electronic circuit is designed for sensing these signals. Six digital I/O are used to output the MOSFET gate pulses. An opto-isolated interface board is also designed to isolate the low-power logic signals from the power stage. We choose the PolarHV HiPerFET IXF44N50P MOSFET as power switches. The circuit components values are as chosen in the simulation section. Fig. 17 shows the block diagram of the implemented circuit, the output voltage, and the holding voltage of T1 , T2 , and T3 switches, respectively from the top to the bottom. Fig. 18 shows the steady-state results of the converter operation as simulated in Fig. 14. One can conclude a high concordance between simulation and experimentation of the proposed concept. The harmonic distortion of the load voltage is nearly similar to the simulation results, as seen by comparing the results of Figs. 15 and 18(b). Harmonics with highest amplitude are centered on the PWM frequency which is 1 kHz. Fig. 19 shows steps variations of ±100% of the nominal dc bus voltage. The loop effects during both transients and steady states show that

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Fig. 19. Output voltage, load current, principal, and auxiliary dc bus voltages.

Fig. 20. System dynamic under load step with loop effect during transition.


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the auxiliary dc bus is well regulated and follows the reference value which is the one-third of the principal one. In case of load variation, Fig. 20 depicts good dynamic response of the proposed control law. Moreover, compared with Fig. 16, one can conclude a good correlation between the simulation and experimental results. In this figure, channel C1 is the load voltage (vab ), C2 is the regulated auxiliary dc bus (V 2), C3 is the input dc voltage (V 1), whereas, C4 is the load current. Channels Z1, Z2, Z3, and Z4 are the zoom effects around the instant of the load step.

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VIII. C ONCLUSION In this paper, a new power converter topology is presented. This topology is quite competitive using relatively small number of capacitors and semiconductor devices compared to existing topologies, thereby avoids bulky installations. With the same number of capacitors, the proposed topology offers better power quality in terms of achievable number of voltage levels, against other multilevel topologies. This results in reduced ratings of passive and active filters achieving a low installation cost. The concept was verified by simulation and validated by experimental results.

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Youssef Ounejjar (M’09) was born in Meknes, Morocco, in 1971. He received the B.Ing. and M.S. degrees in electrical engineering from the Ecole Nationale d’Ingénieurs de Sfax (ENIS), Sfax, Tunisia, in 1996 and 1998, respectively. He is currently working toward the Ph.D. degree in electrical engineering in the École de Technologie Supérieure (ETS), Montréal, QC, Canada. His current research interests are the multilevel power converters.

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Kamal Al-Haddad (S’82–M’88–SM’92–F’07) was born in Beirut, Lebanon, in 1954. He received the B.Sc.A. and M.Sc.A. degrees from the University of Québec à Trois-Rivières, Trois-Rivières, QC, Canada, in 1982 and 1984, respectively, and the Ph.D. degree from the Institut National Polythechnique, Toulouse, France, in 1988. From June 1987 to June 1990, he was a Professor with the Department of Engineering, Université du Québec à Trois Rivières. Since June 1990, he has been a Professor with the Electrical Engineering Department, École de Technologie Supérieure (ETS), Montreal, QC, Canada, where he has been the holder of the Canada Research Chair in Electric Energy Conversion and Power Electronics since 2002. He has supervised more than 70 Ph.D. and M.Sc.A. students working in the field of power electronics. He was the Director of graduate study programs at the ETS from 1992 to 2003. He is a Consultant and has established very solid link with many Canadian industries working in the field of power electronics, electric transportation, aeronautics, and telecommunications. He is the Chief of ETS-Bombardier Transportation North America division, a joint industrial research laboratory on electric traction system and power electronics. He is the Coauthor of the Power System Blockset software of Matlab. He has coauthored more than 300 transactions and conference papers. His fields of interest are in high-efficiency static power converters, harmonics and reactive power control using hybrid filters, switch mode and resonant converters including the modeling, control, and development of prototypes for various industrial applications in electric traction, power supply for drives, telecommunication, etc. Dr. Al-Haddad is a Fellow Member of the Canadian Academy of Engineering, a Life Member of the Circle of Excellence of the University of Quebec and received the outstanding researcher award from ETS in 2000. He is active in the IEEE Industrial Electronics Society where he is Vice President for Technical Activities, an AdCom Member and serves as an Associate Editor of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS.

Luc-André Grégoire was born in Joliette, Canada, on December 8, 1981. He received the B.Ing degree from École de Technologie Supérieure (ETS), Montréal, QC, Canada, in 2008. Since June 2008, he has worked under the supervision of K. Al-Haddad and of M. Ounejjar on experimental prototype of multilevel power converter at the Groupe de Recherche en Électronique de Puissance et Commande Industrielle (GREPCI-ETS).