Packet-Format and Network-Traffic Transparent Optical Signal ...

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in packet formatting and network traffic offered by all-optical switching devices. ... IP-like packets, a clock and data recovery circuit handling asynchronous packets .... is incident, the signal appears at the unswitched (U) port after constructively ...
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Packet-Format and Network-Traffic Transparent Optical Signal Processing Efstratios Kehayas, Student Member, IEEE, George Theodore Kanellos, Leontios Stampoulidis, Student Member, IEEE, Dimitris Tsiokos, Student Member, IEEE, Nikos Pleros, Student Member, IEEE, George Guekos, Member, IEEE, Member, OSA, and Hercules Avramopoulos

Abstract—In this paper, we demonstrate optical transparency in packet formatting and network traffic offered by all-optical switching devices. Exploiting the bitwise processing capabilities of these “optical transistors,” simple optical circuits are designed verifying the independency to packet length, synchronization and packet-to-packet power fluctuations. Devices with these attributes are key elements for achieving network flexibility, fine granularity and efficient bandwidth-on-demand use. To this end, a header/payload separation circuit operating with IP-like packets, a clock and data recovery circuit handling asynchronous packets and a burst-mode receiver for bursty traffic are presented. These network subsystems can find application in future high capacity data-centric photonic packet switched networks. Index Terms—Asynchronous optical packets, burst traffic, optical packet switching, transparent all-optical signal processing, ultrafast nonlinear interferometer (UNI), variable length optical packets.

I. INTRODUCTION

A

DVANCED time and wavelength technologies have led to the rapid increase in point-to-point optical transmission capacity, reporting record rates and distances [1]. This has placed the Metro network in the spotlight, due to its vital role of linking the massive backbone network to the Access network characterized by numerous users. In order to cope with these information rates offered by the backbone links, research in optical networks moved toward designing and building network subsystems that are capable of operating at ever higher bit-rates and handling more wavelength channels. The solutions in the backbone links, however, cannot be applied to the Metro network due to the increased processing, switching and routing activities necessary. Although network systems have been reported to handle Terabit capacities [2], the useful bandwidth available to the end-user is confined by the inefficient use of bandwidth leading to large overheads and guardbands to all network layers. For instance, network studies show that 50% of total IP traffic consists of 40–44-B packets [3]. Bearing in mind that the header itself is 20 bytes, half the bandwidth is not utilizable by the end-user. Factoring in the guardbands imposed

Manuscript received January 9, 2004; revised May 27, 2004. E. Kehayas, G. T. Kanellos, L. Stampoulidis, D. Tsiokos, N. Pleros, and H. Avramopoulos are with the School of Electrical and Computer Engineering, National Technical University of Athens, Zographou, 15773 Athens, Greece (e-mail: [email protected]). G. Guekos is with the Swiss Federal Institute of Technology Zurich, ETH Hoenggerberg, CH-8093 Zurich, Switzerland. Digital Object Identifier 10.1109/JLT.2004.836766

by remaining layers, we are driven to the fundamental question of whether it is wise to continue building upon this network infrastructure and thrust toward higher rates. The answer evolves around the bandwidth offered to the end-user and the specific applications accessed, eventually defining the network traffic. To this end, networks are dominated by short IP packets, while the traffic has a bursty nature due to the diverse bandwidth-demanding applications requested by large number of users comprising the Access networks. Optical packet switching has been proposed as a viable approach [4], [5] for efficiently harnessing the large optical bandwidth [6], since its concept relies on handling the incoming traffic on a packet-by-packet basis, directly in the optical domain. All-optical packet-switched networks are increasingly attracting interest, primarily due to the explosive evolution of semiconductor-based optical switches [7] and their commercialization. Packet switches [8]–[11], schedulers/cell-sorters [12], [13], novel routing [14]–[17] and buffering schemes [18], [19] and optical header processing [20], [21] have been reported, contributing to the “network delayering” through the intelligent optical layer toward a true photonic router [22]. To accomplish this task, however, we need to build optical network elements that are compatible to the specific traffic requirements of today’s networks. Specifically, the optical circuit design must focus on providing on-demand bandwidth with low delays [23], flexibility and granularity and only then upgrade to higher rates. A key advantage of photonic technology over electronics is packet format transparency and if exploited, it can help to solve problems related to bandwidth inefficiency. For this to be realized, optical subsystems are required to perform successfully with short, IP-like optical packets [24], [25], that arrive asynchronously or in bursts while keeping the guardband requirements low. Short packets offer finer granularity, variable length-packets offer flexibility, asynchronous packets avoid costly and expensive synchronization stages, while burst packets relax the packet-to-packet equalization stages. In this paper, we demonstrate packet-format and networktraffic transparent optical processing subsystems operating with ultrashort packets (a few nanoseconds) while maintaining high bandwidth utilization. All reported subsystems are based on the combination of a low- Fabry–Pérot (FP) filter and semiconductor optical amplifiers (SOA)-based interferometric switches. Exploiting the short time-scale response of FP filters we achieve packet-based processing and by using optical gates we realize bit-wise processing and power level equalization. In this frame, we address problems related to synchronization, header/payload

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separation, and packet reception for the following packet formats. • Variable-length packets: Optical signal processing with variable length packets is experimentally presented in a header/payload separation circuit at 10 Gb/s. • Asynchronous packets: A clock-and-data recovery (CDR) circuit ideal for packet reception or regeneration is experimentally demonstrated for asynchronous packets at 10 Gb/s. • Burst-mode traffic: A burst-mode receiver circuit at 10 Gb/s is proposed, based on the CDR circuit and an additional optical gate operating as hard-limiter, required for equalizing the power levels of the incoming bursts. The remaining sections of the paper are organized as follows. Section II is a theoretical analysis investigating the bit-by-bit and packet-to-packet processing capabilities of optical gates and low- FP filters, respectively, verified by experimentally demonstrating a packet clock recovery circuit. Section III illustrates the transparency of optical signal processing in packet length, synchronization, and power fluctuations through experimental and theoretical results for three network subsystems aforementioned, whereas Section IV is an analysis of the guardband requirements imposed by these subsystems. All experimental work was realized with ultrafast nonlinear interferometers (UNI) as the switching elements using 1.5-mm 5-dB bulk InGaAsP–InP ridge waveguide SOA with 25small- signal gain at 1540–1550-nm region and a recovery time of 80 ps, when driven with 700-mA current. A simulation tool was developed to model the response of the FP filter and the gain dynamics of the SOAs [26] used in the Mach–Zehnder interferometers (MZI).The parameters for the SOA in the simulation were 22-dB small-signal gain, 10-fJ saturation energy, and 100-ps recovery time. II. BITWISE AND PACKET-TO-PACKET PROCESSING A. SOA-Based Interferometric Switching Elements Interferometric SOA-based switching devices rely on the fast nonlinear response of semiconductor materials when subjected to high intensity optical signals. Exploiting cross-phase-modulation (XPM) effects of such materials in interferometric arrangements, has led to the development of all-optical, highspeed switching devices performing logic [27], [28] and network functionalities [29]–[32]. Fig. 1 depicts two implementations of such switches that are extensively used: (a) the MZI and (b) the UNI. The principle of operation of both arrangements relies on optically controlling the phase of the incoming signal (Data IN) by a strong signal (Control) through a change in the effective refractive index within the material. Depending on the presence or absence of such a control signal, the data signal interferes destructively or constructively at the output of the interferometer, resulting to all-optical switching. In the case of the MZI, the input signal is spatially separated with the use of couplers. When no control is incident, the signal appears at the unswitched (U) port after constructively interfering at the output coupler. When a control signal is inserted in the SOA as shown in Fig. 1(a), the separated

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Fig. 1. Schematic diagrams and principle of operation of the (a) UNI and (b) the MZI.

data signal experiences a phase shift due to the nonlinear refractive index change within the SOA. As a result, the two signal components now interfere constructively at the switched port (S). In the UNI, the separation is achieved temporally by employing suitable birefringent elements. The UNI consists of a polarization beam splitter (PBS) spliced at 45 with a polarization-maintaining fiber (PMF) creating two orthogonal polarization states. The PMF length is such that it induces delay between the two axes of anisotropy, thus achieving temporal separation of the two orthogonal components. Upon exiting the SOA, these components are rotated 90 and propagate through an identical PMF length canceling their temporal separation. After interfering at the 45 splice, the signal emerges at the U-port. When a control pulse is synchronized with one of the two components, a phase shift is induced and after the PMF, the resultant signal exits through the other output of the PBS, appearing at the S-port. A set of simulation results were obtained using the MZI simulation model for a simple wavelength conversion scheme, where a CW signal is inserted to the MZI as the input and a RZ pulse train as the control signal. Fig. 2 shows the switching characteristics for (a) the unsaturated and (b) saturated switching conditions, in order to verify the bitwise and equalizing properties of optical gates, respectively. Fig. 2(a)(i) shows the eye of a pulsetrain suffering from amplitude modulation entering the MZI switch. Fig. 2(a)(ii) shows the resulting gain variation of the SOA due to the inserted pulses, whereas the asymmetry of the switching curve is due to the recovery time of the semiconductor. Fig. 2(a)(iii) shows the resulting phase response perceived by the CW signal through XPM induced by the control pulses at the upper branch of the MZI, as shown in Fig. 1(a). This gain dependent phase profile of the CW interferences with the unaffected CW signal propagated through the lower branch of the switch. The resulting pulsed output at the S-port is shown in Fig. 2(a)(iv), illustrating the switching window confined within a bit-period, which verifies bitwise processing. The description on the switching so far assumes that the input signal to the optical gate does not affect the gain of the SOA, i.e., the amplifier operates at the small-signal gain regime. In very recent theoretical investigations, we have verified [33] that when the SOA

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Fig. 3. (a) Impulse response. (b) Transfer function of a FP filter for various finesse values.

the impulse response beyond this time instant is zero. For example, the impulse response of a FP filter with finesse of 20 time to decay. For a bit-rate of requires approximately 10 Gb/s (10-GHz FSR) this exponential tail is 800 ps, or 8 b. As the filter finesse decreases, the exponential tail becomes smaller, allowing for processing of smaller packets. C. The Packet Clock Recovery Circuit

Fig. 2. Principles of all-optical switching for (a) unsaturated and (b) saturated conditions. Specifically, (i) shows the input control signal; (ii) shows the gain variation; (iii) shows the phase profile; and (iv) shows the pulsed output.

is forced to operate in the deeply saturated regime, with the aid of the CW signal, the gate behaves as an optical hard-limiter circuit and this is shown in the plots of Fig. 2(b). In more detail, Fig. 2(b)(i) shows an identical input pulsestream as in the previous case. Fig. 2(b)(ii) depicts the gain response of the SOA that is now in the saturated regime, due to the high optical power of the CW signal. Successive pulses push the amplifier toward its gain transparency point, resulting to similar gain ripples with reduced recovery time. The specific gain variation is imprinted to the phase shift of these pulses that is now constant [Fig. 2(b)(iii)]. The amplitude equalized output pulsetrain of Fig. 2(b)(iv) verifies the that the gate operates as an optical hard-limiter, i.e. amplitude equalizer circuit. B. The FP Filter A fundamental building block of the subsystems reported in the subsequent sections employs a low- FP etalon centered at the line rate. The impulse response of this comb-generating passive filter depends solely on its finesse, or value. Fig. 3(a) shows the impulse response in terms of bit slots Bit Rate of such a filter, for three values of the finesse. Fig. 3(b) shows the frequency response expressed in terms of free spectral range (FSR), for three values of Finesse. The time-domain exponential decaying trailing edge, or “tail,” defines the timing boundaries that allows for packet-to-packet signal processing, since

In this section, a packet clock recovery circuit is briefly described verifying the bitwise-operation and amplitude-equalization characteristics of optical gates, while using a low- FP filter that allows for packet-by-packet processing. The necessity for such processing requires that the clock recovery circuit ideally produces a clock signal that exists only for the duration of each packet. This will ultimately allow for subsequent packet processing and minimization of guardbands between packets. The FP filter is used as a passive oscillator centered at the line-rate frequency and determines both the lock-in time and the guardbands required. Hence, the use of high- FP filters [34] for short-packet clock recovery is not advantageous due to the required short impulse response. Previously reported clock recovery circuits, such as phase-locked loops [35] and mode-locked ring-lasers [36] also have long lock-in times and the persistence of the generated clock signal is much greater than the packet length. Self-pulsating DFB lasers acquire phase locking within a few nanoseconds and the clock persistence is over 100 ns [37]. Fig. 4 shows the experimental setup of the clock recovery circuit. A DFB laser emitting at 1549.2 nm was gain switched at 1.290 75 GHz to produce 8-ps pulses after linear compression. PRBS The pulsetrain was modulated with 1.290 75 Gb/s using an electrooptic modulator and 8 rate multiplied using a fiber bit-interleaver. The resulting 10.326 Gb/s pseudorandom data patterns were fed into an additional electrooptic modulator driven by a programmable pulse generator producing packets of various length and period. The data packets passed through a FP filter with identical FSR and finesse of 20.7 producing a clock resembling signal with strong amplitude modulation. This signal was then fed into the UNI gate biased by a CW signal at 1545 nm. Exploiting the step-like transfer function of the saturated gate, due to the strong CW signal, acting as a holding beam [48], clock packets were generated at the switched (S) port of the UNI gate. Fig. 5 shows microwave spectra and oscilloscope traces of the input data, the output of the FP filter

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Fig. 4. Block diagram of the packet clock recovery experimental setup.

Fig. 6. Block diagram of the header/payload separation experimental setup.

packet length (IP-like packets), synchronization (asynchronous packets) and power variation (bursty traffic). Although maximum bandwidth utilization is achieved with signal processing at the line rate, the optical circuits proposed are also compatible with network scenarios using hybrid bit-rate traffic, i.e., packet-to-packet or intrapacket (header and payload) bit-rate variation. For these cases, the clock recovery circuit is designed to operate at the highest bit-rate data by appropriately selecting the FSR of FP filter. Given that the requirements for clock extraction are met and the different bit-rates are integer multiples, the optical circuits will operate successfully with lower bit-rate data. Fig. 5. Microwave spectra and oscilloscope traces for (a) input data packet. (b) FP output. (c) extracted packet clock. The spectra have 11 GHz span and 5 dB/div vertical scale, while the time base of the traces is 100 ps/div.

and the recovered clock packets obtained using packets of 3-ns length. The amplitude modulation of the self-extracted clock packets is 1.2 dB and the switching powers/energies of the UNI were 800 W for the CW signal and 100 fJ/pulse for the control signal. The basic characteristics of the packet clock recovery are its lock-in time of 2 bits and its short exponential tail of 8 b. The maximum number of consecutive “0”s that will still produce a packet clock is 7 for the specific FP filter used. Both the fall time and the number of allowed successive zeros depend on containing the finesse of FP filter. In the case of PRBS 31 successive zeros, a finesse of 80 is required [31]. Hence, the design parameters of the clock recovery circuit are defined by the FP filter that sets the maximum successive zeros within a packet and the extracted clock fall time, which in turn sets the limit to the minimum spacing of the packets. This tradeoff is investigated in more detail in Section IV, analyzing the guardbands requirements. III. TRANSPARENT OPTICAL SIGNAL PROCESSING This section verifies that by using an optical gate as a fundamental building block, simple optical circuits can be designed to be independent to packet-format and network traffic, attributes highly desirable for networks such as the Metro. Exploiting the characteristics of the clock recovery (short lock-in time, short guardbands and short packet clock persistence), network elements are reported as examples, stressing their independency to

A. Variable Length Optical Packets The independency of network elements to packet length is a highly desirable attribute for future optical internet packet switching [24]. This capability offered by optical gates is demonstrated in a header extraction circuit performing “on the fly” header from payload separation using the packet clock recovery circuit and a cascaded optical gate. Compared to previously reported results [21], [38], the circuit complexity is independent to header and packet duration, while it is worth mentioning that it is the first time that such a module is reported to handle short IP-like packets. Fig. 6 shows a simplified experimental setup used to demonstrate header/payload separation with short, variable-length packets at 10 Gb/s. Gain switching and linear compression techniques were used to generate 1.290 75 GHz, 10-ps optical clock pulses. The pulsetrain was then modulated with PRBS at 1.290 75 Gb/s using an electrooptic modulator driven by a PRBS generator. The modulated data were passively rate multiplied to 10.326 Gb/s and by using another electrooptic modulator driven by a pulse generator, successive packets of varying length were generated. Using a fiber coupler, part of the data signal was inserted into the clock recovery circuit and the remaining part into the second UNI gate. Clock recovery is performed exploiting the saturation properties of the SOA through the use of a strong CW signal at 1545 nm. Clock packets with 2-b rise time and 8-b fall time, are self-extracted from the input packet stream and are obtained at the S-port of the UNI gate. The header extraction process is performed in the second UNI gate, where the recovered clock enters as Control signal and the packet stream as input to the gate. The concept

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Fig. 7. Pulse traces showing (a) input packets, (b) self-extracted packet clocks, (c) extracted payloads, and (d) extracted headers for 2.5. ns/div (left column) and 800 ps/div showing the 6.6-ns packet only (right column).

relies on temporally synchronizing the clock packet that defines the switching window of the gate, with the payload bits with the aid of a variable optical delay line (ODL). In this way, the payload bits are switched to the S-port, while the header bits remain unswitched, thus appearing in the U-port. The circuit was tested with 10-Gb/s data packets of short duration and variable payload, header length and spacing. The header length was set to 1.4 ns and the format, defined by the rise time of the recovered clock, contains two logical “1”s as guardbands to enhance clock extraction and two “0”s at the end to prevent switching with the two imperfect clock pulses in the front of the packet. The right column of Fig. 7 shows oscilloscope traces at 2.5 ns/div for two packets of 4.4 ns and 6.6 ns, separated by 6.4 ns. In more detail, it shows oscilloscope traces of (a) the input packets, (b) the extracted clock packet and the extracted, (c) payloads, and (d) headers. The left column only shows the 6.6-ns packet at 800 ps/div. The pulse-to-pulse amplitude modulation evident in all pulse traces are due to the passive rate multiplication and is not degraded at the output of the gate. The CW power used to bias the clock recovery gate was 1.0 mW and the switching energy of the input to the gate was 120 fJ. The switching energies of UNI2 gate were 4 fJ for the data packets and 27 fJ for the extracted clock signal. B. Asynchronous Packets The capability of network components to operate in the asynchronous domain is crucial for avoiding complex and expensive synchronization stages in a network. In this section, as an

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example that optical gates can be insensitive to synchronization, a CDR circuit operating with short, asynchronous 10-Gb/s packets is demonstrated. A CDR circuit consists of two discrete elements: a clock recovery circuit and a decision element driven from the extracted clock and used to regenerate the incoming data before reception and subsequent processing. For asynchronous traffic, the clock recovery and regeneration must be performed on a packet-by-packet basis, irrespective of the precise packet phase on arrival. Previous synchronous electronic CDR circuits use electronic phase-locked loops (PLLs) [39] that are not suitable for asynchronous traffic due to their long lock-in time. Electronic CDRs capable of handling asynchronous traffic have been proposed operating up to 10 Gb/s with nine preamble bits [40]. The experimental setup used to demonstrate the operation of the CDR circuit is shown in Fig. 8. An RZ 10.326-Gb/s continuous pseudorandom data stream was produced and fed to an electrooptic modulator driven by a programmable pulse generator for producing packets with various lengths, period and spacing. These packets were then inserted into the asynchronous packet-flow generator consisting of two 50:50 fiber couplers and a variable ODL, as shown in Fig. 8. The incoming packets were split and combined using the fiber couplers and within one branch, 30.6 ns of differential delay was inserted between the packets. The variable ODL was used to fine tune the “asynchronicity” of the packet streams. The generated asynchronous packets were then split and inserted into the clock recovery module and into an optical gate (UNI2). Packet clock recovery is then performed without the necessity for extracting the absolute phase of the incoming packets. The asynchronous self-extracted clocks are used as control signal and the data packets as inputs to the second UNI gate that acts as the decision element of a typical CDR circuit. The data packets were temporally synchronized with their equivalent clocks in UNI2 and the received packet data stream was obtained at the S-port of UNI2. Fig. 9 illustrates a sequence of four asynchronous data packets, each containing 41 b. The pair of packets 1 and 3 is phase-misaligned with the pairs 2 and 4 in the asynchronous packet flow generator. The time interval between packets 1 and 2 is 1.5 ns, while between packets 2 and 3 is 2.7 ns. Fig. 9(b) shows the corresponding recovered clock packets and Fig. 9(c) shows the recovered packet stream in the S-port of UNI2. Fig. 9 also provides more detailed information about the quality of the recovered asynchronous clock and data packets through a set of eye diagrams. Strong amplitude modulation was intentionally introduced to the input data through the fiber bit interleaver by unbalancing the loss of each split-and-delay stage within the rate multiplier. The recovered clock and data eye diagrams show significant improvement in terms of amplitude and timing jitter. Similar system performance was observed for a range of phase misalignment of the asynchronous packets. The timing jitter performance of the circuit was evaluated using a 40-GHz photodiode and a microwave spectrum analyzer. The input data to the CDR circuit was measured to have 1.5-ps timing jitter and at the output of the system this was reduced to 600 fs, while the recovered clock timing jitter was 300 fs. The operating conditions for the clock recovery gate (UNI1) were 900 W for the CW optical signal and 100 fJ/pulse for the control signal.

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Fig. 10.

Fig. 8.

Block diagram of the CDR experiment setup.

Fig. 9. Asynchronous oscilloscope traces and eye diagrams of (a) input data, (b) recovered clock, and (c) recovered data. The time base for pulse traces and eye diagrams is 2.5 ns/div and 20 ps/div, respectively.

The second gate (UNI2) operated with 2 fJ/pulse for the data input and 22 fJ/pulse for the control. The amplitude and timing jitter reduction measured in decision element (UNI2) is due to the nonlinear transfer characteristics of the saturated gate, when the switching is controlled by an almost jitter-free recovered clock signal. C. Burst Traffic The support of packet and burst-mode operation on a photonic network offers undoubtedly a higher degree of data transparency and facilitates the implementation of many high-speed and high-bandwidth network applications. The inherent special characteristics of bursty and packet data traffic are the large variations in optical power, length, and phase alignment appearing on a packet-by-packet basis [41]. In this context, the bursty nature of the data packets, which arrive at a network endpoint originating from different locations, requires the presence of a burstmode receiver exhibiting large dynamic range and low lock-in time. The early research efforts toward the design of high-speed, burst-mode receivers have resulted in the development of devices with a power fluctuation tolerance of 26 dB operating at bit rates up to 2.5 Gb/s [42], whereas more recent implementations have

Block diagram of the burst-mode receiver proposed.

extended the bit rates to 10 Gb/s exhibiting a dynamic range of 9 dB [43], [44]. In all the above cases, several preamble bytes are required to successfully achieve amplitude and phase recovery. In this section, an all-optical burst-mode receiver is proposed and its performance is investigated using the simulation tool we developed. The simulation results show that optical gates can be employed to instantly handle successive packets with a large difference in optical power (up to 16-dB dynamic range), length and phase alignment, leading to the drastic reduction of the preamble field and thus to higher transmission efficiency. Fig. 10 shows the block diagram of the proposed architecture. Burst-mode reception is completed in three stages; the amplitude equalization stage, the clock recovery and finally the data recovery. The CDR system is based on the same structural concept as the one described previously, whereas a third CW-powered MZI gate plays the role of the amplitude equalizer. For the performance evaluation of this configuration we have simulated PRBS burst packet stream consisting of variable-length, a asynchronous packets. The lengths of the packets are 40 and (or 12.5 ps). The pulse 55 b, and their phase difference is stream has a 3-dB pulse-to-pulse amplitude modulation defined as the highest-to-lowest pulse ratio. The two packets also exhibit 13-dB packet-to-packet power variation defined as the average peak power ratio between them. Fig. 11(a) illustrates the pulse trace and the eye diagram of the bursty packets suffering from amplitude and timing jitter. The introduction of the bursty packet stream into the amplitude equalizing gate results in the reduction of the packet-to-packet power fluctuation due to the CW light injection, which saturates the SOA [33] forcing the gate to operate as a hard-limiter [Fig. 11(b)]. In this biasing point, the SOA provides a constant phase change for a broad range of pulse energies above a specific threshold. To this end, as the control pulse peak power increases beyond this threshold, a phase shift is retained for longer temporal durations of the pulse. This ultimately leads to the broadened, near-rectangular pulse shapes shown in the eye diagram of Fig. 12(b), where the flat part of the pulse corresponds to a phase change. This signal is then inserted in the clock recovery unit and the recovered clock packets are illustrated in Fig. 11(c) showing less than 0.5-dB amplitude modulation. The recovered clocks exhibit no rise time, as the first two bits exiting the FP filter are now within the power equalizing dynamic range of the gate. Finally, the recovered packet clocks are used as inputs to the third optical gate that is optically controlled by the equalized data packets. The received data packets are shown in Fig. 11(d). The examination of the corresponding eye diagram reveals that the packet-to-packet power fluctuation is reduced to 0.4 dB, whereas the two received data packets have 0.8-dB and 0.2-dB pulse-to-pulse amplitude modulation. The eye diagrams shown in Fig. 12(c) and (d) were obtained after pulse shaping

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Fig. 11. Simulation results for burst-mode receiver. Pulse traces and corresponding eye diagrams for (a) input burst packets, (b) power equalized packets, (c) recovered clock packets, and (d) received data packets.

Fig. 12. Schematic representation of packet traffic and corresponding self-extracted packet clock.

using a second-order Gaussian filter with a 3-dB bandwidth of 65 GHz. The simulation tool was also used to evaluate the jitter performance of the system. When the root mean squared timing jitter of the input burst packets was set to be 1.4 ps, the recovered clock jitter was reduced to 750 fs and the received data to 820 fs. IV. OPTICAL PACKET LENGTH AND GUARDBANDS Appreciating the necessity to design optical networks capable of handling asynchronous/bursty packets with IP nature, a dimension that we have not touched on yet is the choice of optical packet length. A crucial design parameter for evaluating the per-

formance of a network is the bandwidth efficiency defined as the percentage of raw information sent within a packet period over the guardbands required for lossless communication. The use of ever shorter packets implies that the available bandwidth in the time domain is sliced into very fine “time slots” distributed to the appropriate users requesting it on random instances. However, shorter packets also decrease the bandwidth efficiency, since the ratio of guardbands (including the header) over the payload increases [45]. Previously reported optical switches [8], [9] use packet lengths of the order of microseconds, achieving approximately 80% bandwidth efficiency [45]. The guardbands imposed by the network elements discussed are investigated in terms of packet length and number of successive zeros existing within these packets. Fig. 12 shows a typical , a header section , packet containing a payload section and guardbands adjacent to the header. The extracted clock has and duration equal to the corresponding a finite rise time . As described in Secpacket increased by the filter fall time tion II, the design parameters of the clock recovery circuit are concerned with tailoring the impulse response of the FP filter. The filter rise time impacts the guardband imposed within the packet and the finesse defines the length of the fall time along with the maximum number of successive zeros that will still produce a clock packet. This exponential tail poses a constraint contributing to on the minimum spacing of the packets the overall guardband requirements imposed by the circuit. The analysis depicted in Fig. 13(a) shows that the bandwidth overhead imposed by the clock recovery is 20% with packet sizes as low as 40 bits, treating the header bits as useful information and setting the maximum number of successive zeros to 7 (Finesse 20). The specific value of overhead is again achieved with 350 b assuming the worst-case scenario of 31 successive zeros followed by 31 successive ones (Finesse 80). The clock and data recovery circuit performs similarly to clock recovery and the bandwidth overhead imposed is shown in Fig. 13(b) for three values of FP filter finesse. The guardband requirements of the header/payload separation circuit in terms of packet length are . The shown in Fig. 13(c) for three different header lengths solid line represents the total overhead imposed by the circuit, while the dotted line is the theoretical overhead imposed by only transmitting the header. The bandwidth overhead is kept below 20% for packets less than 200 b assuming a header length of 10 b, while for packets that have 160-b fixed length header, such as IP packets, the bandwidth overhead of 20% is achieved for packets as short as 1500 b. These overheads pose a constraint on the minimum packet spacing approximately equal to the header length. In practice, the packet spacing will never be zero, as subsequent header processing will always require a certain amount of guardbands. Best operation for ultrashort packets ( 100 b) is achieved for packets with low header to payload ratio most suitable for MPLS-based architectures [5], [46] and all-optical self-routing schemes [15], where the header itself is reduced to a few bits. V. CONCLUSION We have demonstrated that all-optical gates can offer true packet-format and network-traffic transparency due to their in-

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Fig. 13. Bandwidth overhead in terms of packet length for various filter finesses in (a) packet clock recovery. (b) CDR and for various header lengths in (c) header/payload separation circuits.

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Efstratios Kehayas (S’03) received the B.Eng. degree in electronic engineering from Southampton University, Southampton, U.K., and the M.Sc. degree in optics and photonics from Imperial College, London, U.K. Since 2002, he has been with the Photonics Communications Research Laboratory, National Technical University of Athens, Athens, Greece. His research field includes all-optical logic devices.

George Theodore Kanellos received the Diploma degree in telecommunications from the Department of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece, in 2002. He joined the Photonics Communications Research Laboratory, NTUA, in 2002. His main research interest is in theoretical investigation of gain dynamics in semiconductor optical amplifiers and the implementation of novel optical circuits for packet-switched networks.

Leontios Stampoulidis (S’03) received the Diploma degree in telecommunications from the Department of Electronic and Electrical Engineering, University of Patras, Patras, Greece, in 2002. He has been with the Photonics Communications Research Laboratory, National Technical University of Athens, Athens, Greece, since 2002 working on novel optical burst switching architectures and the implementation of all-optical network subsystems.

Dimitris Tsiokos (S’03) received the B.Eng. degree in electronic engineering from the University of Southampton, Southampton, U.K., in 2001 and the M.Sc. degree in optics and photonics from Imperial College, London, U.K., in 2002. He has been with the Photonics Communications Research Laboratory, National Technical University of Athens, Athens, Greece, since 2002. His laboratory-related experience includes all-optical high-speed logic and implementation of high-rate optical sources.

Nikos Pleros (S’03), photograph and biography not available at the time of publication.

George Guekos (S’66-M’69), photograph and biography not available at the time of publication.

Hercules Avramopoulos photograph and biography not available at the time of publication.