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Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication Wameedh N. Flayyih, Member, IEEE, K. Samsudin, S. J. Hashim, Yehea I. Ismail, Fellow, IEEE, and Fakhrul Z. Rokhani, Member, IEEE

Abstract—The presence of different noise sources and continuous increase in crosstalk in the deep sub-micrometer (DSM) technology raised concerns for on-chip communication reliability leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This paper proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as crosstalk avoidance technique and between hybrid automatic repeat request (HARQ) and forward error correction (FEC) as error control policies, three modes of error resiliencies are provided. The results show that in reduced mode, the scheme achieves up to 25.3% power savings at 3 mm wire length as compared to the original non-adaptive scheme at the cost of only 3.4% power overhead in high protection mode. Index Terms—error control; Hamming code; fault tolerance; on chip interconnect.

I.

INTRODUCTION

On-chip communication reliability became a major concern due to the shrinking feature sizes, increased frequencies, and reduced operating voltages in the deep submicron region. Noise sources, which include alpha particles, crosstalk, electromagnetic interference (EMI), power supply noise, and others, can cause transient faults in on-chip bus [1, 2]. Transient faults manifest in the form of logic-violation-induced, LVI, (i.e. logic value flip) or timing-violation-induced, TVI, (i.e. late signal arrival) and they constitute 80% of system failures [1]. In addition to signal integrity concern, continuous increase in crosstalk due to slow scale of wire aspect ratio further affect on-chip bus power consumption [1, 2]. Approaches in handling transient faults for on-chip communication in the presence of the various noise sources can be classified into addressing LVI and TVI faults, individually and jointly. Error control schemes like simple parity, cyclic redundancy check, Hamming codes, and Hamming-based product codes were proposed to handle LVI transient faults only [3-5]. While, crosstalk avoidance code (CAC) schemes and nonManuscript received W. N. Flayyih is with the Computer Engineering Department, College of Engineering, University of Baghdad, Iraq. (e-mail: [email protected]). K. Samsudin, S. J. Hashim, and F. Z. Rokhani are with the Department of Computer and Communication Systems Engineering, Faculty of Engineering, Universiti Putra Malaysia, 43400 UPM Serdang, Malaysia. (e-mail: [email protected]; [email protected]; [email protected]). Y. I. Ismail is with the Center of Nanoelectronics and Devices at the American University in Cairo and Zewail City, Cairo, 12588 Egypt (e-mail: [email protected]).

coding techniques including shielding, skewed transition, and repeater insertion were proposed to handle TVI only [2, 6]. On the other hand, a class of work proposed crosstalk-aware codes that join error control with crosstalk avoidance to address both LVI and TVI faults. Earliest schemes, duplicateadd-parity (DAP) [6], dual rail [7], boundary shift code [8], and modified dual rail code [9], achieved single error correction (SEC) with reduced worst-case crosstalk induced bus delay (CIBD) to (1+2λ)τ0 through duplication and parity calculation over data bits. Note that λ is the ratio of wire coupling capacitance to bulk capacitance and τ0 is the crosstalk-free wire delay [1]. These coding schemes achieve the dual function of speeding up bus signal arrival and increasing resilience against single logic level flips while reducing power consumption. Recently, more powerful crosstalk-aware codes to detect/ correct multi-bit errors were proposed to address steady growth of noise in ultra DSM technology. Hamming product code with skewed transitions [10] achieved multi-bit error detection, however restricted to two errors per row. Crosstalk avoidance and double error correction scheme was proposed in [11], by encoding the data using Hamming SEC and passing the resultant codeword into DAP encoder. This was later enhanced to joint crosstalk avoidance and triple error correction (JTEC) scheme and to JTEC with simultaneous quadruple error detection (JTEC-SQED) scheme [12]. This high error detection/correction enabled lower voltage swing thus effectively reducing power while maintaining the target reliability. These crosstalk-aware multi-bit error control codes are designed to achieve target reliability in the presence of worstcase noise conditions predicted, whereas noise level actually varies during operation due to temperature and supply voltage variations [1, 10, 13]. Accordingly, some works [10, 13] attempt to adapt the detection/correction strength based on the noise level to minimize the power and/or energy consumption. However, they lack the crosstalk-aware capability. In this paper, we consider network on chip (NoC), an emerging paradigm for on-chip communication. We propose adaptive crosstalk-aware multi-bit error control code to further reduce the bus power consumption by providing appropriate communication resiliency based on runtime noise level. For a given noise scenario, an appropriate set of crosstalk avoidance approach and error control policy is selected for power efficient and reliable transmission. The proposed scheme switches between three sets namely, duplication and hybrid automatic repeat request (HARQ), shielding and HARQ, and shielding

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Fig. 1. Proposed adaptive scheme (a) encoder, (b) crosstalk control block and resulting codeword in different modes, (c) decoder, and (d) noise monitor block.

with forward error correction (FEC). The rest of the paper is organized as follows. Section II describes the proposed adaptive scheme. Section III presents the reliability provided by the different schemes. Section IV evaluates the schemes from power and area perspectives. Section V concludes the paper. II.

PROPOSED ADAPTIVE CROSSTALK-AWARE MULTI-BIT ERROR CONTROL CODE

Common approach of arbitrarily combining different coding schemes lead to high complexity design [13]. The proposed approach exploits the inherent characteristics of joint wire duplication and error control policies, and systematic codec integration for reduced hardware complexity in providing adaptable error protection levels while maintaining (1+2λ)τ0 CIBD. The proposed scheme works in three modes; i.e. normal mode and two power saving modes namely duplicated SECDED (D_SECDED), shielded SECDED (S_SECDED), and shielded SEC (S_SEC) respectively. Normal or D_SECDED mode provides highest error protection at no power saving while the two power saving modes (S_SEC, S_SECDED) provide moderate and low error protection leading to moderate and high power saving respectively. In D_SECDED mode, JTEC-SQED scheme is selected which uses duplication and HARQ-based Hamming SECDED as the crosstalk avoidance and error control respectively. JTEC-SQED is employed as it achieves high error protection; i.e. triple error correction, quadruple error detection and will be used in high noise condition. The drawback of this scheme is the increased bus power consumption due to the switching of the duplicated wires and complex decoding algorithm [12]. In the power saving modes, the crosstalk avoidance approach is switched to shielding technique while the error control schemes used are HARQ-based Hamming SECDED and FEC-based Hamming SEC for S_SECDED and S_SEC modes respectively. S_SECDED mode enjoys error protection up to two error detection while S_SEC has single error correction,

thus will be used in moderate and low noise conditions respectively. In these two modes, power reduction is achieved through the non-switching shield wires and non-active hardware logics at both encoder and decoder due to simpler error control coding. Note that shielding is an alternative crosstalk avoidance approach that uses the same number of wires as duplication, and both limit the worst case CIBD to (1+2λ)τ0. In NoC, it is common to place the encoder and decoder as separate pipeline stages to preserve frequency with increased packet latency [12]. Fig. 1(a) shows the adaptive scheme encoder where data is first encoded using Hamming SECDED encoder and then one of the crosstalk avoidance approaches is applied before being sent on the bus. In pipelined on-chip communication, a set of flip-flops precedes the crosstalk control. Hsiao code is implemented for the encoder block due to ability to reduce long chain of XOR gates to calculate overall parity and decoder complexity [8]. A characteristic of Hsiao code is the ability to work as SEC code by dropping any one of the (h+1) parity bits [12]. Reconfiguring to use SECDED or SEC code is achieved through Mode [0] control bit. The crosstalk control block applies duplication in D_SECDED mode, while shielding is applied in S_SECDED and S_SEC modes by setting Mode [1] control bit to 1 and 0 respectively. By duplicating SECDED codeword, Hamming distance is doubled from originally 4 to 8 and with proper decoding strategy, triple error correction and quadruple error detection is achieved [8]. Shielding SECDED or SEC codeword does not increase the Hamming distance and thus their Hamming distances are 4 and 3 respectively. The resulting codeword in the three modes is shown in Fig. 1(b). Note that in S_SECDED and S_SEC modes, shield wires are grounded. Retransmission buffer is required for the HARQ type schemes, i.e. D_SECDED and S_SECDED. In FEC type scheme, i.e. S_SEC, the retransmission buffer is not required and can be disabled to save power. Clock and power gating are the alternatives to disable the buffer and in our implementa-

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tion, clock gating is employed. Fig. 1(c) shows the proposed adaptive scheme decoder that supports reconfiguration among the three modes. In D_SECDED mode, JTEC-SQED scheme implements complex decoding algorithm that requires calculating the syndromes of both codeword copies A and B and correcting them. Two sets of (k+h+1)-registers arrays at the decoder input are used to store both codeword copies. In S_SECDED and S_SEC modes, the decoding process is much simpler than JTEC-SQED as both modes require single codeword copy and to correct single error only. In our implementation, copy A codeword is chosen to be decoded, thus, blocks that process copy B codeword including the register array and JTEC-SQED decision logic can be disabled to save power. In S_SECDED mode, blocks related to codeword correction (i.e. error correction and syndrome calculation) and retransmission request signal generation (i.e. odd/even and decision logic SECDED) are active. In S_SEC mode, blocks related to codeword correction are active while other blocks including 1bit in copy A register array are disabled. Mode [1] control signal together with signal from JTECSQED Decision Logic block select decoded data from corrected copy A when in S_SECDED and S_SEC mode or either corrected copy A or B in D_SECDED mode. The retransmission request signal is selected from respective decision logic of JTEC-SQED or SECDED block and in the case of S_SEC, value of 0 is inserted, all controlled by the two Mode signals. Noise behavior can be monitored by counting the number of errors affecting a victim wire working in half the voltage swing of normal wires [1][13][14] as shown in Fig. 1(d). Reducing VSW amplifies the number of detectable errors over a fixed time window according to (1), enabling quick noise detection. Larger time window increases the decision accuracy at the cost of larger error and sampling counters and delayed response. Alternating zeros and ones are sent over the victim wire and monitoring block compares the detected errors with threshold values to control Mode signals. III.

RELIABILITY

Bus lines are affected by different noise sources manifesting as errors. Wire error probability can be estimated by modeling the noise sources as Gaussian noise source having normal distribution of σN2 variance under wire voltage swing of VSW [1]: 𝑉𝑉𝑆𝑆𝑆𝑆 𝜀𝜀 = 𝑄𝑄 � � 2𝜎𝜎𝑁𝑁

where

𝑄𝑄(𝑥𝑥) =

1

√2𝜋𝜋

∞ −𝑦𝑦 2 2 𝑥𝑥

� 𝑒𝑒

𝑑𝑑𝑑𝑑

(1)

On chip communication reliability can be assessed using the mean time to failure (MTTF). This metric can be measured using the residual word error probability, Pres, which is the probability that the decoder accepts a word having one or more errors as they pass undetected in the first transmission or during the retransmission, thus Pres can be given by [13]: 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟 =

𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 1 − 𝑃𝑃𝑟𝑟𝑟𝑟𝑟𝑟

(2)

where Pund is the word undetected error probability, Pret is the retransmission probability and Pund+Pret≤1. Each coding scheme has different Pund model proportional to its detec-

Fig. 2. Residual word error probability as a function of noise deviation, σN . Wire voltage swing, VSW =1V.

tion/correction capability. For DAP, JTEC, and JTEC-SQED, the undetected error probabilities are as follows [6, 12]: 3𝑘𝑘(𝑘𝑘 + 1) 2 𝜀𝜀 2 2𝑘𝑘 + 2ℎ + 1 4 𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 −𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽 = � � 𝜀𝜀 4 2𝑘𝑘 + 2ℎ + 2 5 𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 −𝐽𝐽𝐽𝐽𝐽𝐽𝐽𝐽 −𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 = � � 𝜀𝜀 5 𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 −𝐷𝐷𝐷𝐷𝐷𝐷 =

(3) (4) (5)

The Pund of JTEC and JTEC-SQED represents the upper limit of undetected error probability assuming all four errors in JTEC are wrongly corrected and all five errors in JTEC-SQED are wrongly corrected or undetected. For S_SEC (Hamming SEC) and S_SECDED (Hamming SECDED), Pund is given in [15] and approximated for small ε to: 𝑘𝑘 + ℎ 2 𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 −𝐻𝐻𝐻𝐻𝐻𝐻 −𝑆𝑆𝑆𝑆𝑆𝑆 = � � 𝜀𝜀 2 𝑘𝑘 + ℎ + 1 3 𝑃𝑃𝑢𝑢𝑢𝑢𝑢𝑢 −𝐻𝐻𝐻𝐻𝐻𝐻 −𝑆𝑆𝑆𝑆𝑆𝑆𝐷𝐷𝐷𝐷𝐷𝐷 = � � 𝜀𝜀 3

(6) (7)

For the FEC-based schemes, Pret = 0, while for Hamming SECDED and JTEC-SQED it is proportional to ε2 and ε4 respectively, which can be neglected for small values of ε. Fig. 2 shows the achieved residual error probability for the different schemes working at VSW=1V at different noise deviations, σN. Under iso-VSW, different error protection strengths lead to range of tolerable noise level. JTEC-SQED achieves the highest reliability as it has the lowest residual error probability owing to its higher error detection represented by the Pund being proportional to ε5. Both DAP and Hamming SEC achieves similar reliability level due to ability to correct single error. Hamming SECDED provides intermediate protection between Hamming SEC and JTEC-SQED. IV.

RESULTS

To evaluate the proposed scheme, it is compared to three schemes: DAP, JTEC, and JTEC-SQED considering NoC communication between two routers. A 32-bit flit size is assumed, passing through a 3-stage pipeline: encoder, link traversal, and decoder; one cycle per stage. A target reliability of Pres=10-18 results in about 65 days MTTF for 8×8 mesh NoC running at 800 MHz frequency. Every two neighbor routers share one monitoring block in the adaptive scheme. Fig. 3(a) shows the achieved residual word error probability with increased noise deviation, σN for the different schemes.

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Fig. 3. (a) Residual word error probability as a function of noise deviation. Voltage swing, VSW for DAP, JTEC, and Adaptive (all modes) are 1.577V, 1.144V, and 1.032V respectively. (b) Average packet latency as a function of injection load for noise deviation 0 V to 0.12 V (8x8 mesh, 4 stage router, and bernoulli injection). -

Each scheme is designed to work at VSW that achieves Pres=10 18 at a maximum σN of 0.12V, as detailed in Table I. For the adaptive scheme, all modes are designed to work in the voltage swing at which D_SECDED mode achieves the target Pres at 0.12V noise deviation. Each mode can maintain the minimum target reliability Pres≤10-18 up to certain σN as indicated by the intersection of the modes' residual word error probability graph with the horizontal line. The S_SEC mode can achieve Pres≤10-18 for σN up to 0.079 V. Above this noise deviation level, the scheme must switch to higher detection mode (i.e. S_SECDED) that maintains the target reliability for σN up to 0.097V. For higher σN, the scheme switches to D_SECDED mode that can achieve the target reliability up to the maximum noise deviation designed for (i.e. σN=0.12V). Thus, the switching points between the three modes are the noise deviations, σN1=0.079V and σN2=0.097 V. Error threshold = BER × Sampling window, where BER is found using (1) for σN1 and σN2 at VSW=0.51V. For a 14-bit sampling counter (i.e. 214 cycles sampling window) the two thresholds corresponding to σN1 and σN2 are 10 and 69 errors respectively, thus requiring a 7-bit error counter. The negligible retransmission effect in all considered schemes led to similar network performance as shown in Fig. 3(b). The figure also shows how network latency is increased when coding is incorporated due to the added encoding and decoding pipeline stages per router. The different schemes were implemented in Verilog HDL and verified using ModelSim. The encoders/decoders were synthesized for 1.1 V supply voltage, 800 MHz target operating frequency using Synopsys Design Compiler with 45-nm Nangate library. Table I compares the number of wires for the TABLE I. LINK VOLTAGE SWING, MAXIMUM NOISE DEVIATION, NUMBER OF WIRES, AREA, AND CODEC POWER FOR DIFFERENT SCHEMES. VSW FOR DAP, JTEC, JTEC-SQED ARE CALCULATED AT TARGET PRES=10-18 VSW Max. noise No. of (V) dev. (V) wires DAP 1.577 0.12 65 JTEC 1.144 0.12 77 JTEC-SQED 1.032 0.12 78 D_SECDED mode 0.12 78/78* S_SECDED mode 1.032 0.097 39/78* S_SEC mode 0.079 38/78* Noise Monitor 0.51 1

Adaptive

Scheme

Area (µm2) Power (mW) Enc. Dec. Enc.

438 607 0.64 537 1128 0.81 938 1272 1.78 1.98 1133 1287 1.94 0.89 0.798 269.7 0.01

Dec.

0.97 1.65 1.89 2.00 1.20 1.18 0.13

*active/total

different schemes, including the number of switching wires (active) as compared to the total number of wires for the adaptive scheme. The synthesized codec area of the proposed scheme, including the noise monitor, is only 15.6% higher than the original JTEC-SQED scheme as shown in Table I due to the careful design of the reduced protection modes allowing hardware resource sharing. In addition to the noise monitor, this overhead comes from the additional circuitry of the crosstalk control and configuration hardware on the encoder and decoder respectively, and the clock gating at the encoder and decoder. In general, the FEC-based schemes (i.e. DAP and JTEC) have smaller encoder area since no retransmission buffers are required. The average link power can be evaluated using [16]: 1 2 𝑃𝑃𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 = (𝐿𝐿 ∙ 𝐶𝐶𝐿𝐿 ∙ 𝛼𝛼𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤 + (𝐿𝐿 − 1) ∙ 𝐶𝐶𝐶𝐶 ∙ 𝛼𝛼𝐶𝐶 ) ∙ ∙ 𝑉𝑉𝑆𝑆𝑆𝑆 ∙ 𝑓𝑓 2

(8)

where L is the number of wires in the link, CL and CC is the wire self capacitance and coupling capacitance between wires respectively, α wire and α C is the wire self-transition and coupling capacitance transition activity factor respectively, VSW is the wire supply voltage, and f is the operating frequency. Based on the predictive technology model [17] and using 45nm technology interconnects of 0.077µm width and spacing, 0.18 µm thickness, 0.11 µm height, and 3.1 dielectric constant, the self and coupling capacitances were obtained. The evaluation considers 1mm to 5mm link lengths. For the adaptive scheme, runtime noise of σN=0.079V, 0.097 V, and 0.12V respectively for the three modes are used for power estimation while non adaptive schemes are independent from noise level. As indicated by Fig. 4(a), DAP has the highest total power consumption due to its higher VSW which results in high link power consumption. Although JTEC and JTEC-SQED have higher codec complexity as compared to DAP, they achieve an overall power savings of 28.5% and 31.2% respectively at 3mm link length. Hardware sharing, induced by careful design of the different protection modes, limits the power consumption of the adaptive scheme including the noise monitor, in D_SECDED mode, to 3.4% higher than the original JTECSQED. On the other hand, S_SECDED and S_ SEC modes achieve power savings of 14.1% and 25.3% respectively, as compared to the original JTEC-SQED, and larger savings are achieved with respect to DAP of 40.9% and 48.6% respectively at 3mm link length. At longer link length (i.e. 5mm), the adaptive scheme achieves larger power savings as compared to DAP with 36.4%, 46.8%, and 52% for D_SECDED, S_SECDED, and S_SEC modes respectively. On the other hand, shorter link length (i.e. 1mm) limits the savings of low VSW operation since the codec complexity overhead dominates the total power consumption. With respect to DAP, D_SECDED mode results in 1.2% overhead, whereas S_SECDED and S_ SEC modes achieve 17.4% and 35% savings respectively. The link length affects JTEC and JTECSQED power consumption as well, increasing the savings over DAP from 15.0% and 4.7% at 1 mm length to 31.9% and 37.9% at 5 mm length respectively. The reduced power consumption in S_SECDED mode as

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Fig. 4. (a) Power consumption of the different coding schemes (including link, encoder, and decoder) for three different link lengths considering 0.12V estimated maximum noise deviation. (b) Power consumption of the different coding schemes (including link, encoder, and decoder) for three different estimated maximum noise deviations considering 3 mm link length. (c) Power consumption and saving breakdown of the three modes in Adaptive scheme normalized to the total power of D_SECDED mode for three different link lengths considering 0.12V estimated maximum noise deviation.

compared to D_SECDED mode comes from two sources. The first source is the reduced number of switching wires, 39 compared to 78 in D_SECDED mode, which reduces the link power consumption by 14.9% as shown in Fig. 4(c). The second source is the reduced decoder operations through disabled hardware blocks that process copy B codeword leading to 39.7% reduction in the decoder power. Clock gating the registers also leads to non-switching of many parts of the decoder combinational logic, which contributes to this large reduction. As a result, S_SECDED enjoys 17% power savings when compared to the D_SECDED mode at 3 mm link length. Since the S_SEC mode is a FEC-based scheme, clock gating the retransmission buffers leads to 55.1% reduction in the encoder power when compared to both S_SECDED and D_SECDED modes. A small reduction of 2.6% in link’s power as compared to S_SECDED mode is achieved due to the unused check bit in the link. At the decoder side, the Odd/Even module, SECDED Decision Logic module, and one flip-flop are disabled leading to 1.7% power reduction with respect to S_SECDED mode. At short link lengths (i.e. 1mm), the codec represents large portion of the total power, thus power saving shown in Fig. 4(c) are mainly contributed by the codecs. As the link length increases, the link power dominates and thus power savings are largely influenced by the link. From another perspective, the estimated maximum noise deviation governs the minimum VSW required to achieve the target reliability, Pres. Higher σN enforces the use of higher VSW, which in turn quadratically increases the link power consumption. Therefore, schemes with lower VSW benefit more at higher estimated σN since their power savings will be higher as shown in Fig. 4(b). The savings of the highest and lowest protection modes of the adaptive scheme, including the noise monitor, at σN=0.08V are 8.8% and 39.6% with respect to DAP respectively. These savings increase to 37.2% and 52.4% at σN=0.16V. V.

CONCLUSIONS

Crosstalk aware multi-bit error detection/correction coding schemes suffer from high power consumption as they are designed for worst-case noise conditions. This paper proposed a coding scheme that jointly provides crosstalk avoidance and adaptively selects the level of error protection based on noise conditions. It was shown that working in the reduced error

protection mode achieves noticeable power savings of 25.3% at 3 mm wire length. Adding this adaptivity incurs area and power consumption overhead of 15.6% and 3.4% respectively. It was noted that higher protection schemes are more effective at higher noise levels as they achieve higher power savings. REFERENCES [1] [2] [3] [4]

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2015.2483379, IEEE Transactions on Circuits and Systems II: Express Briefs

1549-7747 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.