An FPGA based PWM Control for Single-Phase Five-Level Nguyễn Văn Nhờ
Vũ Duy Nhất
Nguyễn Hoài Sơn
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Department of Electrical and Electronics Engineering Ho Chi Minh City University of Technology Abstract — In many applications that need high voltage and high current, Multilevel inverter is chosen due to their advantages of lower THD, lower EMI generation and higher quality of output waveform. However, some problems exist because of their complex computation schemes and topology constructions. To solve the problems, field programmable gate array (FPGA) is chosen for hardware implementation of control circuit. In this paper, an FPGA based PWM control for Single-Phase Five-Level Inverter is presented. The detail design of FPGA is discribed and experiment results are shown to illustrate its efficiency.
FPGA are implemented in [6] [7] [8]. In this paper, FPGA is using to control Single-Phase Five-Level Inverter with the integrating of dead-time generation and dead-time compensation. The experiment results are presented to demonstrate the efficiency of design. II.
CARRIER BASED PWM METHODS FOR CONTROLLING SINGLE-PHASE FIVE-LEVEL INVERTER
A. Single-Phase Five-Level Inverter Topology
Keywords: Carrier based PWM, Single-Phase Five-Level Inverter, Three-Level NPC Inverter, Deadtime compensation, FPGA.
I.
INTRODUCTION
The classic two-level inverter has been used in enormous industry applications. However, the demand of higher power performance to drive high-power systems result in two main research tendencies. One of them is multilevel inverters introduced in paper [1] [2]. These multilevel inverters are highly competing with the conventional inverter using highpower semiconductors. The topologies of multilevel inverter have several advantages such as lower THD, lower EMI generation, better output waveform and higher efficiency for a given quality of output waveform [3] However, an inevitable delay in calculating and applying the switching states to the inverter exists in a full digital system due to their complex computation schemes or predictive current controllers [4]. Therefore, the achieved samping frequency in implemented system is limited. Moreover, the large number of transistors in the multilevel inverter topologies causes a large demand of peripheral to control (I/O ports and PWM modules). To cope with this problem, specific digital hardware technology such as FPGA can be used as an alternative digital solution to ensure fast processing operation [4]. The application of field programmable gate array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density [5]. It is chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can ensure the accuracy of the instants that driving signals are generated [5]. Many experiments using
T21
T41
T11
T31
Vd A1
IA
T22
A2 R-L Load
T42
Vd T12
T32
Figure 1. Single-Phase Five-Level Inverter
Fig. 1 shows the topology of Single-Phase Five-Level inverter. This topology consists of Three-level NPC inverters which are connected through one phase R-L or motor load. Notably, they are supplied with dual DC source fed by passive rectifiers. In Fig. 1, since the transistors are always switched in pairs, the complement transistors are labeled Ti and T’i accordingly. This inverter consists of 8 IGBTs which are switched based on general rules as:
Ti + T’i = 1
(1)
It can be seen that the Single-Phase Five-Level Inverter is considered as combination of two Three-level NPC Inverters which are shown in Fig. 2. The output voltage of NPC Three-Level NPC Inveter is given by (2):
VA1G = (T1 + T2 ).Vd
(2)
B. Carrier based PWM method This inverter topology is controlled using the sine-triangle modulation. Therein, modulating signals are compared with certain triangle waveforms to create respective PWM control. Based on table I, controlling the Single-Phase Five-Level inverter consists of generating switching signals for both threelevel NPC Inverter. With three-level NPC inverter, the Coherent Pulse Width Modulation CPWM is employed. A modulating signal Ums will be compared with two carrier based signals C1 and C2 in Fig. 3 to create switching pulses S1, S2 for transistor T1 and T2 as well as their components. Note that in this paper, S1 and S2 are denoted the ideal switching signals respectively for transistors T1 and T2 in Fig. 1. It’s same for others.
T21 Vd T11 A1 T22 Vd T12 G Figure 2. NPC Three-Level Inverter
Then the relationships between output voltage VA1G and switching state sequences are shown in Table I. TABLE I.
THE RELATIONSHIPS BETWEEN SWITCHING STATE SEQUENCES AND VA1G
T2
T’1
T’2
0
0
1
1
1
0
0
1
2Vd
1
1
0
0
1 C1
C1 Ums
0
0 0
To calculate the output voltage VA1A2 of Single-Phase FiveLevel Inverter, the combination of two NPC legs give equation (3):
0
S2=0 1
0
(3)
= (T1 + T2 - T3 - T4 ).Vd All switching states and their corresponding output voltage are in Table II.
0
S1
1
0
1
S2 S1=1
2Vd Vd
VA1A2 =(VA1 -VA2 ) = (T1 + T2 ).Vd - (T3 + T4 ).Vd
C2 Ums
T1
0
2 C2
1
VA1G Vd
2
VA
Vd
VA 1 0 IA < 0
0 Vd Vd 2Vd
↑ ↓ ↑ ↓
According to the effects of dead time shown in Table V, the main principles of compensation are through expanding or narrowing output voltage pulse width (denoted ↑ and ↓ respectively) based on the current directions. 2) Algorithm for dead time compensation in FPGA In the compensation principles, there are two kinds of changes in switching pulse width including adding or subtracting error voltage pulses with the width of D T (dead time) when the measured current IA is negative or positive respectively. The proposed dead time method (in the Fig. 11) is creating extended compensation pulses at the falling edge of original switching signals as well as narrowed compensation pulses at the rising edge of original switching signals. Then, these extended and narrowed pulses are utilized to modify the non-compensated signals to form compensated signals as in Table VI and Table VII4. And block diagram for the FPGA-based compensation technique is illustrated in Fig. 12.
TABLE VII.
PRINCIPLES FOR COMPENSATING OUTPUT VOLTAGE PULSE (NARROWED TYPE)
Control signal = 0
NonCompensated signals
Input Narrowed pulse
Extended compensation pulse
Extended Output
Output
0
0
0
1
0 -
1
0
1
1
1
0
Output = Input Xor Narrowed pulse ∆T
∆T
Narrowed compensation pulse
IV.
EXPERIMENT RESULTS
A. Deadtime genaration Compensated signal ∆T
∆T
Figure 11. The time diagram of the dead time compensation algorithm in FPGA
Deadtime set up Input pulse
Extended compensation pulse generator
CLK
Extended compensation pulse
Or
Deadtime set up
1 0
Narrowed compensation pulse generator
Output pulse
Narrowed compensation pulse
Figure 13. Experimental result of Dead-time generation (Yellow signal: original signal, blue signal: modified signal) Xor
Current direction
Control signal generator
Mode set up
Control signal
The Fig. 13 shows the experimental result of dead-time generation. It can see that the raising edge of modified signal (the blue signal) is delayed an interval from the raising edge of original signal (the yellow one). In this case, the dead-time interval is one micro second.
Figure 12. Block diagram for the FPGA-based compensation technique
The current value IA can be measured using current sensor and compared with a reference value to determine the current direction. Then the direction is transmitted into FPGA through ILoad pin. However, a simulation current signal can be replace the actual current value in compensation. It depends on External bit to verify which is used. TABLE VI.
PRINCIPLES FOR COMPENSATING OUTPUT VOLTAGE PULSE (EXTENDED TYPE)
Control signal = 1 Input Extended pulse Output 0
0
0
0
1
1
1
0
1
1
1
-
Output = Input Or Extended pulse
B. Deadtime compensation To test the dead-time compensation module, a test pulse is created. Its frequency is 12.5 kHz (period is 80us). The complement pulse is generated based on the test pulse. Then both of them are affected by dead-time before being taken into the driving circuit to drive transistors. The duty cycle of the test pulse is 50% (40us). It is also the expected duty cycle of output voltage. The test pulse and its complement pulse are exactly S1 and S’1 in Fig. 10 what control T1 and T’1 in Fig. 1. The Figures below show the experiment results, whereas: the yellow is test pulse S1, the blue is its complement pulse S’1 and the pink is actual output voltage which is controlled by S1. Fig. 14 and Fig. 15 are the results before using dead-time compensation. In this case, the test condition is carried on with positive current direction IA, so the duty cycle of output voltage is over 50%. The addition of duration is exactly dead-time interval of 3.3us (test condition dead-time value). Then the dead-time compensation is used and the duty cycle of output voltage is right 50% as the results in Fig. 16 and Fig. 17.
Figure 14. Test pulse (yellow) and its complement pulse (blue) in the test without dead-time compensation
Figure 17. Test pulse (yellow) and output voltage (pink) in the test with deadtime compensation
C. Carrier based PWM algorithm
Figure 15. Test pulse (yellow) and output voltage (pink) in the test without dead-time compensation Figure 18. Ouput voltage waveform (yellow) without R-L load
Figure 16. Test pulse (yellow) and its complement pulse (blue) in the test with dead-time compensation
Figure 19. Ouput voltage waveform (yellow) and current wavwform (blue) with R-L load
The Fig. 18 and Fig. 19 show the experiment results of system output. In Fig. 18, the output voltage VA1A2 is captured
without R-L load connection. Fig. 19 is the result with R-L load, so the current IA (the blue) and the voltage VA1A2 (the yellow) are captured simultaneously. V.
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CONCLUSION
The carrier PWM algorithm to control the Single-Phase Five-Level inverter has been reported in this paper. The implementation is designed and implemented using FPGA Spartan 3E. In addition, the dead-time generator and dead-time compensation are also integrated to make the system safe and increase the output quality. The experimental results clearly demonstrate the efficiency of the design.
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