Broadband Doherty Power Amplifiers Mohammadhassan Akbarpour, Mohamed Helaoui, and Fadhel M. Ghannouchi Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada. Email:
[email protected]
Main amplifier
Abstract — In this paper, the transformer-less loadmodulated (TLLM) architecture for designing broadband Doherty amplifiers is presented. In this architecture, the quarter-wave impedance transformers of the Doherty amplifier are not used. As a result, the design will be much more compact and large operational bandwidths can be obtained. The simulation results for an amplifier implemented using this architecture shows that drain efficiency of higher than 47% is obtainable at 6dB power back-off in 1.7-2.8GHz frequency range (50% fractional bandwidth). Index Terms — Broadband amplifier, Doherty amplifier, Efficiency, PAPR, Power back-off.
DM Input divider
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50Ω,λ/4 35Ω,λ/4 Input 50Ω,θ0
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Fig. 1. Doherty architecture. Main amplifier DM
I. INTRODUCTION
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The need for high capacity data transmission, lead to the use of spectrum-efficient modulation schemes. These signals have high Peak-to-Average Power Ratios (PAPR). Having high PAPR signals, the power amplifiers (PAs) should work at a certain amount of output power back-off (OPBO) to meet the linearity requirements. Working in OPBO, causes the PA’s efficiency to decrease drastically. Doherty amplifier is a very well-known architecture that can solve the problem of low efficiency at OPBO [1]. It works based on load modulation. A block-diagram of the Doherty amplifier is shown in Fig. 1. At lower powers, the load impedance seen by the main amplifier is considered to be 2Ropt in which Ropt is the optimum impedance which the main and the peaking amplifiers are designed for. When the input power increases, the current from the peaking amplifier causes the load impedance at the junction point (point J in Fig. 1) to increase and hence the load impedance seen by the main amplifier (point M in Fig. 1) will be decreased to Ropt because of the quarterwave impedance transformer at the output of the main amplifier. Based on load-line theory, it is expected that the load change from a high impedance to a low impedance cause the main amplifier to remain in saturation [2], but this is not the case in practical designs. The load-line theory is valid for the ideal transistors and at the drain level (point DM in Fig. 1), while in Doherty architecture, the load modulation is taking place at the output of the main amplifier (point M in Fig. 1). The effect of matching
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Input matching
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Fig. 2. TLLM architecture
network may alter the load modulation at the transistor’s drain level. Offset lines are usually added to the output of the main amplifier to compensate for the effects of the matching network [2,3]. Another limitation of the Doherty amplifier is its operational bandwidth. The presence of the quarter-wave impedance transformers and offset lines limit the operational bandwidth of the Doherty amplifier. Another limiting factor in the design of the Doherty amplifier is the quasi-open impedance needed at the output of the peaking amplifier at power back-off. It is not possible to have high output impedance at large bandwidth while having proper load impedance at the output of the peaking transistor. The peaking transistor should be able to deliver enough amount of output power to have proper load modulation for the main amplifier. II. BROADBAND TLLM ARCHITECTURE The TLLM architecture [4] solves the bandwidth limitation of the Doherty amplifier by completely
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removing the impedance transformers and offset lines from the Doherty architecture. In the TLLM architecture, the proper load modulation is obtained solely by the output matching networks. This architecture is shown in Fig. 2. The advantages of this architecture can be stated as follows: 1) As can be seen from Fig. 2, the amplifier can be designed for arbitrary complex (and frequency varying) load impedances. This is very important in design cases where the load impedance is the input impedance of an antenna. 2) No offset lines or quarter-wave transformers are used in this architecture, which means that the operational bandwidth of the amplifier is defined solely by the impedance matching networks. 3) The design is based on the realistic optimum impedances obtained from load-pull measurements or simulations from transistor’s nonlinear model. As a result, the design will be more realistic than using the simplified or idealized models and the measurement results will be closer to the simulations. 4) Since the TLLM architecture does not use quarterwave impedance transformers, the losses at the output of the amplifier will be lower than the Doherty amplifier. This helps in getting higher output power as well as higher efficiency. 5) In this architecture, there is no need for high output impedance at the output of the peaking amplifier. Instead, the output impedance should be such that the power leakage at back-off levels is minimized. The output impedance of the peaking amplifier can be a nearly reactive impedance which does not dissipate the RF power at power back-off. The output impedance of the peaking amplifier should be taken into account when designing the main amplifier.
Fig. 3. Load modulation in Doherty and TLLM architectures
architecture, the main amplifier will have 50Ω load impedance at power back-off. In the last 6dB power range, the load impedance will increase to 100Ω. The difference between these two load variations is because of the impedance inverter used in the Doherty architecture. Despite the completely different load modulation, the TLLM architecture will have similar performance compared to the Doherty architecture. Actually, the load impedance seen by the transistor is important in obtaining high efficiency at power back-off as well as high output power at peak power. In the TLLM architecture, the proper load modulation at the drain level is guaranteed by the output matching network. In both cases, the peaking amplifier, have infinite load impedance at power back-off since it does not draw current at back-off level. When the peaking amplifier starts to deliver current to the load, its load impedance begin to decrease. In TLLM architecture, the peaking amplifier’s load impedance at peak power will be 100Ω while in Doherty amplifier it is 50Ω due to the difference in the load seen at the junction (point J in Fig. 1 and Fig. 2). The load changes for both architectures are shown in Fig. 3. For TLLM architecture, when peaking amplifier has reactive output impedance (not quasi-open output impedance), there will be some current going into its output terminal. As a result, the load impedance seen by the peaking amplifier will not be infinite in this case. It will start from a finite reactive impedance at power backoff and it will reach to the impedance of ZL,pk=ZL(Im+Ip)/Ip at peak output power. Im and Ip are the output currents from the main and peaking amplifier at peak power respectively.
III. LOAD MODULATION IN TLLM ARCHITECTURE Since the TLLM architecture does not have the quarterwave impedance transformer, the load modulation at the output of the main amplifier is different from the Doherty amplifier. To show the difference, consider the two architectures shown in Fig. 1 and Fig. 2 with the same load impedance of 50Ω. Also for comparison consider that the two branches have the same amount of output powers at peak input power and the peaking amplifiers have high output impedances. In this case, for the Doherty amplifier, the main amplifier will have 100Ω load impedance at power backoff and in the last 6dB output power range; the load impedance will be decreased to 50Ω. In the TLLM
IV. DESIGN EXAMPLE In this section a design example simulation of the TLLM amplifier is shown using the design procedure presented in [4]. To benchmark this architecture with the Doherty amplifier, we used the same devices and working
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Fig. 4. Schematic of the simulated TLLM power amplifier
conditions as what is used in [5]. In [5], by modifying the output combining network, a broadband Doherty amplifier is designed which gives the largest published fractional bandwidth for the Doherty amplifier so far. The 10-Watt GaN CGH40010F device was used as the main transistor and the 25-Watt GaN CGH40025F device was used as the peaking transistor. Both transistors are from CREE, Durham, NC. The nonlinear models provided by the manufacturer were used for the simulation in Agilent ADS. The bias points were selected to be the same as what is used in [5] for comparison reason. Using the design procedure of [4] and implementing the matching networks by the lumped elements, the amplifier’s schematic shown in Fig. 4 is obtained. As can be seen from this figure, the output matching network of the main amplifier is very compact and simple. It does not use the quarter-wave transformer or the offset lines. As a result, the losses associated to the output matching network will be much lower than the Doherty architecture. The simulated small-signal gain, the maximum output power and the drain efficiency at 6dB power back-off of the amplifier are shown in Fig. 5. The gain roll-off seen in the small signal gain can be easily avoided by modifying the main amplifier’s input matching network if needed. The maximum output power of the amplifier is higher than 42dBm or 16Watts and the drain efficiency is higher than 47% in the 1.7-2.8GHz frequency band. Comparing the drain efficiency with the simulation results shown in Fig. 17 of [5] shows that using TLLM architecture, similar fractional bandwidth is obtained.
Fig. 5. Simulated performance of the TLLM amplifier shown in Fig. 4
design criteria in this architecture are less stringent than the Doherty architecture, allowing wide bandwidths to be obtained from this architecture. REFERENCES [1] W. H. Doherty, "A New High Efficiency Power Amplifier for Modulated Waves," Proc. IRE, vol. 24, no. 9, pp. 1163– 1182, Sep. 1936. [2] B. Kim, J. Kim, I. Kim, J. Cha, "The Doherty power amplifier," IEEE Microw. Mag., vol. 7, no. 5, pp. 42–50, Oct. 2006. [3] R. Darraji, F. M. Ghannouchi, "Digital Doherty Amplifier With Enhanced Efficiency and Extended Range," IEEE Trans. Microw. Theory Tech., vol. 59, no. 11, pp. 2898– 2909, Nov. 2011. [4] M. Akbarpour, M. Helaoui, F. M. Ghannouchi, "A Transformer-Less Load-Modulated (TLLM) Architecture for Efficient Wideband Power Amplifiers", IEEE Trans. Microw. Theory Tech., vol. 60, no. 9, pp. 2863-2874, Sept. 2012. [5] K. Bathich, A. Z. Markos, G. Boeck, "Frequency Response Analysis and Bandwidth Extension of the Doherty Amplifier," IEEE Trans. Microw. Theory Tech., vol. 59, no. 4, pp. 934–944, Apr. 2011.
VII. CONCLUSION The TLLM architecture is capable of designing broadband amplifiers having high efficiency at power back-off. This architecture allows for designing more compact designs than the Doherty architecture. Also the
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