2014 First International Conference on Green Energy ICGE 2014
Performance Assessment of Conventional Modulation Schemes in Terms of Conducted EMI Generated by PWM Inverters Mohamed Salem (1), Mahmoud Hamouda(2), and Jaleleddine Ben Hadj Slama (3) (1)(3) Research unit SAGE, ENISo, Sousse University, Tunisia. (2)Research laboratory SIME, ENSIT, Tunis University, Tunisia. (1)
[email protected], (2)
[email protected], (3)
[email protected]
Abstract: This paper proposes a comparative study between the performance of sine-triangle, third harmonic injection and space vector modulation schemes in terms of conducted (common and differential mode) EMI generated by two-level three-phase voltage source inverters. For this purpose, an experimental setup has been built to measure in time domain the conducted disturbances propagated back into the DC source. The experimental results analyzed in both time and frequency domains showed that these disturbances are effectively related to the applied modulation scheme.
sources and effects on the vicinity systems. In this framework, many research papers studied the effect of power topologies, control parameters and switches technologies on EMI disturbances. In [1], a comparative study between different multilevel topologies in terms of conducted EMI has been proposed. In [2], the authors developed a detailed analysis of EMC caused by multilevel inverters feeding variable speed motors. In [3] and [4], an optimized multilevel topology that allows reducing the common mode voltage was proposed. In [5], a comparative study between FLC (flying capacitors) and NPC (Neutral Point Clamped) multilevel converters showed that the NPC topology is less disturbing in terms of common mode voltages. An optimized modulation scheme has been proposed in [6] so as to reduce the common mode voltage. This work is conducted with the aim to achieve a comparative study between the performance of three conventional PWM schemes (SPWM, THIPWM, and SVPWM) in terms of conducted disturbances (common and differential mode voltages). Therefore, an experimental setup has been developed to measure the disturbance generated by each modulation method. The obtained results are analyzed in the frequency domain so as to deduce the less disturbing technique. This paper is thereafter organized as follows; in section II, a brief review of SPWM, THIPWM and SVM modulation schemes as well as their implementation on an embedded DSP is proposed. Section III gives an overview of the experimental setup used in the present work. The experimental results are discussed in section IV. Finally, some conclusions are given in section V.
Keywords: EMC, EMI, PWM converters, LISN, modulation technique, PWM, SVPWM, THIPWM, DSP. EMI EMC LISN SPWM THIPWM SVPWM
NOMENCLATURE Electromagnetic interference. Electromagnetic compatibility. Line impedance stabilization network. Sine-Triangle Pulse Width Modulation. Third Harmonic injection PWM Space Vector Pulse Width Modulation I. INTRODUCTION
Nowadays, the fast development of power electronic systems greatly increases the sources of electromagnetic disturbance caused by high commutation frequency of power switches. Therefore, the investigation of disturbances caused by such circuits becomes a mandatory task to comply with international standards regarding the generated EMI. In this framework; the experimental measurement of conducted EMI has received a considerable attention by many research laboratories. The research works were realized with the aim to characterize the impact of conducted electromagnetic disturbances generated by high switching frequency static power converters. In particular, significant interests were paid to measure the conducted EMI generated by different topologies of three-phase current and voltage source converters. The three-phase voltage source converters which remain among the most popular conversion structures are widely used in industrial applications such as variable speed drivers, active filters, STATCOMs, UPS, and distributed power generation systems (DPGS). Owing to the high switching frequency operation demanded by modern applications, unwanted conducted disturbances are provided and thus should be measured and analyzed to identify their
II. PULSE WITH MODULATION SCHEMES AND THEIR DSP BASED REAL TIME IMPLEMENTATION
Three-phase voltages inverters consist of six transistors (with six freewheeling diodes placed in anti-parallel) to form three half bridges as depicted in Fig.1. Each middle point of a half bridge is connected to one phase of the induction motor. The modulation scheme consists in generating at any time the opportune gating signals for the six transistors such as the amplitude and frequency of the fundamental output voltages (VA, VB, and VC) follow their target references. In this framework, various modulations techniques have been
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Fig.3 below, are depicted the modulation signals as well as the gating pulses of transistors TAH, TBH and TCH.
addressed in literature so as to achieve the aforementioned objective. Among them the Sine-Triangle Pulse Width Modulation (SPWM), the Third Harmonic Injection (THIPWM) and Space-Vector Pulse Width Modulation (SVPWM) techniques are the most useful for high switching frequency operation. The operational principle of these algorithms will be briefly reviewed in the subsequent sections.
⎧ ⎪V = m sin (2π f t ) + k sin (2π (3 f )t ) o o ⎪ AO ⎪ 2π ⎞ ⎛ ⎟ + k sin (2π (3 f o )t ) ⎨V BO = m sin ⎜ 2π f o t − 3 ⎠ ⎝ ⎪ ⎪ 4π ⎞ ⎛ ⎟ + k sin (2π (3 f o )t ) ⎪V CO = m sin ⎜ 2π f o t − 3 ⎠ ⎝ ⎩ VA*
(1)
VC*
VB*
Fig.1 power circuit of a three-phase voltage source inverter feeding an induction motor
A. Sine Triangle based PWM algorithm (SPWM) Fig. 3 Synthesize of gating signals for TAH, TBH and TCH using the THIPWM scheme
The gating signals are obtained by comparing a system of three-phase low-frequency waveforms (modulating signals) to a high-frequency triangular signal (carrier). In figure 2, is depicted the gating signals of transistors TAH, TBH, and TCH. As can be seen, if the magnitude of the reference signal Vx* (x=A,B,C) is superior to the one of the triangular waveform, TXH (x=A,B,C) is turned on otherwise it is turned off. Moreover, at any time, two transistors of the same leg commutate complementary to the switching period with turn-on delay times of few microseconds to avoid unwanted short-circuits across the DC bus. VA*
VB*
C. Space Vector Pulse Width Modulation algorithm(SVPWM) This modulation scheme is described in [7] and [8]. According to the commutation rule of power switches, 8 possible switching configurations can be performed at any time. Among them 6 active vectors (V1 to V6) and two zero vectors (V0 and V7) can be obtained as depicted in Fig.4 where the zero vectors are omitted for clarity purpose. At any time the instantaneous target output voltages (VA*, VB*, and VC*) are represented in the complex plane by a space vector defined as:
VC*
* Vo
j 2⎛ = ⎜V A* + VB* e 3⎜ ⎝ V3
2π 3
4π 3
⎞ ⎟ ⎟ ⎠
(2)
* Vo
d 1 I V1
V5
Fig. 2 Synthesize of gating signals for TAH, TBH and TCH using the SPWM scheme
j
V2 d 2 I V2
V4
+ VC* e
V1
V6 *
Fig. 4 Synthesize of the output voltage reference vector V o using the SVPWM method
B. Third Harmonic injection PWM algorithm (THIPWM) Compared to the SPWM algorithm, the THIPWM method consists in injecting the third harmonic in the expression of the modulating signals as illustrated in equation (1) where m is the modulation factor, f0 is the fundamental frequency, and k = 0.1925 is the third harmonic amplitude. The value of the maximum modulation factor is therefore increased from m = 1 to m =1.15 leading to a better utilization of the DC bus. In
The reference space vector is thereafter synthesized at each sampling period by using a combination of the twoadjacent active vectors which are impressed with duty cycles d1 and d2 as well as a zero-vector impressed with a duty cycle named d0. Fig.5 below gives a general switching pattern when the reference space vector is lying within sector one of the complex plane.
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d0
d1
d2
d0
d2
d1
d0
4
2
2
2
2
2
4
VC*according to equation (2). Next, the operating sector of the complex plane is deduced. After that, the numerical values of duty cycles d1, d2, and d0 are determined. The final step consists in calculating the opportune values that should be downloaded into the three compare registers (compare units 1, 2, 3). To explain this operation, assume that the space vector is lying within sector 1. According to Fig.5, it follows that the relative turn-on times of TAH, TBH and TCH are (d1+d2+ d0/2), (d2+ d0/2), and (d0/2). Accordingly, the values assigned to compare units 1, 2, 3 are (d0/2), (d1+ d0/2), and (d1+d2+ d0/2) respectively.
Fig. 5 Converter’s switching patterns when the output voltage reference vector is assumed to be lying within sector one of the complex plane
D. DSP based real time implementation The modulation schemes are implemented in real time using a 32-bit fixed-point DSP (TMS320F2812 of Texas Instruments) operating at 150 MHz. This family of DSPs includes two identical event-manager modules namely EVA and EVB. In Fig. 6 is depicted a general block diagram of the event-manager module EVA which can generate 5 independent 16-bit PWM signals on output channels namely PWM 1, 3 ,5, T1PWM, and T2PWM respectively. Three additional PWM signals complementary to PWM 1, 3, 5 could also be generated on output channels PWM 2, 4, 6 [9]. For further explanation of the event manager modules operation the lecturer could refer to [10].
R
PIE 2
Control registers
TCLKINA/ TDIRA ADC start
Timer 1 compare unit
Output logic
T1PWM/T1CMP
GP Timer 1
Compare unit 1
Data bus
Compare unit 2 Compare unit 3
PWM Circuits
PWM1
Output logic
PWM2 PWM Circuits
PWM3
Output logic
PWM4 PWM Circuits
Timer 2 compare unit
Output logic
PWM5
Output logic
PWM6
T2PWM/T2CMP
GP Timer 2
The implementation of the SPWM and THIPWM algorithm is achieved as follows; the counter associated to general purpose timer 1 can operate in three different modes; counting-up, counting-down, and counting-up/down. Hence, in order to emulate the carrier signal used for the SPWM, timer 1 is programmed in up/down counting mode. Thereafter, for each sampling period the counter starts counting up from zero. Once the timer counter matches the “Period Compare Register” value, it starts counting downward. In this case, the switching frequency of the PWM signal will depends upon the value stored in timer 1 “Period Compare Register” as well as the period at which this timer is clocked. The generation of the PWM signal on the output PWM1 will occurs as follows; assume that the output PWM1 is feeding the gate signal of TAH. At any sampling time the instantaneous amplitude of the modulating signal corresponding to VA* will be downloaded into the compare unit1 register. Once the first match occurs during the counting up, the output PWM1 will toggle from low to high logic state. For the second match occurring during the counting down, the PWM1 signal will toggle to zero logic state. The output PWM2 which is complemented to PWM1 will thereafter feed the gating signal of TAL. In a similar manner, the remaining PWM signals for the others transistors are constructed by calculating at any sampling period the instantaneous amplitude of the modulating signals corresponding to VB* and VC*.
MUX
Capture unit
CLK DIR
QEP
CAP1/QEP1 CAP2/QEP2 CAP3/QEP3
Fig. 6 Block diagram of the EVA module [10]
III.
OVERVIEW OF THE EXPERIMENTAL SETUP
A simplified schema and a photo of the experimental system used in this work are shown in Fig.7a-b below. It consists of a three-phase delta-connected induction motor fed by a three-phase two-level voltage source inverter. The power circuit of the inverter is built using MOS transistors type (Nchannel IRFP450). One should underline that the effect of power transistor technology on the EMI disturbance is beyond the objective of this paper; however a detailed analysis was already investigated in [11]. The transistors’ gates are controlled using a TMS320F2812 DSP from Texas Instruments via HCPL3120 opto-drivers. Code Composer Studio software is used to control the whole system via a parallel cable. For all tests, the target frequency of AC output waveforms is 50Hz while the modulation factor is fixed to m = 0.7. The switching frequency of the power transistors is 2.2 kHz with a 2.5 µs turn-on delay time. The measurement of conducted disturbances is performed by using a LISN connected between the converter’s rear end and the DC supply. This LISN is similar to a filter that decouples the DC source from the converter’s power circuit, when common and differential mode disturbances exist. It is also used to measure the common and differential mode voltages. Moreover, this filter should provide constant impedance
The implementation philosophy of the SVPWM algorithm is quite different. First, we should calculate the space vector equivalent to the target output voltages VA*, VB*, and
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A. Representation in time domain Fig.9 depicts the DC voltage waveform used for all tests. It includes an unwanted low frequency ripple of 100 Hz. This ripple is due to the AC/DC conversion of grid voltages. 180
Amplitude (V)
between the inverter’s rear end and the ground over the frequency range [10 kHz - 100MHz]. A simplified diagram of the LISN is given in Fig.8. Its main components are sized as follows: • Two coils (50µH) • Two capacitors (220nF-250 V). • Two resistors (50Ω) • Two capacitors (10µF)
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100
60
20 -0.01
-0.006
-0.002
0
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0.006
0.01
Time (s) Fig.9 Voltage across the DC bus
Fig. 10 depicts the line-to-line modulated output voltage VAB and the load current iA. The average value of the voltage VAO obtained with the SPWM and SVPWM algorithms are shown in Fig.11 and Fig.12 below. The obtained waveforms are quite similar to those expected by theory which emphasizes the correct implementaion in real time of the modulation schemes. iA VAB
Amplitude (100V/div), (1.5 A/div)
Fig. 7.a Simplified schema of the experimental setup including the inverter, control board, LISN, and induction machine.
-0.02
-0.01
0 Time (s)
0.01
0.02
Fig. 10 Line-to-line modulated output voltage and load current 80
Fig. 7.b Photo of the experimental setup
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40 20 0 -20 -40 -60 -80
0
0.01
0.02
0.03
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Time (s)
0.05
Fig. 11 .Average voltage VAO obtained with the SPWM method 80 60
Amplitude (V)
40
Fig.8. Simplified schema of LISN filter
IV. EXPERIMENTAL RESULTS AND INTERPRETATIONS
20 0 -20 -40 -60 -80 0
In this section, experimental results are given in time and frequency domains while the comparative study between the three modulation schemes is achieved in terms of conducted EMI.
0.005
0.01
0.015
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0.025
0.03
0.035
0.04
0.045
Time (s)
Fig. 12 Average voltage VAO obtained with the SVPWM method
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0.05
In Figs 13-14, are depicted the load current waveforms. The zoom of Fig.14 shows 6 different high frequency transient disturbances over a switching period (about 454µs). In our opinion, the difference between the peak amplitudes of these transient currents is due to the fact that the parasitic components between the power transistors and DC source have not the same values.
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Amplitude (V)
240 180 120 60 0
2
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B. Representation and analysis in frequency domain Due to the limitation of time domain analysis to achieve an accurate comparative study between the performance of the modulation schemes, the above results are therefore transferred to the frequency domain so as to obtain the HF voltage harmonic spectrum. In Fig.17 and Fig.18 are shown the spectrums of conducted perturbations (common and differential modes) obtained with the three modulation methods. As well known, the frequency spectrum of interferences emitted by a power electronic circuit usually starts at the switching frequency (in our case 2.2 kHz) and have several noise frequency ranges. Therefore, from 2.2 kHz to few hundred of kHz, peak values are linked to chopping periods as well as the loading conditions. In this frequency range, the spectrum envelops decrease at -20dB/decade. Moreover, from about few hundreds of kHz to 50MHz, the phenomenon appears to be linked to switching transients. The latter, depends on the nature of switches, circuit’s topologies as well as the equivalent capacitances of non-linear components (power transistors and diodes). In this frequency range, the spectrum envelops decrease at –40dB/decade [12]. It should also be pointed out that frequency peaks (in the range of some MHz to several tens of MHz) included in the spectrums are quite equivalent to the resonant signals that appear in the waveforms illustrated in time domain. The spectrums of Fig.17 and Fig.18 show that the three modulation schemes have different spectral signatures. These spectrums are divided into two ranges:
-1
-2
-0.008
-0.004
0
0.008
0.004
Time(s) Fig. 13 Load currents obtained using SVPWM algorithm
0.4 0.3 0.2 0.1 0 -0.1
One switching period
-0.2 0
0.2
0.4
0.6
0.8
1
1.2
Time (s)
X 10
-4
Fig.14 Zoom over two switching periods of the load current waveform
Fig. 15 shows a gating pulse waveform synchronized with voltages Vrsilh and Vrsilb across the LISN resistors. As can be clearly observed, the conducted disturbances are inherently produced at the same time of power transistors’ commutations. One should also observe that the transient and resonant signals (produced by the commutation phenomenon) have different amplitudes and resonant frequencies. In Fig.16, are shown the voltages VDS (Drain-Source) obtained with the SPWM and SVPWM methods. The same phenomenon is observed, where transient oscillations are produced at the same time of transistors’ commutation. These voltage resonances are referred to the differences of potentials incurred at the time of the turn-on/off of active components.
SPWM THIPWM SVPWM
40
VGS
Vrsilh
Amplitude (dBµV)
100
Vrsilb
20
Amplitude (V)
4
Fig. 16 Voltage VDS obtained with SPWM (Red) and SVPWM (Blue)
1
-0.3
x 10-4
0
90 80 70 60 50
-20 -2
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Time(s)
6
40 2 10
8 x 10-4
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Frequency (Hz)
6
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Fig.17. Common mode voltage obtained with three modulation methods SVPWM (blue), THIPWM (Red), and SPWM (Black)
Fig. 15 VGS voltage synchronized with (Vr1 and Vr2) across the LISN resistors
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where the peak values of frequency are linked to chopping periods and loading conditions, the modulation methods have almost the same performance. In the second frequency range, varying from about few hundred of kHz to 50MHz, where the phenomena appears to be linked to switching transients, the SVPWM have the best performance in terms of conducted EMI. In a future paper, a theoretical study based on a high frequency model as well as SPICE based simulation tools will be performed to emphasize the effectiveness of the experimental results reported in this paper.
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SPWM THIPWM SVM
Amplitude (dBuV)
120 100 80 60 40 20 0 2 10
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Frequency (Hz)
VI.
Fig. 18 Differential mode voltage obtained with three modulation methods SVPWM (blue), THIPWM (Red), and SPWM (Black)
[1] M. Beltramini, L. Prissé, P. Asfaux, N.Roux, F. Richardeau, X. Roboam, F. Costa, B. Revol, "Comparison of different inverter architectures and controls in terms of conducted EMI," 2010 IEEE International Conference on Industrial Technology (ICIT), pp. 717-722, 14-17 March 2010.
In the first frequency range (from 300Hz to about 100kHz), the peak amplitudes are located at multiple values of the switching frequency (2.2kHz ,4.4kHz, 8.8kHz, …). The magnitude of the spectrum obtained with the SVPWM and THIPWM methods is slightly higher than the one obtained with the SPWM method. This difference is due to the presence of 3rd harmonic in the modulating signals. In the second frequency range, (from 500 kHz to 50MHz), one can clearly observe that the SPWM modulation method produces higher amplitude peaks than the THIPWM and SVPWM techniques in both differential and common mode voltages. The most significant peaks of frequency are located at 2MHz, 3.8MHz, 5.8MHz, 10MHz, 30MHz, and 48MHz. Moreover, in high frequency ranges, the SVPWM generates less conducted disturbances than the remaining two modulation schemes where the amplitude decrease can reach 12dBµV. Therefore, besides its high performance including a better utilization of the DC bus and the flexibility of generating the switching patterns, the SVPWM modulation method is superior to the SPWM and THIPWM techniques in terms of conducted disturbances. This difference in magnitude of common and differential mode voltage is due to the capability of the SVM method to achieve a flexible switching sequence. Indeed, an opportune distribution of the zero sequence vectors allows avoiding the simultaneous commutations of transistors along two different legs which reduces the common mode voltage amplitude [13]. V.
REFERENCES
[2] A. Videt, "Variateur de vitesse à impact électromagnétique réduit : onduleur multi niveaux et nouvelles stratégies de modulation," Thèse de doctorat, Lille, France, Dec. 2008. [3] P. K. Chaturvedi, Shailendra Jain, and Pramod Agrawal, "Harmonics and Common Mode Voltage Reduction in Multilevel SPWM Technique" India conference, INDICON 2008, vol.2, pp. 447 - 452 [4] Renge, M.M.; Suryawanshi, H.M.; Borghate, V.B.; Ramteke, M. R., "Multilevel Inverter to Eliminate Common Mode Voltage in Induction Motor Drives," IEEE International Conference on Industrial Technology, ICIT 2006, pp.2354,2358, 15-17 Dec. 2006 [5] Behrooz Moghimian Hoosh, Rabah Zaimeddine and Tore M. Undeland , "Comparison of Harmonics and Common Mode Voltage in NPC and FLC Multilevel Converters," 14th International Power Electronics and Motion Control Conference EPE-PEMC, pp. 158-161, 2010. [6] Jonathan W. Kimball and Maciej Zawodniok , "Reducing CommonMode Voltage in Three-Phase Sine-Triangle PWM With Interleaved Carriers," IEEE transaction on Power Electron., vol. 26, no. 8, Aug. 2010. [7] Amitkumar, K. S.; Narayanan, G., "Simplified implementation of space vector PWM strategies for a three level inverter," 7th IEEE International Conference on Industrial and Information Systems (ICIIS) 2012, vol., no., pp.1-6, 6-9 Aug. 2012. [8] T.Vinay Kumar and S.Srinivasa Rao, "Switching State Algorithm for Space Vector Pulse Width Modulation (SVPWM)," in 7th Mediterranean Conference and Exhibition on Power Generation, Transmission, Distribution and Energy Conversion, Agia Napal, 7-10 Nov. 2010. [9] M. Hamouda, H. F. Blanchette, K. Al-Haddad, and F. Fnaiech, "An efficient DSP-FPGA-based real-time implementation method of SVM algorithms for an indirect matrix converter," IEEE Trans. Ind. Electron., vol. 58, no. 11, p. 5024–5031, Nov. 2011. [10] "TMS320x281x DSP Event Manager (EV) Reference Guide, Literature Number: SPRU065C," Nov. 2004. [11] J. Ben Hadj Slama M. TLIG , "Effect of the MOSFET Choice on Conducted EMI in Power Converter Circuits", ,," in 16th IEEE Mediterranean Electrotechnical Conference (MELECON), Tunisia, 2325 March 2012.
CONCLUSION
[12] J. Ben Hadj Slama, S. Hrigua, F. Costa, B. Revol, C. Gautier , "Relevant Parameters of SPICE3 MOSFET Model for EMC Analysis," in IEEE Conference on EMC 2009, Austin, USA, 17-22 Aug. 2009.
This paper investigated the effects of three conventional modulations algorithms on common and differential mode conducted disturbances generated by three-phase two-level voltage source inverters. The experimental measurements were analyzed in time and frequency domains. The comparative study performed in frequency domain showed two main frequency ranges. In the first frequency range, varying from the switching frequency to few hundred of kHz
[13] Keliang Zhou and Danwei Wang, “Relationship between space-vector modulation and three-phase carrier-based PWM: a comprehensive analysis three-phase inverters" IEEE Trans. Ind. Electron, vol. 49, no. 1, pp. 186-196, Feb. 2002.
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