Performance Evaluation of Single Electron

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

Performance Evaluation of Single Electron Transistor with CMOS Technology Shagun Pal1, S. R. P. Sinha2, Rahul Verma3 1,3

Student, Master of Technology (Microelectronics), Department Of Electronics and Communication, I.E.T., Lucknow, India 2 Associate Professor, Department Of Electronics and Communication, I.E.T., Lucknow, India Our research focuses on the logic design functionality using SET technology, making further use of the SET tunnel junction‘s peculiar behavior, i.e., the ability to control the transport mechanism of individual electrons. The aim behind our research is to perform logic operations by transporting individual electrons to or from the output location under the control over the input(s). This paper is organized as follows. In Section 2 we briefly present some back-ground on SET technology. In Section 3 we present modeling of SET logical gates and analyze them. In Section 4 we simulate SET technology and analyse it. In Section 5 we compare Single Electron Transistor with CMOS Technology. Section 6 deals with the power consumption in Set and finally Section 7 concludes the paper.

Abstract—With the dominance of CMOS technology over decades under the rules of Moore’s law, researchers estimates that its further limitation of size will reach a lower limit within the next 10 to 15 years. Recent development in the nanoscale devices paves a new way for low power system design. Among these, Single electron transistor (SET) hover a progress in achieving the lowest power consumption and smaller feature size of nearly 1nm, thereby, exhibiting a larger functionality than a conventional MOSFETs. This paper delves into the performance evaluation of Single electron Transistors with that of CMOS Technology. Keywords—Coulomb Blockade, CMOS, Hybrid Circuits, Single Electron Transistor (SET), SPICE

I. INTRODUCTION Since the seventies the microelectronics industry has followed Moore‘s law, doubling the processing power every 18 months [3]. The ever decreasing feature size, and the alternatively increase in the number of transistors per mm2, enhanced the vast improvements in semiconductorbased designs. At the same time, however, there have been reports [7] that the transistor itself cannot be shrunk beyond certain limits dictated by its operating principle. Thereby, to ensure further feature size deduction, possible successor technologies with greater scaling potential such as Single Electron Tunneling (SET) [2,5] are currently under investigation [6]. Thus far, most studies carried out on SET based logic circuits works upon the tunnel junction using it to implement the SET as a switch equivalent of the MOS transistor [1,4]. This has the advantage that existing CMOS transistor-based designs can easily be ported to SET technology. The drawbacks includes that the current transport though an ―open‖ transistor still amounts for a large number of individual electrons ―dripping‖ through the tunnel island junction. This is hence a far slower process than the transport of just one single electron through the same, and consequently approaches that mimic the CMOS design style do not use the SET technology to its full potential.

II. BACKGROUND In the classic physics theory electrons are viewed of as particles and the theory does not allow electrons to cross a barrier like a piece of insulator. In 1923 L. de Broglie [8] suggested that particles may also behave like waves. Three years later this hypothesis was formally described by Schrodinger, which became the basis for the quantum mechanics theory of today. According to the Schrodinger wave equation, there is a probability that an electron tunnels through a barrier and enters a classically forbidden region and this phenomenon is called tunneling. A. Tunneling The tunnel junction, the basic circuit element of SET technology, is based on this tunneling phenomenon. The tunnel junction is created by separating two conductors with a thin insulator (see Fig. 1) and therefore it behaves in principle like a capacitor. However, given that the insulator is thin enough quantum tunneling may occur. For an electron to tunnel through the junction, the Coulomb energy EC  qe 2 , where C is the capacitance of 2C

the tunnel junction and q e is the charge of an electron (1.60217*10-19 C), is at least needed.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) If the Coulomb energy is not available a tunnel event cannot happen. This phenomenon is known as Coulomb blockade. A voltage source can provide the energy needed for an electron to tunnel. Γs

Drain

V

I

Cd

Cs

qe 2(c j  Ce )

(2)

Where Cj is the capacitance of the tunnel junction and Ce is the capacitance of the remainder of the circuit as seen from the junction's perspective. In other words, tunneling can occur if and only if |Vj|> Vc. Electron tunneling is stochastic in nature and as such the delay cannot be analyzed in the traditional sense. Instead, for each transported electron one can describe the switching delay as:

Γd QD

Source

Vc 

Cg

Gate

Vg

td  Fig. 1. Tunnel junction schematic representation.

There is another condition for observing the tunneling phenomenon. In classical theories an electron was assumed to be well localized. However, in the quantum mechanics theory electrons are described by wave functions, indicating the probability of the presence of an electron. If a tunnel barrier is insufficiently opaque the electron wave function extends through the barrier and the electron is not clearly localized on either site of the tunnel junction. The opaqueness of a tunnel barrier is described by the tunnel resistance Rt. A sufficient condition [10, 11] for observing SET charging effects is:

Rt 

h qe 2

 25.6k

 ln(Perror )qeRt V j  Ve

(3)

Where Perror is the chance that the desired charge transport has not occurred after td seconds [4]. In this paper we assume Perror=10-8. Each transported electron reduces the system energy by E  qe ( V j  Vc ) from which the consumed energy can be calculated. Note that the SET technology can physically be implemented in various ways, e.g., classical semiconductor lithography and by carbon nanotubes . III. BASIC SINGLE ELECTRON LOGIC GATES We can construct single-electron logic circuits in which SETs can operate analogously to MOSFETs of CMOS logic circuits. The Simulation of SET and CMOS based logic circuits are done by SPICE software respectively. Since the structure of CMOS is quite familiar, we are here to discuss the basic gates of Single Electron Transistor.

(1)

Where h is Planck's constant (6.62607*10-34 J-s). For further explanation of the tunnel resistance and the derivation of this equation we refer the reader to [12, 13]. In this research we assume a tunnel resistance Rt of 100 kΩ, which is a commonly used value.

A. Inverter The SET inverter is presented in Fig. 2. When combining two complementary-biased SET transistors in a single circuit, we arrive at the SET inverter structure. The upper SET transistor behaves similarly to a p-type transistor, while the lower transistor operates similarly to an n-type transistor. Output switching (from 0 to 1) is accomplished either by transporting electrons (commonly over 100) from the output node n2 to the top supply voltage terminal s V or (from 1 to 0) by transporting electrons from the bottom ground terminal to the output node n2. Given the SET transistors can be biased in such manner that they behave similarly to p or n transistors; we can convert existing CMOS cell libraries to their SET equivalents.

B. Analyzing SET circuits When designing circuits with tunnel junctions, one needs to be able to calculate the conditions for observing electron tunneling. This could be done by calculating all free energy in the circuit, but even for modest sized circuits this method results in very complex computation [14]. Therefore, the method of the critical voltage is generally employed [15, 16, 17]. This method states that an electron may only tunnel if the voltage across the tunnel junction Vj is greater than a critical voltage Vc. The critical voltage of a tunnel junction can be expressed as:

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) Vdd

Vdd Vdd

J1

Cg1

Cb1

Vg2

Vg1 J2

Vout Vout

Cl Vg

Cl J3

Cb2

Cl Vg1

Cg2

J4

-Vdd

-Vdd

Cl

20mV

Vg2 15mV

10mV

-Vdd

5mV

0V 0V

2mV

4mV

6mV

8mV

10mV

12mV

14mV

16mV

18mV

20mV

22mV

24mV

26mV

V(2) Vin

Fig.2. A schematic diagram of a single-electron inverter and the input output characteristics of the inverter calculated at 4.2 K, 27 K, and 77 K.

B. Single Electron AND gate The SET AND gate is shown in Fig.3. The circuit comprises Six Single Electron Transistor (3 nSET and 3 pSET). Instead of two paralleled sourcing (upper) transistors connected to Vdd and two series-connected sinking (lower) transistors connected to ground. As with the NAND gate, SET transistors U1 and U3 work as a complementary pair, as do transistors U2 and U4. Each pair is controlled by a single input signal. If either input A or input B are "high" (1), at least one of the lower transistors (U3 or U4) will be saturated, thus making the output "low" (0). Only in the event of both inputs being "low" (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go "high" (1).The AND function built up from the basic NAND gate with the addition of an inverter stage on the output. The voltage Vdd is constant and its value is 25mV. The operation of the AND gate is shown in Fig.3. Fig. 3(a) and (b) shows the time variation of input voltages V1 and V2, respectively. The inputs are piecewise constant and apply all possible combinations of logic ‗0‘ and ‗1‘ to the gate. Fig. 3(c) shows the time variation of output voltage.

Fig.3.A Schematic internal circuit of AND gate and its input output response.

C. Single Electron OR gate The SET OR gate is shown in Fig. 4. The circuit comprises eight Single Electron Transistor (4 nSET and 4 pSET). As with the NOR gate, SET transistors U1 and U4 work as a complementary pair, as do transistors U2 and U5 like U3 and U6 . Each pair is controlled by a single input signal. In this circuit upper transistors U1, U2 and U3are serially connected and lower transistors U4, U5 and U6 connected in parallel sourcing to ground. As with the NOR gate, SET transistors U1 and U3 work as a complementary pair, as do transistors U2 and U4.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) Each pair is controlled by a single input signal. If both the input A and input B are "high" (1), both the lower transistors (U3 and U4) will be saturated, thus making the output "low" (0). Only in the event of both inputs being "low" (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go "high" (1).The OR function built up from the basic NOR gate with the addition of an inverter stage on the output. The voltage Vdd is constant and its value is 25mV. The operation of the OR gate is shown in Fig. 4. Fig. 4(a), (b) and (c) shows the time variation of input voltages V1, V2 and V3, respectively. The inputs are piece-wise constant and apply all possible combinations of logic ‗0‘ and ‗1‘ to the gate Fig. 4(d) shows the time variation of output voltage.

IV. SIMULATION OF SET/CMOS HYBRID CIRCUITS One of the problems that has to be addressed in single electronics is how the SETs will be biased. Many circuits require the SETs to be current biased. However, it is impractical to use a separate external current source for every SET on a chip. A better solution is to make current sources on chip for every SET that requires a current source. A simple current source can be constructed using just one CMOS. Figure 5 shows a single-electron transistor that is current biased by a CMOS and the corresponding SPIC E simulation of the circuit. Vdd

NMOS

Vdd

Vout

Vin

Vg1

Cin

Vdd

Single Electron Tunneling Transistor

Cl Vg2 Vout 600mV

Cl Cl Vg2 Vg1

400mV

-Vdd

200mV

-Vdd

0V 0V

40mV V(2)

80mV

120mV

160mV

200mV

240mV

280mV

320mV

360mV

V(4) Vg1

Fig.5.The schematic of a current biased SET with a CMOS output stage and the corresponding SPICE simulation. The solid line is the voltage at the output voltage of the SET stage (green) and the dashed line is the voltage at the output of the CMOS stage (red)

A second CMOS is used in the circuit of Fig. 5 to buffer the output of the SET. This is one way to solve the problem of the large output impedance of SETs. It is fundamental to the operation of SETs that the output impedance must be larger than the quantum resistance (  25k ), otherwise the charge on the island of the SET is not well defined. For SETs that operate at high temperature, the output impedance is typically much larger. This is a problem if the output of the SET has to drive a signal a long distance across the chip.

Fig.4.A Schematic internal circuit of OR gate and its input output response

618

400mV

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) TABLE l The theoretical comparisons between SET and CMOS

The time it takes for the output of the SET to settle to the right value is RC where R is the output impedance of the SET and C is the capacitance of the wire that carries the signal away from the SET. Thus, the high output impedance can make the response of the circuit slow. By adding the CMOS buffer stage at the output of the SET, the output impedance is reduced to 100Ω, increasing the speed of the circuit greatly. The thorny background charge problem can also be addressed by combining SETs with other circuit elements. This problem arises because of the tremendous charge sensitivity of a SET. A single charged vacancy or an interstitial ion in the oxide near a SET can be enough to switch the transistor from conducting to non-conducting. The consequence of this is that when many SETs are fabricated on a chip, some of them will be conducting with zero voltage applied to the gate and some will be nonconducting with zero voltage applied to the gate. During the course of time, the charged defects often move or shift between different positions. These movements are detected by the single electron transistors. The same kinds of charged defects are present and move in field-effect transistor circuits but most field-effect transistors are not as sensitive to charge so the consequences of these background charges are not as great. The background charge problem is probably the single greatest problem preventing the widespread use of SETs in integrated circuits.

Maximal switching speed(s) Supply voltage range Current range RBC sensitivity Maximum voltage gain Maximum operation temperature

CMOS Circuit 10 10

SET circuit

100m nA none high >300 o

100µV Few electron γ high difficult at 300K

10 15

The logic circuit diagrams show that the no of transistor require to realize different logic gates is less in case of SET based logic system.The number of transistors require for realizing different logic gates using both CMOS and SET technology are given in the Table 2. Table 2 Comparison Based On Number Oftransistor

NOT OR AND NAND NOR

CMOS circuit 6 6 4 4 2

SET circuit 2 SET One SEB One SEB One SEB+2 SET One SEB+2 SET

A. Delay Estimation Rising time and falling time of the signal can be estimated using (4).

V. COMPARISON BETWEEN SINGLE ELECTRON AND CMOS TECHNOLOGY All the simulation results reported above clearly show that SET based logic gates take approximately zero delay time in propagating the input signal to output side. A number of SET circuits are discussed and simulated using the macro model for single electron transistor. The possibility of simulating hybrid circuits was one of the motivations for developing a macro model for a single electron transistor. Also a comparison between the power consumption of single electron transistor and CMOS circuits are made.

Tr (or )T f  RC ln((VDD  Vout ) / VDD )

(4)

Tr - Rising time, T f -Falling Time R- Circuit resistance, C- circuit capacitance, VDD -Supply Voltage, Vout -output Voltage. Propagation Delay Time ( PDT ) can be estimated from the time constant of the circuit RC. The sum of the rise time, fall time & propagation delay gives the total delay time (5). Total Delay TD  Tr  T f  PDT

619

(5)

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) Table 3 Comparison Based On Delay

CMOS(ns) SET(ps)

Tr orT f

PDT

TD

16.95 116.5

36.95 316.5

70.85 549.5

The static leakage power due to the thermal enhancement of normal tunneling makes up a considerable portion of the total power as the operation temperature increases. Because the dynamic power has a quadratic level and voltage level rise as the dimensions of SETs are scaled down, supply voltage scalability, while device parameters.

B. Power loss estimation The power loss estimation of logic system is described in thefollowing section. Dynamic Power Loss is calculated using (6)

PT  (C PD  C L )VDD 2 f

VII. CONCLUSION In this paper, the analysis of Nano technology based SET logic gates quantitatively as well as qualitatively and compared its performance with conventional CMOS technology based logic gates. The comparison result shows that the SET based gates consume ultra low power, and switches with very high speed. The number of transistors require for realizing different logic gates using SET are also less. These facts indicate that the future ULSI technology, which requires higher integration, fast switching and ultra low power consumption can be realized with SET based logic system. This technique is simple to perform and does not require any modification of the SPICE internal source code.

(6)

C PD - Power Dissipation Capacitor C L - Load Capacitance VDD – Supply Voltage f – Switching frequency Static power loss can be estimated from the equivalent circuit diagram and the parameter mentioned .It‘s very clear from (6)that the power dissipation increases with increase in frequency and decreases with decrease in voltage level.

REFERENCES [1]

VI. POWER CONSUMPTION IN SET CIRCUITS In general, there are three components that constitute the amount of power consumed in circuit operation: dynamic, short-circuit, and leakage power. The dynamic power is consumed due to the charging and discharging of the output capacitance C L when logic switching occurs, and thus, is inevitable in circuit operation. Short-circuit power occurs when both the nSET and pSET are turned-on simultaneously, conducting short-circuit current from the supply to the ground. The power resulting from the shortcircuit current is only a minor fraction of the total dissipation, as long as the output transient times are relatively large compared to the input rise and fall times. However, the short-circuit power in SET circuits is also a function of operation temperature, and, as the temperature increases, it make up a considerable portion of the total power. The most significant component of the power consumed in the SET circuit is the leakage power. An ideal complementary circuit does not dissipate power when the input does not change. However, in a circuit composed of SETs, leakage power is dissipated by the thermal enhancement of normal tunneling and co-tunneling.

[2]

[3]

[4]

[5] [6]

[7]

[8]

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A.Korotkov, R.Chen, and K.Likharev. Possible Performance of Capacitively Coupled Single-Electron Transistors in Digital Circuits. Journal of Applied Physics, Vol. 78(No. 4):pp. 2520–2530, August 1995. A.N.Korotkov. Single-Electron Logic and Memory Devices. International Journal of Electronics, Vol. 86(No.5):pp. 511–547, 1999. J.Hennessy and D.Patterson. Computer Architecture – A Quantitative Approach. Morgan Kaufmann Publishers, San Franscisco, California, 2nd edition, 1996. J.R.Tucker. Complementary Digital Logic based on the ‖Coulomb Blockade‖. Journal of Applied Physics, Vol. 72(No. 9):pp. 4399– 4413, November 1992. K.K.Likharev. Single-Electron Devices and Their Applications. Proceeding of the IEEE, Vol. 87(No. 4):pp. 606–632, April 1999. Technology roadmap for nanoelectronics. Downloadable from website http://www.cordis.lu/esprit/src/melnarm. htm, 1999. Published on the internet by the Microelectronics Advanced Research Initiative (MELARI NANO), a European Commission (EC) Information Society Technologies (IST) program on Future and Emerging Technologies. Y.Tau, D.A.Buchanan, W.Chen, D.Frank, K.Ismail, S.Lo, G.SaiHalasz, R.Viswanathan, H.Wann, S.Wind, and H.Wong. CMOS Scaling into the Nanometer Regime. Proceeding of the IEEE, Vol. 85(No.):pp. 486– 504, 1999. Diner, S., Fargue, D., Lochak, G., Selleri, F., The wave-particle dualism { a tribute to Louis de Broglie on his 90th birthday, D. Reidel Publishing Company, 1984.

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) [9] [10]

[11]

[12]

[13]

Garcia, N., Damask, A., Physics for computer science students, Springer-Verlag, 1991. Likharev, K. K., Zorin, A. B., Theory of the bloch-wave escillations in small joseph- son junctions, Journal of Low Temperature Physics, 59, pp. 347{382, 1984. Averin, D. V., Likharev, K. K., Coulomb blockade of single-electron tunneling and coherent oscillations in small tunnel junctions, Journal of low temperature physics, 62, no. 3{4, pp. 345{373, 1986. Geerligs L. J., Anderegg, V. F., Van Der Jeugd, C. A., Romijn, J., Mooij, J. E., Influence of dissipation on the coulomb blockade in small tunnel junc- tions, Europhysics Letters, 10(1), pp. 79{85, 1989. Zweger, W., Scharf, M., Crossover from coulomb-blockade to ohmic conduction in small tunnel junctions, Zeitschrift fÄur Physik B {Condensed Matter, 85, pp. 421{426, 1991.

[14] Wasshuber, C., about single-electron devices and circuits, Ph.D. dissertation, TU Vienna, 1998. [15] Geerligs, L. J., Anderegg, V. F., Holweg, P. A. M., Mooij, J. E., Frequency- locked turnstile device for single electrons, Physical Review Letters, 64, no. 22, pp. 2691{ 2694, 1990. [16] Esteve, D., Transferring electrons one by one, Single Charge Tunneling { Coulomb Blockade Phenomena in Nanostructures (H. Grabert and M.H. Devoret, eds.), NATO ASI series B, vol. 294, Plenum Press and NATO Scienti¯c A®airs Division, New York and London, 1992, pp. 109{137. An Analysis of Basic Structures for Effective Computation 83 [17] Grabert, H., Ingold, G. L., Devoret, M. H., Esteve, D., Ppthier, H., Urbina, C., Single Electron Tunneling Rates in Multijunction Circuits, Zeitschrift fÄur Physics B, { Condensed Matter, 84, pp. 143{155, 1991.

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