(PoE) System - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

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Advanced Four-Pair Architecture With Input Current Balance Function for Power Over Ethernet (PoE) System Jiande Wu, Haimeng Wu, Student Member, IEEE, Chushan Li, Student Member, IEEE, Wuhua Li, Member, IEEE, Xiangning He, Fellow, IEEE, and Changliang Xia, Senior Member, IEEE

Abstract—In the typical Power over Ethernet (PoE) system, the conventional powered device (PD) with two-pair architecture can only provide power below 20 W to the distant loads, which greatly restricts its applications in many areas. An advanced type of fourpair architecture with an input current balance function for the PoE system is proposed in this paper to not only improve the power level, but also achieve the high conversion efficiency. The steady-state model of the four-pair architecture is built to explore the existing imbalance problem, which is mainly caused by the structure and impedance inconsistency. The proposed four-pair architecture consists of two main converter modules operated in parallel. An input current balance scheme is adopted to reduce the difference of both primary currents, which can increase the transmission power and improve the current sharing performance. Furthermore, the small-signal model of the paralleled converters with an input current balance control strategy is constructed to give a design guideline for the control loop. Finally, a 50-W prototype is built and tested to verify the effectiveness of the presented architecture and control strategy. Index Terms—Active-clamp forward converter, four-pair architecture, input current balance, powered device (PD), Power over Ethernet (PoE).

I. INTRODUCTION N RECENT years, the Power over Ethernet (PoE) system continues to gain great popularity in the global networking market. It is widely applied to Voice over Internet Protocol (VoIP), web cameras, wireless access points, monitoring systems, sales terminals, home automations, and so on. The typical PoE system is plotted in Fig. 1. The clear advantage of delivering

I

Manuscript received February 2, 2012; revised May 25, 2012; accepted August 6, 2012. Date of current version November 22, 2012. This work was supported in part by the National Nature Science Foundation of China under Grant 61174157, in part by the Zhejiang Province Science and Technology Program under Grant 2011C21056, and in part by the Power Electronics Science and Education Development Program of Delta Environmental & Educational Foundation under Grant DREG2011002. Recommended for publication by Associate Editor F. Wang. J. Wu, C. Li, W. Li, and X. He are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). H. Wu is with the School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU, U.K. (e-mail: aallben@ yahoo.com.cn). C. Xia is with the School of Electrical Engineering and Automation, Tianjin University, Tianjin 300072, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2214401

Fig. 1.

Typical PoE system.

power over the Ethernet cable is the simplification of the wiring network. As a result, the adapter or the second power cable is no longer required. By applying the PoE system, a flexible configuration is achieved and an easy energy management is realized to comfort the customers with variable modern consumer electronic products. In a typical two-pair PoE system, only 12.95 W power can be delivered from power sourcing equipment (PSE) to a powered device (PD) [1]. Meanwhile, the diode bridge rectifier is commonly used for the polarity protection in PSE and PD interface circuit [1], [2]. Furthermore, the conventional flyback converter is usually employed as the main conversion topology [3], [4]. These two factors lead to low conversion efficiency. However, some specialized applications require more power and higher conversion efficiency than the most existing industrial products [1]. In order to achieve a higher power level, there are some possible approaches, including raising the supply voltage, raising the supply current capacity, and reducing the cable resistance. These techniques may be adopted individually or in combination. Unfortunately, the upper 57-V limited voltage should be guaranteed to maintain the compatibility with the existing communication power and satisfy the safety issue [1], [2]. Furthermore, increasing the allowed operating current causes excessive power losses over the network cable, which may lead to overheating and low voltage on the cable’s terminals. Taking these insolvable factors into account, the latest published IEEE 802.3 at standard in 2009 increases the limited current modestly from 350 to 720 mA to better satisfy the higher power requirements. On the other hand, although the four-pair structure is a

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nonstandard scheme in the present standard [2], it can be employed to double the transmission power [3]. Several possible structures with modules in parallel are proposed for the PoE system to improve the output power level in [4]. However, in the existing four-pair architecture with only one dc–dc converter, a current imbalance between each transmission path emerges because of the variations in the diode forward voltage drop, cable resistance, and MOSFET conduction resistance in the dc–dc circuit or the interface circuit. According to the simulation results, in the worst case, the current difference between the two paths can reach nearly 200 mA [3], while the input current in one path is only 750 mA. This could result in one path exceeding its current limit and shutting down the PD. Furthermore, the imbalance is caused by the inherent circuit topology. As a result, it is relatively difficult to handle this situation by the outer hardware or software solutions. Two or more converter modules in parallel are another effective solution to increase the power level. Many published strategies are employed to achieve the load current sharing, such as the droop method [5], master/slave scheme [6], average current sharing method [7], [20], and maximum current sharing method. In order to calibrate the sensing error and eliminate the mismatch in the current-sharing loop, an autotuning control scheme is developed in [21] and a sensorless current estimation and sharing scheme is proposed in [22]. Another advantage for the scheme in [22] is that the current sensing circuit is eliminated to cut down the cost. However, most of the introduced current sharing schemes are proposed to deal with the output load current difference rather than the input current. The two modules with different input voltages may cause different input currents when the output power is the same. In fact, for the PoE system, the input current balance is more important and the current difference should be strictly limited to an acceptable value. Especially when a long cable is employed, the additional output current balance control may make the input current susceptible to imbalance, which reduces the system stability. In this paper, a novel type of four-pair architecture with dual dc–dc converters is proposed to realize a high-efficiency and high-power PoE transmission. An advanced control strategy with little additional hardware cost is introduced to solve the imbalance input current problem discussed previously. Furthermore, the active-bridge rectifier circuit is employed to replace the traditional diode bridge rectifier for the polarity protection to reduce the conduction losses [8]. Moreover, the active-clamped forward converter is selected to improve the conversion efficiency compared with the conventional flyback topology. The adopted modular design can enhance the flexibility and the PD configurability. Excellent input current balance performance is verified by the experimental results from a 50 W prototype. This paper is organized as follows. The detailed steady-state model and the exploration of the proposed four-pair architecture are addressed in Section II. The consideration on the optimal topology selection and the input current balance control scheme is analyzed in Section III. Meanwhile, the small-signal model is derived to facilitate the control loop design. In Section IV, the implementation for the auxiliary circuit and current limit protection approach is explored. Experimental results based on a


Fig. 2. Architecture of the PoE system: (a) PSE with a PSE–PD interface circuit; (b) PD structure in two-pair architecture; (c) PD structure with one dc–dc converter in four-pair architecture.

50 W prototype are illustrated in Section V to show the clear advantages of the proposed solution. The last section summarizes the conclusions drawn from the aforementioned investigation. II. STEADY-STATE MODELING AND ANALYSIS OF THE POE SYSTEM A. Steady-State Modeling and Analysis for Architecture of the Typical PoE System The operation principle of the PoE system can be briefly introduced as follows. The system is divided into three parts: the PSE, the PD, and the PSE–PD interface circuit. The typical architecture of the PoE system is shown in Fig. 2. The PSE, which is usually composed of one individual dc/dc converter, can provide and control the power delivered to the valid PD. The detection of the possible connected PDs is through the Ethernet cable and only the PD with the eligible signature resistor can be classified and powered. The PD is the devices which get power from the PoE system. A dc–dc converter is required to regulate the output voltage to a desired level. Fig. 2(a) illustrates the PSE–PD interface. It consists of four network transformers T1 –T4 , the Ethernet cable P12 –P78 , two bridge rectifiers which can allow the reverse input voltage, and two interface circuits which are fully compliant to IEEE 802.3af for a PD connecting into PoE networks. According to the IEEE802.3 standard, the digital data of the network information are only transmitted through the primary networking transformers T1 –T4 on the data pairs P12 and P36 . The PSE

WU et al.: ADVANCED FOUR-PAIR ARCHITECTURE WITH INPUT CURRENT BALANCE FUNCTION PoE SYSTEM

Fig. 3.

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Steady-state model of four-pair architecture with one dc/dc converter. Fig. 4. Value of delivery current on return path1 and path2 at different input powers.

utilizes the same data pairs or the spare pairs P45 and P78 to provide energy through the diode bridge DB1 or DB2 to the load. There are two alternative two-pair architectures compatible with the presented standard [9]. One configuration of the twopair architecture is that the port AB in Fig. 2(a) is connected to the port a1 b1 in Fig. 2(b), where a dc/dc converter is employed to achieve the voltage regulation. The other alternative configuration of the two-pair architecture is that the port CD in Fig. 2(a) is connected to the port a1 b1 in Fig. 2(b) and the power is transferred over the spare pairs P45 and P78 . In order to protect the PoE system, the current on the transferring path is sensed. When it reaches the limited value, the MOSFET Sw 3 and Sw 4 in the path will be switched OFF immediately to shut down the PD. For the purpose of improving the delivery power, the configurations of the conventional four-pair architecture can be employed by connecting the port AB and CD to the corresponding port a2 b2 and c2 d2 in Fig. 2(c). In this four-pair architecture with one dc/dc converter, if the impedances of each path are identical, the current balance is unnecessary and each path provides half of the required input current to the dc/dc converter. Thus, the output power can be doubled. However, the impedances of the two paths are not always the same. A steady-state model of the four-pair architecture with an individual dc/dc converter is derived to analyze the current condition when the impedances are mismatched. As plotted in Fig. 3, R12 , R36 and R45 , R78 represent the cable resistors on the data pairs P12 , P36 and the spare pairs P45 , P78 , respectively; RT 1 − RT 4 are the network transformer resistors; RBR1 and RBR2 are the diode bridge resistors; Rw 1 and Rw 2 are the resistors on the switches Sw 1 and Sw 2 in PSE; Rw 3 and Rw 4 are the conduction resistors on the switches Sw 3 and Sw 4 . VBR1 and VBR2 are the forward voltage drops on the diode bridges DB1 and DB2 ; VPSE is the voltage on PSE. Assuming the total delivery current is IR , the delivery currents on the return path1 and path2 are IP 1 and IP 2 . From Fig. 3, the following relationship can be obtained: ⎧ ⎪ ⎨ IP 1 × (R36 + RT 1 + RT 2 + RBR1 + Rw 1 + Rw 3 ) + VBR1 = IP 2 × (R78 + RBR2 + Rw 2 + Rw 4 ) + VBR2 ⎪ ⎩ IP 1 + IP 2 = IR . (1)

In order to simplify the analysis, the total resistor of each path can be represented as RA and RB , which are given by RA = R36 + RBR1 + Rw 1 + Rw 3 + RT 1 + RT 2 (2) RB = R78 + RBR2 + Rw 2 + Rw 4 . From (1) and (2), solving for the values of IP 2 and IP 1 yields ⎧ VBR2 − VBR1 RB ⎪ ⎪ + IR ⎨ IP 1 = RA + RB RA + RB (3) ⎪ − VBR2 V RA ⎪ ⎩ IP 2 = BR1 + IR . RA + RB RA + RB From (3), it can be seen that the current imbalance is caused by the diode forward voltage drop and the resistor inconsistency on each path. According to the IEEE standard, the maximum cable resistor unbalance is permitted at 3%. Meanwhile, the diode forward voltage drop and the parasitic resistors on the components also have some variations. For example, when the voltage on PSE is 40 V, it has IR =Pin /40 V, where Pin is the total input power. Supposing that VBR1 = 0.65 V, VBR2 = 1 V, RA = 9.84 Ω, and RB = 7.71 Ω, the maximum current difference can be calculated under different load conditions. The relationship between the current on the return paths and the input power is plotted in Fig. 4. It is distinctly indicated that the maximum current difference under the worst case condition can be close to 180 mA although each path carry only about 700 mA average current. This unbalanced current may cause one of the paths over current and being shut down by the interface circuit. As a result, the other path will also exceed the current limit and the PD may then be powered OFF. B. Steady-State Modeling and Analysis for the Proposed Four-Pair Architecture In order to avoid the current carried over paths to approach the limited value and improve the output power level, the advanced four-pair architecture with two dc/dc converters in parallel is proposed as shown in Fig. 5(a). It is clear that the hardware cost of the PoE system with two dc/dc converters is a little higher than that with a single converter. However, the situation is different once considering the cost from the system point of view if more power is demanded in some applications. Because of the unbalance current in two paths, the system with a single converter cannot deliver enough power. As a result, additional adapter

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Fig. 6.

Block diagram of the system architecture.

III. DESIGN OF A POE SYSTEM WITH FOUR-PAIR ARCHITECTURE AND INPUT CURRENT BALANCE CONTROL SCHEME

Fig. 5. Proposed four-pair architecture. (a) Block diagram of the proposed four-pair architecture with two dc–dc converters in parallel. (b) Steady-state model.

circuit is indispensable in the load terminal, which greatly increases the cost. In conclusion, the proposed PoE system with two converters is competitive and cost effective in the higher power applications. As shown in the two-converter PoE system, each dc/dc converter has its independent loop return to PSE, a control strategy of the current balance is required to be introduced in order to ensure that the return current in each path is identical. The steady-state model of the proposed four-pair architecture is illustrated in Fig. 5(b). Assuming the conversion efficiency is η and the output power is Po , if the output current sharing method is employed, each module can share half of the load current. The following equations can be obtained: (VPSE − Iin1 RC − 2VBR1 ) × Iin1 × η = 0.5Po (4) (VPSE − Iin2 RD − 2VBR2 ) × Iin2 × η = 0.5Po where Iin1 and Iin2 are the values of the input currents; and RC and RD are the total resistors of each loop. RC and RD are derived as follows: ⎧ ⎪ ⎨ RC = R12 + R36 + RT 1 + RT 2 + RT 3 + RT 4 + 2RBR1 +Rw 1 + Rw 3 ⎪ ⎩ RD = R45 + R78 + 2RBR2 + Rw 2 + Rw 4 . (5) Unfortunately, RC and RD may have some variations in the practical applications. From (4), it can be concluded that the input currents of the two dc/dc modules cannot be identical although the output currents of the converters are nearly the same by employing the output current sharing schemes. For example, when the voltage on PSE is 44 V, the input current difference is approximately 100 mA in the worst case at 48 W load. Therefore, an advanced strategy for the current balance control is still required in the proposed four-pair architecture.

In this section, a PoE system with the four-pair architecture and the input current balance control method is analyzed in detail. Compared with the system with aforementioned output current-based balance control schemes, the proposed input current-based balance control strategy may have higher power delivering ability and higher stability. The block diagram of the system architecture is shown in Fig. 6. The configuration of the system is the same as Fig. 5. There are two modules operating in parallel and each module consists of the PSE–PD interface circuit and one dc–dc converter. The input current balance control is introduced between the two dc–dc converters. The power from the PSE flows through the PSE–PD interface circuit and the dc–dc converter to supply the load. The detailed analysis about the input current balance control strategy is given in Sections III-B to III-D. A. Topology Selection The appropriate topology selection is crucial for achieving the high conversion efficiency under certain application occasion. The single-ended converters, such as the flyback or forward converters, are normally applied in the PoE system, depending on the PD’s voltage and current requirements [10], [11]. In addition, the forward–flyback converter is one of the suitable topologies which can be employed in this occasion [23], [24]. In order to select the best topology among them, it is necessary to do a fair and complete comparison in terms of the components, control complexity, potential conversion efficiency, etc. The optional topologies are illustrated in Fig. 7. The forward converters have the advantages of the simple structure, easy to control, and the low output current ripples, but the primary auxiliary winding or the active-clamp circuit should be employed to achieve the magnetic reset. The flyback topology is the most popular selection in the low-power applications for its simplest structure and the least components usage. However, the air gap inside the couple inductor for the energy storage makes the value of the leakage inductance larger than that of the forward converters. As a result, the RCD snubber auxiliary circuit or the active-clamp circuit is required to absorb the turn-off voltage spikes, which increases the losses and complexity [12]. The forward–flyback converters as shown in Fig. 7(c) can be


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TABLE I VOLTAGE AND CURRENT STRESS COMPARISON OF CONVERTERS

flyback converters. At the same time, the same number of switches is used in both converters if the active-clamp technology is applied. But the magnetic core design of the forward converters is simpler than that of the forward–flyback converters. Therefore, the forward converter has lower cost than the forward–flyback converter. In conclusion, forward converters are the optimal candidates for the high-efficiency and costeffective PoE system. Fig. 7. Optional topologies. (a) Forward circuit. (b) Flyback circuit. (c) Forward–flyback circuit.

recognized as the combination of the forward and flyback converters. The advantage of the forward–flyback converters is the continuity of the power transmission, which means the improvement of the power density. However, the problems of the magnetic reset and the voltage spikes still exist because of both the existing forward and flyback modes. Moreover, the design of the magnetic components is relatively complex among these three type converters. Keeping the same input and output voltages, the same switching frequency, and similar size, three optional topologies are compared by their voltage stress, current stress, efficiency, and cost. The corresponding expressions for the voltage and current stresses of the main switch and output diode are listed in Table I. Vi and Vo are the input and output voltages; Io is the output current; D is the duty cycle of the main switch; Ts is the switching period; N is the turns ratio n1 /n2 ; Lm is the magnetizing inductance of the flyback and forward–flyback converters. From Table I, it can be seen that the flyback converters should sustain higher switch voltage stress than the forward or forward–flyback converters, which infers that the flyback converters requires switches with higher voltage stress and larger on-resistance. Thus, it has lower efficiency than the other two topologies. Furthermore, the maximum current of the main switch in the forward converters is similar to that in the forward–

B. Control Scheme Explanation for Two DC–DC Module Parallel Operations According to the aforementioned comparison results, the active-clamp forward converter is employed as the main circuit topology. On the other hand, the current programmed mode, which is widely applied to low-power and low-cost applications, has the advantages of simple dynamic performance, excessive current prevention, and transformer saturation reduction. Thus, it is chosen as the closed-loop control scheme for the individual dc–dc module. At the same time, the input current balance control scheme is introduced between the two converters due to the special requirements in the presented PoE systems. The overall control strategy for the two converters is explained in this section. The schematic of the active-clamp forward converter with the control strategy block is shown in Fig. 8. The method of combining the input current balance control scheme and the conventional current programmed mode control scheme is introduced as follows. The current from the switch S is sampled first by the sample resistor Ri . In the forward converter, if the magnetizing inductance Lm is large enough to make the magnetizing current ignored, the switching period average of the sampled current ¯ip is equal to the input current Iin . A compensator Gc for the input current balance control is utilized to amplify the error signal between the two sampled current from the two modules. The output signal of Gc added with the result from the output voltage control compensator Gv is set as

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Fig. 8. Schematic of an active-clamp forward converter with current programmed mode control and input current balance control.


input voltage vg to control the duty cycle d, respectively, and Fm indicates the transfer function from the combination control signal to the duty cycle d, which are given by ⎧ 1 ⎪ ⎪ Hi = − ⎪ ⎪ N ⎪ ⎪ ⎪ ⎪ (2D − 1) · Ts ⎪ ⎪ Hv = ⎪ ⎪ ⎪ 2 · Lf ⎪ ⎪ ⎨ −D2 Ts (6) Hg = ⎪ ⎪ 2 · Lf · N ⎪ ⎪ ⎪ ⎪ ⎪ Hm = −D ⎪ ⎪ ⎪ ⎪ ⎪ Ts Vi ⎪ ⎪ ⎪ · = 1 + M T F 0 s ⎩ m 2 L m

where M0 represents the slope rate of the ramp compensation signal required for the current programmed mode. Lf is the output inductor. The definitions of other variables are given in Table I. It can be concluded from Fig. 9 that three feedback loops are existed by applying the peak current control. As a result, the design consideration of the closed-loop control for the system is different from that for the converter with only applying the voltage feedback control. D. Small-Signal Model Derivation and Control Consideration for a System With Input Current Balance Control Scheme

Fig. 9. Small-signal model of a forward active-clamp converter with peakcurrent-mode control.

the reference Vc for the peak current control loop. The input current balance is achieved when the output signal of Gc is equal to zero. The aforementioned control scheme has a clear advantage. Only the switch current is sampled for the input current balance control and the current programmed control. As a result, there is little additional hardware cost to achieve the input current balance control. C. Small-Signal Mode for an Individual DC/DC Module With a Current Programmed Mode The control scheme design for an individual dc–dc module is the basis of that for several modules operating together. Therefore, the small-signal model for one active-clamp forward converter with the current programmed mode is briefly given. Referring to [13] and [25], the small-signal model of the forward active-clamp converter with only the peak current mode control is illustrated in Fig. 9. The detailed derivation is given in [13] and [25] and the control to output transfer function can be calculated from this small-signal model. Hm , Hi , Hv , and Hg represent the transfer functions from the variations on the input current iL m , inductor current iL , output voltage vo , and

In this section, the system small-signal model of the two parallel operating active-clamp forward converters with the input current balance control scheme implemented is derived and analyzed. The design consideration for the closed-loop control is also given. For the two parallel active-clamp forward operating converter system, each converter can be modeled according to the individual small-signal model given in Fig. 9. However, after paralleling the two converters together, the model of the system becomes complicated. A useful simplification method is given in [14] and [15], where a single-module converter model is derived to replace the multimodule converter model. At the same time, the single module model has the same closed-loop performance as the original system. Thus, the analysis for a control-loop design becomes much easier. With the help of the simplification method, the small-signal model of the two forward active-clamp converters with the proposed input current balance control strategy is displayed in Fig. 10. As shown in Fig. 10, it has Lf = Lf /2, Co = 2 · Co , Ro = Ro /2, Lm = Lm /2. Some of the parameters are also modified referring to the parallel converter number of the system. Compared with the model shown in Fig. 9, the closed-loop control block and the current balance control block are added in, where Hf is the transfer function of the RC filter including the sample resistor gain Ri , î∗p is the sampled input current disturbance from the other parallel module, and vô∗ is the voltage reference which is equal to zero. At the same time, an additional current source îs is utilized to represent the output current disturbance from the other parallel module. With the establishment of the simplified


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Fig. 10. Simplified model for two parallel operating forward active-clamp converters with peak-current-mode control and input current balance control strategy (L f = L f /2, C o = 2 · C o , R o = R o /2, L m = L m /2).

model, the analysis for the system dynamic and control can be all carried out based on it. In order to make the analysis more straightforward, the model in Fig. 10 can be further simplified to the small-signal diagram displayed in Fig. 11. According to the explanation in [13], by carefully designing the value of Cc and Lm [26], the feedforward loop related to the magnetizing current disturbance îL m can be ignored due to that it is much smaller than the sampled current disturbance îp . According to the small-signal model shown in Fig. 10, îp can be expressed as

ˆ îp = Gpi · îL + Gpd · dˆ = 2D · îL + 2Io · d. N N

(7)

It can be inferred from (7) that two feedback loops are created by adding the input current balance control. The transfer functions of the feedback loops are given by Gd and Gi , respectively. This is different from the system applying the output current balance control [16], [17] where only one feedback loop is added to the original system. On the other hand, î∗p has the same expression with îp . However, no feedback loop is created by this, and thus, it is modeled as two external disturbances which are also displayed in Fig. 11. Based on the model shown in Fig. 10, all the definitions and transfer functions of the blocks in Fig. 11 can be derived, which are shown in Table II. It can be found that there are five feedback loops in the system shown in Fig. 11. Loops T1 and T2 are inherently generated by the peak current control. Loop T3 is introduced by the output voltage feedback control. Loops T4 and T5 are created by the input current balance control. The five feedback loops can be further attributed to three loops which are the current loop Ti , the voltage loop Tv , and the duty cycle loop Td . Their definitions

Fig. 11.

Simplified small-signal diagram for a two-converter system.

TABLE II DEFINITIONS AND TRANSFER FUNCTIONS FOR A SIMPLIFIED SMALL-SIGNAL MODEL

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are given next: ⎧ Gv ⎪ Fm ⎪ T v = T 2 + T 3 = F 3 Hv F m − F 3 ⎪ ⎪ Ri ⎪ ⎪ ⎨ Hi Gi Fm − F 6 Fm T i = T 1 + T 4 = F6 ⎪ 2 Ri ⎪ ⎪ ⎪ ⎪ G ⎪ ⎩ T d = T 5 = − d Fm . Ri

(8)

The system is similar to the system proposed in [16], [17] where the output current balance control is applied. A threeloop control strategy introduced in [14] can be applied to the system to achieve good performance. But in fact, there is no stringent requirement for the PoE system to perform an excess dynamic response for the input current balance control. The stability of the system and the zero steady-state error should only be guaranteed. On the other hand, according to a simple calculation, the gain of the third feedback loop Td is always small especially in the high-frequency part. In this way, the closed-loop design of the system can be further simplified to the control design of the traditional two-loop peak-current mode forward converter. According to the analysis given in [17] and [18], the dynamic character of a multiloop system can be explored by analyzing two critical loop gains which are named as the overall loop gain Ta and the outer loop gain To . The definitions of the two loop gains are expressed by ⎧ ⎨ Ta = Ti + Tv + Td Tv . ⎩ To = 1 + Ti + Td

(9)

The system crossover frequency fc is defined where 20·lg|To (2πfc )| = 0, which is quite similar to the definition in the single-loop system. However, it is indicated in [18] that the conventional ideas used for the single-loop systems to predict the stability performance by a single open-loop gain is no longer available. Both Ta and To contain useful information for a system design. The design process of a two-loop system can be found in [17], [18], and [26]. Three design rules are summarized. 1) The highest possible dc gain of the voltage loop Tv reduces the steady-state error of the output voltage. 2) The crossover frequency of the current loop Tc must exceed that of the voltage loop to obtain the benefit of high bandwidth of the current loop that can improve the closedloop responses. But it should not excess half the switching frequency to ensure the stability. 3) The active-clamp circuit introduces an additional pair of moving pole and zero in the loop gain involved with the magnetizing inductor Lm and the clamping capacitor Cs . Its resonant frequency should be designed away from the crossover frequency fc . According to the circuit parameter given in Section V, the practical design procedures of the closed-loop compensator for the two parallel active-clamp forward converters with current sharing control are analyzed and summarized in the Appendix.

Fig. 12.

PSE–PD interface circuit.

IV. CIRCUIT IMPLEMENTATION A. Design of a PSE–PD Interface Circuit The PSE–PD interface circuit is illustrated in Fig. 12. The PSE–PD interface circuit is designed to ensure the PSE to identify and supply power to PD, which consists of an RJ45 connector with the integrated network transformer, the active bridge, and the PD interface circuit. Compared with the conventional setup of the interface circuit, the active bridge is utilized to replace the diode rectifier bridge for the purpose of the efficiency improvement, which is marked in Fig. 12. Depending on different polarities of the input voltage, one pair of the four MOSFETs are turned ON and kept ON during the operational period. In the typical 48 V/1 A PoE application, the on-resistance of the MOSFET is normally around 100 mΩ. The efficiency of the active bridge at the point of the rate power is 99.6% according to a simple calculation, while the efficiency of the conventional diode bridge is only 98.5% even the Schottky diode with low voltage drop is implemented. Thus, the conduction losses can be reduced by the means of the active bridge scheme. B. Design of Overcurrent Protection Strategy In the PoE system, in order to avoid the excessive line loss and overheating which may potentially accelerate the aging of the cable, the transmitted current should be strictly restrict within a permitted range. However, the current detection and the current limiting strategy may significantly influence the long-term stability of the whole system, which should be designed carefully. The widely applied cycle-by-cycle mode can limit the current indefinitely when the system detects the overcurrent signal. On the contrary, too sensitive action may lead to the reliability reduction of the system because the PWM signal is terminated immediately when the protection occurs. Consequently, the delayed hiccup mode is employed to achieve the overcurrent protection efficiently [19]. The operational principle of the delayed hiccup mode can be explained as follows: as shown in Fig. 13, when an overcurrent condition is detected at the beginning of t1 , a delayed restart timer is started, which can be easily realized by a charging capacitor. At this time, the PWM output is limited to a small duty cycle. If the overcurrent condition still keeps, the voltage


Fig. 13.

Waveforms explanation for the delayed Hiccup mode. Fig. 15.

Fig. 14. = 48 V.

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Input currents with and without current balance control.

Experimental waveforms in module one at full load with V in 1 =V in 2

of the capacitor is charged to a threshold voltage Vth and trigger the restart process. Then, it is discharged and the PWM output shuts down for a period of t2 . After that, the circuit begins the soft-start process t3 . The durations of the shut-down and soft-start processes are all controlled, which is connected to a capacitor being charged by a constant current source. As soon as the circuit is restarted, the overcurrent condition is being detected again. If there is still an overcurrent signal, the voltage on the capacitor CRES may increase again and the hiccup mode sequence is repeated as described previously. By applying the delayed hiccup mode, the circuit can be fully protected as a long cool-down time period t2 is inserted. At the same time, the circuit could show strong anti-interference ability as it may not be shut down by a single detected overcurrent signal. V. EXPERIMENTAL RESULTS In order to further validate the effect of the proposed fourpair PoE architecture with an input current balance scheme, a PoE prototype of 36–60 V input and 12 V output is built. The specifications are shown in Table III. The key waveforms of the individual module at full load with Vin1 = Vin2 = 48 V are shown in Fig. 14, which illustrate the gate-source voltages vgs1 , vgsc1 and the drain-source voltages vds1 , vdsc1 of the main switch S1 and the active-clamp switch SC 1 . It can be seen that the voltage spikes across the switches are slightly small by applying the active-clamp circuit. Therefore, the low-voltage, low-conduction-loss devices can be utilized to achieve high efficiency conversion.

Fig. 16. Input currents and efficiency. (a) Input currents and efficiency at different load conditions. (b) Input currents and efficiency at different input voltages with 4 A load.

The input currents of these two dc/dc modules operated in parallel with and without the current balance control are demonstrated in Fig. 15. The result shows that the imbalance becomes larger with the increase of the load if no current balance control is applied. One module bears nearly four times larger current than the other one under the condition of 2 A load. On the contrary, the input currents in these two modules are almost identical with the input current balance control. According to the results, the system power delivering ability is greatly enhanced by the implementation of the input current balance control. The input currents and conversion efficiency under different load conditions are shown in Fig. 16(a); it can be found that the input currents of these two modules can be maintained nearly identical from the light load to full load, and the conversion efficiency can be kept near 90% from the half to full load. Fig. 16(b) indicates the input currents and conversion efficiency at the different input voltages under the full-load condition. As

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Fig. 18.

Prototype picture.

can be built to a fairly small size as high-efficiency and simple structure is achieved. VI. CONCLUSION

Fig. 17. Input current demonstration when input voltage V in 2 various (a) V in 1 at 42 V with 4 A load, (b) V in 1 at 48 V with 4 A load, (c) V in 1 at 54 V with 4 A load.

seen from the chart, within the range of setting input voltage, the current balance circuit performs well to ensure the difference of input current within 30 mA which is nearly 4% of the maximum current limit. The conversion efficiency increases with the input voltage rising and reaches over 90% when the input voltage is keeping above 60 V. It is inferred from the results that the system efficiency is retained in its optimal level as two converters share the same current stress. In order to further verify the current balancing performance under the different input voltages, one of port input voltages Vin1 is set at 42, 48, and 54 V, respectively, and the other input voltage Vin2 is varied from 36 to 60 V in steps of 2 V; the values of input current in these two modules are recorded and illustrated in Fig. 17(a)–(c) .The results show the good performance of the current balance control over most of the input range. The input current imbalance is restricted within a small difference when the voltages are close and it becomes larger with the bigger difference between the input voltages. However, even under extreme conditions, the results are acceptable for the input current are both under the maximum current limit, which infers that the input current balance works well in all allowed conditions. Finally, the picture of prototype is shown in Fig. 18. The circuit

In order to get more power from the PoE system, a current balanced four-pair architecture with two dc/dc converter modules is introduced in this paper to replace the conventional single dc/dc scheme where the imbalance is almost difficult to be controlled because of its inherent characteristics. Depending on the requirement of the PoE system, the most suitable converter topology is selected by comparing the several potential topologies to achieve the high-efficiency conversion. A control strategy of the input current balance is introduced to solve the problem of imbalance and ensure each return path shares the current identically to void one port exceed its current limit and shut down the PD. The detailed control scheme, the small-signal models, and the circuit implementation including the current limited protection are illustrated and described. Finally, the experimental results have proven that the proposed topology and control strategy can perform well. APPENDIX ANALYSIS AND DESIGN OF A CLOSED-LOOP CONTROL FOR THE PROPOSED SYSTEM The parameters of the power stage are shown in Table III. The resonant frequency of the output LC filter ωo is 1.4 kHz. As shown in Fig. 10, the sample resistor Ri = 0.1 Ω. The transfer function of the input current RC filter Hf is given by Hf =

1 Rh · Ch · s + 1

Ri =

0.1 Ω . 1 × 10−4 · s + 1

(A.1)

The design procedures are given next. Step 1: The external ramp slope M0 is decided first. According to [25], set M0 = 0.5Vo /Lo . This is a common design since the well-known subharmonic oscillation issue existing in the peak current mode control can be eliminated in all cases. Furthermore, the effect of the input voltage variations to the output voltage can be damped to zero.


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TABLE III SPECIFICATION OF THE TESTED PROTOTYPE

Fig. A.2. Bode diagram of voltage loop gain T v and outer loop gain T o , overall loop gain T a : (a) T v and (b) T o and T a .

in the form of Gv =

Fig. A.1. Bode diagram of current loop gain T i and duty cycle gain T d : (a) T i and (b) T d .

Step 2: The transfer functions of the small-signal model shown in Fig. 11 are derived except the voltage compensator gain Gv and the current compensator gain Gi . The below analysis is based on the case which is under the full load and Vin = 36 V. Step 3: The current compensator gain Gi is decided next. As the current feedback loop has no critical stable issue, following the design rules mentioned in Section III, the gain Gi is given by Gc =

s + 10 . s

(A.2)

Step 4: The current loop gain Ti and the duty cycle gain Td are plotted in Fig. A.1. It can be found that the crossover frequency fci of Ti is 30 kHz, which is much less than half of the switching frequency. The crossover frequency fcd of Td is 4 kHz. Since the phase delay is approximately −90◦ in the high-frequency part, there is no stable issue for the current loop and the duty cycle loop. It can also be found that the gain of Td is much smaller than Ti especially in the high-frequency part, which infers that the system loop gain design can focus on Ti and Tv . Step 5: The system crossover frequency fc is defined as the crossover frequency of the outer loop gain To . This is adjusted by designing the voltage compensator gain Gv . Traditional PI controller is applied to voltage compensator, where Gv is given

Kp s + Ki . s

(A.3)

Step 6: Move the left half plane zero of the compensator to equal ωo . It has Ki /Kp = ω o . At the same time, it is reasonable to adjust Kp to get the demanded fc . This can be done by solving the equation |Tv (2πfc )| = |Ti (2πfc )|. However, there is a much simpler way to do this, which is to plot To and varying Kp to get fc by explore the bode diagram. In this design, fc is set to be 3 kHz where Kp = 0.47 and Ki = 4100. The loop gain of Tv and To is plotted in Fig. A.2. The crossover frequency fcv of Tv is 15 kHz, which is smaller than Ti . It can be seen that the phase delay of To is always much smaller than −180◦ within a wide range, which shows a perfect stability performance. Step 7: The overall loop gain Ta , which is also very important to analyze the system dynamic performance, is plotted in Fig. A.2(b). It can be found that the crossover frequency fca is 30 kHz, which is the same as fci . This is because the highfrequency part of Ta is dominated by Ti . If the design is wrong and fcv is higher than fci , fca turns to be the same as fcv . And the system becomes unstable. Step 8: The active-clamp loop is decided at last. The magnetizing inductor Lm is 200 μH according to the transformer design. The value of the clamping capacitor Cc is adjusted to make sure that the inherent resonant frequency fr is far away from the crossover frequency fc . The fr can be expressed as (A.4). If fr is set to be 40 kHz, it has Cc = 80 nF according to the calculation fr =

1−D √ = 40 kHz. 2 · π · Lm Cc

(A.4)

The closed-loop design for the two active-clamp forward converter systems with input current sharing is formulated stepwise, and can be used easily. Moreover, it should be noted that the procedure is a general design guideline, which can be easily applied to a two-loop controlled converter system.

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REFERENCES [1] IEEE 802.3af standard (2003). [Online]. Available: http://www. ieee802.org/3/af/ [2] IEEE 802.3at standard, (2009). [Online]. Available: http://www. ieee802.org/3/at/ [3] S. R. Tom, “Current balancing in four-pair, high-power PoE applications,” Power Management, Texas Instruments Incorporated, Dallas, 2007. [4] B. King and R. Kollman, “To get more power from Ethernet,” Electron. Products China, pp. 68–70, 2008. [5] J.-W. Kim, H.-S. Choi, and B. H. Cho, “A novel droop method for converter parallel operation,” IEEE Trans. Power Electron., vol. 17, no. 1, pp. 25– 32, Jan. 2002. [6] J. Rajagopalan, K. Xing, Y. Guo, F. C. Lee, and B. Manners, “Modeling and dynamic analysis of paralleled DC/DC converters with master-slave current sharing control,” in Proc. 11th Annu. Appl. Power Electron. Conf. Exposition, Mar. 3–7, 1996, vol. 2, pp. 678–684. [7] U. Supatti, S. Boonto, C. Prapanavarat, and V. Moneyakul, “Design of an H∞ robust controller for multi-module parallel DC-DC buck converters with average current mode control,” in Proc. IEEE Int. Conf. Ind. Technol., Dec.11–14, 2002, vol. 2, pp. 992–997. [8] G. Smith, “LM5073HE evaluation board with active bridge,” National Semiconductor, Application Note 1875, Jul. 2, 2008. [9] M. Patoka, “High-power PoE PD using TPS2375/77-1,” Texas InstrumentTM Application Report SLVA225, 2007. [10] High Power PoE Applications, AND8333, Application Report on Semiconductor, (Apr. 2008). [11] B. Bell, “Operation and benefits of active-clamp forward power converters,” Power Designer, National Semiconductor, Application Report 108, 2005. [12] L. Bor-Ren, H.-K. Chiang, K.-C. Chen, and D. Wang, “Analysis, design and implementation of an active clamp flyback converter,” in Proc. Int Conf. Power Electron. Drives Systems, 2005, pp. 424–429. [13] A. Fontan, S. Ollero, E. de la Cruz, and J. Sebastian, “Peak current mode control applied to the forward converter with active clamp,” in Proc. 29th Annu. IEEE Proc. Power Electron. Spec. Conf., 1998, pp. 45–51. [14] B. Choi, B. H. Cho, F. C. Lee, and R. B. Ridley, “Three-loop control for multimodule converter systems,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 466–474, Oct. 1993. [15] Choi, B. H. Cho, R. B. Ridley, and F. C. Lee, “Control strategy for multi-module parallel converter system,” in Proc. 21st Annu. IEEE Power Electron. Spec. Conf., 1990, pp. 225–234. [16] C. Lin and C. Chen, “Single-wire current-share paralleling of currentmode controlled DC power supplies,” in Proc. 29th Annu. IEEE Power Electron. Spec. Conf., 1998, vol. 1, pp. 52–58. [17] J. J. Shieh, “Analysis and design of parallel-connected peak-current-modecontrolled switching DC/DC power supplies,” IEE Proc. –Electr. Power Appl., vol. 151, no. 4, pp. 434–442, Jul. 2004. [18] R. B. Ridley, B. H. Cho, and F. C. Y. Lee, “Analysis and interpretation of loop gains of multiloop-controlled switching regulators [power supply circuits],” IEEE Trans. Power Electron., vol. 3, no. 4, pp. 489–498, Oct. 1988. [19] “Active clamp current mode PWM controller,” National Semiconductor, LM5026 datasheet, 2005. [20] D. Sha, Z. Guo, and X.-Z. Liao, “Cross-feedback output-current-sharing control for input-series-output-parallel modular DC–DC converters,” IEEE Trans. Power Electron., vol. 25, no. 11, pp. 2762–2771, Nov. 2010. [21] J. A. Abu-Qahouq, “Analysis and design of N-phase current-sharing autotuning controller,” IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1641– 1651, Jun. 2010. [22] R. F. Foley, R. C. Kavanagh, and M. G. Egan, “Sensorless current estimation and sharing in multiphase buck converters,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2936–2946, Jun. 2012. [23] J.-H. Lee, J.-H. Park, and H Jeon, “Series-connected forward-flyback converter for high step-up power conversion,” IEEE Trans. Power Electron., vol. 26, no. 12, pp. 3629–3641, Dec. 2011. [24] W. Li, L. Fan, Y. Zhao, X. He, D. Xu, and B. Wu, “High-step-up and highefficiency fuel-cell power-generation system with active-clamp flybackforward converter,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 599– 610, Jan. 2012. [25] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. New York: Springer, 2001. [26] Q. M. Li and F. C. Lee, “Design consideration of the active-clamp forward converter with current mode control during large-signal transient,” IEEE Trans. Power Electron., vol. 18, no. 4, pp. 958–965, Jul. 2003.

Jiande Wu was born in Zhejiang, China, in 1973. He received the B.Sc. degree from the Department of Electrical Engineering, Zhejiang University, Hangzhou, China, and the M.Sc. degree in power electronics from the College of Electrical Engineering, Zhejiang University, in 1994 and 1997, respectively. Since 1997, he has been a faculty member at Zhejiang University, where he is currently a Lecturer. His research interests include applications of power electronics and network communication.

Haimeng Wu (S’10) was born in Zhejiang, China, in 1986. He received the B.Sc. degree from Chongqing University, Chongqing, China, and the M.Sc. degree from the College of Electrical Engineering, Zhejiang University, Hangzhou, China, in 2008 and 2011, respectively. He is currently working toward the Ph.D. degree at the School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, U.K. His current research interests include dc–dc power conversion and control algorithm for electric vehicles.

Chushan Li (S’10) received the B.E.E. degree from the Department of Electrical Engineering, Zhejiang University, Hangzhou, China, in 2008. He is currently working toward the Ph.D. degree from the College of Electrical Engineering, Zhejiang University. From April to September in 2008, he was an Internship Student with the Power Application Design Center, National Semiconductor (Hong Kong) Co. Ltd. From December 2010 to October 2011, he was a Visiting Scholar with the Freedm Center, North Carolina State University, where he was involved in research on solid state transformer and smart grid. His research interests include renewable energy technology and ac–ac power conversion in utility applications

Wuhua Li (M’09) received the B.Sc. and Ph.D. degrees in applied power electronics and electrical engineering from Zhejiang University, Hangzhou, China, in 2002 and 2008, respectively. From September 2004 to March 2005, he was an Intern, and from January 2007 to June 2008, he was a Research Assistant in GE Global Research Center, Shanghai, China. From July 2008 to April 2010, he was with the College of Electrical Engineering, Zhejiang University, as a Postdoctoral Fellow. In May 2010, he became a faculty member at Zhejiang University as a Lecturer. In December 2010, he was promoted as an Associate Professor. From July 2010 to September 2011, he was a Ryerson University Postdoctoral Fellow with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada. He has published more than 70 technical papers and holds more than 20 issued/pending patents. His research interests include high efficiency power converters and renewable energy power conversion system.


Xiangning He (M’95–SM’96–F’10) received the B.Sc. and M.Sc. degrees from the Nanjing University of Aeronautical and Astronautical, Nanjing, China, in 1982 and 1985, respectively, and the Ph.D. degree from Zhejiang University, Hangzhou, China, in 1989. From 1985 to 1986, he was an Assistant Engineer at the 608 Institute of Aeronautical Industrial General Company, Zhuzhou, China. From 1989 to 1991, he was a Lecturer at Zhejiang University. In 1991, he received a Fellowship from the Royal Society of U.K., and conducted research in the Department of Computing and Electrical Engineering, Heriot-Watt University, Edinburgh, U.K., as a Postdoctoral Research Fellow for two years. In 1994, he joined Zhejiang University as an Associate Professor. Since 1996, he has been a Full Professor in the College of Electrical Engineering, Zhejiang University. He was the Director of the Power Electronics Research Institute and the Head of the Department of Applied Electronics, and he is currently the Vice Dean of the College of Electrical Engineering, Zhejiang University. He is the author or coauthor of more than 200 papers and one book titled Theory and Applications of Multi-level Converters (Beijing China: China Machine Press). He holds 12 patents. His research interests include power electronics and their industrial applications. Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 Elite Prize Excellence Award, the 1996 Outstanding Young Staff Member Award, and the 2006 Excellent Staff Award from Zhejiang University for his teaching and research contributions. He received seven Scientific and Technological Achievements Awards from the Zhejiang Provincial Government and the State Educational Ministry of China in 1998, 2002, 2009, and 2011, respectively, and five Excellent Paper Awards. He is a Fellow of the Institution of Engineering and Technology (formerly IEE), U.K.

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Changliang Xia (M’08–SM’12) was born in Tianjin, China, in 1968. He received the B.S. degree from Tianjin University, Tianjin, China, in 1990, and the M.S. and Ph.D. degrees from Zhejiang University, Hangzhou, China, in 1993 and 1995, respectively, all in electrical engineering. He is currently a Professor in the School of Electrical Engineering and Automation, Tianjin University, and also in Tianjin Key Laboratory of Advanced Technology of Electrical Engineering and Energy, Tianjin Polytechnic University. In 2008, he became “Yangtze Fund Scholar” Distinguished Professor and is currently supported by the National Science Foundation of China for Distinguished Young Scholars. His research interests include electrical machines and their control systems, power electronics, and control of wind generators.