power electronics 1

Power Electronics

ii

Table of Contents

1 1

Principles and Elements

Basic Semiconductor Physics and Technology

of

1.1

4

1.1.1 The alloyed junction 1.1.2 The diffused junction Example 1.2: Constant Surface Concentration diffusion – predepostion 7 Example 1.3: Constant Total Dopant diffusion – drive in 8 Example 1.4: Constant Total Dopant diffusion – drive in 8 1.1.3 The epitaxy junction 1.1.4 The ion-implanted junction Example 1.5: Ion implantation 12

POWER ELECTRONICS Devices, Drivers, Applications, and Passive Components

Barry W Williams B.Sc., Dipl.Eng., B.Eng., M.Eng.Sc., Ph.D., D.I.C. Professor of Electrical Engineering University of Strathclyde Glasgow

Published by Barry W Williams ISBN 978-0-9553384-0-3 © Barry W Williams 2006

BWW

Example 1.1: Resistance of homogeneously doped silicon 2 Processes forming pn junctions

1.2

Thin Film Deposition 1.2.1 Chemical Vapour Deposition (CVD) 1.2.2 Physical Vapour deposition (PVD)

1.3

Thermal oxidation and the masking process

17

1.4

Polysilicon deposition

20

1.5.

Lithography – optical and electron 1.5.1 Optical Lithography 1.5.2 Electron Lithography

21

1.6

Etching 1.6.1 Wet Chemical Etching 1.6.2 Dry Chemical Etching

26

1.7

Lift-off Processing

32

1.8

Resistor Fabrication

32

1.9

Isolation Techniques

33

1.10

Wafer Cleaning

33

1.11

Planarization

35

1.12

Gettering

35

1.13

Lifetime control

36

1.14

Silicide formation

36

1.15

Ohmic contact

38

1.16

Glassivation

41

1.17

Back side metallisation and die separation

41

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1.18 1.19

Power Electronics

Wire bonding

3.2

41

Types of silicon 1.19.1 Purifying silicon 1.19.2 Crystallinity 1.19.3 Single crystal silicon 1.19.3i Czochralski process 1.19.3ii Float-zone process 1.19.3iii Ribbon silicon 1.19.4 Multi-crystalline Silicon 1.19.5 Amorphous Silicon

43

1.20

Silicon Carbide

48

1.21

Si and SiC physical and electrical properties compared

48

51

2.1 2.2

53

The pn junction under reverse bias (steady-state)

53

2.2.1 2.2.2 2.2.3 2.3 2.4

52

The pn junction under forward bias (steady-state)

3.3

70 70

73

85

The silicon-controlled rectifier (SCR) 3.3.1i - SCR turn-on 3.3.1ii - SCR cathode shorts 3.3.1iii - SCR amplifying gate

Thermal effects

54

Models for the bipolar junction diode

55

Example 2.4:

Thyristors 3.3.1

Punch-through voltage Avalanche breakdown Zener breakdown

2.4.1 Piecewise-linear junction diode model Example 2.2: Using the pwl junction diode model Example 2.3: Static linear diode model 2.4.2 Semiconductor physics based junction diode model

The bipolar npn power switching junction transistor (BJT)

3.2.1i - BJT gain 3.2.1ii - BJT operating states 3.2.1iii - BJT maximum voltage - first and second breakdown 3.2.2 The metal oxide semiconductor field effect transistor (MOSFET) 3.2.2i - MOSFET structure and characteristics 3.2.2ii - MOSFET drain current 3.2.2iii - MOSFET transconductance and output conductance 3.2.2iv - MOSFET on-state resistance 3.2.2v - MOSFET p-channel device Example 3.1: Properties of an n-channel MOSFET cell 78 3.2.2vi - MOSFET parasitic BJT 3.2.2vii - MOSFET on-state resistance reduction 1 - Trench gate 2 - Vertical super-junction 3.2.3 The insulated gate bipolar transistor (IGBT) 81 3.2.3i - IGBT at turn-on 3.2.3ii - IGBT in the on-state 3.2.3iii - IGBT at turn-off 3.2.3iv - IGBT latch-up 1 - IGBT on-state SCR static latch-up 2 - IGBT turn-off SCR dynamic latch-up 3.2.4 Reverse blocking NPT IGBT 83 3.2.5 PT IGBT and NPT IGBT comparison 84 3.2.6 The junction field effect transistor (JFET) 84

The pn Junction Built-in potential of an abrupt junction

Power switching transistors 3.2.1

2 Example 2.1:

iv

3.3.2 3.3.3 3.3.4 3.3.5

The asymmetrical silicon-controlled rectifier (ASCR) The reverse-conducting thyristor (RCT) The bi-directional-conducting thyristor (BCT) The gate turn-off thyristor (GTO) 3.3.5i - GTO turn-off mechanism

56 56

3.3.6

The gate commutated thyristor (GCT) 3.3.6i - GCT turn-off 3.3.6ii - GCT turn-on

2.4.2i - Determination of zero bias junction capacitance, Cjo 2.4.2ii - One-sided pn diode equations Space charge layer parameter values 60

3.3.7 3.3.8 3.4

The light triggered thyristor (LTT) The triac

Power packages and modules

95

4

3 65

99

Power Switching Devices and their Static Electrical Characteristics

Electrical Ratings and Characteristics of Power Semiconductor Switching Devices

3.1

4.1

Power diodes 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5

The pn fast-recovery diode The p-i-n diode The power Zener diode The Schottky barrier diode The silicon carbide Schottky barrier diode

65

General maximum ratings of power switching semiconductor devices 99 4.1.1 4.1.2 4.1.3 4.1.4

4.2

Voltage ratings Forward current ratings Temperature ratings Power ratings

The fast-recovery diode

101

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4.2.1 4.2.2 4.2.3 4.3

Power Electronics

Turn-on characteristics Turn-off characteristics Schottky diode dynamic characteristics

Example 5.2: 5.3

The bipolar, high-voltage, power switching npn junction transistor 104 4.3.1

Transistor ratings 4.3.1i - BJT collector voltage ratings 4.3.1ii - BJT safe operating area (SOA)

4.3.2

5.4

4.3.3 4.4

BJT phenomena

The power MOSFET 4.4.1 4.4.2

5.5

109

MOSFET absolute maximum ratings

The insulated gate bipolar transistor 4.5.1 4.5.2

4.6

4.6.2

Example 5.3: Heat-sink design for a diode 141 5.5.2 Heat-sinking for IGBTs Example 5.4: Heat-sink design for an IGBT - repetitive operation at a high duty cycle 141 5.5.3 Heat-sinking for power MOSFETs Example 5.5: Heat-sink for a MOSFET - repetitive operation at high peak current, low duty cycle 142 Example 5.6: Heat-sink design for a mosfet - repetitive operation at high duty cycle 143 Example 5.7: Two thermal elements on a common heatsink 143 144 Example 5.8: Six thermal elements in a common package

114

IGBT switching IGBT short circuit operation

The thyristor 4.6.1

138

Heat-sinking for diodes and thyristors 5.5.1i - Low-frequency switching 5.5.1ii - High-frequency switching

Dynamic characteristics 4.4.2i - MOSFET device capacitances 4.4.2ii - MOSFET switching characteristics 1 - MOSFET turn-on 2 - MOSFET turn-off

4.5

136

Switching transition power loss, Ps Off-state leakage power loss, PA Conduction power loss, Pc Drive input device power loss, PG

Heat-sinking design cases 5.5.1

136

Graphical integration Practical superposition

Power losses from manufacturers’ data sheets 5.4.1 5.4.2 5.4.3 5.4.4

Transistor switching characteristics 4.3.2i - BJT turn-on time 4.3.2ii - BJT turn-off time

Semiconductor transient repetitive power capability 135

Average power dissipation 5.3.1 5.3.2

vi

116

SCR ratings 4.6.1i - SCR anode ratings 4.6.1ii - SCR gate ratings

Static characteristics

5.6

Appendix: Comparison between aluminium oxide and aluminium nitride 145

5.7

Appendix: Properties of substrate and module materials

5.8

Appendix: Ampacities and Mechanical Properties of Rectangular Copper Busbars 147

147

4.6.2i - SCR gate trigger requirements 4.6.2ii - SCR holding and latching currents

4.6.3

Dynamic characteristics

6

4.6.3i - SCR anode at turn-on 4.6.3ii - SCR anode at turn-off

4.7

The gate turn-off thyristor

151

Load, Switch, and Commutation Considerations

119

4.7.1 Turn-on characteristics 4.7.2 Turn-off characteristics 4.8

Appendix: Effects on MOSFET switching of negative gate drive

6.1

Cooling of Power Switching Semiconductor Devices

123

6.2 6.3

5.1

Thermal resistances 5.1.1 5.1.2

5.2

124

Modes of power dissipation

130

Switch characteristics

164

Switching classification

164

6.3.1 6.3.2 6.3.3 6.3.4

Contact thermal resistance, Rθc-s Heat-sink thermal resistance, Rθs-a

5.2.1 Steady-state response 5.2.2 Pulse response Example 5.1: Semiconductor single power pulse capability 133 5.2.3 Repetitive transient response

151

6.1.1 The resistive load Example 6.1: Resistive load switching losses 154 Example 6.2: Transistor switching loss for non-linear electrical transitions 155 6.1.2 The inductive load Example 6.3: Zener diode, switch voltage clamping 157 Example 6.4: Inductive load switching losses 161 6.1.3 Diode reverse recovery with an inductive load Example 6.5: Inductive load switching losses with device models 162

121

5

Load types

6.4

Hard switching Soft switching Resonant switching Naturally-commutated switching

Switch configurations

166

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7 169

Driving Transistors and Thyristors 7.1

Application of the power MOSFET and IGBT 7.1.1

Gate drive circuits 9.2

Application of the Thyristor 7.2.1 Thyristor gate drive circuits 7.2.2 Thyristor gate drive design Example 7.2: A light dimmer

7.3

9.3

9.4 180

181 9.5

185

8.1

The non-polarised R-C snubber

9.6

8.2

The soft voltage clamp Example 8.3:

8.3

Soft voltage clamp design

193

8.4

Snubbers for bridge legs

212

8.5

Appendix: Non-polarised turn-off R-C snubber circuit analysis

213

8.6

Appendix: Polarised turn-off R-C-D switching aid circuit analysis

216

Snubbers for series connected devices

242

Turn-off snubber circuit active energy recovery Turn-on snubber circuit active energy recovery Turn-on and turn-off snubber circuit active energy recovery General active recovery concepts

Snubber energy recovery for magnetically coupled based switching circuits 249 9.7.1 Passive recovery 9.7.2 Active recovery

9.8

General passive snubber energy recovery concepts

191

Polarised switching-aid circuits

241

9.7

190

8.3.1 The polarised turn-off snubber circuit - assuming a linear current fall 8.3.2 The turn-off snubber circuit - assuming a cosinusoidal current fall 200 Example 8.4: Capacitive turn-off snubber design 8.3.3 The polarised turn-on snubber circuit - with air core (non-saturable) inductance Example 8.5: Turn-on air-core inductor snubber design 206 8.3.4 The polarised turn-on snubber circuit - with saturable ferrite inductance Example 8.6: Turn-on ferrite-core saturable inductor snubber design 209 8.3.5 The unified turn-on and turn-off snubber circuit

Snubbers for multi-level inverters

9.6.1 9.6.2 9.6.3 9.6.4

186

8.1.1 R-C switching aid circuit for the GCT, the MOSFET, and the diode Example 8.1: R-C snubber design for MOSFETs 187 8.1.2 Non-polarised R-C snubber circuit for a converter grade thyristor and a triac Example 8.2: Non-polarised R-C snubber design for a converter grade thyristor 189

238

Turn-on snubbers Turn-on and turn-off snubbers

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter 9.5.2 Snubbers for the diode-clamped multi-level inverter 9.5.3 Snubbers for the flying-capacitor multi-level inverter

8 Protecting Diodes, Transistors, and Thyristors

232

Passive recovery Active recovery

Inverter bridge legs 9.4.1 9.4.2

225


Unified turn-on and turn-off snubber circuit energy recovery 9.3.1 9.3.2

221


Energy recovery for capacitive turn-off snubber circuits 9.2.1 9.2.2

177

Drive design for GCT and GTO thyristors

Energy recovery for inductive turn-on snubber circuits 9.1.1 9.1.2

7.1.2 Gate drive design procedure Example 7.1: MOSFET input capacitance and switching times 177

221

Switching-aid Circuits with Energy Recovery 9.1

169

7.1.1i - Negative gate drive 7.1.1ii - Floating power supplies 1 - capacitive coupled charge pump 2 - diode bootstrap

7.2

viii

250

10

257

Series and Parallel Device Operation, Protection, and Interference 10.1

Parallel and series connection and operation of power semiconductor devices 257 10.1.1 Series semiconductor device operation 10.1.1i - Steady-state voltage sharing

Example 10.1: Series device connection – static voltage balancing 259 10.1.1ii - Transient voltage sharing

Example 10.2: Series device connection – dynamic voltage balancing 262 10.1.2 Parallel semiconductor device operation 10.1.2i - Matched devices 10.1.2ii - External forced current sharing

Example 10.3: Resistive parallel current sharing – static current balancing

265 (a) current sharing analysis for two devices:– ro = 0 (b) current sharing analysis for two devices:– ro ≠ 0 (c) current sharing analysis for n devices:– ro = 0 Example 10.4: Transformer current sharing–static and dynamic current balancing 270

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10.2

Power Electronics

Protection

271

10.2.1 Overcurrent

11.3

276

278

11.4

10.2.2i - Transient voltage suppression devices 10.2.2ii - Comparison between Zener diodes and varistors

Example 10.7: Non-linear voltage clamp 10.2.3 The Crowbar 10.3

273

Interference

284

10.3.1 Noise 10.3.1i - Conducted noise 10.3.1ii - Radiated electromagnetic field coupling 10.3.1iii - Electric field coupling 10.3.1iv - Magnetic field coupling

10.3.2 Mains filters 10.3.3 Noise filtering precautions

11 Naturally Commutating AC to DC Converters – Uncontrolled Rectifiers 11.1

Single-phase uncontrolled converter circuits - ac rectifiers

289

289

11.1.1 Half-wave circuit with a resistive load, R 11.1.2 Half-wave circuit with a resistive and back emf R-E load Example 11.1: Half-wave rectifier with resistive and back emf load 291 11.1.3 Single-phase half-wave circuit with an R-L load

11.1.7ii 11.1.7iii

Example 11.6: 11.1.7iv

11.2

- Single-phase full-wave bridge rectifier circuit with an output L-C filter Full-wave diode rectifier with L-C filter and continuous load current 305 - Single-phase full-wave bridge recifier with highly inductive loads–constant load current - Single-phase full-wave bridge rectifier circuit with a C-filter and resistive load Single-phase full-wave bridge circuit with C-filter and resistive load 311 - Other single-phase bridge rectifier circuit configurations

Three-phase uncontrolled rectifier converter circuits

Voltage multipliers 11.4.1 Half-Wave Series Multipliers 11.4.2 Half-Wave Parallel Multipliers 11.4.3 Full-Wave Series Multipliers Example 11.9: Half-wave voltage multiplier Example 11.10: Full-wave voltage multiplier 11.4.4 Three-phase voltage multipliers 11.4.5 Series versus parallel voltage multipliers

345

349 350

Marx voltage generator

350

11.6

Definitions

352

11.7

Output pulse number

352

11.8

AC-dc converter generalised equations

353

12 Naturally Commutating AC to DC Converters – Controlled Rectifiers Single-phase full-wave half-controlled converter

361

12.1i - Discontinuous load current 12.1ii - Continuous load current

Example 11.2: Half-wave rectifier with source resistance 295 11.1.4 Single-phase half-wave circuit with an R-L load and freewheel diode 299 Example 11.3: Half-wave rectifier – with load freewheel diode 11.1.5 Single-phase full-wave bridge rectifier circuit with a resistive load, R 11.1.6 Single-phase full-wave bridge rectifier circuit with a resistive and back emf load Example 11.4: Full-wave rectifier with resistive and back emf load 253 11.1.7 Single-phase full-wave bridge rectifier circuit with an R-L load Example 11.5:

320

11.5

12.1

11.1.3i - Inductor equal voltage area criterion 11.1.3ii - Load current zero slope criterion

11.1.7i

DC MMFs in converter transformers

11.3.1 Effect of multiple coils on multiple limb transformers 11.3.2 Single-phase toroidal core mmf imbalance cancellation – zig-zag winding 11.3.3 Single-phase transformer connection, with full-wave rectification 11.3.4 Three-phase transformer connections 11.3.5 Three-phase transformer, half-wave rectifiers - core mmf imbalance 11.3.6 Three-phase transformer with hexa-phase rectification, mmf imbalance 11.3.7 Three-phase transformer mmf imbalance cancellation – zig-zag winding 11.3.8 Three-phase transformer full-wave rectifiers – zero core mmf

2

10.2.1i - Pre-arcing I t 2 10.2.1ii - Total I t let-through 10.2.1iii - Fuse link and semiconductor I2t co-ordination 10.2.1iv - Fuse link derating and losses

Example 10.5: AC circuit fuse link design 10.2.1v - Fuse link dc operation 10.2.1vi - Alternatives to dc fuse operation Example 10.6: DC circuit fuse link design 10.2.2 Overvoltage

x

313

11.2.1 Three-phase half-wave rectifier circuit with an inductive R-L load 11.2.2 Three-phase full-wave rectifier circuit with an inductive R-L load 11.2.2i - Three-phase full-wave bridge rectifier circuit with continuous load current 11.2.2ii - Three-phase full-wave bridge rectifier circuit with highly inductive load Example 11.7: Three-phase full-wave rectifier 318 Example 11.8: Rectifier average load voltage 319

12.2

Single-phase controlled thyristor converter circuits

365

12.2.1 Single-phase half-wave circuit with an R-L load 12.2.1i - Case 1: Purely resistive load 12.2.1ii - Case 2: Purely inductive load 12.2.1iii - Case 3: Back emf E and R-L load

Example 12.1: Half-wave controlled rectifier 12.2.2 Single-phase half-wave half-controlled

368

12.2.2i - discontinuous conduction 12.2.2ii - continuous conduction

12.2.3 Single-phase full-wave controlled rectifier circuit with an R-L load 12.2.3i - α > φ , β - α < π , discontinuous load current 12.2.3ii - α = φ , β - α = π , verge of continuous load current 12.2.3iii - α < φ , β- π = α, continuous load current (and also purely inductive load) Example 12.2: Controlled full-wave converter – continuous and discontinuous conduction 375 12.2.4 Single-phase full-wave, fully-controlled circuit with R-L and emf load, E 12.2.4i - Discontinuous load current 12.2.4ii - Continuous load current Example 12.3: Controlled converter - continuous conduction and back emf 380 Example 12.4: Controlled converter – constant load current, back emf, and overlap 381

361

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12.3

Power Electronics

Three-phase half-controlled converter

382 13.4

12.3i - α ≤ ⅓π 12.3ii - α ≥ ⅓π

12.4

Three-phase fully-controlled thyristor converter circuits

384

Inductive-resistive load Purely inductive load i. ½π ≤ α ≤ ⅔π [mode 3/2] ii. ⅔π ≤ α ≤ π [mode 2/0]

Example 12.5: Three-phase half-wave rectifier with freewheel diode 386 12.4.3 Three-phase full-wave fully-controlled circuit with an inductive load

13.4.2 Fully-controlled three-phase ac regulator with wye load and neutral connected 13.4.3 Fully-controlled three-phase ac regulator with delta load 13.4.4 Half-controlled three-phase ac regulator Resistive load

12.4.3i - Resistive load 12.4.3ii - Highly inductive load – constant load current

Example 12.6: Three-phase full-wave controlled rectifier with constant output current 391 12.4.4 Three-phase full-wave converter with freewheel diode Example 12.7: Converter average load voltage 393 Overlap

394

12.6

Overlap – inversion

397

12.7

Purely inductive load 13.4.5 Other thyristor three-phase ac regulators i. Delta connected fully controlled regulator ii. Three-thyristor delta connected regulator Example 13.4: Star-load three-phase ac regulator – untapped neutral 444

400

(i) Half-wave and full-wave, fully-controlled converter (ii) Full-wave, half-controlled converter (iii) Half-wave and full-wave controlled converter with load freewheel diode

12.8

Definitions

401

12.9

Output pulse number

402

12.10


404

13.5

Cycloconverter

449

13.6

The matrix converter

452

13.7

Power Quality: load efficiency and supply current power factor

454

13.7.1 Load waveforms 13.7.2 Supply waveforms Example 13.5: Power quality - load efficiency 456 Example 13.6: Power quality - sinusoidal source and constant current load 456 Example 13.7: Power quality - sinusoidal source and non-linear load 457

14

13

461 413

AC Voltage Regulators 13.1

i. 0 ≤ α ≤½π ii. ½π ≤ α ≤ ⅔π iii. ⅔π ≤ α ≤ 7π/6

399

Summary

Single-phase ac regulator

413

DC Choppers 14.1

DC chopper variations

461

14.2

First Quadrant dc chopper

462

14.2.1 Continuous load current Steady-state time domain analysis of first quadrant chopper - with load back emf and continuous output current

13.1.1 Single-phase ac regulator – phase control with line commutation Case 1: α > φ Case 2: α ≤ φ 13.1.1i 13.1.1ii 13.1.1iii 13.1.1iv -

i. Fourier coefficients ii. Time domain differential equations

Resistive Load Pure inductive Load Load sinusoidal back emf Semi-controlled single-phase ac regulator

14.2.2 Discontinuous load current Steady-state time domain analysis of first quadrant chopper - with load back emf and discontinuous output current

Example 13.1a: Single-phase ac regulator – 1 423 Example 13.1b: Single-phase ac regulator - 2 424 Example 13.1c: Single-phase ac regulator – pure inductive load 245 Example 13.1d: Single-phase ac regulator – 1 with ac back emf composite load 427 13.1.2 Single-phase ac regulator – integral cycle control – line commutated Example 13.2: Integral cycle control 430 13.2 13.3

437

i. 0 ≤ α ≤ ⅓π [mode 3/2] ii. ⅓π ≤ α ≤ ½π [mode 2/2] iii. ½π ≤ α ≤ π [mode 2/0]

12.4.2i - α < π/6 12.4.2ii - α >π/6 12.4.2iii - α >5π/6

12.7

Three-phase ac regulator

13.4.1 Fully-controlled three-phase ac regulator with wye load and isolated neutral Purely resistive load

12.4.1 Three-phase half-wave, fully controlled circuit with an inductive load 12.4.2 Three-phase half-wave converter with freewheel diode

Example 12.8: Converter overlap

xii

Single-phase transformer tap-changer – line commutated Example 13.3: Tap changing converter Single-phase ac chopper regulator – commutable switches

432 434

437

i. Fourier coefficients ii. Time domain differential equations

Example 14.1: DC chopper (first quadrant) with load back emf 470 Example 14.2: DC chopper with load back emf - verge of discontinuous conduction 474 Example 14.3: DC chopper with load back emf - discontinuous conduction 475 14.3

Second Quadrant dc chopper

478

14.3.1 Continuous load inductor current 14.3.2 Discontinuous load inductor current Example 14.4: Second quadrant DC chopper - continuous inductor current 482

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15.4 14.4

Two quadrant dc chopper - Q I and Q II

484

Two quadrant dc chopper – Q 1 and Q IV

433

15.5

14.5.1 dc chopper: – Q I and Q IV – multilevel output voltage switching (three level) 14.5.2 dc chopper: – Q I and Q IV – bipolar voltage switching (two level) 14.5.3 Multilevel output voltage states, dc chopper 497 Example 14.6: Asymmetrical, half H-bridge, dc chopper 14.6

Four quadrant dc chopper

Reversible dc link converters

554

15.4.1 Independent control 15.4.2 Simultaneous control 15.4.3 Inverter regeneration

Example 14.5: Two quadrant DC chopper with load back emf 484 14.5

xiv

Standby inverters and uninterruptible power supplies

557

15.5.1 Single-phase ups 15.5.2 Three-phase ups 15.6

499

14.6.1 Unified four quadrant dc chopper - bipolar voltage output switching 14.6.2 Unified four quadrant dc chopper - multilevel voltage output switching Example 14.7: Four quadrant dc chopper 506

Power filters

559

16

561

DC to AC Inverters – Resonant Mode

15 509

DC to AC Inverters – Switched Mode 15.1

dc to ac voltage-source inverter bridge topologies

16.1

Resonant dc-ac inverters

561

16.2

L-C resonant circuits 16.2.1 - Series resonant L-C-R circuit 16.2.2 - Parallel resonant L-C-R circuit

562

16.3

Series resonant inverters 16.3.1 - Series resonant inverter – single inverter leg

565

509

15.1.1 Single-phase voltage-source inverter bridge 15.1.1i - Square-wave (bipolar) output 15.1.1ii - Quasi-square-wave (multilevel) output

1 - Lagging operation (advancing the switch turn-off angle) 2 - Leading operation (delaying the switch turn-on angle)

Example 15.1: Single-phase H-bridge with an L-R load 515 Example 15.2: H-bridge inverter ac output factors 516 Example 15.3: Harmonic analysis of H-bridge with an L-R load 518 Example 15.4: Single-phase half-bridge with an L-R load 518

16.3.2 - Series resonant inverter – H-bridge voltage-source inverter 16.3.3 - Circuit variations 16.4

15.1.1iii - PWM-wave output

15.1.2 Three-phase voltage-source inverter bridge

Parallel resonant current-source inverters

570

16.4.1 - Parallel resonant inverter – single inverter leg 16.4.2 - Parallel resonant inverter – H-bridge current-source inverter

15.1.2i - 180° (π) conduction 15.1.2ii - 120° (⅔π) conduction

Example 16.1: Half-bridge with a series L-C-R load

572

15.1.3 Inverter ac output voltage and frequency control techniques 16.5

15.1.3i - Variable voltage dc link 15.1.3ii - Single-pulse width modulation

Example 15.5: Single-pulse width modulation

dc-to-ac controlled current-source inverters

17

Multi-level voltage-source inverters 15.3.1 15.3.2 15.3.3 15.3.4

Diode clamped multilevel inverter Flying capacitor multilevel inverter Cascaded H-bridge multilevel inverter PWM for multilevel inverters 15.3.4i - Multiple offset triangular carriers 15.3.4ii - Multilevel rotating voltage space vector

577

DC to DC Converters - Switched Mode 17.1

The forward converter 17.1.1 17.1.2 17.1.3 17.1.4

543

15.2.1 Single-phase current source inverter 15.2.2 Three-phase current source inverter 15.3

575

529

15.1.3iii - Multi-pulse width modulation 15.1.3iv - Multi-pulse, selected notching modulation 15.1.3v - Sinusoidal pulse-width modulation (pwm) 1 - Natural sampling 2 - Regular sampling 3 - Frequency spectra of pwm waveforms 15.1.3vi - Phase dead-banding 15.1.3vii - Triplen Injection modulation 1 - Triplens injected into the modulation waveform 2 - Voltage space vector pwm

15.2

Single-switch, current source, series resonant inverter

578

Continuous inductor current Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current 17.1.4i - fixed on-time tT, variable switching frequency fvar 17.1.4ii - fixed switching frequency fs, variable on-time tTvar

17.1.5 Output ripple voltage Example 17.1: Buck (step-down forward) converter 583 17.1.6 Underlying operational mechanisms of the forward converter

546 17.2

Flyback converters

588

17.3

The boost converter

589

17.3.1 Continuous inductor current

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17.3.2 17.3.3 17.3.4 17.3.5

Power Electronics

Discontinuous capacitor charging current in the switch off-state Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

18 18.1

17.3.6 Output ripple voltage 593 Example 17.2: Boost (step-up flyback) converter Example 17.3: Alternative boost (step-up flyback) converter 595 The buck-boost converter 17.4.1 17.4.2 17.4.3 17.4.4 17.4.5

597

18.2

18.3

17.6

18.4 602

Flyback converters – a conceptual assessment

607

612

18.4.4 Zero-voltage, resonant-switch, dc-to-dc converter -½ wave, CR parallel with load version Example 18.2: Zero-current, resonant-switch, dc-to-dc converter - ½ wave 673 Example 18.3: Zero-current, resonant-switch, dc-to-dc converter - full-wave 675 Example 18.4: Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave 676 18.5

677

18.5

Appendix: Matrices of resonant switch buck, boost, and buck/boost converters 681

614

Comparison of basic converters

615

19 687

HV Direct-Current Transmission

17.8.3i - The isolated output, forward converter 17.8.3ii - The isolated output, flyback converter

19.1

621 623

Multiple-switch, balanced, isolated converters

19.2

17.10

Basic generic smps transfer function mapping

627

17.11

Appendix: Analysis of non-continuous inductor current operation

629

HVDC electrical power transmission

687

HVDC Configurations

688

19.2i - Monopole and earth return 19.2ii - Bipolar 19.2iii - Tripole 19.2iv - Back-to-back 19.2v - Multi-terminal

625

17.9.1 The push-pull converter 17.9.2 Bridge converters

Operation with constant input voltage, Ei Operation with constant output voltage, vo

Resonant switch, dc to dc step-up voltage converters 18.5.1 ZCS resonant-switch, dc-to-dc step-up voltage converters 18.5.2 ZVS resonant-switch, dc-to-dc step-up voltage converters

17.8.1 Critical load current 17.8.2 Bidirectional converters 17.8.3 Isolation

17.9

660

-½ wave, CR parallel with switch version

The Ćuk converter

Example 17.7: Transformer coupled flyback converter Example 17.8: Transformer coupled forward converter

Resonant switch, dc to dc step-down voltage converters

18.4.3i - Zero-voltage, full-wave resonant switch converter

Example 17.5: Reversible forward converter 610 17.6.5 Comparison of the reversible converter with alternative converters

17.8

Series–parallel load resonant dc to dc converters 655 18.3.1 LCC resonant tank circuit 18.3.2 LLC resonant tank circuit Example 18.1: Transformer-coupled, series-resonant, dc-to-dc converter 658

18.4.1i - Zero-current, full-wave resonant switch converter

Continuous inductor current Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

17.7.1 Continuous inductor current 17.7.2 Discontinuous inductor current 17.7.3 Optimal inductance relationship 17.7.4 Output voltage ripple Example 17.6: Cuk converter

652

18.4.2 Zero-current, resonant-switch, dc-to-dc converter -½ wave, CR parallel with switch version 18.4.3 Zero-voltage, resonant-switch, dc-to-dc converter

17.6.4i - fixed on-time tT, variable switching frequency fvar 17.6.4ii - fixed switching frequency fs, variable on-time tTvar

17.7

Parallel loaded resonant dc to dc converters

18.4.1 Zero-current, resonant-switch, dc-to-dc converter -½ wave, CR parallel with load version

604

The output reversible converter 17.6.1 17.6.2 17.6.3 17.6.4

647

18.2.1 Modes of operation- parallel resonant circuit 18.2.2 Circuit variations


17.5

Series loaded resonant dc to dc converters 18.1.1 Modes of operation - series resonant circuit 18.1.2 Circuit variations

Continuous choke (inductor) current Discontinuous capacitor charging current in the switch off-state Discontinuous choke current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

17.4.6 Output ripple voltage 17.4.7 Buck-boost, flyback converter design procedure Example 17.4: Buck-boost flyback converter

647

DC to DC Converters - Resonant Mode


17.4

xvi

19.3

Typical HVDC transmission system

689

19.4

Twelve-pulse ac line frequency converters

690

19.4.1 Rectifier mode 19.4.2 Inverter mode

Power Electronics

xvii

19.5

Power Electronics

Twelve-pulse ac line frequency converter operation control

695

20.7.3 - Unified power flow controller - UPFC

19.5.1 Control and protection 19.5.2 HVDC Control objectives 19.6

20.8

Filtering and power factor correction

VSC-Based HVDC

Combined Active and Passive Filters

747

20.8.1 - Current compensation – shunt filtering 20.8.2 - Voltage compensation – series filtering 20.8.3 - Active and passive combination filtering

698

Example 19.1: Basic six-pulse converter based hvdc transmission 699 Example 19.2: 12-pulse hvdc transmission 700 19.7

xviii

20.9

702

20.10

705

21

Summary of Compensator Comparison and Features

749

Summary of General Advantages of AC Transmission over DC Transmission 750

19.7.1 VSC-Based HVDC control 19.7.2 Power control concept 19.8

HVDC Components

751

Energy Sources and Storage: Primary Sources

Example 19.3: HVDC transmission with voltage source controlled dc-link 707 19.9

Twelve-pulse transformer based HVDC

709

19.10

HVDC VSC Features

709

19.11

Features of conventional HVDC and HVAC transmission

710

21.1

Hydrocarbon attributes

751

21.2

The fuel cell

753

21.3

Materials and cell design

755

21.3.1 21.3.2 21.3.3 21.3.4 21.3.5

20 713

FACTS Devices and Custom Controllers

21.4 20.1

Flexible AC Transmission Systems - FACTS

713

20.2

Power Quality

713

20.3

Principles of Power Transmission

714

Example 20.1: AC transmission line VAr Static Reactive Power Compensation

717

20.5

Static Shunt Reactive Power Compensation

718

21.4.1 Proton H Cation Conducting Electrolyte 21.4.2 Anion (OH-, CO32-, O2-) Conducting Electrolyte 21.5

Six different Fuel Cells

760

21.6

Low-temperature Fuel Cell Types

761

21.6.1 Polymer exchange membrane fuel cell 21.6.2 Alkaline fuel cell 21.6.3 Direct-methanol fuel cell 21.7

Custom Power

High-temperature Fuel Cell Types

764

21.7.1 Phosphoric-acid fuel cell 21.7.2 Molten-carbonate fuel cell 21.7.3 Solid oxide fuel cell 724

20.6.1 - Thyristor switched series capacitor TSSC 20.6.2 - Thyristor controlled series capacitor TCSC 20.6.3 - Series Static VAr compensator SVC (TCR//C) Example 20.3: Series thyristor controlled reactor specification – integral control 728 Example 20.4: Series thyristor controlled reactor specification – Vernier control 730 20.6.4 Static series phase angle reactive power compensation/shift SPS 20.7

758

+

20.5.1 - Thyristor controlled reactor TCR 20.5.2 - Thyristor switched capacitor TSC 20.5.3 - Shunt Static VAr compensator SVC (TCR//TSC) Example 20.3: Shunt thyristor controlled reactor specification 723 Static Series Reactive Power Compensation

Fuel Cell Chemistries

715

20.4

20.6

Electrodes Catalyst Electrolyte Interconnect Stack design

735

20.7.1 - Static synchronous series compensator or Dynamic Voltage Restorer - DVR 20.7.2 - Static synchronous shunt compensator – STATCOM

21.8

Fuel Cell Summary

768

21.9

Fuels

768

21.10

Fuel Reformers

769

21.10.1 Natural gas reforming 21.11

Hydrogen storage and generation from Sodium Borohydride

772

21.12

Fuel Cell Emissions

772

21.13

Fuel Cell Electrical characteristics

773

Power Electronics

xix

21.14

Power Electronics

Thermodynamics Example 21.1: Formation of water vapour Example 21.2: Derivation of Ideal Fuel Cell Voltage Example 21.3: Carbon fuel cell

774 775 776 778

21.15

Fuel Cell features

779

21.16

Fuel Cell Challenges

780

781

21.18

Photovoltaic Cells: Converting Photons to Electrons

784

21.19

Silicon structural physics

784

21.20

Semiconductor materials and structures

785

21.22

814

22.4

The lead-acid battery

816

22.6

820

The nickel-metal-hydride battery

22.7

The lithium-ion battery 22.7.1 22.7.2 22.7.3 22.7.4

PV Cell Structures

823

22.6.1 Nickel-metal-hydride battery properties 22.6.2 Nickel-metal-hydride battery characteristics

Silicon Polycrystalline thin films Single-Crystalline Thin Film Nanocrystalline 794

Homojunction Device Heterojunction Device p-i-n and n-i-p Devices Multi-junction Devices

825

Cathode variants cells General Lithium-ion Cell characteristics General Lithium-ion Cell properties Cell protection circuits

22.8

Summary of key primary and secondary cell technologies

832

22.9

The Electrochemical Double Layer Capacitor - supercapacitor

833

22.9.1 Double layer capacitor model 22.9.2 Supercapacitor general properties

Equivalent circuit of a PV cell

797

23

21.22.1 Ideal PV cell model 21.22.2 Practical PV cell model 21.22.3 Maximum-power point

839

Inverter Grid Connection for Embedded Generation

21.23

Photovoltaic cell efficiency factors

800

21.24

Module (or array) series and parallel PV cell connection

801

Example 21.4: PV cell and module characteristics

The nickel-cadmium battery 22.5.1 Nickel-Cadmium battery properties

Fuel cell summary

21.21.1 21.21.2 21.21.3 21.21.4

Characteristics of Secondary Batteries

22.5

21.17

21.21

22.3

21.4.1 The Flooded lead acid cell 22.4.2 Different lead-acid cell and battery arrangements 22.4.3 Lead-acid battery properties

21.16.1 Chemical Technology Challenges 21.16.2 System Technology Challenges

21.20.1 21.20.2 21.20.3 21.20.4

xx

24

802

21.25

Battery storage

803

21.26

The organic photovoltaic cell

804

21.27

Summary of PV cell technology

806

843

Inductors and Transformers 24.1

Inductor and transformer electrical characteristics

844

24.1.1 Inductors 24.1.2 Transformers or magnetically coupled circuits

22

24.2

Energy Sources and Storage: Secondary Sources 22.1

Batteries

22.2

The secondary electro-chemical cell 810 22.2.1 REDOX Galvanic Action 22.2.2 Intercalation Action

Magnetic material types

846

24.2.1 Ferromagnetic materials

809

24.2.1i - Steel 24.2.1ii - Iron powders 24.2.1iii - Alloy powders 24.2.1iv - Nanocrystalline

809

24.2.2 Ferrimagnetic materials- soft ferrites 24.3

Comparison of material types

847

24.4

Ferrite characteristics

848

Power Electronics

xxi

Power Electronics

24.14

24.4.1 Dimensions and parameters 24.4.2 Permeability 24.4.2i 24.4.2ii 24.4.2iii 24.4.2iv 24.4.2v

-

25.1 25.2

24.4.4i - Core losses at low H 24.4.4ii - Core losses at high H

24.4.6i - Parameter effects 24.4.6ii - Time effects

25.3 858

865

25.4

869 873

Thermal properties

25.5

Repetitive pulsed power resistor behaviour Example 25.6: Pulsed power resistor design 25.5.1 Empirical pulse power 25.5.2 Mathematical pulse power models Example 25.7: Solid carbon ceramic resistor power rating

878

25.6

24.8

Appendix: Technical data for a ferrite applicable to power applications

882

24.9

Appendix: Technical data for iron, nickel, and cobalt applicable to power applications 882

24.10

Appendix: Cylindrical inductor design

25.7

24.11

Appendix: Copper wire design data

885

24.12

Appendix: Minimisation of stray inductance

885

909 910

911

Stability and endurance Example 25.8: Power resistor stability Special function power resistors 25.7.1 25.7.2 25.7.3 25.7.4

883 883 884

905

25.4.1 Resistors with heatsink Example 25.4: Derating of a resistor mounted on a heatsink 908 25.4.2 Short time or overload ratings Example 25.5: Non-repetitive pulse rating 909

869

881

912 913

914

Fusible resistors Circuit breaker resistors Temperature sensing resistors Current sense resistors

25.8

Appendix: Carbon ceramic electrical and mechanical data and formula 917

25.9

Appendix: Preferred resistance values of resistors (and capacitors) 917

26

24.11.1 Reduction in wiring residual inductance 24.11.2 Reduction in component residual inductance 24.11.2i - Capacitors 24.11.2ii - Capacitors - parallel connected 24.11.2iii - Transformers

Appendix: Laminated bus bar design

899

25.3.1ii - Voltage coefficient of resistance

862

Appendix: Soft ferrite general technical data

24.13

Electrical properties

25.3.2 Maximum working voltage 25.3.3 Residual capacitance and residual inductance Example 25.3: Coefficients of resistance for a solid carbon ceramic resistor 905

24.7

Example 24.8: Wound strip air core inductor Example 24.9: Multi-layer air core inductor

896

Example 25.2: Temperature coefficient of resistance for a thick film resistor 902

860

Power ferrite transformer design 24.6.1 Ferrite voltage transformer design Example 24.6: Ferrite voltage transformer design 24.6.2 Ferrite current transformer 24.6.3 Current transformer design requirements 24.6.4 Current transformer design procedure Example 24.7: Ferrite current transformer design 24.6.5 Current measurement: closed loop ferrite transformer 24.6.6 Current measurement: Rogowski Coil

896

25.3.1 Resistor/Resistance coefficients

24.5.1i - Core temperature and size considerations

24.6

Resistor construction

25.3.1i - Temperature coefficient of resistance

Ferrite inductor and choke design, when carrying dc current

Example 24.4: Inductor design including copper loss 24.5.2 Saturable inductors 24.5.3 Saturable inductor design Example 24.5: Saturable inductor design

896

858

24.4.6iii - Temperature effects

24.5.1 Linear inductors and chokes Example 24.3: Inductor design with Hanna curves

895

Resistor types

25.2.1 Film resistor construction 25.2.2 Carbon composition film resistor construction Example 25.1: Carbon film resistor 25.2.3 Solid Carbon ceramic resistor construction 25.2.4 Wire-wound resistor construction

24.4.5 Temperature effects on core characteristics 24.4.6 Inductance stability

24.5

891

Resistors

24.4.3 Coercive force and remanence 24.4.4 Core losses

Example 24.2: Temperature effect on inductance 24.4.7 Stored energy in inductors

Appendix: Materials by types of magnetization

25

Initial or intrinsic permeability, µi ∧ Amplitude permeability, µa and maximum permeability, µ Reversible or incremental permeability, µrev, µ∆ Effective permeability, µe Complex permeability, µ

Example 24.1: Inductance variation with time

xxii

919

Capacitors 888

26.1

Capacitor general properties 26.1.1 Capacitance

920

Power Electronics

xxiii

26.1.2 Volumetric efficiency 26.1.3 Equivalent circuit 26.1.4 Lifetime and failure rate Example 26.1: Failure rate Example 26.2: Capacitor reliability 26.1.5 Self-healing 26.1.6 Temperature range and capacitance dependence 26.1.7 Dielectric absorption 26.2

Power Electronics

26.2.1 Construction 26.2.2 Voltage ratings 26.2.3 Leakage current 26.2.4 Ripple current Example 26.3: Capacitor ripple current rating 26.2.5 Service lifetime and reliability

Glossary of terms

924 924

Liquid (organic) and solid, metal oxide dielectric capacitors

932

26.2.5ii - Solid, oxide capacitors

Example 26.5: Lifetime of tantalum capacitors 26.3

933

Plastic film dielectric capacitors

934

26.3.1 Construction 26.3.1i - Metallised plastic film dielectric capacitors 26.3.1ii - Foil and plastic film capacitors 26.3.1iii - Mixed dielectric capacitors

26.3.2 Insulation 26.3.3 Electrical characteristics 26.3.3i - Temperature dependence 26.3.3ii - Dissipation factor and impedance 26.3.3iii - Voltage derating

Example 26.6: Power dissipation limits - ac voltage

940

26.3.3iv - Pulse dVR /dt rating

26.3.4 Non-sinusoidal repetitive voltages Example 26.7: Capacitor non-sinusoidal voltage rating 942 Example 26.8: Capacitor power rating for non-sinusoidal voltages 943 26.4

Emi suppression capacitors

943

26.4.1 Class X capacitors 26.4.2 Class Y capacitors 26.4.3 Feed-through capacitors 26.5

Ceramic dielectric capacitors

945

26.5.1 Class I dielectrics 26.5.2 Class II dielectrics 26.5.3 Applications 26.6

Mica dielectric capacitors

Bibliography

972

Physical constants

982

INDEX

930

948

26.6.1 Properties and applications 26.7

Capacitor type comparison based on key properties

950

26.8

Appendix: Minimisation of stray capacitance

950

26.9

Appendix: Capacitor lifetime derating

950

953

Glossary of wafer processing terminology Glossary of electrochemical battery terminology Glossary of Fuel Cell Terminology Glossary of Solar Electric terminology Glossary of Capacitor terminology

926

26.2.5i - Liquid, oxide capacitors

Example 26.4: A1203 capacitor service life

xxiv

983

Power Electronics

xxv

PREFACE

The book is in four parts. Part 1 covers power semiconductor switching devices, their static and dynamic electrical and thermal characteristics and properties. Part 2 describes device driving and protection, while Part 3 presents a number of generic applications. The final part, Part 4, introduces capacitors, magnetic components, and resistors, and their characteristics relevant to power electronic applications. 1 2 3 4 5

Basic Semiconductor Physics and Technology The pn Junction Power Switching Devices and their Static Electrical Characteristics Electrical Ratings and Characteristics of Power Semiconductor Switching Devices Cooling of Power Switching Semiconductor Devices

6 7 8 9 10

Load, Switch, and Commutation Considerations Driving Transistors and Thyristors Protecting Diodes, Transistors, and Thyristors Switching-aid Circuits with Energy Recovery Series and Parallel Device Operation, Protection, and Interference

11 12 13 14 15 16 17 18 19 20 21 22 23

Naturally Commutating AC to DC Converters – Uncontrolled Rectifiers Naturally Commutating AC to DC Converters – Controlled Rectifiers AC Voltage Regulators DC Choppers DC to AC Inverters – Switched Mode DC to AC Inverters – Resonant Mode DC to DC Converters - Switched-mode DC to DC Converters - Resonant-mode HV Direct-Current Transmission FACTS Devices and Custom Controllers Energy Sources and Storage: Primary Sources Energy Sources and Storage: Secondary Sources Inverter Grid Connection for Embedded Generation

24 25 26

Inductors and Transformers Resistors Capacitors

The 122 non-trivial worked examples cover the key issues in power electronics.

BWW July 2008

CHAPTER

1


The majority of power electronic circuits utilise power semiconductor switching devices which ideally present infinite resistance when off, zero resistance when on, and switch instantaneously between those two states. It is necessary for the power electronics engineer to have a general appreciation of the semiconductor physics aspects applicable to power switching devices so as to be able to understand the vocabulary and the non-ideal device electrical phenomena. To this end, it is only necessary to attempt a qualitative description of switching devices and the relation between their geometry, material parameters, and physical operating mechanisms. Typical power switching devices such as diodes, thyristors, and transistors are based on a monocrystalline group IV silicon semiconductor structure or a group IV polytype, silicon carbide. These semiconductor materials are distinguished by having a specific electrical conductivity, σ, somewhere between that of good conductors (>1020 free electron density) and that of good insulators (> p in the n-type silicon 1 = ρ=

q µn n

1.6 × 10

)

−19

1 = 0.086Ωcm × 720 × 1017

3

Power Electronics

For a length of 100µm, the resistance is

R =ρ×

Length L 100 × 10 −4 =ρ× = 0.086 × = 8.6kΩ Area W ×t 10 × 10 −4 × 1 × 10 −4

From equation (1.5) the sheet resistance is given by W 10 × 10−4 Rs = R = 8.6kΩ × = 860 Ω/square L 100 × 10−4 If the length is assumed to be one of the shorter dimensions, then for a length 10µm or 1µm, the resistance is 86Ω or 0.86Ω, respectively, while the sheet resistance possibilities, depending on the thickness reference axis, are 86 Ω/square and 8.6 Ω/square. For a p-type material, the 40% decrease in mobility of holes µp increases resistivity by a factor of 1/0.4 = 2.5. Each aspect resistance therefore increases by a factor 2.5, viz., increases to 21.5kΩ, 215Ω, and 2.15Ω for lengths 100µm, 10µm, and 1µm, respectively. From equation (1.4) the sheet resistances are increased to 2.15kΩ/square, 215Ω/square, and 21.5Ω/square.

♣

The carrier concentration equilibrium can be significantly changed by irradiation by photons, the application of an electric field or by heat. Such carrier injection mechanisms create excess carriers. If n-type silicon is irradiated by photons with enough energy to ionise the valence electrons, electronhole pairs are generated. There is already an abundance of majority electrons in the n-type silicon, thus the photon-generated excess minority holes are of more relative and detectable importance. If the light source is removed, the time constant associated with recombination, or decay of excess minority carriers, is called the minority carrier hole lifetime, τh. For a p-type silicon, exposed to light, excess minority electrons are generated and after the source is removed, decay at a rate called the minority carrier electron lifetime, τe. The minority carrier lifetime is often called the recombination lifetime. A difficulty faced by manufacturers of high-voltage, large-area semiconductor devices is that of obtaining uniformity of n-type phosphorus doping throughout the usual high-resistivity silicon starting material. Normal crystal-growing (by liquid encapsulated, contactless, Czochralski crystal growth – see section 1.19.3i) and doping techniques give no better than ±10 per cent fluctuation around the wanted resistivity at the required low concentration levels ( 1420°C

furnace crucible graphite with fused silica liner

back-filled inert gas 82% argon

(a)

stationary EM induction heater

melt

single crystal Si

initial crystal seed

vacuum or inert gas 82% argon

(b)

Figure 1.21. Techniques for producing a single crystal silicon boule: (a) Czochralski method and (b) the float-zone method.

Wafer preparation The next step is the same for both single-crystal formation methods. The boule ends are cropped using a water-lubricated, single-blade diamond saw. The ingot is then ground to a uniform diameter in a lathe, and each end is bevelled with a sand belt to reduce the possibility of shattering the ingot. X-ray diffraction can then be used to determine the crystal structure orientation, which is marked by grinding the length of cylindrical side of the boule. The cylindrical single-crystal ingot is sawed, using a multi-blade, inner-diameter saw in conjunction with a wet lubricant, into thin wafers for further processing. The sawing wastes 20% to 50% of the silicon as sawdust, known as kerf. The sliced wafers are mechanically lapped under pressure using a counter-rotating machine to achieve flatness and parallelism on both wafer sides. Most lapping operations use slurries of either aluminium oxide or silicon carbide. The edges of the individual wafers are also rounded by wet automatic grinders. After lapping, the wafers are etched with a solution containing nitric, acetic, and hydrofluoric acids (HF, CH3C00H, and HN03). This etching process removes external surface damage and reduces the thickness of the wafer.


46

Next, the wafers are polished using an aqueous mixture of colloidal silica and sodium hydroxide. The wafers are mounted onto a metal carrier plate that is attached by vacuum to the polishing machine. The chemical polishing process usually involves two or three grinding and polishing steps with progressively finer slurry, which decreases wafer thickness and results in a mirror-like lustre finish. Sometimes carrier pads must be stripped from the metal carrier plates. The pads are usually stripped with solvents such as methylene chloride, methyl ethyl ketone, or a glycol ether mixture. Finally, the wafers are cleaned to remove any particles or residue remaining on the exterior surface of the polished wafer. Various cleaning steps and solutions containing ammonia, hydrogen peroxide, hydrofluoric acid, hydrochloric acid (NH3, H202, HF, and HCℓ), and deionized water may be used. The finished wafers are inspected and packaged for shipping, since most semiconductor manufacturers purchase wafers from specialist wafer producers. 1.19.3iii Ribbon silicon Although single-crystal silicon technology is well developed, the Czochralski and float-zone processes are complex and expensive, as are the ingot-casting processes discussed under multi-crystalline silicon. Another crystal-producing process is ribbon silicon growth, where the single crystals cost less than from other processes, because they form the silicon directly into thin, usable wafers of single-crystal silicon. By forming thin crystalline sheets directly, sawing and slicing steps of cylindrical boules are avoided. One ribbon growth technique, termed edge-defined film-fed growth, starts with two crystal seeds that grow and capture a sheet of material between them as they are pulled from a source of molten silicon. A frame entrains a thin sheet of material when drawn from a melt. This technique does not waste much material, but the quality of the material is not as high as Czochralski process and float zone produced silicon. The resultant silicon quality is inferior for large-area, high-voltage, power semiconductor switching devices. 1.19.4 Multi-crystalline Silicon Multi-crystalline (or poly-crystalline) silicon describes when the active portion of the silicon is made up of several relatively large crystals, called grains, up to a square centimetre or so in area. Having several large crystals in a cell introduces a problem. Charge carriers can move around relatively freely within one crystal, but at the interface between two crystals, called the grain boundary, the atomic order is disrupted. Free electrons and holes are much more likely to recombine at grain boundaries than within a single crystal. There are several ways to minimize the problems caused by grain boundaries: • adjusting growth conditions through treatments such as annealing (heating followed by a slow cooling rate stage) the semiconductor material so that grains are columnar and as large as possible. The impurities are also better distributed; • designing cells so that the charge carriers are generated within or close to the built-in electric field; and • filling broken bonds at grain edges with elements such as hydrogen or oxygen, which is called passivating the grain boundaries. Multi-crystalline silicon based devices are generally less efficient than those made of single-crystal silicon, but they can be less expensive to produce. Multi-crystalline silicon is produced in a variety of ways. • The most common commercial methods involve a casting process in which molten silicon is directly cast into a mould and allowed to slowly solidify into an ingot. The starting material can be a refined lower-grade silicon, rather that the higher-grade semiconductor grade required for single-crystal material. The mould is usually square, producing an ingot that can be cut and sliced into square cells, minimising wasted silicon. • The procedure of extracting pure multi or poly-crystalline silicon from tri-chlorine-silan can be (among others) performed in special furnaces. Furnaces are heated by electric current, which flows through (in most cases) silicon electrodes. The 2 m long electrodes measure 8 mm in diameter. The current flowing through electrodes can reach up to 6000 A. The furnace walls are additionally cooled preventing the formation of any unwanted reactions due to gas side products. The procedure results in pure polycrystalline silicon used as a raw material for solar cell production. Poly-crystalline silicon can be extracted from silicon by heating it up to 1500°C and then cooling it down to 1412°C, which is just above solidification of the material. The cooling is accompanied by origination of an ingot of fibrous-structured poly-crystalline silicon of dimensions 40x40x30 cm. The structure of poly-crystalline silicon in part of the material is settled, yet it is not adjusted to the structure of the other part.

47

Power Electronics

1.19.5 Amorphous Silicon Amorphous silicon is produced in high frequency furnaces in a partial vacuum atmosphere. In the presence of a high frequency electrical field, gases like silane, B2H6 or PH3 are blown through the furnaces supplying the silicon deposit with boron and phosphorus. Amorphous solids, like common glass, are materials whose atoms are not arranged in any particular order. They do not form crystalline structures, and they contain large numbers of structural and bonding defects. Economic advantages are that it can be produced at lower temperatures and can be deposited on low-cost substrates such as plastic, glass, and metal. These characteristics make amorphous silicon the leading thin-film material. Since amorphous silicon does not have the structural uniformity of single or multi crystalline silicon, small structural deviations in the material result in defects such as dangling bonds, where atoms lack a neighbour to which they can bond. These defects provide sites for electrons to recombine with holes, rather than contributing to the electrical circuit. Ordinarily, this kind of material would be unacceptable for electronic devices, because defects limit the flow of current. However, amorphous silicon can be deposited so that it contains a small amount of hydrogen, 5% to 10%, in a process called hydrogenation. The result is that the hydrogen atoms combine chemically with many of the dangling bonds, as shown in figure 1.22, essentially neutralising or removing them and permitting electrons to move through the material. Staebler-Wronski Effect Instability currently retards amorphous silicon exploitation in some semiconductor applications. In the case of photo-voltaic cells, the amorphous cells experience an electrical output decreases over a period of time when first exposed to sunlight. The electrical output stabilizes with a net output loss of 20%. The reason is related to the amorphous hydrogenated nature of the material, including tiny microvoids or atomic-level gaps in the amorphous silicon structure several angstroms in diameter (1 angstrom =10-10 m). Other causes include oxygen or carbon impurities that are in the cells and ordinary stresses in the system that break silicon-silicon bonds in the region of the imperfections. hydrogen atom dangling bond silicon atoms

Figure 1.22. Amorphous silicon showing the dangling bonds and hydrogen sites.

Devices suffering from light induced degradation can recover their effectiveness if they are annealed at 150°C for a few minutes. Annealing is also effective at the normal operating temperatures of silicon, about 50° to 80°C. This is called self-annealing. Summary of substrate structural features Monocrystalline: An inorganic or organic compound functions in a device in a single crystal form (monocrystal). Only small molecules/oligomers (finite monomers) can be used. • Advantages: high reproducibility of properties, very high conductivity and carrier mobility. • Drawbacks: complexity of fabrication of devices, low mechanical strength. Polycrystalline: An inorganic or organic compound functions in a device in a form of a film/layer/bulk of many microscopic crystals. Both small molecules and low molecular weight polymers can be used. • Advantages: good reproducibility of properties, high conductivity and mobility. • Drawbacks: poor luminescent/optoelectronic properties. Microcrystalline: composed of micrometre-size well-shaped crystals/lamellas (thin plates or layers). Nanocrystalline: composed of nanometre-size crystals, often featured in shape (porous, hollow, etc). Small-molecule amorphous solids: • Advantages: simple fabrication of devices, good reproducibility of properties, good luminescent/ optoelectronic properties. • Drawbacks: low thermal stability (glass transition).


48

Amorphous polymers: • Advantages: simple fabrication of devices, high mechanical and thermal stability, good luminescent/ optoelectronic properties. • Drawbacks: low reproducibility of properties, low conductivity and carrier mobility. 1.20

Silicon Carbide

Wide bandgap semiconductors (GaN (III-V), SiC, diamond, etc.) have better high voltage and temperature characteristics than silicon devices. However, because silicon carbide, SiC, sublimes at high temperature, ≈1800ºC, processing is more difficult than for silicon (which melts at a lower temperature of 1415°C). The similar chemistry properties of silicon and silicon carbide (both in group IV) means that many of the existing processes for silicon can be applied to silicon carbide, but with some refinement and higher processing temperatures. The exception is thermal diffusion which is not effective if a good SiC surface morphology is to be retained. The SiC crystal boules are grown by seeded sublimation using the physical vapour transport (PVT) method. Alternatively, chemical vapour deposition (CVD) can be used, where SiH4, C3H8, and H2 are typically injected into the chamber. This process is mainly used for producing SiC epitaxial growth. A hot walled CVD reactor can deposit 100µm at a rate of 1 to 5 µm/hour at 1200ºC to 1500ºC. Crystal defects (micropipes, stack faults, etc.) occur at a rate of less than 1 per cm2. Proprietary defect healing technology can significantly decrease the defect rate. The main single crystal polytypes for power switching device fabrication are 4H-SiC and 6H-SiC (this lattice structure terminology is based on the Ramsdell notation). Nitrogen for n-type and aluminium or boron for p-type can be used in epitaxial growth and ion implantation. Substrates usually have an n or p epitaxial drift layer. Typical n-type epitaxy (50µm) can be thicker than a p-type layer (10µm), and the n-type epitaxy has a thin 1µm n-type buffer or fieldstop. Ion implantation is shallow, typically less than 1µm, and requires high temperature and 30 to 300keV. Subsequent annealing is at 1650ºC. The lower the temperature, the longer the annealing time. Contact metallization can use nickel on highly n-doped SiC, which is annealed at 1150ºC for a few minutes (with deuterium). A nickel and titanium Schottky metal combination is suitable for p+ region metallization. Si02 is an electrical-insulator that can be grown on both Si and SiC. Oxide growth for SiC is slower than that on silicon and involves nitridation of nitric oxide, N20, at 1300ºC. Because of the physical and chemical stability of silicon carbide, acid wet etching is ineffective and dry reactive ion etching tends to be used for etching processes. 1.21

Si and SiC physical and electrical properties compared

The processing of silicon is a mature, cost efficient technology, with 300mm wafers and submicron resolution common within the microelectronics industry. So-called wide bandgap semiconductors like silicon carbide (processed on 100mm wafers) offer promising high voltage and temperature power switching device possibilities as material quality and process yields improve. Figure 1.22 shows and allows comparison of the key physical and electrical properties of the main semiconductor materials applicable to power switching device fabrication. The higher • the energy bandgap, Eg, the higher the possible operating temperature before intrinsic conduction mechanisms produce adverse effects; • the avalanche breakdown electric field, ξb, the higher the possible rated voltage; • the thermal conductivity, σT, the more readily heat dissipated can be removed; and • the saturation electron drift velocity, νsat, and the electron mobility, µn, the faster possible switching speeds. Although the attributes of wide bandgap materials are evident, processing is more difficult than with Si and some of the parameters vary significantly with a wide operating (and processing) temperature range. SiC performance characteristic figures are slightly better than those for GaN, except, importantly, GaN has better carrier mobility. GaN growth is complicated by the fact that nitrogen tends to revert to the gaseous state, and therefore only thin layers are usually grown on sapphire or SiC substrates. Lattice-substrate boundary misfit occurs because of the significant difference in molecule sizes and packing. This limitation is more accentuated with GaN on silicon. There is a 17% misfit in molecule package and a 56% mismatch in thermal expansion (αGaN = 5.59×10-6 and αSi = 3.59×10-7 @ 300K). To prevent cracking during processing cooling, an intermediate transition layer like AℓN, is introduced. Wide band gap based, low-voltage (1800

3

1100 2500

phase change

6.15

GaN: Eg 3.4 eV, thermal conductivity 1.3 W/cmK

Reading list Bar-Lev, A., Semiconductors and Electronic Devices, Prentice-Hall International, 1979. Streetman, B. G. and Banerjie, S. K., Solid State Electronic Devices, Prentice-Hall International, 6th Edition, 2005. Sze, S. M., Physics of Semiconductor Devices, John Wiley & Sons, New York, 2nd Edition, 1981. Van der Ziel, A., Solid State Physical Electronics, Prentice-Hall International, 3rd Edition, 1976. Van Zeghbroeck, B., Principles of Semiconductor Devices, http://ece-www.colorado.edu/~bart/book/ Zetterling, C. M., Process technology for Silicon Carbide devices, IEE, 2002. http://www.siliconfareast.com/ http://www.semiconductorglossary.com/


Blank

50

2 The pn Junction The diode is the simplest bipolar semiconductor device. It comprises p-type and n-type semiconductor materials brought together, usually after diffusion, to form a (step or abrupt) junction as shown in figures 2.1a and 2.2a. A depletion layer, or alternatively a space charge layer, scl, is built up at the junction as a result of diffusion caused by the large carrier concentration gradients. The holes diffuse from the p-side into the n-side while electrons diffuse from the n-side to the p-side, as shown in figure 2.1b. The n-side, losing electrons, is charged positively because of the net donor charge left behind, while the p-side conversely becomes negatively charged. An electric potential barrier, ξ, builds up, creating a drift current which opposes the diffusion flow, both of which balance at thermo-dynamic equilibrium as shown in figure 2.1c. The electric field is a maximum at the junction and zero at the scl edges. There are no free carriers in the scl. The zero external bias, built-in, junction potential or scl potential is given by

Φ =

kT j N N An A 2 D q ni

(V)

(2.1)

where q is the electron charge, 1.6 x 10 -19 C k is Boltzmann’s constant, 1.38 x 10-23 J/K Tj is the junction temperature, K. Thus Φ= k T j / q = 0.0259 eV at room temperature, 300 K.

(a)

Io IDRIFT

IDIFFUSION xn

xp

Ф

Figure 2.1. The step junction: (a) the junction if carriers did not diffuse: + ionised donors, - ionised acceptors, + holes and - electrons; (b) electron and hole movements: ---- diffusion flow, ─── drift flow; (c) ionised impurities and free carriers equilibrium distribution; and (d) scl electric field and voltage.

BWW

The pn Junction

52

One important feature of the pn junction is that current (holes) flows freely in the p to n direction when forward-biased, that is, the p-region is biased positive with respect to the n-region. Only a small leakage current flows in the reverse voltage bias case. This asymmetry makes the pn junction diode useful as a rectifier, exhibiting static voltage-current characteristics as illustrated in figure 2.2.

on

+ -

Vb

 −kTqV  I = I o  e − 1     j

+

off

-

Figure 2.2. Typical I-V static characteristics of a silicon pn junction diode, and the effects of junction temperature, Tj.

Example 2.1:

Built-in potential of an abrupt junction

A silicon abrupt p-n junction has a p-type region of 2x1016 cm-3 acceptors and an n-type region containing 2x1016 cm-3 acceptors in addition to 1017 cm-3 donors. Calculate i. the thermal equilibrium density of electrons and holes in the p-type region, and both densities in the n-type region ii. the built-in potential of the p-n junction at room temperature iii. the built-in potential of the p-n junction at 400K, assuming the intrinsic concentration increases 300 fold over that at 300K Solution i. The thermal equilibrium densities, using n i2 = p × n from chapter 1, are: in the p-type region p = N A = 2 × 1016 cm−3 2 n = ni

(1.5 × 10 ) = 10

p

2

2 × 1016 cm3

= 1.125 × 103 cm−3

in the n-type region n = N D − N A = 8 × 1016 cm−3 2 p = ni

(1.5 × 10 ) = 10

n

2

8 × 1016 cm3

= 2.813 × 103 cm−3

ii. The built-in potential at room temperature from equation (2.1) is   kT j p n 2 × 1016 × 8 × 1016  Φ = = 0.766V An n 2 p = 0.259V × An  2  q ni  1.5 × 1010  

(

)

iii. The intrinsic carrier density is temperature dependant, and increases to 300 x 1.5x1010 = 4.5x1012 at 400K.

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53

The built-in potential at 400K is

Φ =

 kT j p n 400K 2 × 1016 × 8 × 1016 × An  An n 2 p = 0.259V × 2  q ni 300K ( 4.5 × 1012 )

♣ 2.1



  = 0.630V  

The pn junction under forward bias (steady-state)

If the p-region is externally positively-biased with respect to the n-region as shown in figure 2.3b, the scl narrows and current flows freely. The emf positive potential supplies holes to the p-region, while the negative emf potential provides electrons to the n-region. The carriers both combine, but are continuously replenished from the emf source. A large emf source current flows through the diode, which is termed forward-biased.

2.2

The pn junction under reverse bias (steady-state)

If a bias voltage is applied across the p and n regions as shown in figure 2.3c, with the p-terminal negative with respect to the n-terminal, then the scl widens. This is because electrons in the n-region are attracted to the positive external emf source while holes in the p-region are attracted to the negative emf potential. As the scl widens, the peak electric field ξm at the junction increases as shown in figure 2.3d. The only current that flows is the small leakage current which is due to carriers generated in the scl or minority carriers which diffuse to the junction and are collected. The junction condition is termed reverse-biased. Increasing applied reverse bias eventually leads to junction reverse voltage breakdown, Vb, as shown in figure 2.2 (third quadrant), and the diode current is controlled (limited) by the external circuit. Junction breakdown is due to one of three phenomena, depending on the doping levels of the regions and, most importantly, on the concentration of the lower doped side of the junction.

p

p

n

n

xp

xp

(d)

Figure 2.3. Diagrammatic representation of a pn junction diode showing minority carrier flow: (a) without external applied voltage; (b) with forward applied voltage; (c) with reverse applied voltage; and (d) electric field and scl change with increased reverse applied voltage.

The pn Junction

2.2.1

54

Punch-through voltage

The reverse voltage extends the scl to at least one of the ohmic contacts and the device presents a short circuit to that voltage in excess of the punch-through voltage, VPT. Punch-through tends to occur at low temperatures with devices which employ a low concentration region (usually the n-side), as is usual with high-voltage devices. The punch-through voltage for silicon can be approximated by

VPT = 7.67 × 10 −16 Nc Wc 2 where

2.2.2

(V)

(2.2)

Nc is the concentration in /cc of the lighter doped region and Wc is the width of that region in µm.

Avalanche breakdown

Avalanche breakdown or multiplication breakdown, is the most common mode of breakdown and occurs when the peak electric field, ξm, in the scl at the junction exceeds a certain level which is dependent on the doping level of the lighter doped region. Minority carriers associated with the leakage current are accelerated to kinetic energies high enough for them to ionise silicon atoms on collision, thereby creating a new hole-electron pair. These are accelerated in opposite directions, because of the high electric field strength, colliding and ionising repeatedly - hence the term avalanche, impact ionisation or carrier multiplication. If the lighter doped silicon region has a concentration of 1013 < N c < 5 × 1014

( /cc)

then the avalanche voltage may be approximated by

V b = 5.34 × 1013 N c - ¾

(V)

(2.3)

(V/m)

(2.4)

The peak electric field at the junction will be

ξb = 3.91 × 105 Nc 1 / 8

and the width of the scl, mainly in the lighter doped region, at breakdown is given by

W = 2 Vb / ξb

= 2.73 × 108 Nc -7 / 8

2.2.3

(≈

1 × 10 −14 Vb

)

(m)

(2.5)

Zener breakdown

Field or Zener breakdown occurs with heavily doped junction regions and at usually less than 5V reverse bias. It occurs when the scl is too narrow for avalanche yet the electric field grows very large and electrons tunnel directly from the valence band on the p-side to the conduction band on the n-side. This reverse current is called the Zener effect. These three modes of reverse voltage breakdown are not necessarily destructive provided the current is uniformly distributed and limited by the external circuit. If the current density in a particular area is too high, a local hot spot may occur, leading to device thermal destruction. 2.3

Thermal effects

The pn junction current, I, shown in figure 2.2, is related to the scl voltage, V, according to

I (V ) = I o [e

-qV / k Tj

- 1]

(A)

(2.6)

where Io, is the reverse (saturation) leakage current in amps. The forward conduction voltage decreases with increased junction temperature, Tj. That is, the on-state voltage has a negative temperature coefficient. In practical silicon pn diodes, at low currents, the temperature coefficient is typically -2.4 mV/K, becoming less negative with increased current. At higher currents, the coefficient becomes positive because of the reduced carrier mobility at higher temperatures, which causes non-scl regions to increase in resistance. The effects of the change in temperature coefficient at higher currents, in practical devices, are shown dotted in figure 2.2. Neglecting the exponential silicon bad gap temperature dependence, the temperature effects at high current, on the diffusion constant component of the leakage current Io in equation (2.6), called the saturation current, is given by 1.8

 T    300 

I o (T ) = I o (25°C) × 

(2.7)

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55

Silicon carbide diodes have a higher temperature coefficient, typically +8mV/K. The avalanche voltage increases with temperature, as does the reverse leakage current. The effects of temperature on the reverse bias characteristics are shown in figure 2.2. In the case of silicon carbide, increased temperature decreases the avalanche voltage and increases the leakage current. The silicon temperature coefficient for avalanche is positive since the mean distance between collisions is reduced due to the increased thermal energy, which increases the vibrational amplitude. Higher electric fields are necessary for the carriers to gain sufficient kinetic energy for ionisation. Equation (2.6) also indicates that the reverse bias current increases with increased junction temperature. This positive temperature coefficient does not generally result in thermal instability with silicon devices, provided sufficient heat sinking is employed on smaller devices. 2.4

Models for the bipolar junction diode

Semiconductor device electrical models are used extensively for power electronic circuit simulation. A basic piecewise-linear model is applicable to simple manual calculations, where the terminal I-V characteristics are empirically modelled based on ideal circuit elements. A more complex and accurate model is required for computer transient circuit analysis simulation. Such accurate models are based on the semiconductor physics of the device. Many power switching semiconductor device manufacturers provide values for the model parameters suitable for circuit simulation in the packages PSpice and SABER. 2.4.1

Piecewise-linear junction diode model

The pn junction diode is a unilateral device that, to a good approximation, conducts current in only one direction. Figure 2.4a shows a piecewise-linear (pwl) model of the diode that is suitable for static modelling in power electronic circuits. It includes a perfect diode, an on-state voltage source Eo, and a series resistor of resistance value Ro to account for the slope in the actual forward conduction characteristic. The forward I-V characteristic at a given temperature is given by VF ( I F ) = E0 + IF R0

for VF > E0

(V)

(2.8)

Figure 2.4. Piecewise-linear approximations of junction diode characteristics: (a) ideal diode with an offset voltage and resistance to account for slope in the forward characteristic and (b) model including reverse bias characteristics.

The pn Junction

56

The model in figure 2.4a does not incorporate the static reverse characteristics of leakage and avalanche. These are shown in figure 2.4b, where Vb from equation (2.3) models the avalanche limit and Ri ( = Vb / I o ) gives linear leakage current properties for a given junction temperature. The three diode components in figure 2.4b are assumed ideal. The model given by equation (2.8) is adequate for calculation of static balancing requirements of parallel and series connected diodes and thyristors, as considered in section 10.1 and the associated problems, 10.4, 10.5, and 10.9 to 10.12.

Example 2.2:

Using the pwl junction diode model

An approximation to the forward I-V characteristic of the diode shown in figure 2.4a, is given by VF ( I ) = 1.0 + 0.01 I F . For a constant current of 45A for ⅔ of a cycle, calculate the diode i. on-state voltage; ii. mean power loss; and iii. rms current. F

Solution i. ii.

The on-state voltage at 45A is given by VF (45A) = 1.0 + I F 0.01 = 1.0V + 45A × 0.01Ω = 1.45V If the on-state duty cycle is δ = ⅔, the average power loss is

iii.

P = δ × VF × I F = ×1.45V × 45A = 43.2W The diode rms current is given by

−

I rms = δ × I dc =  × 45A = 36.7A

♣ Example 2.3:

Static linear diode model

A Schottky diode is used to half-wave rectify a square wave ±15V source in series with a 1Ω load resistor. If the diode model shown in figure 2.4b is modelled with Ro = 0.01 Ω, Eo = 0.2V, Ri = 1000Ω, and Vb = 30V, determine: i. the diode model forward and reverse bias operating point equations for the series circuit ii. the load current and diode voltage iii. the rectifier losses (neglecting any recovery effects) and the load power dissipation iv. estimate the power dissipated in the load if the source is ac with the same fundamental component as the square wave v. what is the non-fundamental power dissipated with the square wave source? Solution When the diode is forward biased 1 iF = ( vDF − Eo ) for vDF ≥ 0.2V Ro Kirchhoff’s voltage law for the series circuit gives Vs = iF RL + vD F Eliminating the diode voltage vDF gives the series circuit current V − Eo for iF = s Vs ≥ Eo Ro + RL

IF

i.

V DF Ro =0.01Ω

V=±15V

V DR Ri =1000Ω

E o =0.2V

for 0 < Vs < Eo iF = 0 The diode forward voltage is therefore given by R L =1Ω V R + Eo RL = Eo + iF Ro for i > 0 vDF = s o Ro + RL When the diode is reversed biased, below the reverse breakdown voltage Vb = 30V 1 iR = vDR for vDR < Vb Ri Vs = iR RL + vDR

IR

VL

Power Electronics

57

Eliminating the diode voltage vD gives the series circuit leakage current Vs iR = Ri + RL The diode reverse voltage is thus given by VR vDR = s i = iR Ri Ri + RL ii.

The circuit voltages and current are, when the diode is forward biased, 15V - 0.2V = 14.65A iF = 0.01Ω + 1Ω VD = 0.2V + 14.65A×0.01Ω = 0.35V F

If RL >> Ro, the diode forward current equation can be simplified using Ro = 0. When the diode is reverse biased 15V = 15.0mA iR = 1000Ω + 1Ω VD = 15mA×1000Ω = 15.0V R

If Ri >> RL the diode reverse current and voltage equations can be simplified using RL = 0. iii.

The rectifier losses are, when forward biased, PD = vD × iF F

F

= 0.35V × 14.65A = 5.127W

and when reverse biased PD = vD × iR R

R

=15V × 15mA = 0.225W Total diode losses for a square wave are therefore ½×(5.127W + 0.225W) = 2.68W. The power from the square wave supply is ½× (15V×14.65A + 15V×15mA ) = 110.0 W

with 110W – 2.68W = 107.32W dissipated in the 1Ω load resistor. iv. The magnitude of the fundamental of a square wave is 4/π times the square wave magnitude, that is, 15V×4/π = 19.1V peak. The forward biased diode does not conduct until the supply voltage exceeds 0.2V. This is a small percentage of the sine wave magnitude (≈1%), hence can be neglected in the loss estimate. The forward current flow is approximately 19.1V - 0.2V iF = × sin ωt = 18.7 × sin ωt 1Ω + 0.01Ω The rms of a sine is 1/√2 its magnitude and 1/√2 again for a half-wave rectified sine. That is 18.7A iFrms = = 9.35A rms 2 2 The reverse leakage current is given by 19.1V iR = × sin ωt = 0.019 × sin ωt 1000Ω + 1Ω which gives an rms current of 19mA iRrms = = 9.5mA rms 2 2 The power dissipated in the 1Ω load resistor is PL = ( iF2 + iR2 ) × RL .

rms

.

rms

= ( 9.352 + 0.00952 ) × 1Ω = 87.42W + 90µW = 87.42W

Clearly, if RL > Ct. The scl capacitance, Cj (V) can be evaluated from the pn diode structure and doping profile, as follows.

space charge layer

Q

Qn=qAxnND

(cm-3)

Qn= -Qp

qND + xp xp

o

xn qNA

ξ

(V/cm)

Qp=-qAxpNA

ξm

V = ∫ξ

o (V)

o

W

Figure 2.6. The charge Q, electric field ξ, and voltage potential V, in the space charge layer of a step pn junction.

Power Electronics

59

2.4.2i - Determination of zero bias junction capacitance, Cjo Poisson’s equation, in conjunction with Gauss’s law, for the one dimensional step junction shown in figure 2.6, give d 2V dξ q ND qN =− = =− A (2.9) 2 ε εs dx dx s The dielectric permittivity εs = εr εo comprises the free space permittivity εo = 8.854x10-12 F/m and the relative permittivity εr = 11.8 for silicon and 9.7 for SiC.  q  ε s ND for − xn < x < 0 d ξ ( x)  (2.10) = dx − q N x x < < 0 for p  ε s A Integrating both parts of equation (2.10) over the shown bounds, gives ξ(x):  q  ε s ND x + ξ m for − xn < x < 0 dV( x)  = ξ ( x) =  dx  − q N x + ξ for 0 < x < xp m  ε s A q q where the maximium field intensity (at x = 0) is ξm = ε ND xn = NA xp

(2.11)

εs

s

The piece-wise parabolic voltage potential across the scl shown in figure 2.6, is given by integration of the electric field, that is 0 x q q V = ∫ ( ND x + ξ m ) dx + ∫ (− NA x + ξ m ) dx εs 0 −x εs (2.12) = ½ ξ m Wo Since the charges each side of the metallurgical junction must balance, equation (2.12) can be rearranged to give the scl width. p

n

 2ε V  s  q

Wo =

 1 1  +    NA ND  

(2.13)

From equation (2.1), a zero bias voltage Φ exists without the presence of any external voltage. Therefore, to incorporate non-equilibrium conditions, the electrostatic barrier potential becomes Φ-V, where V is the externally applied reverse bias voltage. Consequently the scl width expression becomes:

 2ε (Φ -V )  s q 

W=

 1 1 +   NA ND

   

(2.14)

The scl width voltage dependence can be expressed in terms of the zero bias scl width, W0  2ε Φ  s  q

W (V ) =

= W0 1 xn0 =

 1 1  V +   1 N N Φ D   A 

V Φ

W0 1+ ND / N A

xn (V ) = xn0

(2.15)

V 1Φ

x p0 =

W0 1+ NA / ND

x p (V ) = x p0

(2.16)

V 1Φ

The magnitude of the voltage dependant charge on each side of the junction is 1

 N N N N 2 V Q(V ) = q A D A W = A  2 qε sΦ D A  1+ ND + NA N N Φ D A   =

V Q0 1Φ

(2.17)

The pn Junction

60

The junction capacitance is given by differentiation of equation (2.17) with respect to V 1

 ND NA  2 ε s A dQ q = εs A  Cj = (2.18)  = dV W  2ε s (Φ -V) ND + NA  Equation (2.18) can be rearranged to give the PSpice capacitance form, in terms of the zero bias junction capacitance Cjo. Cjo Cj (V ) = 1  V 2 1 1 − Φ  (2.19)    q ND NA  2 ε s A where Cjo = ε s A   = Wo  2ε s Φ ND + NA 

The electric field at the metallurgical junction, from equation (2.12) is given by V ξ j (V ) = ξ 0 1 where ξ 0 = 2Φ / W0 Φ

(2.20)

2.4.2ii - One-sided pn diode equations When NA >> ND, which is the usual case in high voltage pn diodes, equations (2.12) to (2.20) are approximated by the following one-sided diode equations. W0 =

 2 εs Φ    ≈  q ND 

xno

and

x po ≈ 0

Q0 = A 2 qε sΦND Cjo = εs A

(2.21)

εs A q ND = 2ε s Φ Wo

These equations show that the scl penetrates mostly into the n-side, (hence the name one-sided), which supports most of the voltage, as shown in the last diagram in figure 2.6.

Example 2.4:

Space charge layer parameter values

A 10µm thick p-type 2x1016 /cc silicon epitaxial layer is grown on an n- - type 1x1014 /cc silicon substrate, of area 1 cm2, to form an abrupt pn junction. Calculate the following PSpice parameter values, at room temperature: i. ii. iii.

zero bias junction potential, Φ; zero bias scl width, maximum electric field, charge, and junction capacitance, W0, ξ0, Q0, Cjo; and avalanche breakdown voltage, Vb.

If the substrate is 150µm thick, for a 1000V reverse bias, calculate: iv. v.

scl width and penetration depth each side of the junction, W, xn, xp; charge each side of the junction, maximum electric field, and the capacitance, Q, ξj, Cj.

Solution i.

From equation (2.1), the zero bias built-in voltage is kT N N 2 × 1016 × 1× 1014 Φ = j An A 2 D = 0.0259 An q ni 2.25 × 1020

= 0.0259 × An(8.89 × 109 ) = 0.534V

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ii.

From equations (2.15), (2.20), (2.17), and (2.19) W0 =

 2Φ ε  1 1 s × +    q  NA ND

   

W0 =

2 × 0.53 V × 11.8 × 8.85 × 10−12  1  1 × +  −19 22 20  1.6 × 10 1× 10  2 × 10 

= 2.65µm

ξ 0 = 2 Φ / W = 2 × 0.534 / 2.65µm ξ 0 = 0.40 MV/m 1

 ND NA  2 Q0 = A  2Φqε s  ND + NA   Q0 = 1×10−4 2 × 0.53V × 1.6 × 10−19 × 11.8 × 8.85 × 10−12 ×

2 × 1042 2.01× 1022

= 4.21 nC

1

 qε ND NA  2 C jo = A  s   2Φ ND + NA  1

 1.6 × 10−19 × 11.8 × 8.85 × 10−12 2 × 1042  2 × = 3.95 × 10−9 F C jo = 1×10 × 22  2 0.53V 2.01 10 × ×   −4

iii.

=

3.95 nF

From equation (2.2), the estimated punch-through voltage is VPT = 7.67 × 10 −16 Nc Wc 2 = 7.67 × 10−16 × 1014 × (150) 2 = 1727V

That is, punch through occurs when the reverse bias is greater than the operating voltage, 1000V. If the diode is to breakdown due to avalanche then the avalanche breakdown voltage given by Vb (equation (2.3)) must be less than VPT, 1727V. Vb = 5.34 × 1013 Nc-¾ = 5.34 × 1013 × (1× 1014 )-¾ = 1689V

iv.

From equation (2.15) the scl width at -1000V reverse bias is W = W0 1-

V

= 2.65µ 1+

Φ

1000V 0.533V

= 114.6µm

From equation (2.16) the scl penetration into each side of the junction at -1000V is W 114.6 W 114.6 = = xn = xp = 1 + ND / NA 1 + 0.005 1 + NA / ND 1 + 200

xn = 114.0µm

x p = 0.57µm

Note that when NA >> ND, xn ≈ W, thus the lower the relative concentration of ND, the deeper the scl penetration and the higher the portion of V supported in ND. The junction scl can under these circumstances be analysed based on simplified equations – called one-sided junction equations. v. The charge magnitude each side of the junction, shown in figure 2.6, is given by equation (2.17). The electric field at the junction is given by equation (2.20), while the junction capacitance at -1000V is given by equation (2.19): V 1000V = 4.2nC × 1+ Q j = Q0 1Φ 0.533V . = 182 4 nC

ξ j = ξ 0 1-

V Φ

ξ j = 17.5 MV/m

= 0.40M × 1+

(>ND. Calculate the percentage error in using the assumptions. 2.6. A silicon pn diode with NA = 1018 cm3 has a capacitance of 10-7 F/cm2 at an applied reverse voltage of 1V. Calculate the donor density ND. 2.7. A silicon pn diode has a maximum electric field magnitude of 107 V/cm and a scl width of 200µm. The acceptor concentration is 100 times the donor density. Calculate each doping density. 2.8. Repeat example 2.2 for the equivalent 4H silicon carbide junction diode having the same electrical operating conditions. Use the silicon carbide data given below.

See problems 10.4, 10.5, and 10.9 to 10.12. Useful SI data for silicon and silicon carbide: q = -1.6x10-19 C ξo = 8.85x10-12 F/m ξr Si = 11.8 ξr SiC = 9.7 kT/q = 0.0259 eV at 300K ni Si = 1.5x1016 m-3 ni SiC = 2.5x10-3 m-3

The pn Junction

Blank

64

3 Power Switching Devices and their Static Electrical Characteristics

There is a vast proliferation of power switching semiconductor devices, each offering various features, attributes, and limitations. The principal device families of concern in the power switching semiconductor range are the diode, transistor, and thyristor. Each family category has numerous different members. The basic characteristics of the three families and a range of their members will be presented.

3.1

Power diodes

The homojunction p-n diode is the simplest semiconductor device, comprising one pn junction. In attempts to improve both static and dynamic diode electrical properties for different application conditions, numerous diode types have evolved. 3.1.1

The pn fast-recovery diode

The doping concentration on each side of the junction influences the avalanche breakdown voltage, the contact potential, and the series resistance of the diode. The junction diode normally has the p-side highly doped compared with the n-side, and the lightly doped n-region determines many of the properties of the device. The n-region gives the device its high-voltage breakdown and under reverse bias, the scl penetrates deeply into the n-side. The lower the n-type concentration and the wider the nside, the higher will be the reverse voltage rating and also, the higher the forward resistance. These nregion requirements can lead to thermal I2R problems in silicon. Larger junction areas help reduce the thermal instability problem. It is usual to terminate the lightly doped n-region with a heavily doped n+ layer to simplify ohmic contact and to reduce the access resistance to the scl. For better n-region width control, n-type silicon is epitaxially grown on an n+ substrate. The p+ anode is diffused or implanted into the epitaxial region, forming an epitaxial diode. In devices specifically designed for high reverse bias applications, care must be taken to avoid premature breakdown across the edge of the die or where the junction surfaces. Premature edge breakdown is reduced by bevelling the edge as shown in figure 3.1a, or by diffusing a guard ring as shown in figure 3.1b, which isolates the junction from the edge of the wafer. The scl electric field is lower at the bevelled edge than it is in the main body of the device. In the case of a lightly doped p-type guard ring, the scl is wider in the p-ring, because of its lower concentration, than in the p+ region. The maximum electric field is therefore lower at the pn-ring junction for a given reverse bias voltage. Negatively charged glass film techniques are also employed to widen the scl near the surface, as shown in figures 3.1c and 3.1d. Multiple guard rings are sometimes employed for very high breakdown voltage devices. Similar techniques are extendable to devices other than diodes, such as thyristors. Field

BWW


66

control bevelling on more complex junction structures is achieved with double-negative or doublepositive bevelling as shown in parts e and f of figure 3.1. The bevelling is accomplished by grinding, followed by etching of the bevel surface to restore the silicon crystalline mechanical and structure quality. The processed area is passivated with a thin layer of polyimide, which is covered in silicon rubber. Negative bevels tend to be more stable electrically with ageing. The foregoing discussion is directly applicable to the rectifier diode, but other considerations are also important if fast switching properties are required. The turn-on and reverse recovery time of a junction are minimised by reducing the amount of stored charge in the neutral regions and by minimising carrier lifetimes. Lifetime killing is achieved by adding gold or platinum, which is an efficient recombination centre. Electron and proton irradiation are preferred non-invasive lifetime control methods. Irradiation gives the lowest forward recovery voltage and the lowest reverse leakage current. The improved switching times must be traded off against increased leakage current and on-state voltage. Switching times are also improved by minimising the length (thickness) of the n-region.

cathode

anode cathode (a)

(b)

anode

anode

n+

n+

cathode

cathode (c)

(e)

(d)

(f)

Figure 3.1. To prevent edge breakdown under junction reverse bias: (a) reduction of the space charge region near the bevel; (b) p-type guard ring; (c) glass guard ring; (d) glass plus p-type guard ring; (e) double negative bevel; and (f) double positive bevel angle.

3.1.2

The p-i-n diode

The transient performance of diodes tends to deteriorate as the thickness of the silicon wafer is increased in attaining higher reverse voltage ratings. Gold lifetime killing only aggravates the adverse effects incurred with increased thickness. The p-i-n diode allows a much thinner wafer than its conventional pn counterpart, thus facilitating improved switching properties.

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The p-i-n diode is a pn junction with a doping profile tailored so that an intrinsic layer, the i-region, is sandwiched between the p-layer and the n-layer, as shown in figure 3.2. In practice, the idealised iregion is approximated by a high resistivity n-layer referred to as a v-layer. Because of the low doping in the v-layer, the scl will penetrate deeply and most of the reverse bias potential will be supported across this region.

n

i

p.d. = area p.d. = area

Figure 3.2. Cross-section and electric field distribution of: (a) a pn diode and (b) a p-i-n diode.

The power p-i-n diode can be fabricated by using either the epitaxial process or the diffusion of p and n-regions into a high-resistivity semiconductor substrate. The i-region width Wi , specifies the reverse voltage breakdown of the p-i-n diode, which is the area under the electric field in figure 3.2b, viz., Vb ≈ ξb W ≈ 25Wi

(in µm )

(V)

(3.1)

The thickness Wi , along with the distribution of any gold within it, determines the nature of the reverse and forward-conducting characteristics. These characteristics are more effective and efficient in fast p-in diodes than in the traditional pn structures.

3.1.3

The power Zener diode

Zener diodes are pn diodes used extensively as voltage reference sources and voltage clamps. The diode reverse breakdown voltage is used as the reference or clamping voltage level. The leakage current in a good pn diode remains small up to the reverse breakdown point where the characteristic has a sharp bend. Such an electrical characteristic is called hard. Premature breakdown at weak spots in the junction area or periphery cause high leakage currents before final breakdown, and such diodes are said to have soft breakdown characteristics. Zener diodes are especially made to operate in the breakdown range. Above a few volts, the breakdown mechanism is avalanche multiplication rather than Zener and the breakdown reference voltage VZ is obtained by proper selection of the pn junction doping levels. Once in breakdown VZ remains almost constant provided the manufacturer’s power rating, P = VZ I, is not exceeded. Where the breakdown mechanism is due to the Zener effect, the temperature coefficient is negative, about -0.1 per cent/K, changing to positive, +0.1 per cent/K, after about 4.5V when the avalanche multiplication mechanism predominates. Zener diodes require a hard breakdown characteristic not involving any local hot spots. They are available in a voltage range from a few volts to about 280V and with power dissipations ranging from 250mW to 75W, with heat sinking. Transient suppressing Zener diodes can absorb up to 50kW, provided energy limits and number of cycles are not exceeded, as shown in figure 10.21. Practically, Zener diodes are difficult to make, less than ideal in application, and should be avoided if possible. The basic I-V characteristics, and electrical circuit symbol for the different types of diodes, are shown in figure 3.3.


68

forward bias

reverse bias

Figure 3.3. Diodes: (a) static I-V characteristic; (b) symbol for a rectifier diode; (c) voltage reference or Zener diode; and (d) Schottky barrier diode.

3.1.4

The Schottky barrier diode

The Schottky diode is a metal-semiconductor diode device which offers low on-state voltages, but in silicon is presently restricted to applications imposing a reverse bias of less than 400V. At lower voltages, less than 40V, devices of up to 300A are available and the maximum junction operating temperature is 175°C, which is higher than for conventional silicon pn junction devices. The Schottky diode is formed by a metal (such as chromium, platinum, tungsten or molybdenum) in homogeneous contact with a substrate piece of n-type silicon, as shown in figure 3.4a. The contact is characterised by a potential barrier Φb > 0 (termed Schottky barrier height) which determines the forward and reverse properties of the Schottky diode. In forward conduction, electrons are emitted from the negative potential n-type silicon to the positive potential metal, passing over the barrier potential. Unlike the bipolar pn diode, only electrons are carriers, hence the Schottky barrier diode is a unipolar device. The forward on-state voltage drop is dominated by and proportional to the barrier potential Φb, while unfortunately the reverse leakage current is approximately inversely related. Thus a Schottky diode with a very low forward voltage drop will have very high reverse leakage current relative to the pn diode counterpart, as shown in figure 3.5. Chromium provides the lowest forward voltage drop but is limited to an operating temperature of 125°C and has a high leakage current. Platinum allows operating temperatures to 175°C with a leakage current several orders of magnitude lower than chromium. The trade-off is a higher forward voltage. A guard ring is used to improve device robustness, but its function is to act like a Zener diode and thus protect the Schottky barrier under excessive reverse bias. An optimally designed epitaxial layer, as shown in figure 3.4b, is also employed which reduces the field at the less than perfect metalsemiconductor interface and allows the whole interface to go safely into reverse bias breakdown. There are a number of important differences between Schottky barrier and pn junction diodes. • In a pn diode, the reverse bias leakage current is the result of minority carriers diffusing into the scl and being swept across it. This current level is highly temperature-sensitive. In the Schottkybarrier case, reverse current is the result of majority carriers that overcome the barrier. A much higher leakage value results at room temperature, but is not temperature-dependent. • The forward current is mostly injected from the n-type semiconductor into the metal and very little excess minority charge is able to accumulate in the semiconductor. Since minimal minority carrier recombination occurs, the Schottky barrier diode is able to switch rapidly from forward conduction to reverse voltage blocking. • Since under forward bias, barrier injection comes only from the semiconductor, and there is little recombination in the scl; thus the device can be represented by the ideal diode equation (2.6). • The majority electrons injected over the barrier into the metal have much higher energy than the other metal electrons which are in thermal equilibrium. Those injected electrons are therefore called hot, and the diode in some applications is referred to as a hot electron diode.

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(a)

(b)

Figure 3.4. The Schottky barrier diode: (a) the basic structure and (b) the space charge layer region extending into the epi-substrate region under reverse bias.

+ -

+ -

Figure 3.5. Schottky and epi diode I-V characteristics with different Schottky barrier potentials.


70

An important point arising from this brief consideration of the Schottky barrier diode is the importance of the connection of an n-type semiconductor region to aluminium metallization that occurs in unipolar and bipolar semiconductor devices. A practical method of forming aluminium ohmic contacts on n-type materials where Φb > 0, is by doping the semiconductor very heavily (>1019 /cm3), above the degeneracy level. Thus, in the contact region, if a barrier exists, the scl width is small enough ( 0 and V gs −Vth > Vds , the drain current is given by

Id = µ

Wc C a (V gs −VTH )Vds − ½ Vds2 Lc

(3.9)

and when the gate voltage is below the threshold level, V gs < VTH ,

Id = 0

(3.10)

Figure 3.12. MOSFET gate voltage characteristics: (a) transfer characteristics of gate voltage versus drain current and (b) transconductance characteristics of gate voltage versus transconductance, gfs.

Figure 3.12a shows that drain current exhibits both a positive and negative temperature coefficient with the drain current IDQ being the boundary condition. If the drain current is greater than IDQ there is a possibility of destruction by over-current at low temperatures, while if the drain current is less than IDQ, over-current can produce thermal runaway and destruction. Operation with a gate voltage corresponding to IDQ avoids the need for any gate drive temperature compensation. At high gate voltages, the on-resistance of the resistive region and the drain current in the constant current region, become somewhat independent of the gate voltage. This phenomenon is best illustrated in the Id vs Vds characteristic by the curve cramping at high gate voltages in figure 3.10c. 3.2.2iii - MOSFET transconductance and output conductance Inspection of the static drain source characteristics of figure 3.10c reveals that as the gate voltage increases from zero, initially the drain current does not increase significantly. Only when a certain threshold gate voltage, VTH, has been reached, does the drain current start to increase noticeably. This is more clearly illustrated in figure 3.12b which shows the characteristics of drain current Id and small signal transconductance gfs versus gate voltage, at a fixed drain voltage. It will be seen from these characteristics that no conduction occurs until Vgs reaches the threshold level, VTH, after which the Id versus Vgs characteristic becomes linear, the slope being the transconductance gfs. The amplification factor, forward transconductance, gfs, is defined as g fs

∂I d ∂Vgs

Vds = constant

Differentiating equations (3.7) and (3.8), for Vds ≥ Vgs − VTH , with respect to gate voltage, gives at low current g fs = µ

Wc Lc

Ca (Vgs − VTH ) = 2

Wc µn Ca I Dn Lc

(mho)

(3.11)

at high current

g fs = ½ vsatWc Ca

(mho)

(3.12)

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At high electric fields, that is high currents, the carrier velocity νsat saturates. In the ohmic region, V gs > 0 and V gs −Vth > Vds , the forward transconductance is

g fs = µ

Wc CV Lc a ds

The output conductance, gd, is defined as ∂I d gd ∂Vds

(3.13)

Vgs = constant

The output conductance quantifies the drain current variation with gate voltage variation for a constant gate voltage. Differentiating equations (3.7) and (3.8), with respect to drain voltage, gives zero, gd = 0, for each case in the saturation region. In the ohmic region the output conductance is

gd = µ

Wc C (V −VTH −Vds ) Lc a gs

(3.14)

A typical minimum threshold voltage is about 2V and exhibits temperature dependence of approximately -10mV per K (α = 0.5 per cent/K), as shown in figure 3.13. At high gate voltages, the drain current becomes constant as the transconductance falls to zero, implying the upper limit of forward drain current. The temperature variation of transconductance is small, typically -0.2 per cent/K, which results in extremely stable switching characteristics. The typical temperature coefficient for the gain of a bipolar junction transistor, the MOSFET equivalent to gfs , is +0.8 per cent/K. The temperature dependence of the MOSFET forward conductance is approximated by −2.3

 T  g fs (T ) ≈ g fs (25°C) ×  (mho)   300  since temperature effects are dominated by mobility variation with temperature.

(3.15)

Inherent in the MOSFET structure are voltage-dependent capacitances and on-state resistance.

3.2.2iv - MOSFET on-state resistance In the fully on-state the drain-source conduction characteristics of the MOSFET can be considered as purely resistive. The on-resistance Rds(on) is the sum of the epitaxial region resistance, the channel resistance, which is modulated by the gate source voltage, and the lead and connection resistance. One reason for the wide proliferation of special gate geometries is to produce extremely short, reproducible channels, in order to reduce Rds(on). In high-voltage devices, the on-resistance is dominated by the resistance of the epitaxial drain region when the device is fully enhanced. For high-voltage n-channel devices, the on-state resistance is approximated by Rds (on) = 6.0 × 10−7 × Vb2.5 / A (Ω) (3.16) where Vb is the breakdown voltage in volts A is the die area in mm2. A p-channel device with the same Vb as an n-channel device has an Rds(on) two to three times larger as given by Rds (on) = 1.6 × 10−6 × Vb2.5 / A (Ω) (3.17) The factor l/gfs of Rds(on) is added to give the total Rds(on). On-state drain-source loss can therefore be based on Id2Rds(on). On-resistance Rds(on) increases with temperature and approximately doubles over the range 25°C to 200°C, having a positive temperature coefficient of approximately +0.7 per cent/K above 25ºC, as shown in figure 3.13. The temperature dependence of the on-state resistance is approximated by 2.3

 T  Rds (on) (T ) = Rds (on) (25°C) ×  (Ω ) (3.18)   300  where the temperature T is in degrees Kelvin. This relationship (as does forward conductance in equation (3.15)) closely follows the mobility charge dependence with temperature.

Since Rds(on) increases with temperature, current is automatically diverted away from a hot spot. Thus unlike the bipolar junction transistor, second breakdown cannot occur within the MOSFET. The breakdown voltage Vb has a positive temperature coefficient of typically 0.1 per cent/K as shown by V(BR)DSS in figure 3.13.


78

3.2.2v - MOSFET p-channel device P-channel MOSFETs are very similar to n-channel devices except that the n and p regions are interchanged. In p-channel devices the on-resistance, for a given die area, will be approximately twice that of a comparable n-channel device. The reason for this is that in the n-channel device the majority carriers are electrons but in the p-channel device, the majority carriers are holes which have lower mobility. If the area of a p-channel device is increased to produce an equal Rds(on), then the various capacitances of the p-channel device will be larger, and the device costs will be greater. In the linear region, the drain current is W µpC a  Vds2  −I Dp = (V gs +VTp )Vds −  L 2  

For saturation

W µpC a  Vds2  (V gs +VTp )Vds −  L 2   The transconductance in the saturation region is ∂i W  W  g fs p = D =   µpC a (V gs +VTp ) = 2   µpC a (−I Dp ) ∂v gs Q  L  L  −I Dp =

V(BR)DSS

Vgs(TH)

Vgs =0V

ID=1mA

gfs Vds=50V

Figure 3.13. Normalised drain-source on-resistance, transconductance, gate threshold voltage, and breakdown voltage versus junction temperature.

Example 3.1:

Properties of an n-channel MOSFET cell

A silicon n-channel MOSFET cell has a threshold voltage of VTH = 2V, Wc = 10µm, Lc = 1µm, and an oxide thickness of tox = 50nm. The device is biased with VGS = 10V and VDS = 15V. i. Assuming a quadratic model and a surface carrier mobility of 300 cm2/V-s, calculate the drain current, cell dissipation, forward transconductance, and output conductance. ii. Assuming carrier velocity saturation (5x106 cm/s), calculate the drain current, cell dissipation, forward transconductance, and output conductance. Solution i. The MOSFET is biased in saturation since Vds > Vgs - VTH . Therefore, from equation (3.7) the drain current equals:

I d = ½ µ Ca

Wc (Vgs − VTH ) 2 where Ca = ε / tox Lc

3.85 × 8.85 × 10−12 10µm × × (10V − 2V) 2 = 6.5 mA 50 × 10−9 1µm The dc power dissipation is 6.5mAx15V=97.5mW. From equation (3.11), the transconductance equals: = ½ × 300 × 10−4 ×

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79

g fs = µ C a

Wc (Vgs − VTH ) Lc

3.85×8.85×10-14 10 × ×(10V - 2V) = 1.64 mho 50×10-9 1 The output conductance gd is zero. = 300×10-4 ×

ii. When the electron velocity saturates, the drain current is given by equation 3.8 I d = ½ vsat Wc Ca (Vgs − VTH ) 3.85×8.85×10-12 × (10V - 2V) = 136 mA 50×10-9 The dc power dissipation is 136mAx15V=2W, a dc operating condition well in excess of the cell capabilities. The transconductance is given by equation 3.10 g fs = ½ vsatWc Ca = ½ × 5×10 4 × 10-5 ×

= ½ × 5×104 × 10-5 ×

3.85×8.85×10-12 = 16.1 mho 50×10-9

The output conductance gd is zero.

♣ 3.2.2vi - MOSFET parasitic BJT Figure 3.14 shows the MOSFET equivalent circuit based on its structure and features. The parasitic npn bipolar junction transistor shown in figure 3.14b is key to device operation and limitations. Capacitance exists within the structure from the gate to the source, Cgs, the gate to the drain, Cgd, and from the drain to the source, Cds. The capacitance Cgs varies little with voltage; however Cds and Cgd vary significantly with voltage. Obviously these capacitances influence the switching intervals, an aspect considered in chapter 4.4.2. The emitter of the parasitic npn transistor is the source of the MOSFET, the base is the p-type body and the collector is the drain region. In the construction of the MOSFET, the emitter and base of the npn transistor are purposely shorted out by the source metallization to disable the parasitic device by reducing its injection efficiency. However, this short circuit cannot be perfect and Rbe models the lateral p-body resistance, while Cob is essentially Cds. The npn transistor has a collector-emitter breakdown voltage, between Vcbo and Vceo. If an external dv/dt is applied between the drain and source as shown in figure 3.14b, enough displacement current could flow through Cob to generate a voltage drop across Rbe sufficient to turn on the parasitic bipolar device, causing MOSFET failure in second breakdown. When the drain to source voltage is negative, current can flow from the source to drain through Rbe and the base to collector junction of the parasitic npn transistor within the structure, the dashed line shown in figure 3.14b. This is termed the body diode, inherent in the MOSFET structure. Drain

n+

n

-

RD

Cgd

C gd p+

n

C ds

Cds

R be

Rbe

+

Cgs Idiode

Source

Gate

Rg

C gs

(a)

SiO 2

Source

(b)

Figure 3.14. MOSFET – n-channel enhancement mode: (a) structure and (b) equivalent circuit diagram with parasitic npn bipolar transistor forming an inverse diode.


80

3.2.2vii - MOSFET on-state resistance reduction Most power switching devices have a vertical structure, where the gate and source of the MOSFET (or emitter in the case of the IGBT) are on one surface of the substrate, while the drain (or collector) is on the other substrate surface. The principal current flows vertically through the substrate but the conductive channel is lateral due to the planar gate structure, as shown in figure 3.11. The structure resistance components between the drain and source are: • the drift region; • the JFET region; • the accumulation region; and • the channel region. The drift region contribution dominates whilst the contribution from the ohmic contacts and n+ substrate are not significant, in high voltage devices. The channel voltage drop is proportional to channel length and inversely related to width. The channel should therefore be short, but its length is related to voltage rating since it must support the off-state scl.

Whilst retaining the necessary voltage breakdown length properties, two basic approaches have been pursued to achieve a more vertical gate (channel) structure, viz., the trench gate and vertical superjunction, as shown in parts b and c of figure 3.15. Both techniques involve increased fabrication complexity and extra costs. 1 - Trench gate

A channel is formed on the vertical sidewalls of a trench etched into the die surface as shown in figure 3.14b. The JFET resistive region is eliminated, which not only reduces the total resistance but allows smaller cell size thereby increasing channel density and decreasing the short-circuit capacity. The trench corners must be rounded to avoid high electric field stress points. By extending the gate into the drift region, the gate to drain capacitance increases, hence increasing gate charge requirements. S o urc e

g a te n+ p

n

-

epi

n +s u b

D rain (a )

S o urce

S o u rce g a te

ga te

n ++ p

n p

n

g a te

-

n

p

n

-

e pi

n +s u b

n D ra in

D ra in

(b ) (c ) Figure 3.15. Three MOSFET channel structures: (a) conventional planar gate; (b) trench gate; and (c) vertical superjunction.

2 - Vertical super-junction

The structure has vertical p-conducting regions in the voltage sustaining n- drift area, that are extend to the p-wells below the gate, as shown in figure 3.14c. In the off-state, the electric field is not only in the vertical direction but also in the horizontal plane. This means the n-drift region width can be decreased, the on-state resistance is decreased, and the gate charge is reduced for a given surface area. Up to sixteen mask steps are needed which involves repeated cycles of n-type epi-layer growth, masked boron implantation, and finally diffusion. The resultant specific resistance is near linearly related to breakdown voltage, as opposed to Rds (on) × Area ∝ Vbr2.5 , equation (3.16). Typically Rds(on) is five times lower than for the conventional MOSFET, which only uses up to six mask steps.

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Whilst the trench gate concept can be readily applied to other field effect devices without voltage rating limits, the vertical super-junction is confined to the MOSFET, and then at voltage ratings below about 1000V. 3.2.3

The insulated gate bipolar transistor (IGBT)

The high off-state and low on-state voltage characteristics of the bipolar junction transistor are combined with the high input impedance properties of the MOSFET to form the insulated gate bipolar transistor, + IGBT, as shown in figure 3.16. The basic structure is that of a MOSFET but with a p implanted into the + drain region. This p collector provides reverse blocking capabilities of typically 40V, which can be enhanced if p-wells through the substrate are used to isolate the die periphery. 3.2.3i - IGBT at turn-on Electrons from the n- drift region flowing into the p+ collector region, cause holes to be emitted from the high efficiency p+ region into the drift region. Some of the holes flow to the emitter p+ region as well as through the lateral mos-channel into the n+ well. This charge enhancement causes the scl, hence collector voltage, to collapse as the device turns on. 3.2.3ii - IGBT in the on-state The p+ substrate conductively modulates the n- region with minority carriers, which whilst conducting the main collector current, produces a low on-state voltage at the expense of a 0.6 to 0.8V offset in the output voltage characteristics due to the collector pn junction. From figure 3.16c, the IGBT collector current is approximated by

I c = I mos (1 + β pnp )

(3.19) Ic

Icp

(a)

Icp

Imos

(b)

Ic Ic

αpnp

Icp

αnpn Icp

(c) (d) Figure 3.16. Insulated gate bipolar transistor (IGBT): (a) circuit symbol; (b) physical structure showing current paths: (c) normal operation equivalent circuit; and (d) high current latching equivalent circuit.


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3.2.3iii - IGBT at turn-off Excess p-stored charge that remains after the high voltage scl has been established must recombine in the externally inaccessible n- drift region. This storage charge produces a tail current. The operational mechanisms are those of any minority carrier device and result in slower switching times than the majority carrier MOSFET. On-state voltage and switching characteristics can be significantly improved by using the trench gate technique used on the MOSFET, as considered in section 3.2.1 and shown in figure 3.15b. A less stable structure improvement involves using wider trenches, judiciously spaced, so that accumulated holes under the trench, enhance emitter injection of electrons. This injection enhancement reduces the on-state voltage without degrading the switching performance.

Further performance enhancement is gained by using the punch through, PT-IGBT, structure shown in figure 3.17a, which incorporates an n+ buffer region. The conventional non-punch through NPT-IGBT structure is shown in figure 3.17b. Both collector structures can have the same emitter structure, whether a lateral gate as shown, or the MOSFET trench gate in figure 3.15b. Figure 3.17 shows the electric field in the off-state, where the PT-IGBT develops a field as in the pin diode in figure 3.2b, which allows a thinner wafer. The NPT-IGBT requires a thicker wafer (about 200µm for a 1200V device) which results in a larger substrate resistance and a slower switching device. • The PT-IGBT has n+ and p+ layers formed by epitaxial growth on an n- substrate. The electric field plot in figure 3.17b shows that the off-state voltage scl consumes the n- substrate and is rapidly reduced to zero in the n+ buffer. • The NPT-IGBT has a lightly doped n- substrate with the p-regions (p wells and p collector) formed by ion implantation. The electric field distribution in figure 3.17b shows that the n- drift region has to be wide enough to support all the off-state voltage, without punch through to the p collector implant. collector p minority carrier injection

Ic

Imos

n- substrate

p n

emitter

gate

emitter

(b)

collector p+ + n

minority carrier injection

n+ buffer

n-

p n

emitter

gate

Si02

emitter

(a)

Figure 3.17. Insulated gate bipolar transistor structures and electric field profile: (a) fieldstop PT-IGBT and (b) conventional NPT-IGBT.

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3.2.3iv - IGBT latch-up The equivalent circuit in figure 3.16d shows non-ideal components associated with the ideal MOSFET. The parasitic npn bipolar junction transistor (the n+ emitter/ p+ well/ n- drift region are the npn BJT e-b-c) and the pnp transistor (p+ collector/ n- drift/ p+ well are the pnp BJT e-b-c) couple together to form an SCR thyristor structure, as considered in section 3.3. Latching of this parasitic SCR can occur: • in the on-state if the current density exceeds a critical level, which adversely decreases with increased temperature or • during the turn-off voltage rise when the hole current increases in sensitive regions of the structure due to the charge movement associated with the scl widening. 1 - IGBT on-state SCR static latch-up is related to the temperature dependant transistor gains which are related to the BJT base transport factor bt and emitter injection efficiency γ, defined for the BJT in equation (3.2) (3.20) α pnp + α npn = bt γ pnp + bt γ pnp = 1 pnp

pnp

To avoid loss of control and possible IGBT failure, the factors in equation (3.20), which is valid for onstate latch-up, are judiciously adjusted in the device design. Common to both device types is the gate structure, hence the base-emitter junction of the npn parasitic BJT have the same properties. In each structure, the shorting resistor Rbe decreases the injection efficiency of the npn BJT emitter. This resistance is minimized by highly doping the p+ wells directly below the n-emitters and by shortening the length of the n-emitter. The gain αnpn in equation (3.20) is decreased since the injection efficiency γnpn is lowered. Reduction of the pnp BJT gain of the PT-IGBT and NPT-IGBT is achieved with different techniques. • For the NPT-IGBT, the emitter injection efficiency of holes from the p+ zone into the n- drift region is high because of the large difference in doping concentrations at the junction. Adversely this yields a high injection efficiency γpnp. The base transport factor bt pnp is already low because of the large width of the n- drift region, and is further reduced by lifetime killing of minority carriers in the n- drift region by using gold doping or electron beam radiation. • For the PT-IGBT, the p+ emitting junction at the collector is a well-controlled shallow implant thus reducing the injection efficiency γpnp. Charge carrier lifetime killing in the n- drift region to reduce the base transport factor btpnp, is therefore not necessary. 2 - IGBT turn-off SCR dynamic latch-up can occur while the collector voltage is rising, before the collector current decreases. Equation (3.20) is modified by equation (3.5) to account for voltage avalanche multiplication effects. Mnpn α npn + Mpnp α pnp = 1

where M =

(3.21)

1 1 − (vce / Vb ) m

This dynamic latch-up mode is adversely affected by increased temperature and current magnitude during the voltage rise time at turn-off. Since vce Vb , M → 1 , and the multiplication effect is not significant in the on-state static latch-up analysis. IGBTs are designed and rated so that the latch-up current is 10 to 15 times the rated current. 3.2.4

Reverse blocking NPT IGBT

The conventional IGBT inherently has reverse voltage blocking capabilities, albeit low. Normally, the collector boron ion p+ implant forms a transparent abrupt junction, optimised for on-state voltage and turn-off speed. Because the n region surfaces on the emitter side of the device, the uncontrolled field in this region produced by a reverse voltage, causes premature breakdown. To avoid this, the first processing step is to surround each IGBT die region on the wafer by a deep boron p-well which is selectively driven in from the emitter side. The collector side is mechanically ground to about 100µm, so as to expose to boron diffusion. The remaining processes are essentially as for the conventional NPT IGBT, which results in a structure as shown in figure 3.18. The reverse bias scl is modified and silicon nitride passivation of the emitter surface and an n-channel field stop results in a controlled scl profile, as shown dashed in figure 3.18. Other than increased processing complexity (hence costs) minimal on-state voltage - switching speed compromise arises. Effectively, a device with the performance lagging by one technology generation is achieved. Reverse blocking capability extension to the desirable PT IGBT structure is problematic since the nbuffer region is of a higher concentration than the n-substrate. Thus the formed pn junction will have a significantly lower avalanche breakdown voltage level, as predicted by equation 2.3.


Conventional NPT igbt section

84

reverse E fielded modified

collector metallization p+ collector implant n

die edge Deep p diffusion from emitter side

p n emitter metal gate

2 p guard rings

n channel stop

Figure 3.18. Reverse voltage blocking NPT-IGBT structure.

3.2.5

PT IGBT and NPT IGBT comparison

Generally, faster switching speed is traded for higher on-state losses, and vice versa. Table 3.1 PT versus NPT IGBTs

IGBT TYPE conduction loss (same switching speed)

switching speed (same on-state loss)

PT IGBT Lower vce(sat) Decreases slightly with temperature A slight positive temperature co-efficient at high current densities allows parallel connection.

NPT IGBT Higher vce(sat) Increases with temperature Suitable for parallel connection

Faster switching due to high gain and reduced minority carrier lifetime More rugged due to wider base and low pnp gain

short circuit rating turn-on switching loss

Largely unaffected by temperature

Largely unaffected by temperature

turn-off switching loss

Loss increases with temperature but start lower than NPT devices

Virtually constant with temperature

3.2.6

The junction field effect transistor (JFET)

The field effect for a FET may be created in two ways: • A voltage signal controls charge indirectly using a capacitive effect as in the MOSFET, section 3.2.2. • In a junction FET (JFET), the voltage dependant scl width of a junction is used to control the effective cross-sectional area of a conducting channel. If the zero bias voltage cuts off the channel then the JFET is normally off, otherwise if a reverse bias is needed to cut-off the channel, the JFET is termed normally on. The electrical properties of SiC make the JFET a viable possibility as a power switch. Two normally on JFET structures are shown in figure 3.19, where it is seen how the scl layer decreases the channel width as the source to gate voltage reverse bias increases. In SiC, the channel has a positive temperature coefficient, Ron ∝ T 2.6 , hence parallel connection is viable. Natural current saturation with a positive temperature coefficient means lengthy short-circuit currents of over a millisecond can be sustained. Although the channel is bidirectional, in the biased off-state an integral fast, robust pn body diode is inherent as seen in figure 3.19b.

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85 s o u rc e

-

s o u rc e

+

g a te

-

g a te

m e ta l

n

+

n

-

n+

p

n+

+

p scl

+

n

-

(a )

scl

channel

n

s

m e ta l

d r a in s o u rc e

p

+

+

n

g

s o u rc e

g a te p

+

n

+

d p+

-

n d r ift r e g io n (b )

n b u ffe r 4 H n + s u b s tr a te

d r a in

b o d y d io d e

Figure 3.19. Cross-section of the SiC vertical junction field effect transistor: (a) trench gate with channel shown and (b) variation incorporating a pn body diode.

3.3

Thyristors

The name thyristor is a generic term for a bipolar semiconductor device which comprises four semiconductor layers and operates as a switch having a latched on-state and a stable off-state. Numerous members of the thyristor family exist. The simplest device structurally is the silicon-controlled rectifier (SCR) while the most complicated is the triac. 3.3.1

The silicon-controlled rectifier (SCR)

The basic SCR structure and doping profile in figure 3.20 depicts the SCR as three pn junctions J1, J2, and J3 in series. The contact electrode to the outer p-layer is called the anode and that to the outer nlayer is termed the cathode. With a gate contact to the inner p-region, the resultant three-terminal, 4 layer thyristor device is technically called the silicon-controlled rectifier (SCR). A low concentration n-type silicon wafer is chosen as the starting material. A single diffusion process is then used to form simultaneously the p1 and p2 layers. Finally, an n-type layer, n1, is diffused selectively into one side of the wafer to form the cathode. The masked-out areas are used for the gate contact to the p1 region. To prevent premature breakdown at the surface edge, bevelling is used as in figure 3.1, to ensure that breakdown will occur uniformly in the bulk. A number of observations can be made about the doping profile of the SCR which relate to its electrical characteristics. The anode and cathode would both be expected to be good emitters of minority carriers into the n2 and p1 regions respectively because of their relative high concentrations with respect to their injected regions. The n2 region is very wide, typically hundreds of micrometres, and low concentration, typically less than 1014 /cc. Even though the hole lifetime may be very long, 100µs, the base transport factor for hole minority carriers, bt-n2 is low. The low-concentration provides high forward and reverse blocking capability and the associated reverse-biased scl’s penetrate deeply into the n2 region. Gold lifetime killing or electron irradiation, most effective in the n2 region, is employed to improve the switching speed by increasing the number of carrier recombination centres.


86

Figure 3.20. The silicon-controlled rectifier, SCR: (a) net impurity density profile; (b) circuit symbol; and (c) cross-sectional view.

The two-transistor model of the SCR shown in figure 3.21 can be used to represent the p2-n2-p1-n1 structure and explain its electrical and thermal characteristics. Transistor T1 is an npn BJT formed from regions n2-p1-n1 while T2 is a pnp BJT formed from SCR regions p2-n2-p1. The application of a positive voltage between anode and cathode does not result in conduction because the SCR central junction J2 is reverse-biased and blocking. Both equivalent circuit transistors have forward-biased emitter junctions and with reverse-biased collector junctions, both BJT’s can be considered to be cut off. 3.3.1i - SCR turn-on It is evident from figure 3.21c that the collector current of the npn transistor provides the base current for the pnp transistor. Also, the collector current of the pnp transistor along with any gate current IG supplies the base drive for the npn transistor. Thus a regenerative current situation occurs when the loop gain exceeds unity. The base current of the pnp transistor T2 with dc current gain α2 is I b 2 = (1 - α 2 ) I A - I co 2 which is supplied by the collector of the npn transistor. The current Ico is the collector junction reverse bias leakage current. The collector current of the npn transistor T1 with a dc current gain of α1 is given by I c1 = α1 I K + I co1

By equating Ib2 and Ic1 (1 - α 2 ) I A - I co 2 = α1 I K + I co1

Since IK = IA + IG IA =

α1 I G + I co1 + I co 2 α1 I G + I co1 + I co 2 = 1 - (α1 + α 2 ) 1 - G1

where α1 + α2 is called the loop gain, G1.

(A)

(3.22)

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Ib2 = α1IK

Ib1

Figure 3.21. Cross-section of the SCR showing its model derivation: (a) schematic of the SCR cross-section; (b) the division of the SCR into two transistors; and (c) the npn-pnp two-transistor model of the basic SCR.

At high voltages, to account for avalanche multiplication effects, the gains are replaced by Mα, where M is the avalanche multiplication coefficient in equation 3.15. Hence, G1 becomes M1α1 + M2α2. By inspection of equation (3.22) it can be seen that a large anode current results when G1 → 1, whence the circuit regenerates with each transistor driving its counterpart into saturation. All junctions are forwardbiased and the total device voltage is approximately that of a single pn junction, with the anode current limited by the external circuit. The n2-p1-n1 device acts like a saturated transistor and provides a remote contact to the n2 region. Therefore the device behaves essentially like a p-i-n diode (p2-i-n1), where the voltage drop across the i-region is inversely proportional to the recombination rate. Typical SCR static IV characteristics are shown in figure 3.22.

Figure 3.22. The silicon-controlled rectifier static I-V characteristics.

At low current levels, α1 and α2 are small because of carrier recombination effects, but increase rapidly as the current increases. The conventional gate turn-on mechanism is based on these current gain properties. External gate current starts the regeneration action and the subsequent increase in anode current causes the gains to increase, thus ensuring a high loop gain, whence the gate current can be removed. The I-V characteristics in figure 3.22 show this property, where a minimum anode current IL is necessary for the loop gain to increase sufficiently to enable the SCR to latch on by the regeneration mechanism. The SCR can be brought into conduction by a number of mechanisms other than via the gate (other than the light triggered SCR used in high-voltage dc converters). • If the anode-cathode voltage causes avalanche multiplication of the central junction, the increased current is sufficient to start the regenerative action. The forward anode-cathode breakover voltage VBF is dependent on the central junction J2 avalanche voltage and the loop gain according to VBF = Vb (1 - α1 - α 2 )1/ m (V) (3.23) + where the avalanche breakdown voltage, at room temperature, for a typical SCR p n central


88

junction J2 is given by equation (2.3) Vb = 5.34 × 1013 × N D-¾ (V) (3.24) 14 13 where ND is the concentration of the high resistivity n2 region when 10 < ND < 5x10 /cc. • Turn-on can also be induced by means of an anode-to-cathode applied dv/dt where the peak ramp voltage is less than VBF. The increasing voltage is supported by the central blocking junction J2. The associated scl width increases and a charging or displacement current flows according to i = d(Cv)/dt. The charging current flows across both the anode and cathode junctions, causing hole and electron injection respectively. The same mechanism occurs at the cathode if gate current is applied; hence if the terminal dvldt is large enough, SCR turn-on occurs. • The forward SCR leakage current, which is the reverse-biased pn junction J2 leakage current, doubles approximately with every 8K temperature rise. At elevated temperatures, the thermally generated leakage current (in conjunction with the gains increasing with temperature and current) can be sufficient to increase the SCR loop gain such that turn-on occurs. 3.3.1ii - SCR cathode shorts All SCR turn-on mechanisms are highly temperature-dependent. A structural modification commonly used to reduce device temperature sensitivity and to increase dv/dt rating is the introduction of cathode shorts. A cross-sectional structure schematic and two-transistor equivalent of the cathode shorting technique are shown in figure 3.23. It will be seen that the cathode metallization overlaps the p1 region, which is the gate contact region. The technique is based on some of the anode forward-blocking current being shunted from the cathode junction via the cathode short. The cathode electron injection efficiency is effectively reduced, thereby decreasing α1 which results in an increase in the forward voltage-blocking rating VBF and dv/dt capability. The holding and latching currents are also increased.

Figure 3.23. Shorted cathode SCR: (a) SCR cross-section showing some anode current flowing through cathode shorts and (b) the SCR two-transistor equivalent circuit SCR with cathode shorts.

The cathode-anode, reverse breakdown voltage VBR is shown in figure 3.22. The anode p2+n2 junction J1 characterises SCR reverse blocking properties and VBR is given by (equation (3.6)) VBR = Vb (1 - α 2 )1/ m If a very high resistivity n2 region, NDn2, is used (in conjunction with low temperature) and breakdown is due to punch-through to J2, then the terminal breakdown voltage will be approximated by (equation (2.2)) VPT = 7.67 × 10-16 N Dn2 Wn22 where Wn2 is the width of the n2 region. This relationship is valid for both forward and reverse SCR voltage breakdown arising from punch-through.

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3.3.1iii - SCR amplifying gate At SCR turn-on, only a small peripheral region of the cathode along the gate region conducts initially. The conducting area spreads at about 50m/s, eventually encompassing the whole cathode area. If at turn-on a very large anode current is required, that is a high initial di/dt, a long gate-cathode perimeter is necessary in order to avoid excessively high, localised initial cathode current densities. The usual method employed to effectively enlarge the SCR initial turn-on area is to fabricate an integrated amplifying gate, as shown in figure 3.24. A small gate current is used to initiate the pilot SCR, which turns on very rapidly because of its small area. The cathode current of this pilot SCR provides a much larger gate current to the main SCR section than the original gate triggering current. Once the main device is fully on, the pilot device turns off if the gate current is removed. An important property of the SCR is that once latched on, the gate condition is of little importance. The regenerative action holds the device on and SCR turn-off can only be achieved by reducing the anode current externally to a level below which the loop gain is significantly less than unity.

Figure 3.24. The amplifying gate SCR: (a) cross-section of the structure and (b) two-SCR equivalent circuit.

3.3.2

The asymmetrical silicon-controlled rectifier (ASCR)

The doping profiles and cross-sectional views comparing the asymmetrical SCR and conventional SCR are shown in figure 3.25. In each case the electric field ξ within the p1n2 junction reverse-bias scl is shown and because the n2 region is lightly doped, the scl extends deeply into it. The scl applied reverse-bias voltage is mathematically equal to the integral of the electric field, ξ (area under the curve). If, in the conventional SCR, the scl edge reaches the p2+ layer, then punch-through has occurred and the SCR turns on. To prevent such a condition and to allow for manufacturing tolerances, the n2 region is kept thick with the unfortunate consequence that on-state losses, which are proportional to n2 layer thickness, are high. In the case of the ASCR, a much thinner n2- region is possible since a highly doped n layer adjacent to the p2+ anode is utilised as an electric field stopper. The penalty paid for this layer construction is that in the reverse voltage blocking mode, the n2p2+ junction avalanches at a low voltage of a few tens of volts. Thus the ASCR does not have any usable repetitive reverse-blocking ability, hence the name asymmetrical SCR. By sacrificing reverse-blocking ability, significant improvements in lower on-state voltage, higher forward-blocking voltage, and faster turn-off characteristics are attained.


90

Figure 3.25. Doping profile, cross-section, and the electric field of J2 in the forward biased off-state for: (a) and (b) the conventional SCR; (c) and (d) the asymmetrical SCR.

3.3.3

The reverse-conducting thyristor (RCT)

The RCT is electrically equivalent to an SCR in anti-parallel with a diode, but both are integrated into the same wafer. The reason for integrating the SCR and diode is to minimise external interconnecting lead inductance. The circuit symbol, cross-sectional wafer view, and typical doping profile are shown in figure 3.26. Since no reverse voltage will be applied to the RCT there is only the cathode-side deep p-diffused layer. This and the ASCR n-region type field stopper result in low forward voltage characteristics. As in the ASCR case, the highly n-type doped anode end of the wide n-region also allows higher forward voltages to be blocked. Both anode and cathode shorts can be employed to improve thermal and dv/dt properties. As shown in figure 3.26a, an amplifying gate can be used to improve initial di/dt capability. The integral anti-parallel diode comprises an outer ring and is isolated from the central SCR section by a diffused guard ring, or a groove, or by irradiation lifetime control techniques. The guard ring is particularly important in that it must confine the carriers associated with the reverse-blocking diode to that region so that these carriers do not represent a forward displacement current in the SCR section. If the carriers were to spill over, the device dv/dt rating would be reduced - possibly resulting in false turnon. Gold or irradiation lifetime killing can be employed to reduce the turn-off time without significantly increasing the on-state voltage.

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p

Figure 3.26. Reverse conducting thyristor with an amplifying gate structure: (a) cross-section of the structure and (b) typical doping profile of the SCR section.

3.3.4

The bi-directional-conducting thyristor (BCT)

Two anti-parallel connected SCRs can be integrated into one silicon wafer, as shown in figure 3.27. As a result of integrated symmetry, both devices have near identical electrical properties. The mechanical feature different to the triac, is that there are two gates – one on each side of the wafer. Also, unlike the triac, the two SCR sections are physically separated in the wafer to minimise carrier diffusion interaction. The equivalent circuit comprises two SCRs connected in anti-parallel. As such, one device turning off and supporting a negative voltage, represents a positive dv/dt impressed across the complementary device, tending to turn it on. Also, any charge carries which diffusion from the SCR previously on, exasperate the dv/dt stress on the off SCR. The two central amplifying gate structures are as for the RCT, in figure 3.26a. A separation of a few minority carrier lateral diffusion lengths, along with an increased density of cathode shorts along the separating edge of each cathode and in the amplifying gate region close to the anode of the complementary SCR, enhance the physical separation. The amplifying gate fingers are angled away from the separation regions to minimise the shorting effect of the complementary SCR anode emitter shorting. The on-state voltage of each SCR is fine tuned, match for on-state loss, using electron irradiation.


92

Figure 3.27. Cross-section structure of the bidirectional conducting phase-control SCR with an amplifying gate structure.

3.3.5

The gate turn-off thyristor (GTO)

The gate turn-off thyristor is an SCR that is turned on by forward-biasing the cathode junction and turned off by reverse-biasing the same junction, thereby preventing the cathode from injecting electrons into the p1 region. Other than its controlled turn-off properties, the GTO’s characteristics are similar to the conventional SCR. The basic structure and circuit symbol are shown in figure 3.28. 3.3.5i - GTO turn-off mechanism In the on-state, due to the high injection efficiency of junctions J1 and J3, the central p-base is flooded with electrons emitted from the n-cathode and the central n-base is flooded with holes emitted from the p-anode,. If a reverse gate current flows from the cathode to the gate, with a driving voltage tending to reverse bias the gate-cathode junction – then p-base holes are extracted from the gate, suppressing the cathode junction from injecting electrons. Eventually the cathode junction is cut-off and the pnp transistor section, now without base current turns off, thereby turning off the GTO.

Figure 3.28. The gate turn-off thyristor: (a) circuit symbol and (b) the basic structure along an interdigitated finger showing plasma focussing in the p1 region at the cathode junction at turn-off.

The turn-off mechanism can be analyzed by considering the two-transistor equivalent circuit model for the SCR shown in figure 3.21c. The reverse gate current IGQ flows from the gate and is the reverse The base current for transistor T1 is given by base current of the npn transistor T1.

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I B = α 2 I A − I GQ , where I GQ = − I G . The reverse base current in terms of the gain of T1 is I RB = (1 − α1 ) I K . The GTO as a three terminal device must satisfy I A = I K + I GQ and to turn-off the GTO, IB < IRB. These conditions yield (α1 + α 2 − 1) I A < α 2 IGQ

The turn-off gain of the GTO, βQ, is defined as the ratio of anode current IA to reverse gate current IGQ, that is β Q ≡ I T / I GQ (3.25) < α1 / (α1 + α 2 - 1) Thus for high turn-off gain it is important to make α1 for the npn section as close to unity as possible, while α2 of the pnp section should be small. A turn-off current gain of 5 is typical. During the turn-off process, the conducting plasma is squeezed to the centre of the cathode finger, since the lateral p1 region resistance causes this region to be last in changing from forward to reverse bias. This region has the least reverse bias and for reliable GTO operation, the final area of the squeezed plasma must be large enough to prevent an excessive current density. Device failure would be imminent because of localised overheating. The doping profile is characterised by a low p1 region sheet resistance and an inter-digitated cathode region to ensure even distribution of the reverse bias across the cathode junction at turn-off. Both turnoff and temperature properties are enhanced by using an anode shorting and defocusing technique as shown in figure 3.29a, but at the expense of any reverse-blocking capability and increased on-state voltage. The shown two-level cathode and gate metallization used on large-area devices allow a flat metal plate for the cathode connection. As with the conventional SCR, a reverse conducting diode structure can be integrated, as shown in figure 3.29b. 3.3.6

The gate commutated thyristor (GCT)

GTO frequency limitations and the need for an external parallel connected capacitive turn-off snubber (to limit re-applied dv/dt), have motivated its enhancement, resulting in the gate commutated thyristor, GCT. As shown in figure 3.29c, a number of processing and structural variations to the basic GTO result in a more robust and versatile high power switch.

•

•

•

n-type buffer An n-type buffer layer allows a thinner n-drift region. A 40% thinner silicon wafer, for the same blocking voltage, reduces switching losses and the on-state voltage. An integral reverse conducting diode is also possible, as with the conventional SCR and GTO. transparent emitter A thin lightly doped anode p-emitter is used instead of the normal GTO anode shorts. Some electrons pass through the layer as if the anode were shorted and recombine at the anode contact metal interface, without causing hole emission into the n-base. Effectively, a reduced emitter injection efficiency is achieved without anode shorts. Consequently, gate current triggering requirements are an order of magnitude lower than for the conventional GTO. low inductance A low inductance gate structure, contact, and wafer assembly ( 3.3kV). 4.1.2

Forward current ratings

The forward current ratings are usually specified after consideration of the following factors. • • •

Current at which the junction temperature does not exceed a rated value. Current at which internal leads and contacts are not evaporated. External connector current-handling capabilities.

1700V 3600A 6500V 600A

Figure 4.1. Electrical rating bounds for power switching silicon devices, where (a) frequency related losses limit upper power through-put and (b) voltage is restricted by silicon limitations while current is bounded by packaging and die size constraints.

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4.1.3

Temperature ratings

The maximum allowable junction temperature Tl j , is dependent on the quality of the materials used and the type of junction, and is traded off against the reduced reliability that arises from deterioration and accelerated service life. The higher the junction temperature, the higher the rate of deterioration. The relationship between service life Lt in hours, and the junction temperature Tj (K) is approximated by log10 Lt ≈ A + B / T j

(4.1)

where A and B are constants which are related to the device type. 4.1.4

Power ratings

Power dissipated in a semiconductor device is converted into thermal energy which produces a l are the temperature rise. The major parameters limiting the maximum allowable power dissipation P d maximum allowable junction temperature and the device case temperature Tc. These parameters are related to one another by the thermal resistance Rθ, according to l l = T j - Tc P (W) (4.2) d Rθ j-c The virtual junction to case thermal resistance Rθ j-c is a physical value representing the ratio, junction temperature rise per unit power dissipation. Thermal resistance is a measure of the difficulty in removing heat from the junction to the case. Most maximum power values are specified at a case temperature of 25°C, and are derated linearly to zero as the case-operating temperature increases to Tl j , which is typically a maximum of 175°C for silicon power switching devices. 4.2

The fast-recovery diode

Static I-V diode characteristics were considered in chapter 2 and chapter 3.1. In low-frequency applications the only problem posed by a rectifier is heat dissipation, which can be readily calculated if the current waveform is known. On the other hand, calculation of losses in rectifiers for high-frequency application requires knowledge of device switching phenomena. The forward and reverse recovery characteristics are the most important fast-recovery bipolar pn diode electrical switching properties.

Figure 4.2. Diode forward recovery measurement: (a) specification of forward recovery time, tfr and peak forward voltage, Vfp and (b) diode anode current test waveform.

4.2.1

Turn-on characteristics

During the forward turn-on period of a rectifier, an overshoot voltage is impressed in a forward bias direction across the diode as the forward current increases. The forward recovery characteristics of time tfr and peak forward voltage Vfp are measured as shown in figure 4.2, with a specified increase in forward current diF/dt, rising to a maximum forward current level IF. Two mechanisms predominate and contribute to the forward voltage overshoot phenomenon. The first mechanism is resistive, while the second is inductive.

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102

Initially at turn-on, the device resistance is dominated by the ohmic resistance of the lowconcentration n-region. As the concentration of the injected minority carriers increases, the n-region becomes conductively modulated and the associated ohmic voltage drop decreases significantly. These charging effects contribute to a minor initial capacitive component which serves to clamp Vfp initially to zero.

Figure 4.3. Diode forward turn-on characteristics for two initial anode di/dt cases: (a) forward current and effective change in resistive component, r and (b) anode voltage and voltage contribution vℓ, as a result of die inductance.

The forward diF /dt causes a voltage drop across the internal device inductance. This inductance comprises both the diode wafer internal inductance and the bonding and connection inductance. In bipolar power devices, the inductance of the wafer predominates. Any inductance contribution to the forward transient voltage ceases when the steady-state current level IF is reached, as shown in figure 4.3. It will be seen that the peak forward transient voltage increases as diF /dt increases. The resistive component predominates at low diF /dt. As with most minority carrier based power semiconductor characteristics, the turn-on phenomenon is significantly worsened by an increase in junction temperature. That is, both tfr and Vfp are increased with increased temperature. Although a pre-reversed biased junction condition does not significantly prejudice the turn-on characteristics, if the junction is pre-forward biased slightly, the turn-on transitional phase can be significantly reduced. The Schottky diode, a majority carrier device, does not suffer from forward turn-on transient effects. Package inductances dominate at turn-on. 4.2.2

Turn-off characteristics

When a forward-conducting bipolar junction diode is abruptly reverse-biased, a short time elapses before the device actually regains its reverse blocking capabilities. Most importantly, before the diode does regain blocking ability, it may be considered as a short circuit in its normally blocking direction. During forward conduction there is an excess of minority carriers in each diode region and the holes in the n-region and electrons in the p-region must be removed at turn-off. The attempted reverse bias results in a reverse current flow as shown in figure 4.4. The total recovery charge Qo is given by Qo = τ I F (4.3) where IF is the forward current before switching. In the usual p+n diode, the excess minority holes in the n-region are more dominant. The lifetime τ is therefore the hole lifetime τh. Since carrier lifetime increases with temperature, recovery charge increases with temperature. The recovery charge Qo has two components, one due to internal excess charge natural recombination and the other, the reverse recovery charge QR, due to the reverse diode current shown in figure 4.4. The excess charges reside in the neutral scl regions of the diode that border the junction. The excess charge concentration is largest at the scl edge on the n-side, reducing to zero well before the cathode contact. Turn-off is initiated at tf and the reverse recovery current irr commences. The rate of rise of this current is determined solely by the external inductance L of the switching circuit and the circuit applied reverse voltage E, according to dI F E (A/s) (4.4) =− dt L

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Until the time to, the diode carries forward current and is forward-biased. When the current reverses, the forward voltage drop decreases slightly but the device still remains positively biased. The external circuit inductance L supports the voltage E. The excess carrier concentrations now begin to reduce as holes leave via the junction, in providing the reverse current, irr. Holes are therefore extracted first and quickest at the edge of the scl.

Figure 4.4.

Diode voltage and current during reverse recovery at turn-off.

At time t1, the hole concentration at the scl edge reaches zero, the charge Q1 has been removed (plus natural recovery) and charge Q2 remains. The reverse current now reduces rapidly since insufficient holes exist at the scl edge. The scl widens quickly, as it is charged. That is, the diode regains its ability to support reverse voltage and at the maximum reverse current IRM, dIF /dt reduces to zero. Since dIF / dt = 0, the voltage across the circuit inductance L drops rapidly to zero and E is applied in reverse bias across the diode. Between t1 and t2 the rate of change of reverse current dirr /dt is high and, in conjunction with L, produces a reverse voltage overshoot to VRM. After time t2, dirr /dt reduces to zero, the circuit inductance supports zero volts, and the diode blocks E. In specifying the reverse recovery time, trr = t2 - t0, the time t2 is defined by projecting irr through ¼IRM as shown in figure 4.4. The reverse recovery time trr and peak reverse recovery current IRM, at high magnitude dIF I dt such that QR ≈ Q0, are approximated by trr ≈ 2.8 × 10-6 Vb I F / dI F / dt and

I RM ≈ 2.8 × 10-6 Vb I F × dI F / dt

(s) (A)

(4.5)

where the avalanche breakdown voltage for a step junction, Vb, is given by equation (2.3). The reverse recovery charge QR is therefore given by QR = ½ I RM trr = 3.92 × 10-12 Vb2 I F

(C)

(4.6)

that is, the reverse recovery charge is proportional to the forward current, as shown in figure 5.9a for dIF /dt >100 A/µs. Figure 4.5 illustrates snap-off and soft recovery diode properties (Sr) which are characterised by the recovery dirr /dt magnitude. The higher the value of dirr /dt, the higher is the induced diode overshoot VRM and it is usual to produce soft recovery diodes so as to minimise voltage overshoot VRM, resulting from inductive ringing. Reverse recovery properties are characterised for a given temperature, forward current IF, and dIF/dt as shown in figure 5.9. 4.2.3

Schottky diode dynamic characteristics

Being a minority carrier device, the Schottky barrier diode, both in silicon and silicon carbide, is characterised by the absence of forward and reverse recovery, plus the absence of any temperature influence on switching. Forward recovery traits tend to be due to package and external circuit inductance.


104

Reverse recovery is dominated by the barrier charging – a capacitive effect, which increases slightly with increased temperature, reverse di/dt, and IF. The barrier charge requirements are significantly less than the highly temperature dependant minority carrier charge Qo, associated with the bipolar pn junction diode. Unlike the pn diode, as Schottky junction charging occurs, the junction reverse bias voltage begins to increase immediately. Turn-off voltages are well controlled, less snappy, as the scl capacitor barrier junction acts like a capacitive turn-off snubber, as considered in chapter 8.3. Whereas the transient performance is virtually independent of temperature, the static forward and reverse I-V characteristics are highly temperature dependant. In the case of silicon carbide, the reverse leakage current increases by 4% /K, the reverse breakdown voltage decreases by -4% /K while a 0.45% /K increase in on-state voltage means die can be readily parallel connected. In contrast, it will be noticed in figure 2.2 that reverse breakdown voltage and leakage current of a bipolar junction diode, both have a positive temperature co-efficient.

Figure 4.5. Comparison of fast recovery diode dirr/dt characteristics of: (a) short current tail, producing snap-off (low Sr) and (b) gradual current tail, producing soft recovery (high Sr).

4.3

The bipolar, high-voltage, power switching npn junction transistor

The electrical properties of the high-voltage power switching npn transistor are related to and dominated by the wide low-concentration n- collector region employed to obtain high-voltage characteristics in all semiconductor devices. Many of the limitations and constraints on the MOSFET, IGBT, and the different thyristors are due to their parasitic bjt structures, which introduce undesirable BJT characteristics and mechanisms. It is therefore essential to understand the electrical characteristics and properties of the BJT if the limitations of other switching semiconductor devices are to be appreciated.

4.3.1

Transistor ratings

4.3.1i – BJT collector voltage ratings The breakdown voltage ratings of a transistor can be divided into those inherent to the actual transistor (Vceo, Vcbo) and those that are highly dependent on the external base circuit conditions (Vcer, Vces, Vcev). Figure 4.6 shows the various voltage breakdown modes of the BJT, which are defined as follows. Vcbo Vceo Vces Vcer Vcev

Collector to base voltage-current characteristics with the emitter open; that is, Ie = 0, where V(BR)cbo is the collector to base breakdown voltage with Ie = 0 and the collector current Ic specified as Icbo. Collector to emitter characteristics with the base open circuit such that the base current Ib = 0, where V(BR)ceo is the collector to emitter breakdown voltage with Ib = 0 and Ic specified as Iceo. Collector to emitter characteristics with the base shorted to the emitter such that Vbe = 0, where V(BR)ces is the collector to emitter breakdown voltage with Ic specified as Ices. Collector to emitter characteristics with resistance R between the base and the emitter such that Rbe = R, where V(BR)cer is the collector to emitter breakdown voltage with Ic specified as Icer. Collector to emitter characteristics with reverse base to emitter bias Veb = X, where V(BR)cex is the collector to emitter breakdown voltage with Ic specified as Icex.

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Each breakdown voltage level and its relative magnitude can be evaluated. 1 – BJT V(BR)cbo - maximum collector-base voltage with the emitter open circuit The V(BR)cbo rating is just less than the voltage Vb, where the base to collector junction breaks down because of avalanche multiplication, as illustrated in figure 4.6. The common base avalanche breakdown voltage Vb is determined by the concentration of the collector n-region, Nc /cc, and as its resistivity increases, Vb increases according to (equation (2.3)) Vb = 5.34 × 1013 × N c-¾

(4.7)

(V)

It can be assumed that V(BR)cbo ≈ Vb. 2 – BJT V(BR)ceo - maximum collector-emitter voltage with the base open circuit

Avalanche multiplication breakdown of a common emitter connected transistor occurs at a collector voltage Va when the common emitter amplification factor β becomes infinite. The gain β, from equation 3.4 and accounting for avalanche multiplication, is defined by αM β= 0 (4.8) 1 − α0 M where M is the avalanche multiplication factor, which is collector junction voltage Vcb dependent, according to (equation 3.17) m

 V  M = 1 /  1- cb  (4.9)  Vb  The factor m is empirically determined and is between 2 and 4 for the collector-base doping profile of the high-voltage silicon npn transistor. The common base current amplification factor α0 is for a voltage level well below any avalanche.

I0

Iceo

V(BR)ceo

Icer

V(BR)cer

Ices

V(BR)ces

Icex

V(BR)cex

Icbo

V(BR)cbo

Figure 4.6. Relative magnitudes of npn transistor collector voltage breakdown characteristics, showing first and second breakdown.

At high Vcb voltages, near Va, avalanche multiplication causes a high injection of hole carriers. Thus no base current is required and a β → ∞ condition effectively occurs. With such conditions, equation (4.8) indicates that α0 M → 1 which, upon substitution into equation (4.9), yields Va = Vb m 1- α 0 ≈ V( BR )ceo (V) (4.10) Va becomes the common emitter avalanche breakdown voltage V(BR)ceo which is commonly called the collector emitter sustaining voltage, Vceo(sus).


It can be shown that (see figure 4.6) V( BR )cbo > V( BR )cex > V( BR )ces > V( BR )cer > V( BR )ceo

106

(4.11)

With low-gain BJTs, Va is almost Vb in value, but with high-gain devices Vb may be 2 to 3 times that of Va. Notice in figure 4.6 that negative resistance characteristics occur after breakdown, as is the case with all the base circuit-dependent breakdown characteristics. The inserted diagram in figure 4.6 shows how base-emitter resistance affects collector-emitter voltage breakdown. Importantly, the breakdown voltage increases as the base-emitter resistance decreases. This is because the injection efficiency of the emitter is reduced. This shorting feature is exploited extensively in alleviating parasitic problems in the MOSFET, IGBT, and thyristor devices, and is discussed in the respective device sections. 4.3.1ii – BJT safe operating area (SOA) The safe operating area represents that electrical region where a transistor performs predictably and retains a high reliability, without causing device destruction or accelerated deterioration. Deterioration or device destruction can occur when operating within the absolute maximum device ratings, as a result of second breakdown (s/b) or excessive thermal dissipation. Typical SOA characteristics are shown in figure 4.7. These collector characteristics are for a single pulse, of a given duration, such that the transistor operates in the linear region and at a case temperature of 25°C. The dc or continuous operation case has the most restrictive SOA curve, while a short single pulse of 1µs duration enables the full device I-V ratings to be exploited. The SOA is basically bounded by the maximum collector Ilc and the collector emitter breakdown voltage V(BR)ceo. In figure 4.7 it will be seen that four distinct operating region limits exist, viz., A to D. A Maximum collector current which is related to allowed current density in the leads and contacts and the minimum gain of the transistor. The maximum lead current is given by I = K d 2 / 3 where the diameter d is in mm and K depends on the type and length of wire. For lengths greater than 1mm, K = 160 for both copper and silver.

B Maximum thermal dissipation, which is related to the absolute maximum junction temperature Tlj , and the thermal resistance or impedance from the virtual junction to the case. -1 In this thermally limited region, the collector power loss is constant and Ic = P Vc . Thus the thermal limit gradient is -1, when plotted on logarithmic axes as in figure 4.7.

Limit of forward second breakdown (s/b). This breakdown occurs when the local current C density is too high and a hot spot is created which causes thermal runaway. The physical causes of the high current concentration phenomenon are a fall in electrical potential or instability of lateral temperature distribution in the base area. These occur as a consequence of base-width concentration non-uniformity, a faulty junction or improper chip mounting. A typical s/b characteristic is shown in figure 4.6, and is characterised by a rapid drop in collector -n voltage to the low-impedance area after s/b. The s/b SOA limit can be modelled by I s / b = PV , where n, the gradient in figure 4.7, ranges from 1.5 to 4 depending on the fabrication processes and structures that have been employed. S/b, with a forward-biased base emitter is usually characterised by a short circuit at the emitter periphery, since this area is more forward-biased than central regions because of lateral base resistance effects. S/b, with a reverse-biased base-emitter junction, occurs in the central emitter region because of current focussing to that area as a result of the same lateral base resistance effects. D Maximum collector voltage under worst case conditions. In switching applications the V(BR)ceo limit can be exceeded provided suitable base conditions exist. At turn-off, when the collector current has fallen below Icex, the collector supporting voltage can be increased from V(BR)ceo to V(BR)cex if the proper reverse bias base emitter junction conditions exist. The SOA together with this small extension area form the reverse bias SOA. Turn-on in switching applications can take place from a V(BR)cex condition, provided the collector current rise time is very short, usually much less than 1µs. As the rise time value decreases, the current that can be switched at turn-on increases. Under such conditions a significant portion of Ic can be switched from V(BR)cex. The SOA together with this large switch-on extension area form the forward bias SOA, as shown in figure 4.7.

The SOA is usually characterised for a case temperature of 25°C. In practice much higher case temperatures are utilised and then the power and s/b SOA limits are modified with the aid of the derating curves of figure 4.8. At a given case temperature, above 25°C, power derating is greater than s/b derating. No derating is necessary for case temperatures below 25°C.

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Ic

Figure 4.7. Safe operating area (SOA) bounds of an npn high-voltage power switching transistor including forward and reverse bias SOA. Temperature derating for a case temperature of 75°C is shown.

Figure 4.7 shows the derating, according to figure 4.8, of the dc and 1ms operating loci when the case temperature is increased from 25°C to 75°C. Figure 4.8 indicates that the power limit line B is derated to 71.5 per cent, while the s/b limit line C is reduced to 80 per cent. The slope of the 10µs single pulse limit line indicates that no s/b component exists, thus only power derating need be employed. This is because the pulse period of a few microseconds is short compared to the die thermal constant, whence the rate of local heating is too brief to disperse and cause second breakdown.

75ºC

Figure 4.8. Power and second breakdown derating versus case temperature.

It is important to note that when a transistor is employed in a switching application, where the device is either cut-off or hard-on, the full SOA bounded by Ic and V(BR)ceo can usually be exploited. As indicated in figure 4.7, provided the collector switching times are of the order of a microsecond or less, no power or s/b derating need be factored. Design is based on total power losses, such that the maximum allowable junction temperature, Tlj is not exceeded. For high reliability and long device lifetime only one electrical limit, either Ic or V(BR)ceo, should be exploited in a given application. 4.3.2

Transistor switching characteristics

If a current pulse is supplied into the base of a common emitter connected transistor, as shown in figure 3.8, the resultant collector current waveform is as shown in figure 4.9. The collector voltage waveform is essentially collector load circuit dependent and therefore is not used to characterise transistor switching. 4.3.2i – BJT turn-on time: ton = td + tri Turn-on consists of a delay time td followed by a current rise time tri. The delay time corresponds mainly to the charging of the base-emitter junction diffusion capacitance. The turn-on delay time can be significantly reduced by increasing the applied rate and magnitude of the forward base current Ibf. The current rise time is related to the effective base zone width and, as the base charge increases because of the base current, the collector current increases.


108

4.3.2ii – BJT turn-off time: toff = ts + tfi In order to cut-off a transistor from the saturated state, all the accumulated charges must be neutralised or removed from the base and from the lightly doped n- region of the collector. The turn-off process is started by removing the forward base current Ibf, and applying the reverse base current Ibr. The excess minority carriers, namely holes, in the collector n- region are progressively reduced in the process of providing the collector current. The excess minority carriers in the base are removed by the reverse base current. The reverse base current does not influence the collector n- region recombination process. The period after the cessation of positive base current until the transistor enters the linear region is termed storage or saturation time, ts. Generally, and undesirably, the larger the forward gain βf, the greater the saturation time, ts.

Figure 4.9. Defining transistor base and collector current switching times for turn-on and turn-off.

Optimal turn-off occurs when the emitter junction cuts off, as a result of Ibr, just as the collector junction cuts off and enters the linear region. Thus the collector current fall time can be decreased by increasing the reverse base current immediately after the collector junction has cut off. In switching applications, operation in the linear region is to be avoided, or at least traversed rapidly, because of the associated high device power losses. Although in the saturated state, with Ibf >> Ic / βf, gives minimum forward gain and losses, this state is not conducive to a rapid turn-off transition to the cut-off region. In switching applications, in order to increase turn-off speed (decrease ts and tfi), the transistor may be held in the quasi-saturation region by reducing and controlling the forward base current magnitude such that the device is on the verge of saturation, Ibf ≈ Ic / βf, but is not in the linear region. The quasi-saturation on-state losses are slightly higher. In the quasi-saturated on-state the collection n- region can be considered as extra series collector circuit resistance, which decreases as the neutral base region penetrates and reduces to zero when saturation occurs. 4.3.3

BJT phenomena

Although the BJT is virtually obsolete as a discrete power switching device for new circuit designs, it has been considered in some detail both in this chapter and chapter 3.2.1. This is because its operating electrical mechanisms explain the major limiting electrical operating factors of all controlled power switching devices. • mosfet: In chapter 3.2.2 the reverse conducting inherent body diode in the MOSFET is part of a parasitic npn transistor. This BJT structure can produce unwanted MOSFET dv/dt turn-on. Notice in figure 3.14a that the source metallization overlaps the p+ well, there-in producing a base to emitter shunting resistor, as shown by Rbe in figure 3.14b. The emitter shunts perform two essential functions, but inadvertently creates a non-optimal diode. o First, the shunt decreases the injection efficiency hence gain of the npn BJT, decreasing the likelihood of a drain dv/dt resulting in sufficient Miller capacitance current to turn-on the parasitic BJT, as considered in chapter 3.2.1.

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Second, by decreasing the BJT gain, the npn section voltage rating is increased from Vceo to Vcer as considered in section 4.3.1. • igbt: In figure 3.16d the equivalent circuit of the IGBT has a parasitic pnp-npn thyristor structure. Once again, the emitter metallization (Rbe) shunts the base to emitter of the npn BJT, helping to avoid latch-up of the SCR section, as modelled by the derivation of equation (3.18). Also the voltage rating of the npn section is increased from Vceo to Vcer. Improved thermal stability also results. Judicious profiling of the transistor sections is essential. • gto thyristor: All the electrical operating mechanisms of the SCR are explainable in terms of BJT mechanisms, including turn-on, turn-off, and thermal stability. Emitter shorts (Rbe shunts) are used extensively to decrease gain, increase thermal stability, and increase voltage ratings and are essential in providing separation in the bi-directional conducting thyristor, as considered in chapter 3.3.4. The GTO thyristor also uses emitter shorts in order to achieve a stable device at turn-off, as shown in figure 3.28. o

An understanding of BJT electrical operating mechanisms is fundamental to the design and operation of semiconductor power switching devices, whether principally bipolar operating devices or unipolar devices which have bipolar parasitic structures. 4.4

The power MOSFET

The main electrical attributes offered by power MOSFETs are high switching speeds, no second breakdown (s/b), and high impedance on and off voltage control. MOSFETs, along with IGBTs, have replaced the bipolar junction transistor due to their superior switching performance and simpler gate control requirements. 4.4.1

MOSFET absolute maximum ratings

The basic enhancement mode power MOSFET structure and electrical circuit symbol are shown in figure 3.11. The SOA bounds shown in figure 4.10 is confined by four outer bounds. The n- epitaxial layer concentration and thickness is the key parameter in specifying the drain high-voltage ratings, such as Vds and Vdg, which increase with temperature at approximately +0.1 per cent/K, as shown in figure 3.13. B One important rating feature of the power MOSFET is that it does not display the s/b that occurs with the bipolar transistor. Figure 4.10 shows the safe operating area for transistors, with the bipolar junction transistor s/b limitation area shaded. The physical explanation as to why MOSFETs do not suffer from s/b is based on the fact that carrier mobility in the channel decreases with increased temperature at -0.6 per cent/K. If localised heating occurs, the carrier mobility decreases in the region affected and, as a consequence, the localised current reduces. This negative feedback, self-protection mechanism forces currents to be uniformly distributed along the channel width and through the silicon die. This property is exploited when paralleling MOSFET devices. As a result of the enlarged SOA, the power MOSFET is generally a much more robust device than its bipolar counterpart. This region is thermally limited, as defined by I = P / V −1 giving the -1 slope on the log-log axes in figure 4.10. C The drain current rating is also related to the epitaxial properties. Its resistance specifies the I d2 Rds (on) power loss, which is limited by the junction to case thermal resistance, Rθ j-c. The continuous, usable drain current above 25°C is thus given by Tl j − Tc (A) Id = (4.12) Rds (on) Rθ j-c A

D When the MOSFET is on, with minimum drain voltage at maximum drain current, it operates in the resistive mode where the drain current is given by 1 (A) Id = Vds (4.13) Rds (on)

The SOA region at high currents and low voltages is thus characterised by a line of slope 1, on logarithmic axes, as shown in figure 4.10. The gate to source voltage Vgs controls the channel and the higher the value of Vgs, the higher the possible drain current. The gate to source is a silicon dioxide dielectric capacitor which has an absolute forward and reverse voltage that can be impressed before dielectric breakdown. Typical absolute maximum voltage levels vary from ±10V to ±40V, as the oxide layer thickness increases and capacitance advantageously decreases.


110

C

D B

A

Figure 4.10. The safe operating area of the power MOSFET, which does not suffer second breakdown.

4.4.2


The important power MOSFET dynamic characteristics are inter-terminal voltage-dependent capacitance and drain current-switching times. The various MOSFET capacitances are dominant in specifying switching times. 4.4.2i – MOSFET device capacitances Figure 4.11 shows an equivalent circuit for the power MOSFET, extracted from figure 3.14, which includes three inter-terminal, non-linear voltage-dependent capacitances Cgd, Cgs, and Cds. The magnitudes are largely determined by the size of the chip and the cell topology used. Therefore higher current devices inherently have larger capacitances. Electrically, these capacitances are strongly dependent on the terminal drain-source voltage. Manufacturers do not generally specify Cgd, Cgs, and Cds directly but present input capacitance Ciss, common source output capacitance Coss, and reverse transfer capacitance Crss. These capacitances, as a function of drain to source voltage, are shown in figure 4.12a. The manufacturers’ quoted capacitances and the device capacitances shown in figure 4.12b are related according to Ciss = Cgs + Cgd ;

Cds shorted

Crss = Cgd

Coss = Cds +

(F) (F)

Cgs . Cgd Cgs + Cgd

≈ Cds + Cgd

;

Cgs shorted

(4.14) (4.15)

(4.16) (F)

Figure 4.11. MOSFET equivalent circuit including terminal voltage dependent capacitance and inductance for the TO247 package.

111

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Figure 4.12. MOSFET capacitance variation with drain-to-source voltage: (a) manufacturers’ measurements and (b) inter-terminal capacitance values.

The measurement frequency is usually 1 MHz and any terminals to be shorted are connected with large, high-frequency capacitance, so as to present a short circuit at the measurement frequency. Device capacitances are predominant in specifying the drain current switching characteristics, particularly Cgd with its large capacitance variation at low drain voltage levels. 4.4.2ii – MOSFET switching characteristics The simple single-ended MOSFET circuit with an inductive load LL in figure 4.13, can illustrate how device capacitances influence switching. The MOSFET gate is driven from a voltage source whose output impedance is represented by Rg, which also includes any MOSFET gate series internal resistance. The dc input resistance of a power MOSFET is in excess of 1012 Ohms and when used as a switch, the power required to keep it on or off is negligible. However energy is required to change it from one state to the other another, as shown in figure 4.14. This figure shows the relationship between gate charge, gate voltage, and drain current for a typical MOSFET. The initial charge Qgs is that required to charge the gate-source capacitance and Qgd is that required to supply the drain-gate Miller capacitance. For a given gate charging current, switching speed is proportional to gate voltage. The gate charge required for switching, and hence switching speed, is not influenced significantly by the drain current magnitude, and not at all by the operating temperature. The switching speed is directly related to time delays in the structure because of the channel transit time of electrons. External to the device, the switching time is determined by the energy available from the drive circuit. A gate drive design example based on gate charge requirement is presented in chapter 7.1.2. The switching transients can be predicted for an inductive load, when the load is the parallel inductor and diode, with no stray unclamped inductance, as shown in figure 4.13. It is assumed that a steady load current IL flows. The various turn-on and turn-off periods shown in figure 4.15 are related to the sequential charging periods shown in figure 4.14. Any gate circuit inductance is neglected.

LL

Figure 4.13. MOSFET basic switching circuit used to demonstrate current switching characteristics.


112

1 – MOSFET turn-on Period I - turn-on delay, td on The gate voltage rises exponentially to the gate threshold voltage VTH according to equation (4.17), that is - t / Cin Rg Vgs (t ) = Vgg [1 - e ] (V) (4.17)

where Cin, the gate input capacitance is approximated by Cgd + Cgs, or Ciss. The drain voltage remains unchanged, that is, it supports the supply voltage Vdd and virtually no MOSFET drain current flows. The turn-on delay time is given by -1

 V  td on = Cin Rg An  1 - TH  (s) (4.18)  Vgg   Equations (4.17) and (4.18) can be modified to account for a negative initial gate voltage (as presented in Appendix 4.1), a condition which increases the turn-on delay time, but increases input noise immunity. QT

Vgg

Ig t Id

IL Vdd

Vds

t

Figure 4.14. Typical relationships between gate charge, voltage, and current and magnitude of drain current and voltage being switched.

Period II - current rise, tri

Drain current commences to flow in proportion to the gate voltage as indicated by the transconductance characteristics in figure 3.12a. The gate voltage continues to rise according to equation (4.17). The drain voltage is clamped to the rail voltage Vdd and the drain current rises exponentially to the load current level IL, according to - t / Rg Cin I d (t ) = g fs (Vgg − VTH ) [1 - e ] (A) (4.19) The current rise time tri can be found by equating Id = IL in equation (4.19).  g fs V gg −VTH   t ri = R g C in ln   g fs V gg −VTH − I L   

(

(

)

)

(4.20)

Period III - voltage fall, tfv When the drain current reaches the load current level, the drain voltage will fall from Vdd to the low onstate voltage. This decreasing drain voltage produces a feedback current via Cgd to the gate, which must

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113

be provided by the gate drive. This feedback mechanism is called the Miller effect and the effective gate input capacitance increases to Cin = Ciss + (1 - Av)Cgd where Av = ∆Vds /∆Vgs. For a constant load current, from figure 3.12a, the gate voltage remains constant at Vgs = VTH + I L / g fs

(V)

(4.21)

as shown in figure 4.15b. Since the gate voltage is constant, the Miller capacitance Cgd is charged by the constant gate current V - Vgs V - (VTH + I L / g fs ) I g = gg (A) = gg (4.22) Rg Rg and the rate of change of drain voltage will be given by dVgd dVds I = = g dt dt Cgd

(V/s)

(4.23)

that is Vds (t ) = Vdd -

Ig Cgd

t

(V)

(4.24)

The drain voltage decreases linearly in time and the voltage fall time is decreased by increasing the gate current. Assuming a low on-state voltage, the voltage fall time tfv is given by t fv = Vdd Cgd / I g = Vdd Cgd Rg / (Vgg − VTH ) (s) (4.25) Period IV

Once the drain voltage reaches the low on-state voltage, the MOSFET is fully on and the gate voltage increases exponentially towards Vgg.

Figure 4.15. Distinct switching periods of the MOSFET with an inductive load at: (a) (b) (c) (d) comprising turn-on; (e) (f) (g) (h) forming turn-off.


114

2 – MOSFET turn-off Period V - turn-off delay, td off The MOSFET is fully on, conducting the load current IL, and the gate is charged to Vgg. The gate voltage

falls exponentially from Vgg to VTH + IL/ gfs according to -t / R C Vgs (t ) = Vgg e g in

(4.26)

(V)

in a time given by td off = Rg Cin An

Vgg VTH + I L / g fs

(4.27)

(s)

This delay time can be decreased if a negative off-state gate bias is used. The drain conditions are unchanged. Period VI - voltage rise, trv

The drain voltage rises while the drain current is fixed to the load current level, IL. Accordingly the gate voltage remains constant and the gate current is given by V + I L / g fs I g = TH (A) (4.28) Rg This current discharges the Miller capacitance according to I dVds dVdg = = g dt dt C gd

Vds (t ) =

Thus

Ig Cgd

t

where the low on-state voltage has been neglected. The voltage rise time trv is given by C V trv = gd dd Ig

(V/s)

(4.29)

(V)

(4.30)

(4.31)

(s)

and is decreased by increasing the gate reverse current magnitude. The drain voltage rises linearly to the dc supply Vdd. Period VII - current fall, tfi

When the drain voltage reaches the supply rail, the load current in the MOSFET begins to decrease, with load current being diverted to the diode Df. The gate voltage decreases exponentially according to -t / R C Vgs (t ) = (VTH + I L / g fs ) e g in (V) (4.32) and is mirrored by the drain current -t / R C I d (t ) = ( I L + g fsVTH ) e g in - g fsVTH

(A)

(4.33)

The current fall time tfi is given by Id = 0 in equation (4.33) or when the gate-source voltage reaches the threshold voltage, that is, from equation (4.32)  IL  t fi = Rg Cin An  1 + (s) (4.34)   g fs VTH   Period VIII – off-state The MOSFET drain is cut-off and the gate voltage decays exponentially to zero volts according to -t / R C Vgs (t ) = VTH e (V) (4.35) g in

Based on the total gate charge QT delivered by the gate source Vgg, shown in figure 4.14, the power dissipated in the MOSFET internal gate resistance, hence contributing to device losses, is given by RG int PG ( Rint ) = Vgg QT f s (W) (4.36) RG int + RGext

4.5

The insulated gate bipolar transistor

4.5.1

IGBT switching

The IGBT gate charge characteristics for switching and the switching waveforms are similar to those of the MOSFET, shown in figures 4.14 and 4.15 respectively, whilst the I-V on and off state characteristics

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are similar to the BJT. The collector switching characteristics depend on the injection efficiency of the collector p+ emitting junction. The higher the injection efficiency, the higher the pnp transistor section gain and the lower the on-state voltage. The poorer the injection efficiency, the more the characteristics resemble a MOSFET. The turn-on waveforms and mechanisms are essentially those for the MOSFET shown in figure 4.15. Figure 4.16 shows IGBT turn-off which has components due to MOSFET and BJT action. As with the MOSFET, distinct turn-off stages exist when switching an inductive load. Period V - turn-off delay, td off

The gate voltage falls to a level determined by the gate threshold, VTH, the forward transconductance, gfs and the MOSFET section current level. Period VI - voltage rise, trv

As the collector voltage rises the collector current remains constant, hence the gate voltage remains constant while charging the Miller capacitance. For a high gain pnp section the voltage rise time is virtually independent of gate resistance, while for an IGBT closely resembling a MOSFET the voltage rise is gate current magnitude dependent.

Period VII - current fall, tfi The current falls in two stages, the first, phase VII, due to MOSFET action, as are the previous two phases (periods V and VI). As with the conventional MOSFET the current falls rapidly as the MOSFET section current, shown in figure 4.16b reduces to zero.

V

VI

VII

VIII

Figure 4.16. IGBT: (a) turn-off waveforms and (b) equivalent circuit during turnoff.

Period VIII – current tail time With the gate voltage at the threshold level, the pnp transistor section turns off in a Vceo mode, phase VIII. A relatively low-magnitude, lengthy current tail results which is dependent on the pnp transistor section minority carrier lifetime in the n base and the injection efficiency of the p+ collector region.

The switching frequency and current rating of an IGBT are both limited by the minimum of the package dissipation limit (as with any other semiconductor device) and a factor solely dependant on the switching times at turn-on and turn-off. As the switching frequency increases, the current rating decreases. The MOSFET upper frequency is restricted solely by losses, that is, temperature.


4.5.2

116

IGBT short circuit operation

Under certain electrical conditions the IGBT may be subjected to short circuits, and safely turned off with out damage. Two different short circuit conditions are characterised: I. II.

IGBT turn-on into a pre-existing load short circuit Subsequent to IGBT turn-on, a short circuit load

condition occurs during the on-state period I. Pre-existing short circuit at turn-on The collector electrical characteristics are determined by the gate drive parameters and conditions. As the collector voltage falls, the collector current di/dt is determined by the stray inductance, characterised at less than 25µH. In this fault mode the IGBT is characterised for up to ten times the rated current, provided the IGBT is turned off within 10us, but at a slower rate than normal. II. Short circuit arising during the normal on-period When a load short circuit occurs during the IGBT on period, the collector current rises rapidly and is determined by the supply voltage Vs and stray inductance Ls according to dirise /dt = Vs /Ls. The collector voltage de-saturates and as the collector voltage rise towards the supply Vs the resultant dv/dt produces a Miller capacitance charging current, which flows into the gate circuit. Depending on the gate drive impedance, the gate voltage rises, which adversely allows higher collector current. When turn-off is initiated, by reducing the gate voltage to below the threshold level, the resultant collector current fall produces a high voltage across the stray inductance, VLs = Ls difall /dt, which adds to the collector voltage which is already near the supply rail Vs. Because of this over voltage, this mode of short circuit turn-off is more severe than turning off from a pre-existing short circuit. The maximum allowable short circuit current at turn-off is dependant on the gate voltage and reduces from ten times rated current at a gate voltage of 18V down to five times rated current at 12V. The short circuit must be commutated within 10us at a slower than normal rate so as to ensure the over voltage due to stray inductance remains within rated voltage limits. Repetitive short circuits are restricted to a frequency of less than one Hertz and can only accumulate to 1000 before device deterioration accelerates; both mechanical bonding and electrical. Stress during the fault period can be reduced if the gate voltage is clamped so that it cannot rise during the Miller capacitance charge period. A Zener diode (plus a reverse series diode if reverse gate bias is used) across the gate to emitter provides low inductance gate voltage clamping, but the Zener standby to clamping voltage ratio of 1:1.4 limits clamping effectiveness. The preferred method is to clamp the gate to the gate supply voltage by a Schottky diode between the gate (diode anode) and gate positive supply (diode cathode). Judicious gate supply ceramic capacitance decoupling will minimise loop inductance which otherwise would deteriorate clamping effectiveness. A difficulty arises when attempting to utilise the 10µs short circuit capabilities of the IGBT. To improve device robustness, short circuit turn-off is staged, or slowed down. It is prudent to utilise the over current capability of the IGBT in order to reduce nuisance tripping or to briefly ignore capacitor charging which are not true faults. A difficulty arises when a demand pulse is significantly less than 10µs. The gate drive must be able to cater for sub 10µs pulses with normal turn-off yet differentiate 10µs delayed slow turn-off when a short circuit fault is serviced. 4.6

The thyristor

Most of the thyristor ratings and characteristics to be considered are not specific to only the siliconcontrolled rectifier, although the dynamic characteristics of the gate turn-off thyristor are considered separately. 4.6.1

SCR ratings

The fundamental four layer, three junction thyristor structures and their basic electrical properties were considered in chapter 3.3. 4.6.1i - SCR anode ratings Thyristors for low-frequency application, such as in 50-60 Hz and 300-360Hz ac supply systems, are termed converter-grade thyristors. When a higher switching frequency is required, so-called gate commutated devices like the GTO and GCT are applicable. Such devices sacrifice voltage and current ratings for improved self-commutating capability. The repetitive peak thyristor voltage rating is that voltage which the device will safely withstand in both the forward off-state VDRM, and reverse direction VRRM, without breakdown. The voltage rating is primarily related to reverse leakage or forward blocking current IRRM and IDRM respectively, at a given

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junction temperature, usually 125°C. Since forward blocking current doubles with every 10K rise in junction temperature Tj, power dissipation increases rapidly with Tj, which may lead to regenerative thermal runaway, turning the device on in the forward direction. Current related maximum ratings reflecting application requirements include • peak one cycle surge on-state current ITSM • repetitive and non-repetitive di/dt • I2t for fusing. The maximum junction temperature can be exceeded during non-recurrent over-current cycles. The maximum non-repetitive on-state surge current is generally quoted for one 10 millisecond sinusoidal period at Tlj . Any non-recurrent rating can be tolerated only a limited number of times before failure results. Such non-recurrent ratings are usually specified to allow fuse and circuit breaker short-circuit protection. The I2t rating for a 10ms period is another parameter used for fuse protection, where I is non-repetitive rms current. When used in 60Hz systems, the ratings are specifies with respect to 8.33ms If the device is turned on into a fault, the initial current-time relationship, di/dt, during turn-on must be within the device’s switching capability. In cases where the initial di/dt is rapid compared with the active plasma area-spreading velocity of 50 µm/µs, local hot spot heating will occur because of the high current densities in those areas that have started to conduct. A repetitive di/dt rating is also given for normal operating conditions, which will not lead to device deterioration. This repetitive di/dt rating will be specified for a given initial blocking voltage and peak forward current. Certain gate drive conditions are specified and the device must survive for 1000 hours.

IG T , V G T

IG , V G

(a)

(b)

Figure 4.17. Thyristor gate ratings illustrating: (a) the preferred operating region and (b) minimum gate requirements and their temperature dependence.

4.6.1ii - SCR gate ratings The gate ratings usually specified are • peak and mean gate power, PGM and PG • peak forward and reverse gate to cathode voltage, VGFM and VGRM • peak forward gate current, IFMG. These gate ratings are illustrated in figure 4.17. The peak gate power rating is obtained by using a low duty cycle pulse, with a mean power that does not exceed PG. The reverse gate voltage limit, VGRM, is specified by the avalanche voltage breakdown limit of the reverse-biased gate-to-cathode junction. Figure 4.17 not only shows limit ratings, it also indicates the preferred gate voltage and current, and the minimum requirements which will ensure turn-on at different junction temperatures. 4.6.2

Static characteristics

The static anode voltage-current characteristics of a thyristor are similar to those of a diode. Gate commutated thyristors tend to have higher on-state voltages for a given current than comparable converter-grade devices. This higher on-state voltage is one of the trade-offs in improving the switching performance.


118

4.6.2i - SCR gate trigger requirements Below a certain gate voltage, called the gate non-trigger voltage VGD, the manufacturer guarantees that no device will trigger. This voltage level is shown in figure 4.17b. The hatched insert area in figure 4.17a (figure 4.17b) contains all the possible minimum trigger values (IGT, VGT) for different temperatures, that will result in turn-on. The gate requirements (IGT, VGT) have a negative temperature coefficient as indicated in figure 4.17b. To ensure reliable turn-on of all devices, independent of temperature, the trigger circuit must provide a dc signal (IG, VG) outside the shaded area. This area outside the uncertainty area, but within the rating bounds, is termed the preferred gate drive area. An increase in anode supporting voltage tends to decrease the gate drive requirements. But if the gate signal is a pulse of less than about 100µs, the turn-on (IG, VG) requirement is increased as the pulse duration is decreased. The gate current increase is more significant than the voltage requirement increase. Typically, for a pulse reduced from 100µs to 1µs, the voltage to current increase above the original requirement is 2:10 respectively. This increased drive requirement with reduced pulse time is accounted for by the fact that some of the initial gate p-region charge recombines. When the free charge reaches a certain level the device triggers. Thus, to get the required charge into the gate in a relatively short time compared with the recombination time requires higher current, and hence higher voltage, than for dc triggering. 4.6.2ii – SCR holding and latching currents If the on-state anode current drops below a minimum level, designated as the holding current IH, the thyristor reverts to the forward blocking state. This occurs because the loop gain of the equivalent circuit pnp-npn transistors falls below unity and the regenerative hold-on action ceases. The holding current has a negative temperature coefficient; that is, as the junction temperature falls, the device holding current requirement increases. The holding current is typically about 2% of the rated anode current, and increases as switching performance is improved (and on-state voltage increases). A somewhat higher value of anode on-state current than the holding current is required for the thyristor to latch on initially (IL>IH). If this higher value of anode latching current IL is not reached, the thyristor will revert to the blocking state as soon as the gate trigger signal is removed. After latch-on, however, the anode current may be reduced to the holding current level, without turn-off occurring. These two static current properties are shown in the I-V characteristics in figure 3.22. With inductive anode circuits, it is important to ensure that the anode current has risen to the latching current level before the gate turn-on signal is removed. Continuous gate drive avoids this inductive load problem but at the expense of increased thyristor gate power losses. 4.6.3


The main thyristor dynamic characteristics are the turn-on and turn-off switching intervals, which are associated with the anode and gate circuit interaction. 4.6.3i – SCR anode at turn-on Turn-on comprises a delay time td and a voltage fall time tfv, such that the turn-on time is ton = td + tfv. The turn-on delay time for a given thyristor decreases as the supporting anode voltage at turn-on is increased. The delay time is also decreased by increased gate current magnitude. The gate p-region width dominates the high gate current delay time characteristics while carrier recombination is the dominant factor at low gate current levels. The anode voltage fall time is the time interval between the 90 per cent and 10 per cent anode voltage levels. The associated anode current rise characteristics are load dependent and the recurrent di/dt limit must not be exceeded. As introduced in chapter 3.3.1, a thyristor can be brought into conduction by means of an anode impressed dv/dt, called static dv/dt capability, even though no gate external current is injected. The anode voltage ramp produces a displacement current according to i = dQ/dt as the central junction scl charges and its width increases. The resultant displacement current flows across the cathode and anode junctions causing minority carrier emission and, if sufficient in magnitude, turn-on occurs. Static dv/dt capability is an inverse function of device junction temperature and is usually measured at Tlj . 4.6.3ii – SCR anode at turn-off As analysed in chapter 3.3.1, once a thyristor is turned on, it remains latched-on provided • the holding current remains exceeded • it is forward biased. If the supply voltage is ac, a thyristor will turn off after the supply voltage has reversed and the anode current attempts to reverse. The thyristor is thus reverse-biased and this turn-off process is called line commutation or natural commutation, as defined in chapter 6.3.4.

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If the supply voltage is dc and the load is a series L-C resonant circuit, the anode current falls to zero when the capacitor is charged. The load current falls below the holding current level and the SCR turns off. This is termed load commutation, which is a form of load resonant switching as defined in 6.3.3. In thyristor applications involving dc supplies and resistive/inductive loads, a thyristor once on will remain on. Neither the supply nor the load is capable of reducing the anode current to below the holding current level, or producing a reverse bias across the thyristor. Such a thyristor can be turned off only if the anode current is interrupted or forced below the holding current level. External circuitry, called a commutation circuit, is employed to accomplish turn-off, by reverse-biasing the thyristor and reducing the anode current to near zero. This external turn-off approach, now obsolete, is called thyristor forced commutation. A topological variation of the forced commutated circuitry method is called resonant link commutation. The gate turn-off thyristor eliminates the need for this external commutation circuitry since the GTO can be commutated from its gate using reverse gate current. 4.7

The gate turn-off thyristor

In essence, the gate turn-off (GTO) thyristor has similar ratings and characteristics to those of the conventional converter grade SCR, except those pertaining to turn-off. Both GTO turn-on and turn-off are initiated from the gate, hence the power-handling capabilities of the GTO gate are much higher than those of SCR devices. 4.7.1

Turn-on characteristics

Because of the higher p1 gate region concentration, the GTO thyristor holding current level and gate trigger requirements are somewhat larger than those of the conventional SCR. Higher anode on-state voltages also result. At low anode current levels, a steep trailing edge at the end of the gate on-pulse may cause the GTO to unlatch even though the anode current is above the dc holding current level. For this reason, together with the fact that the cathode comprises many interdigitated islands, a continuous, dc gate on-drive is preferred. Continuous gate current prevents any cathode islands from falling out of conduction should the anode current be reduced to near the holding current level. If cathode islands should turn off prematurely and the anode current subsequently rise, the GTO no longer has its full current handling capability and it could overheat specific islands, leading to device destruction. With very high voltage GTO’s, turn-on is like that of a high voltage npn transistor which has low gain, limiting the initial rate of rise of anode current, until the regenerative latching action has occurred. Hence an initial, high current of up to six times the steady-state gate requirement is effective for a few microseconds. 4.7.2

Turn-off characteristics

Before commencing turn-off, a minimum on-time of tens of microseconds must be observed so that the principal current may distribute uniformly between the cathode islands. This is to ensure that all cells conduct, such that turn-off occurs uniformly in all cells, rather than being confined to a few cells, where the current to be commutated may be higher than individual cells can survive. The anode current of a GTO in the on-state is normally turned off via a low voltage source, negative gate current, IRG. The negative gate current IGQ, which is just sufficient to turn-off the on-state current IT is defined as the minimum turn-off current. Turn-off amplification (equation 3.21) is defined as βQ = I TGQ / I GQ (4.37) where βQ is related to the internal construction of the GTO thyristor. Figure 4.18 illustrates typical gate and anode turn-off waveforms for the GTO. Application of reverse gate current causes the anode current to reduce after a delay period ts. This delay time is decreased as the reverse gate current diGQ/dt increases; that is, as IRGM increases and ts decreases. Increased anode on-state current or junction temperature increases the delay time and turn-off time. The reverse gate current prevents cathode injection and the anode current rapidly falls to the storage current level, Itail. The subsequently slow current fall time, ttail, is due to charges stored in regions other than the gate and cathode that are not influenced by the reverse gate current and must decrease as a result of natural recombination, producing a decaying principal anode current. Anode n+ shorts are used to accelerate the recombination process, reducing both storage current and storage time, but at the expense of reverse blocking ability and on-state voltage. Avalanche of the cathode junction (typically 20V) is acceptable during turn-off for a specified time. Reverse gate bias should be maintained in the off-state in order to prevent any cathode injection.


VA, IA

120

PRQ

PFQ >IH

VA(t) IA(t)

T

toff > toff min

ton > ton min

Vbr

Figure 4.18. Schematic representation of GTO thyristor turn-off waveforms.

After turn-off some dispersed charges still exist. A minimum off-time of the order of tens of microseconds is needed for these charges to recombine naturally. This time increases with increased blocking voltage rating. If a turn-on were to be initiated before this recombination is complete, the area of un-combined charge will turn-on first, resulting in a high di/dt in a confined area, which may cause a hot spot and possibly destruction. During the storage and fall time, power loss PRQ occurs as illustrated in figure 4.18 and is given by T

1 VA (t ) I A (t )dt (4.38) (W) T 0 where T = t gq + ttail . The cathode junction loss, due to the gate turn-off reverse current can also be incorporated, which may become significant as the turn-off gain reduces to unity. PRQ =

∫

The actual anode voltage turn-off waveform is dependent on the load circuit. Care is needed in preventing excessive loss at turn-off, which can lead to device destruction. One technique of minimising turn-off loss is to increase the rate at which the reverse gate current is applied. Unfortunately, in reducing the turn-off time, the turn-off current gain βQ is decreased, from typically 25 to 3. The anode turn-off voltage VA(t) in figure 4.18 assumes a capacitive turn-off snubber is used. Such a capacitive switching aid circuit is not essential with the GCT, which uses unity reverse gain at turn-off, as considered in chapter 3.3.5.

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4.8

Appendix: Effects on MOSFET switching of negative gate drive

The effects of negative gate voltage on MOSFET turn-on and turn-off delays, which were analysed in section 4.4.2, are given by Vgs (t ) = (Vgg - Vgg - ) [1 - e td on = Rg Cin An

] + Vgg -

Vgg − Vgg − Vgg − VTH

Vgs (t ) = (Vgg - Vgg − ) e td off = Rg Cin An

- t / Cin Rg

- t / Rg Cin

+ Vgg −

Vgg − Vgg − VTH + I L / g fs − Vgg −

(V)

(4.39)

(s)

(4.40)

(V)

(4.41)

(s)

(4.42)

Reading list See chapter 3 reading list Van Zeghbroeck, B., Principles of Semiconductor Devices, //ece-www.colorado.edu/~bart/book, 2004.

Power device manufacturers http://www.infineon.com/eupec/toc.htm http://www.fujielectric.co.jp/eng/fdt/scd/index.html http://www.irf.com/indexsw.html http://www.onsemi.com/ http://www.pwrx.com/ http://www.st.com/stonline/products/families/transistors/transistors.htm http://www.ixys.com/ http://www.microsemi.com/ http://www.semikron.com/ http://www.fairchildsemi.com/index2.html http://www.dynexsemi.com/ http://www.westcode.com/products.html http://www.infineon.com/cgi-bin/ifx/portal/ep/home.do?tabId=1 http://www.abb.com/product/us/9AAC910029.aspx?country=00 http://www.mitsubishichips.com/Global/products/power/index.html http://www.semicon.toshiba.co.jp/eng/ http://www.nxp.com/products/power_management/index.html


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5 Cooling of Power Switching Semiconductor Devices

Semiconductor power losses are dissipated in the form of heat, which must be transferred away from the switching junction, if efficient switching is to be maintained. The reliability and life expectancy of any power semiconductor are directly related to the maximum device junction temperature experienced. It is therefore essential that the thermal design determines accurately the maximum junction temperature from the device power dissipation. Every 10°C junction temperature decrease doubles devices lifetime. Heat can be transferred by any of, or a combination of, three mechanisms, viz., • Convection - heat transferred to a moving fluid which takes the heat away • Conduction - heat flows through thermal conducting material, away from the heat source • Radiation - heat flow by long-wave electromagnetic radiation, e.g. infra red. Electromagnetic thermal radiation is given by Pd = σ ε A (T14 − T24 ) where Pd is the rate of heat transfer (that is, the power dissipated), W σ is the Stefen-Boltzmann constant (5.67×10-8 W/m2K4) ε is a surface property, termed emissivity, see table 5.4 A is the area involved in the heat transfer, m2 T is absolute temperature, K

(5.1)

The one dimensional model for general molecular (non-radiation) heat transfer is given by δT δT + γ AA (W) (5.2) Pd = −λ A δA δt where δT =T2 -T1 or ∆T, is the temperature difference between regions of heat transfer λ is thermal conductivity, see Table 5.2 γ is density of the heatsink material c is specific heat capacity, ∆T = W/mc (W is energy, m is mass) A is distance (thickness). Equation (5.2) shows that the thermal power generated Pd is balanced by the stored thermal power (first term on the right hand side) and the thermally dissipated power (second term on the right hand side). Assuming steady-state heat dissipation conditions, then δ T / δ t = 0 in equation (5.2). Conduction through a solid is therefore given by Pd =

BWW

λ A

A ∆T

(W)

(5.3)


124

Convection heat transfer through fluid or air, under steady-state conditions, is given by Newton’s law of cooling, that is Pd = h A ∆T (W) (5.4) The heat transfer coefficient h (= λ / A ) depends on the heat transfer mechanism used and various factors involved in that particular mechanism. For natural vertical convection in free air, the losses for a plane surface may be approximated by the following empirical formula ∆T 5 (W) A where ℓ is the vertical height in the direction of the air flow. Pd = 1.35 A 4

(5.5)

Two cases occur for forced air flow, and the empirical losses are •

for laminar flow Pd = h A ∆T = 3.9

•

v A ∆T A

(W)

(5.6)

(W)

(5.7)

for turbulent flow

v4 A ∆T A where v is the velocity of the vertical air flow. Pd = h A ∆T = 6.0

5

It is generally more convenient to work in terms of thermal resistance which is defined as the ratio of temperature change to power. From equation (5.4), thermal resistance Rθ is ∆T 1 A (5.8) Rθ = = = (K/W) Pd hA λ A The average power dissipation Pd and maximum junction temperature Tl j , in conjunction with the ambient temperature Ta, determine the necessary heat sink, according to equation (5.8) Tl − Ta (W) (5.9) Pd = j Rθ j-a where Rθ j-a is the total thermal resistance from the junction to the ambient air. The device user is restricted by the thermal properties from the junction to the case for a particular package, material, and header mount according to Tl − Tc (W) (5.10) Pd = j Rθ j-c where Tc is the case temperature, K and Rθ j-c is the package junction-to-case thermal resistance, K/W. An analogy between the thermal equations and Ohm’s law and Kirchhoff’s laws is often made to form models of heat flow. The temperature difference ∆T could be thought of as a voltage drop ∆V, thermal resistance Rθ corresponds to electrical resistance R, and power dissipation Pd is analogous to electrical current I. [viz., ∆T = Pd Rθ ≡ ∆V = IR]. See Table 5.8. 5.1

Thermal resistances

A general thermal dissipation model, or thermal equivalent circuit for a mounted semiconductor is shown in figure 5.1. The total thermal resistance from the virtual junction to the open air (ambient), Rθ j-a, is R × ( Rθ c-s + Rθ c-a ) (5.11) (K/W) Rθ j-a = Rθ j-c + θ c-a Rθ c-a + Rθ c-s + Rθ s-a In applications where the average power dissipation is of the order of a watt or so, power semiconductors can be mounted with little or no heat sinking, whence Rθ j-a = Rθ j-c + Rθ c-a (K/W) (5.12) Generally, when employing heat sinking, Rθ c-a is large compared with the other model components and equation (5.11) can be simplified to Rθ j-a = Rθ j-c + Rθ c-s + Rθ s-a (K/W) (5.13)

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virtual junction

Tjunction

Rθ c −a

package case

Tcase

Rθj −c

heatsink

Theatsink

ambient

Tambient

Rθ c−hs

Rθ hs−a

Figure 5.1. Semiconductor thermal dissipation equivalent circuit.

5.1.1

Contact thermal resistance, Rθ c-s

The case-to-heat-sink thermal resistance Rθ c-s depends on the package type, interface flatness, mounting pressure, and whether thermal-conducting grease and/or an insulating material is used. In general, increased mounting pressure decreases the interface thermal resistance, and no insulation with thermal grease results in minimum Rθ c-s. Common electrical insulators are mica, aluminium oxide, and beryllium oxide in descending order of thermal resistance, for a given thickness and area. Table 5.1 shows typical contact thermal resistance values for smaller power device packages, with various insulating and silicone grease conditions. Silicon based greases are best, for example Assmann V6515, spread at a thickness of 100µm to 150µm. Grease in excess of this will be squeezed out under clamping pressure. Initial grease thermal resistance decreases slightly after a few normal deep thermal cycles. 5.1.2

Heat-sink thermal resistance, Rθ s-a

The thermal resistance for a flat square plate heat sink may be approximated by 3.3 ¼ 650 Rθ s-a = Cf + Cf (K/W) A λA

(5.14)

Typical values of heatsink thermal conductance λ in W/K cm at 350 K, are shown in Table 5.2 and A is the thickness of the heat sink in mm A is the area of the heat sink in cm2 Cf is a correction factor for the position and surface emissivity of the heat-sink orientation according to Table 5.3. Table 5.1. Typical case-to-heat-sink thermal resistance value for various small packages

Package

TO-3

TO-66 TO-220 TO-247 SOT-227 ISOTOP

Insulating washer No insulating washer Teflon Mica (50 -100 µm) No insulating washer Mica (50 -100 µm) Mylar (50 -100 µm) No insulating washer Mica (50 -100 µm) No insulating washer Mica (50 -100 µm) No insulating washer Mica (50 -100 µm)

Rθc-s (K / W) Silicone grease with without 0.3 0.10 1.25-1.45 0.7-0.8 1.2-1.5 0.5-0.7 0.15-0.2 0.6-0.8 0.6-0.8 0.3-0.5 2.0-2.5 0.1-0.2 0.5-0.7 0.1-0.2 0.5-0.7

0.4-0.5 1.5-2.0 1.2-1.4 1.5-2.0 4.0-6.0 0.4-1.0 1.2-1.5 0.3-0.4 1.0-1.2


Table 5.2. Thermal conductivity Material

diamond aluminium copper brass steel mica beryllium oxide ceramic AℓN A1203 solder (non-lead) silicon grease still air

λ (W/K cm)

2 2.08 3.85 1.1 0.46 0.006 2.10 1.4 0.27 0.44 0.01 0.0004

Table 5.3.

126

Heatsink correction factor

Surface position Cf

Shiny

Blackened

vertical horizontal

0.85 1.0

0.43 0.50

Table 5.4.

Emissivity values

Material

ε

Matt surface Polished aluminium A1203

0.95 0.04 0.15

The correction factor Cf illustrates the fact that black surfaces are better heat radiators and that warm air rises, creating a ′chimney′ effect. Equation (5.14) is valid for one power-dissipating device, in the centre of the sink, at a static ambient temperature up to about 45°C, without other radiators in the near vicinity. In order to decrease thermal resistance, inferred by equation (5.8), finned-type heat sinks are employed which increase sink surface area. Figure 5.2 illustrates graphs of thermal performance against length for a typical aluminium finned heat sink. This figure shows that Rθ s-a decreases with increased sink length. Minimal reduction results from excessively increasing length as shown in figure 5.2b. The maximum distance between fins depends on the depth and width of the fins, with deep finned heatsinks needing more space between adjacent fins than a shallow design unless fan cooling is used. As shown in table 5.5, the minimum spacing is determined by fin depth and airflow. The deeper the fins the more space needed between them since a portion of the heat is radiated to adjacent fins, which helps to stabilise the temperature, but does little to dispose of the heat (in figure 5.2a, about 25% of the heat is dissipated by radiation). Table 5.5.

Fin spacing versus flow and fin length Fin length (mm) Airflow (m/s) natural convection 1.0 2.5 5.0

75 150 225 300 Fin Spacing (mm) 6.5 7.5 10 13 4.0 5.0 6.0 7.0 2.5 3.3 4.0 5.0 2.0 2.5 3.0 3.5

As the flow height is increased, the air at the top of a vertical heatsink is hotter than that entering at the bottom. If the fin depth is increased, there is more mutual radiation between fins, and as the spacing is reduced, mutual radiation increases further. Airflow is also restricted because of the smaller physical area for air to pass, since more of the available space is occupied by the heatsink itself. The typical performance of a heatsink is linearly proportional to the width of the sink in the direction perpendicular to the flow and proportional to the square root of the fin length in the direction of the air flow. Therefore it is better to increase the width rather than the length, provided the width is not already excessive compared to the length. The effect of radiation heat transfer (hence emissivity) is important in natural convection, as it can be responsible for up to 25% of the total heat dissipation. Unless the heatsink is facing a hotter surface nearby, it is imperative to have the heat sink surfaces thinly painted or correctly anodised to enhance radiation. The emissivity coefficient, ε, indicates the radiation of heat from a body according the Stefan-Boltzmann Law, compared with the heat radiation from an ideal black body where the emissivity coefficient is ε = 1. Regardless of the composition of the emitting surface, the microscopic (and macroscopic) roughness of the surface causes differences in emissivity because a rougher surface has a larger emitting area. Generally, the emissivity of most opaque emitting surfaces increases as wavelength becomes shorter. The emissivity coefficient, ε, for some common surface qualities of aluminium and copper can be found in the table 5.6.

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Table 5.6. Emissivity coefficient of various Surface Treatments at 100oC Emissivity

Surface

ε

Polished aluminium

0.05

Polished copper

0.07

Rolled sheet steel

0.66

Oxidised copper

0.70

Black anodised aluminium

0.70 - 0.90

Black air-drying enamel

0.85 - 0.91

Dark varnish

0.89 - 0.93

Black oil (organic) paint

0.92 - 0.96

The low emissivity coefficients of untreated, polished aluminium and copper means they have surface finishes that limit the radiated heat from a body. Two thin coats of flat white Krylon #1502 (or equivalent) which has an emissivity of 0.96, should be used on all untreated (emissivity-wise) areas. Unless otherwise stated, the heat sink is assumed anodised black (emissivity of up to 0.97) and vertically mounted with negligible thermal resistance from case to sink. In accordance with the data in table 5.3, a general derating of 10 to 15 per cent for a bright surface and 15 to 20 per cent in the case of a horizontal mounting position, are usually adopted. Figure 5.2b also shows the improvement effects on dissipation due to the high thermal conductivity (heat spreader effect) of oxidised copper.

Al Cu

Cu

Cu

Al

Al

Figure 5.2. Heat-sink typical data (for aluminium and copper): (a) cross-section view; (b) heat-sink length versus thermal resistance for a matt black surface finish; (c) temperature rise versus dissipation for an anodised finish and different lengths; and (d) as for (c) but with a matt black surface finish.

Thermal resistance increases with altitude, h, above sea level, as air density decreases, according to Rθ ( h ) = RO metres / (1 − 5 × 10 −5 h ) . For example: a 1°C/W heatsink degrades to 1.11°C/W at an altitude of 2,000 metres, or 1.18° C/W at 3,000 metres. When heatsinks (dissipating a total power of PDtotal) are vertically stack to share the same vertical natural convention air flow, the air temperature of the flow at the upper heatsink, after passing n-1 heatsinks, is

T air = T amb +

n −1 c v n

PD total

(5.15)


128

The chimney effect results in an air flow velocity v, which increases further up the heatsink stack. This and the air density increase results in the upper heatsink being the coolest, even though the passing air is the warmest! The effective sink thermal resistance can be significantly reduced by forced air cooling, as indicated in figure 5.3a and by equations (5.6) and (5.7). If the air flow is • laminar, heat loss is proportional to the square root of air velocity, equation (5.6); • turbulent, heat loss is proportional to velocity to the power of 0.8, equation (5.7). Liquid cooling can further reduce effective thermal resistance to as low as 0.01K/W and may provide a much more compact clamp heat-sink arrangement, as shown in figure 5.3b. Both oil and water (which has 4 times the thermal capacity and 770 times the density of air) are used as the coolant and the heatsink arrangement can either be immersed in the fluid, or the fluid is pumped through a hollow heat sink. The heat can then be dissipated remotely. Water has the advantage of low viscosity, so can be pumped faster than mineral oil. While oil may be inflammable, water corrodes thus requiring the use of de-ionised water with an oxide inhibitor, like antifreeze (ethylene glycol). Oil emersion has the added advantage of offering possibilities of increasing the breakdown and corona voltage levels, particularly with devices voltage rated and operated at above a few kilovolts. H2O

Aℓ

Aℓ

Cu

Si

H2O (a)

H2O (b)

Figure 5.3. Improved cooling with (a) forced air cooled heat-sink - relative thermal resistance improvement with surface air flow and (b) compact indirect water cooling.

Immersion cooling involves more than just the selection of a direct immersion liquid on the basis of heat transfer characteristics alone. Chemical compatibility of the coolant with the mounting and packaging materials exposed to the liquid are the primary consideration. There may be several coolants which can provide adequate cooling, but a limited few will be chemically compatible. Water is an example of a liquid which has desirable heat transfer characteristics, high thermal conductivity for example, but is generally unsuitable for direct immersion cooling because of other chemical characteristics, such dielectric constant. The fluorocarbon liquids listed in table 5.5 are generally considered to be the most suitable liquids for direct immersion cooling, despite their poorer thermo-physical properties. As shown in Table 5.7, the thermal conductivity, specific heat, and heat of vaporization of fluorocarbon coolants are lower than water. These coolants are clear, colourless per-fluorinated liquids with a relatively high density and low viscosity. They also exhibit a high dielectric strength and a high volume resistivity. The liquid therefore serves both to cool and insulate the components. The boiling points for available ‘fluorinert’ liquids range from 30 to 253 °C. All of the high power and high voltage electronics can be immersed in the fluorinert. As a component heats up, the fluorinert in contact with it vaporizes and it is this liquid to vapour phase transition which effectively removes the excess heat from the components. The fluorinert vapour is cooled by a heat exchanger located in the area above the fluid. This cooling technique allows high power electronics to operate continuously and reliably in a small volume.

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Table 5.7. Comparison of thermo-physical properties of some fluorocarbon coolants and water PROPERTY

units

Boiling Point

FC-72

FC-77

H2O

56

97

100

kg/m

1.680

1.780

0.997

W.s/kg.K

1.088

1.172

4.179

W/m.K

0.0545

0.057

0.613

kg/m.s

4.50

4.50

8.55

W.s/kg

8.79

8.37

243.8

N/m

8.50

8.00

58.9

-1

1.60

1.40

0.20

1.72

1.75

78.0

@ 1 Atm, °C -3

3

Density ×10

-3

Specific Heat ×10

Thermal Conductivity 4

Dynamic Viscosity ×10

-4

Heat of Vaporization L ×10 3

Surface Tension ×10

3

Thermal Coefficient of Expansion ×10

K

Dielectric Constant

These liquids should not be confused with the ‘Freon’ coolants which are chlorofluorocarbons (CFCs). Although some of the ‘Freons’ exhibit similar cooling characteristics, concern over their environmental effect preclude their use. Heat pipes are efficient, reliable, passive, silent, high thermal conducting devices for extracting and remotely dissipating heat. A heat pipe, shown in figure 5.4, is a hollow metal or ceramic tube (for high voltage isolation), typically less than 1mm diameter and a few hundred cm long, closed at each end and containing a dielectric, non-electrical conducting transfer fluid (refrigerant such as methanol, water or Freon when insulation is required) under reduced pressure so as to reduce the fluid boiling point. Freon boils at 47°C at one atmosphere, is inert, non-toxic, and has an acceptable dielectric constant. The component to be cooled is mounted on the evaporator end (the hot end), where the heat boils and expands the liquid to the vapour phase. This vapour rises through the adiabatic tube section to the remote condenser end of the tube (the cold end), taking the heat within it. The vapour condenses back to the liquid phase, releasing its latent heat of vaporisation, and creating a pressure gradient which helps draw more vapour towards the condenser. The temperature difference between the ends may only be a couple of degrees. The remotely situated condenser end is connected to an external heatsink or a radiator type grill, for cooling. The condensed working fluid runs back to the evaporator end due to gravity, or along a wick due to capillary pressure action, depending on the physical application orientation design for the heat pump. The typical temperature operating range is within the bounds 55°C to over 200°C, depending on the coolant. cooling fins Tamb

evaporation Tj condensation

heat source

Figure 5.4. The heat pipe principle.

The heat power transfer capabilities of a heat pipe are related to its cross-sectional area A and length ℓ according to equation (5.3) A (W) (5.16) PD = k A while the temperature difference ∆T between the hot and cold ends is  1 1  (K) (5.17) ∆T = k ′PD  +   Ae Ac  where Ae and Ac are the effective evaporator and condenser surface areas.


5.2

130

Modes of power dissipation

For long, >1ms, high duty cycle pulses the peak junction temperature is nearly equal to the average junction temperature. Fortunately, in many applications a calculation of the average junction temperature is sufficient and the concept of thermal resistance is valid. Other applications, notably switches driving highly reactive loads, may create severe current-crowding conditions which render the traditional concepts of thermal design invalid. In these cases, transistor safe operating area or thyristor di/dt limits must be observed, as applicable. In yet other applications, heat cycling can cause power module faults, hence device failure, due to • thermal cycling – is associated with large base plate (case) temperature changes, ∆Tc • power cycling – is associated with large junction temperature changes, ∆Tj The die is connected to a low thermal impedance substrate, usually utilising copper in the form of so called direct copper bonding, as shown in figure 5.5a and the forced water cooling effectiveness is shown in figure 5.5c. Direct copper bonding Direct copper bonding DCB is a process in which copper (on each side) and a ceramic material, usually either aluminium oxide or aluminium nitride, are fused together at high temperature. By avoiding a thick copper base, the base is thinner and lighter, with lower thermal resistance and much better thermal cycling capabilities. The properties of DCB substrates are • High mechanical strength and stability • Good cohesion and corrosion resistance • High electrical insulation • Excellent thermal conductivity • Reliable thermal cycling stability • Matched thermal expansion coefficient to silicon and gallium arsenide • Good heat spreading • Processable, e.g. copper is etchable like a pcb • Environmentally friendly • High copper current density Thermal cycling Intermittent equipment operation, start-up, and shutdown in extreme temperature conditions may cause power module thermal stresses due to the different linear expansion temperature co-efficients of the materials associated with the soldered substrate mounting to the copper base plate in multi-chip large area packages (see table in Appendix 5.7). Large base plate (case) temperature changes in excess of 80K over a few minutes, stress the hard solder bonding between the copper base plate and the insulating substrate (usually AℓN or Aℓ203), as shown in figure 5.5a. This fatigue leads to eventual crack failure after a finite number of cycles N, approximated by k (5.18) N= A × ∆T 2 where A is the die area and ∆T is the thermal shock temperature change. The constant k depends on the package, type of hard soldering, etc. Large, multiple die IGBT modules suffer from thermal shock limitations and relatively low reliability, because of the sheer large number of die soldered to the substrate over a large area in the module. Figure 5.5b shows how the number of thermal cycles to fracture for DCB substrates varies with copper thickness, when cycled between -40°C to +110°C. For a case temperature change of ∆T = 80K, lifetime can be as low as 3,500 cycles and may only involve powering up and shutting down the associated equipment. Although Aℓ/SiC is far superior to copper from a differential thermal expansion perspective, its thermal conductivity is only a little better than that of aluminium. Floating silicon wafers in disc type packages suffer to a much lesser extent (an order) from the effects of differential thermal expansion when thermally cycled. Power cycling Rapid cycling of the chip junction temperature causes mechanical stress around the silicon chip to aluminium wire bond interface, due to their different linear expansion temperature co-efficients. Eventually a crack occurs on the silicon side of the interface, as indicated in figure 5.5a. Short rapid junction temperature changes, over tens of seconds, of ∆Tj =100K, can lead to failure within 2500 cycles. The number of cycles to failure increases by just over an order for every 10°C decrease in ∆Tj.

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power cycle crack

Aluminium wire

Si chip solder layer Cu foil

thermal cycle crack

insulation substrate with adhered copper foil both sides Cu foil solder layer Cu base plate

10

3

10

2

mK/W

10

(b)

(c)

typical substrate thermal resistance

number of thermal cycles until failure

(a) 4

10

1 0

0.2

0.4

0.6

0.8

copper thickness

1

60

50

40 Al202 substrate

30

Al3N4 substrate 0

1.2

1

2

3 water flow

mm

4

5

6

l/min

Figure 5.5. Direct copper bonding: (a) sectional view of power module substrate showing boundary regions where power cycle cracking and thermal cycle cracking, occur; (b) copper thickness affect on power failure; and (c) thermal resistance dependence on liquid cooling flow rate and substrate material.

In a related thermal application, where the power dissipated in the semiconductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average temperature, may be the limiting condition. Figure 5.6 shows by comparison such a condition, where the operating frequency, not the maximum power dissipated, is dominant in determining junction temperature. In this case thermal impedance Zθ j-c is used instead of thermal resistance Rθ j-c such that Zθ j-c = r(tp) Rθ j-c, where r(tp) is the normalising factor yielded from the normalised transient thermal impedance curves for the particular device. Appropriate values for the power pulse width tp and duty cycle factor δ must be used.

tp

t2 T2

T2

T1

T1

80ºC

T

Figure 5.6. Waveforms illustrating that peak junction temperature is a function of switching frequency: (a) lower switching frequency with 10 ms pulse and a 20 per cent duty cycle and (b) high frequency and 1 ms pulse with a duty cycle the same as in (a).


5.2.1

132

Steady-state response

Large cycle-by-cycle temperature fluctuations occur at low frequencies. As frequency increases, thermal inertia of the junction smoothes out instantaneous temperature fluctuations, as shown in figure 5.6b, and the junction responds more to average, rather than peak power dissipation. At frequencies above a kilohertz and duty cycles above 20 per cent, cycle-by-cycle temperature fluctuations usually become small, and the peak junction temperature rise approaches the average power dissipation multiplied by the steady-state junction-to-case thermal resistance, within a few per cent. Because of thermal inertia (long thermal time constant), the heat sink and package case respond only to average power dissipation, except at ultra low frequencies. The steady-state thermal conditions for the case and junction (equation (5.10)) are given by Tl − Tc Tc − Ta (W) (5.19) = Pd = j Rθ j −c Rθ c-s + Rθ s-a where Pd is the average power dissipation, which is the maximum power multiplied by the on-time duty cycle δ for rectangular power pulses. The difficulty in applying equation (5.19) often lies in determining the average power dissipation. 5.2.2

Pulse response

When a junction dissipates power associated with a single pulse, the junction temperature increases during the pulse and decays to the original temperature after the energy pulse ceases. The junction temperature variation may vary from an ambient temperature to a level above the normal maximum operating limit, a change of over 150°C. The upper temperature due to the power pulse can cause silicon damage, if the maximum allowable limit is exceeded too often or by a large amount on just one occasion. Equation (5.2) is valid for one dimensional steady state and transient thermal conditions, and the transient temperature equation is given by the first order solution to λA δT Pd = − T + γ AA (W) (5.20) δt A The time domain solution for the temperature rise is ∆T (t ) = ∆Tl × 1 − e −t / τ (5.21)

(

)

where the maximum temperature eventually attained if the power pulse were maintained, above ambient, is P A P ∆Tl = d = d = Pd Rθ (5.22) (K )

λA

hA

and the thermal time constant γ A2 thermal capacity, J/K τ = =

λ

(s)

power per K, W/K

(5.23)

The transient thermal impedance Zθ is defined as −t / τ ∆Tl × 1 − e p ∆T −t / τ Z θ = r t p Rθ = = = 1 − e p Rθ l Pd ∆T

(

( )

)

(

)

(5.24)

Rθ

That is, thermal resistance Rθ is modified by the factor r(tp) to yield transient thermal impedance Zθ:

(

r (t p ) = 1 − e

−t p / τ

)

(5.25)

This one dimensional solution assumes a homogeneous thermal conducting material with a single point heat source, producing a uniform heat flow path. Since the practical case is far from ideal, manufacturers provide data for dynamic temperature effects based on a concept termed thermal impedance. The thermal solution given by equation (5.21) gives acceptable results when applied to solid carbon resistors (being a homogeneous material), as considered in chapter 25 (specifically, see example 25.7).

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Example 5.1:

Semiconductor single power pulse capability

A semiconductor has a thermal capacity (mc) of 0.1J/K and a steady state thermal resistance to its case of Rθ = 0.5 K/W. If the junction temperature is not to exceed 125°C in a 25°C ambient, determine the allowable power dissipation, hence transient thermal impedance, as a function of a single power pulse duration. Plot the results for five time decades, reducing from 1s. Solution The power dissipation per K is 1 = 2 W/K Rθ 0.5 K/W From equation (5.23) the thermal time constant τ is given by thermal capacity, J/K 0.1 J/K τ = = = 0.05s power per K, W/K 2 W/K After time tp, the junction temperature rise from 25°C must not exceed 125°C, that is ∆T(tp) = 100K, thus equation (5.21) gives −t / 0.05s ∆T t = ∆Tl × 1 − e −t / τ = ∆Tl × 1 − e p = 100K

Pd / K =

(

( ) p

1

=

)

(

)

As a specific example of the procedure, consider a tp = 10ms energy pulse. ∆T (10ms ) = ∆Tl × 1 − e −10ms / 0.05s = 100K

(

)

which yields ∆Tl = 551.6K. That is, after a long period (>>10ms) the junction temperature would increase by 551.6K. From equation (5.22), this temperature rise corresponds to continuous power of ∆Tl 551.6 K Pd = = = 1103.3 W Rθ 0.5 K/W In 10ms the temperature must only rise 100K, hence, from equation (5.24) the transient thermal impedance Zθ is ∆T 100 K = = 0.091K/W Z θ = r t p Rθ = Pd 1103.3 W Thus the thermal resistance Rθ is modified, or normalized, by Z 0.0001K/W = 0.181 r (10ms ) = θ = 0.5 K/W Rθ

( )

The table shows the normalised thermal impedance factor, r(tp), for other pulse durations, which are plotted in the accompanying figure. Notice the similarity of the single pulse results given for a practical power device in figure 5.8. ∆Tl t →∞

tp

Pd = ∆Tl / R

θ

Zθ = ∆T/Pd

r (tp) = Zθ / Rθ

pulse time

temperature rise

power dissipated

thermal impedance

normalised

(s)

(K)

(W)

(K/W)

pu

1

100

200

0.5

1

0.1

116

231

0.432

0.86

0.01

552

1103

0.091

0.181

0.001

5050

10100

0.0099

0.0198

0.0001

50050

100100

0.0010

0.0020

0.00001

500050

1000100

0.0001

0.0002


134

Thermal Impedance 1

pu

0.1

single pulse

r = Z/R

0.01

1−e

−t p / 0.05s

0.001

0.0001 0.00001

0.0001

0.001

0.01

single pulse w idth, t p

0.1

1

(s)

♣ 5.2.3

Repetitive transient response

Minimal temperature variation occurs if the power switching period T is shorter than the thermal time constant, T < τ, whence the concept of steady state thermal resistance is applicable, as presented in 5.2.1. When the relative magnitudes are reversed such that T > 5 τ, then the temperature effects of the power pulse die away, and the single pulse transient thermal impedance approach presented in 5.2.2 is applicable. The transition or boundary between junction operation that can be assumed steady state junction temperature operation (T < τ) and that of a series of discrete non-interacting single pulses (T > 5 τ) can be analysed by extending the one dimensional thermal transient equation (5.21) in conjunction with figure 5.6a. Figure 5.6a shows how the temperature increases from T1 to T2 during the time tp when power is dissipated, and decreases from T2 to T1 during time t2 when no power is being dissipated by the junction. This increasing and decreasing of the junction temperature occurs cyclically over each period T. Based on equation (5.21) the junction temperature increases exponentially according to T (t ) = ∆Tl − ∆Tl − T e −t /τ

(5.26)

and decreases exponentially according to T (t ) = T 2 e −t /τ

(5.27)

(

1

)

where the thermal time constant τ and maximum possible junction temperature rise are defined by equations (5.23) and (5.22), respectively. Since these temperature variations are in steady state the temperature constants T1 to T2 can be solve using the boundary conditions. This gives −t / τ 1−e p and T1 = T 2 e −t 2 / τ (5.28) T 2 = ∆Tl 1 + e −T / τ The junction temperature swing, ∆T is ∆T j = T 2 − T1 = ∆Tl

(1 − e

−t p / τ

) (1 − e

−t 2 / τ

)

(5.29) 1+e The maximum variation in junction temperature occurs for square wave power, that is tp = t2 = ½T: T  ∆T j = ∆Tl tanh  (5.30)  max  4τ 

(

−T / τ

)

This equation highlights that the magnitude of the temperature change is highly dependant on the power switching frequency 1/T relative to the thermal time constant τ of the semiconductor.

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Example 5.2:

Semiconductor transient repetitive power capability

A semiconductor with a thermal capacity of 0.02J/K and a thermal resistance from the junction to the case of ½K/W, dissipates 100W at a repetition rate of i. 50Hz ii. 300Hz. By calculating the worst-case junction temperature variation, indicate whether steady state constant junction temperature based analysis is a valid assumption. Solution The long term junction temperature rise with 100W continuous is given by equation (5.22), which yields ∆Tl = P R = 100W × ½K/W = 50K d

θ

The thermal time constant τ is given by equation (5.23), giving thermal capacity, J/K 0.02 τ = = = 0.01 (s ) 1 power per K, W/K ½ Worse case temperature variation occurs with a 50% power duty cycle, as given by equation (5.30) T T    ∆T jmax = ∆Tl tanh   = 50K × tanh    4τ   4 × 0.01s  From this equation: at 50Hz, T = 20ms, ∆T jmax = 23.1K at 300Hz, T = 3.33ms, ∆T jmax = 4.1K The temperature variation of 4.1K at 300Hz is small compared to the maximum allowable junction temperature, typical between 125°C and 175ºC, thus thermal analysis of this device in a 300Hz application, can be thermal resistance calculation based as presented in 5.2.1. On the other hand the same device used in a 50Hz application will experience 5.6 times the junction temperature swing. This 23.1K variation represents a significant portion of the allowable junction operating temperature, and could mean a thermal resistance approach is unsafe. The following thermal impedance design approach is recommended.

♣

equal areas

Figure 5.7. Conversion of non-rectangular power pulse (a) into equivalent rectangular pulse (b).

The concept of thermal impedance is based on rectangular power pulses. Non-rectangular pulses are converted to equivalent energy, rectangular pulses having the same peak power, Pp, of period tp, as shown in figure 5.7. The resultant rectangular power pulse will raise the junction temperature higher than any other wave shape with the same peak and average values, since it concentrates its heating effects into a shorter period of time, thus minimising cooling during the pulse. Worse case semiconductor thermal conditions result.


136

Figure 5.8. Transient thermal impedance curves; normalised with respect to the steady state thermal resistance, Rθ j-c.

Figure 5.8 shows the thermal impedance curves for a power switching device, normalised with respect to the steady-state thermal resistance Rθ j-c. The curve labelled ′single pulse′ shows the rise of junction temperature per watt of power dissipated as a function of pulse duration. The thermal impedance for repetitive pulses Z, of duty cycle δ, can be determined from the single pulse value z according to Z ( t p , δ ) = δ + (1 − δ ) z ( t p ) (K/W) (5.31) The equation (5.10) becomes Pp =

Tl j − Tc Z (t p , δ )

=

Tl j − Tc r (t p ) Rθ j−c

(W)

(5.32)

Note that the peak power value Pp is employed, and then only for thermal analysis from the junction to the case. That is, Zθ j-c is the only thermal impedance term that exists. 5.3

Average power dissipation

Two commonly used empirical methods for determining power dissipation Pd are • graphical integration and • power superposition. 5.3.1

Graphical integration

Graphical integration may be formulated by digitally storing a complete cycle of test device voltage and current under limiting steady-state temperature conditions. Each voltage and current time-corresponding pair are multiplied together to give instantaneous values of power loss. Numerical integration techniques are then employed to give the average power dissipation. 5.3.2

Practical superposition

This technique is based on substituting a smooth dc voltage source for a complex waveform. A two-pole, two-position switching arrangement is used, which firstly allows operation of the load with the device under test, until the monitored case temperature stabilises. Then, by throwing the switch to the test mode position, the device under test (DUT) is connected to a dc power supply, while the other pole of the switch supplies the normal power to the load to keep it operating at full power level conditions. The dc supply is adjusted so that the semiconductor case temperature remains approximately constant when the switch is thrown to each position for about 10 seconds. The dc source voltage and current values are multiplied together to obtain the average power dissipated. 5.4

Power losses from manufacturers’ data sheets

The total power dissipation Pd is the sum of the switching transition loss Ps, the on-conduction loss Pd, drive input device loss PG, and the off-state leakage loss PA .

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The average total power loss is given by Pd = f s ∫

1 / fs 0

v(t ) i (t ) dt

(W)

(5.33)

where fs is the switching frequency and v(t) and i(t) are the device instantaneous voltage and current over one complete cycle of period 1/fs. The usual technique for determining total power loss is to evaluate and sum together each of the individual average power loss components. 5.4.1

Switching transition power loss, Ps

Figure 5.9 shows typical power device voltage-current switching waveforms. Normally an exact solution is not required and an approximation based on straight line switching intervals is usually adequate. For a resistive load, as derived in chapter 6 Ps = 61 Vs I mτ f s (W) (5.34) and for an inductive load, as derived in chapter 6 Ps = ½Vs I mτ f s (W) (5.35) where τ is the period of the switching interval (both on and off), and Vs and Im are the maximum voltage and current levels as shown in figure 5.9. Switching losses occur at both turn-on and turn-off.

5.4.2

Off-state leakage power loss, PA

During the switched-off period, a small, exponentially temperature dependent current I A , will flow through the switch. The loss due to this leakage current is PA = IA Vs (1 − δ ) (W) (5.36) where δ is the on-time duty cycle of the switch. Normally PA is only a small part of the total loss so that the error in neglecting PA is not usually significant.

Figure 5.9. Typical voltage and current at turn-off switching transition for: (a) an inductive load and (b) a resistive load. Current and voltage are interchanged at turn-on.

5.4.3

Conduction power loss, Pc

The average conduction power loss under a steady-state current condition is given by Pc = δ I onVon (W) (5.37) although equation (5.33) is valid in the general case when the integration is performed over the interval corresponding to δ. The conduction loss for the MOSFET is usually expressed in terms of its on-state resistance (equations (3.14) and (4.12)) Pc = δ I d2( rms ) Rds ( on ) T −25°C (5.38) α j  (W) δ I d2( rms ) Rds ( on ) (25°C) 1 +   100  where α is the temperature coefficient of the on-state resistance, which is positive. A linear resistance approximation of equation (5.38) is quite accurate above 25°C if α is small, such that Pc can be approximated by Pc ≈ δ I d2( rms ) Rds ( on ) (25°C) {1 + α (T j − 25°C)} (W) (5.39)


5.4.4

138

Drive input device power loss, PG

A portion of the drive power is dissipated in the controlling junction or, in the case of the MOSFET, in the internal gate resistance. Usually more power is dissipated in the actual external drive circuit resistance. Drive input loss is normally small and insignificant compared with other losses, and can usually be ignored. Two possible exceptions are: • One notable exception is in the case of the power GTO thyristor, where continuous gate drive is used to avoid loss of latching or when the holding current is high. The holding current can be 3% of the anode current thus the gate to cathode junction loss can be included in the total loss calculation for better accuracy. Thus, for a gate junction voltage VGC the gate losses are given by Pg = δ I G VGC (5.40) The recovery loss of the gate commutated thyristor (GCT) cathode junction can be included since it is significant because the full anode current is extracted from the gate, thus is involved in recovery of the cathode junction. • A second exception is the MOSFET and IGBT at high switching frequencies, >50kHz, when the loss in the device, associated with providing the gate charge QT is given by equation (4.35): RG int (5.41) (W) PG ( Rint ) = Vgg QT f s RG int + RGext

5.5

Heat-sinking design cases

Heat-sink design is essentially the same for all power devices, but the method of determining power loss varies significantly from device type to device type. The information given in data sheets, in conjunction with the appropriate equation in table 5.9, allows the designer to calculate power semiconductor thermal rating for a variety of conditions. Generally heatsink design is more readily visualised if a thermal equivalent electrical circuit model approach is adopted, as shown in figure 5.1. The equivalence of parameters is shown in Table 5.8. The examples to follow illustrate the approach. Table 5.8. Thermal equivalent electrical circuit parameters

thermal parameter temperature degrees drop Kelvin power Watts dissipated thermal K/W resistance 5.5.1

∆T

thermo electric model potential Volts ∆V difference

Magnetic model Magneto motive Ampforce turns

ℑ

P

current flow

Amps

I

flux

Wb

Φ

Rθ

Ohm’s resistance

Ohms

R

reluctance

Ampturns/Wb

ℜ

Heat-sinking for diodes and thyristors

At low switching frequencies (2200°C, 800°C oxidizing

2054°C

98%

95%

>3.25

>3.65

100 - 300

27

15

Dielectric Constant

(at 1MHz)

8.7

9.2

4

3-7

Loss Tangent

(x10 @1 MHz)

Volume Resistivity

(ohm-cm)

Flexural Strength

(kgf/mm)

3 12

>1014

>10 at 20oC >108 at 500oC

>25

>280

Substrate Specification Maximum Dimension

(mm)

140 x 100mm,

100 x 200

Thickness

(mm)

0.63 - 0.2 mm

0.63 - 0.30mm

Surface Roughness

(micron)

as fired as lapped as polished

0.3 0.075 0.025

as fired as lapped as polished

0.3 0.075 0.025

0.1016/25.4

Flatness

coefficient of thermal expansion

-6

10 K

-1

At room temperature, thermal conductivity of aluminium nitride ceramics is independent of Aℓ3N4 grain size or number of grain-boundaries, but is controlled by the internal structure of the grains, such as the degree of oxidation (oxygen contamination).

10

9

8

7

6 0

0.2

0.4

0.6

copper thickness

0.8

1

1.2

mm

The coefficient of thermal expansion for direct copper bonded (DCB) substrates with a layer of 0.6 mm alumina sandwiched between Cu layers of various thicknesses.

Power Electronics

147

5.7

Appendix: Properties of substrate and module materials relative permittivity

material

linear thermal expansion coefficient

specific thermal conductivity

dielectric loss factor 10GHz, 25°C

εr Al203

9.8

temperature coefficient of εp

type

@25°C

tanδε

λ

∆l/l /∆T

∆ε/ε∆T

×10-4

W/m K

10-6/K

10-6/K

1

37

6.3

136

insulator

sapphire

9.4

1

42

6

110

insulator

Quartz glass Beryllium oxide ceramic Be0 GaAs Silicon 3 ρ=10 Ωcm PTFE

3.78

1

1.7

0.55

13

insulator

6.3

60

210

6.1

107

insulator

12.9

20

46

5.7

semiconductor

11.9

150

145

4.2

semiconductor

3

0.2

106

350

plastic

polyolefin

2.32

0.5

108

480

plastic

393

17

7

copper

Temperature coefficient of expansion ppm/K

material

Aluminium

Al

23.0

Copper

Cu

17

Cu/Mo/Cu Silicon Silicon carbide Aluminium nitride

5.8 Si

3.5

SiC

3.7

Al3N4

4.4

sapphire

7.9

λ

specific heat capacity c

W /m K

J/ kg K

kg/m3

thermal conductivity

material

5.8

metal

density ρ

silicon

Si

120

700

2330

solder

PbSn

50

150

8400

copper

Cu

385

385

8930

alumina

Al203

22

80

3720

Aluminum nitride

Al3N4

170

725

3300

Polyimid

0.2

1100

1400

Dielectric layer

0.3

1400

1120

encapsulation

0.5

2000

Appendix: Ampacities and Mechanical Properties of Rectangular Copper Busbars

Effect of emissivity and number of busses on ampacity (current carrying capacity) - data show how higher emissivities improve ampacity. Multiple busses also affect ampacity in a nonlinear relationship. Ampacity may be raised by increasing heat dissipation through the use of convection cooling or surface treatments. Surface treatments which improve emissivity are oxidation or thinly coated, flat, inorganic based spray paints.


148

Ampacity, A number of 6mmx100mm busses

30°C rise

50°C rise

65°C rise

emissivity ε

emissivity ε

emissivity ε

0.15

0.4

0.7

0.9

0.15

0.4

0.7

0.9

0.15

0.4

0.7

0.9

1

1100

1250

1400

1600

1500

1700

1900

2000

1700

1950

2200

2300

2

1900

2050

2200

2300

2550

2750

2950

3100

2950

3200

3400

3600

3

2500

2700

2850

3000

3400

3600

3850

4000

3950

4200

4500

4600

4 3100 3300 3450 3600 4200 4400 4700 4800 4900 5100 5400 5600 6mm spacing. Ampacities of bus bar systems of other configurations must be calculated taking into account size, spacing, number of bus bars, and overall skin-effect ratio.

Problems

5.1.

A thyristor bridge switches at 1 kHz and the total energy losses per thyristor are 0.01 Joule per cycle. The thyristors have isolated studs and a thermal resistance of 2 K/W. The heat sink has a thermal resistance of 1.8 K/W. Calculate the maximum number of thyristors that can be mounted on one heat sink if the thyristor junction temperature is not to exceed 125°C in an ambient of 40°C. What is the heat sink temperature? [3 devices, Ts= 94°C]

T

T

Figure 5.12. Problem 5.2.

5.2.

A transistorised switch consists of two IGBTs and two 1 Ohm current-sharing resistors, as shown in figure 5.12, mounted on a common heat-sink. Each transistor has a thermal resistance Rθj-hs of 2 K/W, while each resistor has a thermal resistance Rθ r-hs of 1 K/W. The maximum switching frequency is 1 kHz and the maximum duty cycle is 99.99 per cent. The heat-sink thermal resistance Rθ hs-a is 1 K/W. The energy losses per transistor are 5 mJ/A per cycle. If the ambient temperature is 30°C, maximum allowable junction temperature is 150°C, and the maximum allowable resistor internal temperature is 100°C, calculate the switch maximum current rating based on thermal considerations. What are the operating temperatures of the various components, assuming ideal current sharing? [6.88 A, Tr = 100°C, Ths = 88°C, Tj = 122.5°C]

5.3.

Figure 5.13a shows the circuit diagram for a power current sink which utilises a 40V source. Both the IGBTs T and wire wound resistors R are mounted on a common heat-sink, of thermal resistance Rθ hs-a = 1 K/W. The transistor has a thermal resistance of 2 K/W from the junction to the heat-sink, and 10 K/W from the junction to air via the transistor casing exposed to the air. The resistor has a mounting thermal resistance from the insulated wire to the heat-sink of 1 K/W and 10 K/W from the wire to the air via its casing exposed to the air. The maximum transistor junction temperature is 423 K, the maximum resistor wire temperature is 358 K and the ambient air temperature is 303 K. Based on thermal considerations, what is the maximum current rating of the current sink and under such conditions, what is the heat-sink temperature?

149

Power Electronics

What power rating would you suggest for the 1 Ohm current measurement resistor? Are there any difficulties in operating the transistor in the linear region in this application if it is in a 120 W dissipation package which is derated according to figure 5.13b? [1.36 A, 69°C, > 2 W]

T

Figure 5.13. Problem 5.3.

5.4.

A power IGBT switches a 600 V, 25 A inductive load at 100 kHz with a 50 per cent on-time duty cycle. Turn-on and turn-off both occur in 100 ns and the collector on-state voltage is to be 2 V. Calculate the total power losses, Pd, of the switch. The switch has a thermal resistance Rθj-hs = 0.05 K/W, and the water-cooled heatsink provides a thermal resistance Rθhs-w = 0.05 K/W. Calculate the operating junction temperature if the water for cooling is maintained at 35°C. The 25 A steady state load current is stepped to 200 A. Calculate the surge power dissipation Ps, at 200 A, assuming transistor switching and on-state characteristics remain unchanged. The junction temperature for a power surge during steady-state operation is given by case (d) in table 5.2. With the aid of figure 5.8, determine the junction temperature at the end of a 0.1s, 200 A pulse. How long is it before the junction temperature reaches Tl j = 125°C, with a collector current of 200 A? (Assume Rθc-hs = 0). [175 W, 52.5°C, 1400 W, 112.6°C, 0.5 s]

5.5

Rework example 5.6 finding the case temperature when the switching losses equal the on-state loss.

5.6

A 20kHz, step-down, 340V dc chopper feeds an inductive load with an average current of 20A and a peak to peak ripple of 20A. Thus the MOSFET switch on-state current rise from 10A to 30A while the freewheel diode current falls from 30A to 10A when the switch is off. The MOSFET onstate resistance is 0.1Ω and has switch on and off times of 100ns and 200ns respectively. The switch duty cycle is 75% and it has a thermal resistance Rθ j-c of 0.4K/W and is mounted on a heatsink of thermal resistance Rθc-a of 0.6K/W in a maximum ambient temperature is 40°C. Calculate: i. switching losses, using equations 6.9 and 6.10 ii. switch on-state losses iii. mosfet junction operating temperature [3.4W + 20.4W = 23.8W; Irms = 15.8A, 25W; Tj = 88.8°C]


blank

150

6 Load, Switch, and Commutation Considerations Power switching devices are employed for controlling inductive, resistive or capacitive loads. Inductive loads include electrical machines, transformers, solenoids, and relays. High-current in-rush occurs with loads such as incandescent lamps, pulse-forming networks, snubbers, and motors. Incandescent lamps are essentially resistive, but the cold resistive in-rush current during turn-on is 12 to 18 times the steadystate current. This turn-on surge presents special switch-on problems. Capacitive loads, such as fluorescent lighting, also present high-current in-rush at turn-on. Electromechanical loads, such as shakers, present loads that vary between capacitive and inductive over their operating frequency range. The interaction of the load circuit on the switch arrangement and its commutation depends on three inter-related factors. • The type of load, usually inductive, and rarely purely resistive. • Switching mechanism classification, how the load effects switching commutation, namely hard switching, resonant, etc. • The switch characteristics required to fulfil the supply and load I-V requirements, such as a bidirectional current switch, an asymmetrical sustaining voltage switch, etc. Each of the three factors and their interdependence with the switching mechanisms are considered separately. 6.1

Load types

The two principal load types of general interest in power electronics are • the resistive load and • the inductive load. Turn-on and turn-off voltage and current switching waveforms, hence losses in a switch, depend on the type of load. 6.1.1 The resistive load A purely resistive load is rarely encountered in power switching applications (other than at load resonance). Figure 6.1 shows a simple resistive load being switched by a common emitter-connected IGBT transistor, which could equally be another appropriate semiconductor switch, for example, a MOSFET. When the gate is driven by the voltage waveform shown in figure 6.2a, the resultant collector voltage and current waveforms are as shown in figures 6.2b and 6.2c. These figures show that at turnon, as the collector current increases, the voltage across the resistive load increases proportionally, as the collector voltage vce decreases at the same rate. That is, at turn-on, vc e (t ) = Vs − ic (t ) RL , while at turnoff the inverse process occurs. Figure 6.2d shows transistor instantaneous power loss during turn-on and turn-off, which in each case has a peak value of ¼VsIm when the collector voltage and current reach half their respective maximum values. The energy loss W during switching is given by W =

∫v

ce

(t ) ic(t ) dt

(J)

where the integration is performed over the switching transition period.

BWW

(6.1)


152

Vg

Figure 6.1. A typical IGBT transistor switching circuit incorporating a resistive load.

Figure 6.3 shows the safe operating area (SOA) characteristics for an IGBT, on logarithmic axes. Illustrated are the collector switch-on and switch-off trajectories, which are virtually coincident. In the offstate, point A on figure 6.2b, the transistor supports the supply rail voltage Vs while in the fully on-state, point C on figure 6.2b, the collector current Im is Vs /RL, neglecting the low on-state voltage of the transistor. During switching the collector voltage and current traverse the I-V switching trajectory between the steady-state operating conditions on → Vs /RL and off → Vs, as shown in figure 6.3.

Vg ON

turn-on

OFF

on-state

turn-off

off-state

Figure 6.2. Transistor switching waveforms for a resistive load: (a) on-off gate drive voltage; (b) collectorto-emitter voltage; (c) collector and load current waveform; and (d) instantaneous collector-emitter losses.

Power Electronics

153

It is important that this trajectory does not exceed the shown SOA bounds set by the device voltage and current limits, and that the SOA region be traversed rapidly. For slow transitions, greater than a few microseconds, power dissipation considerations become the limiting design factor, which is a thermal limitation. In order to perform the required thermal design calculations (for heatsink determination) it is necessary to be able to specify device-switching losses. To simplify analysis, the switching waveforms shown in figure 6.2 are linearised as shown in figure 6.4. As indicated on these waveforms, the collector voltage fall at turn-on is given by vce (t ) = Vs (1 − t / ton ) while the collector current rise is ic (t ) = I m t / ton , where I m = Vs / RL . Combining vce(t) and ic(t) by eliminating time t, gives ic = Vs (1 − vce / Vs ) / RL (6.2) As shown in figure 6.3, this describes the linear turn-on transition of slope -1/RL from the on-state voltage with Vs / RL collector current, shown as C, to the off-state at A where no current flows and the collector supports the supply Vs. Note figure 6.3 uses logarithmic axes, so the transition trajectory does not appear as a straight line (the inset figure is for linear axes). Using equation (6.1), the switch-on loss for a resistive load is given by t t t Wonr = ∫ Vs (1 − ) I m dt ton ton 0 on

V2 (J)  s ton RL where I m = Vs / RL and ton is the period of the switch-on interval, as shown in figure 6.4. =  I mVs ton

Ic

(6.3)

or

C

B

I SOA

C -1/RL

A

V

VCES

Figure 6.3. Transistor I-V characteristics showing safe operating area and the switching trajectory with a resistive load, on logarithmic axes, and inset, on linear axes.

Similarly, using the time dependant collector voltage and current equations shown on figure 6.4a, the turn-off switching loss is given by t t t Woffr = ∫ Vs I (1 − ) dt toff m toff 0 (6.4) Vs2 =  I mVs toff or (J)  toff RL where toff is the turn-off period as shown in figure 6.4. The average power loss due to switching, which is required for the thermal design outlined in chapter 5, is obtained by multiplying energy loss W by the switching frequency fs. That is, the turn-on switching loss is given by Pon =  ImVs ton fs (W) (6.5) while the turn-off loss is given by Poff =  Im Vs toff fs (W) (6.6) off

Because of IGBT current tailing and voltage overshoot at turn-off, the practical switching losses will be larger than those given by the linear approximating methods outlined.


off

on

on

154

off

Figure 6.4. Linear approximations of switching intervals for a purely resistive load: (a) collector voltage and current linear waveforms and (b) corresponding energy and power losses.

Example 6.1:

Resistive load switching losses

An IGBT switches a 10 ohms resistive load across a 100V dc supply. If the switch on-state duty cycle is 25%, (δ = ¼), calculate the average load voltage and current. Calculate the switch losses if the switch-on time is ton =1µs, switch-off time is toff =2µs, and the on-state voltage is 2V. Solution When the switch is on, the current in the resistor is IL =Vs /R = 100V/10Ω = 10A. The average load voltage is Vo = δ Vs = 0.25 × 100V = 25V The average load current is I o = Vo / R = 25V/10Ω = 2.5A

The total switch losses PT are made up of three components. PT = on-state loss + loss at switch-on + loss at switch-off 1 1 PT = δ × vce × I L + V I t f + 6 s L on s 6 Vs I L toff f s = ¼×2V×10A + 16 ×100V×10A×1µs × 10kHz + 16 ×100V×10A×2µs × 10kHz =

5W

+

5 3

W

+

10 3

W

= 10W

Since the off-state leakage current and gate power losses are not specified, it is assumed these are insignificant. Technically the load current should be calculated based on 98V across the load since the switch supports 2V. Also the switching loss calculations should use a voltage of 98V, rather than 100V and a load current of 9.8A rather that 10A. The percentage error is small, and becomes increasingly insignificant at higher voltages.

♣

Power Electronics

155

Example 6.2:

Transistor switching loss for non-linear electrical transitions

Assume the transistor collector current at turn-off falls according to ic = ½ I m (1 + cos π t / T0 ) for 0 ≤ t ≤ T0 For a resistive load, RL

(6.7)

i. Calculate transistor loss at turn-off. ii. Show that the switching trajectory across the SOA is as for the linear current fall case, as given by equation (6.2) and shown in figure 6.3. iii. Calculate the peak power dissipation and the time when it occurs. Solution i.

The collector voltage for a resistive load, on a dc supply Vs, is given by vce (t ) = Vs − ic (t ) RL = Vs − ½ I m (1 + cos π t / T0 ) RL

and since Vs = I m RL

vce (t ) = ½Vs (1 − cos π t / T0 ) The turn-off energy loss is given by

∫ =∫

Woff =

T0 0 T0 0

p(t ) dt =

∫

T0 0

ic (t )vce (t ) dt

½ Im (1 + cos π t / T0 ) × ½ Vs (1 − cos π t / T0 ) dt

=  Vs Im T0

ii.

Combining vce(t) and ic(t) so as to eliminate the time variable, yields V v ic = s (1 − ce ) RL Vs which is the same straight line expression as in equation (6.2) and shown in figure 6.3, for the linear switching transition case. iii.

Instantaneous power dissipation is given by V v P = vceic = vce s (1 − ce ) RL Vs

Peak power Pˆ occurs when dP/dvce = 0, that is, when vce = ½Vs, whence on substitution into the power expression P, yields Pˆ = ¼ Vs 2 / RL = ¼ Vs I m at t = ½T0

♣ Turn-on loss can be similarly analysed to yield virtually identical expressions, as is required in problem 6.4.

6.1.2

The inductive load

The voltage spikes generated by inductive loads at turn-off may have high energy content, and the power generated may cause excessive device temperature, voltage stressing, and device failure. At turn-off, the switch decreases the inductive load current from Im to zero at a high di/dt and the resultant inductive voltage spike is given by di v (t ) = L (V) dt where L is the load inductance. The spike energy to be absorbed by the switch is given by W = ½ LI m2 (J) Both the voltage spike and its associated energy may be well outside the capabilities of the switching device. The peak voltage induced must be limited to a value below the breakdown rating of the device. Four commonly employed voltage limiting techniques are shown in figure 6.5.


156

Df

Vg

Vg

R

D Vg

Vg

(d)

Figure 6.5. Four methods of limiting inductive load turn-off voltage spike and of absorbing the associated energy: (a) freewheel clamping diode; (b) Zener diode clamp; (c) R-C snubber circuit; and (d) capacitor soft voltage clamp.

The freewheel diode Df in figure 6.5a is used to clamp the maximum device voltage to the supply rail voltage. The stored load energy is dissipated after turn-off as a result of the current that flows in the diode and load. The low impedance of the diode causes the current to decay slowly, since the inductor stored energy can only dissipate slowly in the freewheeling loop resistive components. A shorter current decay time can be achieved if series loop resistance R is added, as shown in figure 6.5a. Now the peak off-state voltage experienced by the switch is increased from Vs in the case of only the diode, to Vs + ImR because of the initial voltage drop across the optionally added resistor. This extra voltage drop, ImR, decreases exponentially to zero. The resistor in figure 6.5a can be replaced by a Zener diode, thereby clamping the switch voltage at turn-off to Vs + VZ. The load now freewheels at a fixed voltage VZ thereby improving the rate of current decay, which is now constant. The inductive load current will fall linearly from Im to zero in a time given by t = LI m / Vz (s) An alternative Zener diode clamping circuit, as shown in figure 6.5b, can be employed in low power applications. The Zener breakdown voltage Vz is selected between the rail voltage Vs, and the switch breakdown voltage (Vs < Vz < VBR ) . At turn-off, the Zener diode clamps the switch voltage to a safe level VZ and absorbs the stored inductive load energy. The higher the clamping voltage level, the faster the energy is dissipated. The inductive load current decays linearly to zero in a time given by t = LIm /(Vz - Vs ) (s) (6.8) The two different Zener diode approaches perform the same switch clamping function in the same current decay time, if the voltage experienced by the switch is the same, but with different Zener diode losses. The desirable feature in the case of the Zener diode in parallel to the switch as in figure 6.5b, is that the protection component is directly across the element to be voltage protected. When placed in parallel with the load as in figure 6.5a, the switch is indirectly voltage protected, relying on the supply decoupling being a low inductance path. A reverse blocking diode Df in figure 6.5a is mandatory.

Power Electronics

157

The parallel-switch Zener diode approach in figure 6.5b has a number of disadvantages • • •

The Zener diode voltage rating must be in excess of the supply rail, Vs, while any Zener value can be used when the Zener diode is in parallel with the load. At higher voltages, >280V, Zener diodes will have to be series connected, thus the low inductance advantage of clamping with just one component is diminished. Assuming no resistance in the load, the energy dissipated with the two Zener diode approaches differs. When in parallel with the load, the load energy ½ LI m2 is dissipated while in the second case, load and supply energy are dissipated in the clamping Zener diode. The extra supply energy, in addition to ½ LI m2 , dissipated in the Zener diode, is ½ LIm2 Vs /(Vz − Vs ) . This is derived by recognising that, assuming a purely inductive load, the dc supply Vs delivers a current Im which linearly falls to zero over the period given by equation (6.8).

The R-C snubbing circuit shown in figure 6.5c is commonly used in power conversion circuits to limit spikes caused by transformer leakage inductance, diode recovery, and interconnection wire inductance. The stored load energy is resonated to the snubber capacitor at switch turn-off. The reset resistor R (non-inductive) must overdamp the L-C-R oscillation by absorbing the transferred energy. The resistor also limits the snubber capacitor discharging current to a maximum of Vs /R at switch turn-on. For a purely inductive load, the snubber resistor power losses are given by the sum of the turn-off and turn-on losses, that is P = (½ LI m2 + ½CVs2 ) f s (W) Figure 6.5d shows a capacitive voltage clamp used to soft clamp the switch voltage overshoot caused by the inductive energy stored in the load. The capacitor retains a charge of at least Vs. At switch turnoff, when the switch collector voltage reaches the capacitor (supply Vs) voltage level, the inductive stored load energy is transferred to the capacitor and concurrently, the capacitor discharges the energy in excess of Vs into the supply. When the capacitor is over charging, energy is taken from both the load inductance and the supply. When the capacitor discharges through the resistor back into the supply, the earlier energy taken from the supply is returned. The net effect is that only the energy ½ LI m2 is dissipated in the resistor. A reset resistor of low inductance is not necessary – a wirewound resistor can be used. This capacitive soft voltage clamp is analysed in detail in chapter 8.2. Example 6.3:

Zener diode, switch voltage clamping

A reed relay coil of 1 mH inductance is switched at 20 kHz with a 20 per cent on-time duty cycle, across a 100 V dc rail. The energy stored in the coil at turn-off is dissipated in a 25 V Zener diode connected as shown in figure 6.5a. i. Sketch the coil current and voltage, and the switch voltage waveforms. ii. What is the average coil voltage? iii. What Zener diode voltage is required for the circuit in figure 6.5b so as to produce the same coil current waveform as in figure 6.5a when using a 25 V Zener diode? iv. For each circuit, calculate the power requirement of the Zener diode and the average power delivered from the 100 V supply. v. Calculate the minimum resistance that replaces the Zener diode in figure 6.5a if the coil is to be switched on with almost zero current. Draw the coil current and switch voltage waveform, showing the switch peak voltage at turn-off. vi. Discuss the relative features of each voltage clamping approach. Solution The three voltage clamping circuits being considered are shown in figure 6.6a. i.

With a 20kHz switching frequency, the coil current rises and falls every 50µs, with an on-state duty cycle representing 10µs for the current to increase in the coil and 40µs for the current reset decay to reach zero. From V=Ldi/dt, in steady-state, with zero coil resistance and zero initial current, the peak coil current is I = Vs t /L = 100Vx10µs/1mH = 1A. Thus the coil current rises linearly from zero to 1A in 10 µs. During reset, the coil current waveform depends on the reset circuit. For Zener diode (constant voltage) reset, the current falls linearly, while with a resistor the reset current decays with an L / R exponential time constant, as shown in figure 6.6b, for each case. The various circuit voltage and current waveforms are shown in figure 6.6b, where data derived from the rest of this example has been incorporated.

Load, Switch, and Commutation Considerations 100V

100V

158

100V

Df

Df

Z1 25V

Z2

Figure 6.6a. Three inductive load clamping circuits. I coil

I coil

1A

on

off

I sw itch 0

on

1A

off

I Zener

Iresistor IZener

I sw itch

10

50 t (µs) switch voltage

0

10

50 t (µs)

10

switch voltage

175V

125V 100V

100V

Coil voltage equal areas 0V -25V

Coil voltage equal areas t

0V

t

-25V

Figure 6.6b. Coil voltage and current waveforms.

ii.

From V=Ldi/dt, for a steady-state continuous waveform, ∫ VL (t )dt = 0 , thus 1/ T ∫ v (t )dt = Vave = 0 , as shown on the coil voltage waveform (the coil voltage areas cancel to zero).

iii. The parallel Zener diode requirement is VZ2 = Vs+VZ1 = 100V+25V = 125V. iv. Zener diode VZ1 in the parallel-load reset circuit: The energy ½LI 2 is transferred from the coil to the Zener diode when the switch is turned off. The power dissipated in the Zener diode at 20kHz is therefore ½ LI 2 f s = ½×1mH×1A 2 ×20kHz = 10 W . The total power drawn from the supply is the power stored by the coil at the end of the 10µs ontime, namely 10W. Zener diode VZ2 in the parallel-switch reset circuit: When the coil releases its stored energy (10W) into the Zener, current is also drawn from the supply. The total average power delivered by the supply over the 50µs period is given by Vs I ave = ½ × 100V×1A = 50W . This comprises ½LI 2 (10W) from the supply into the coil when the switch is on for 10 µs, and the remainder (40W) into the Zener diode (plus the coil energy, 10W), when the switch is off for 40 µs. The Zener diode losses are 50W during the switch off period. v. When a resistor is used in the reset circuit, the current decays exponentially from 1A to 0A. The resistance determines the peak switch voltage. The resistance does not affect the amount of energy dissipated, only the period over which the coil energy is released, dissipated as heat. Assume the coil current to be near zero after three L/R time constants, that is 3L/R = 40µs = toff.

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For L = 1mH, this gives R = 75Ω, with a power dissipation rating of 10W from part iv. At switch turn-off the collector voltage rises to (100V+1A×75Ω) 175V and then decays to 100V. Use an 82Ω (preferred value, exceeding 75Ω which reduces the time constant), 15W metal oxide resistor for low inductance. vi.

A Zener diode approach gives a fixed over-voltage on the switch, independent of current or stored energy. When clamping is in parallel with the switch, only one clamping element is needed, but its power requirement is significantly higher than when the clamp (Zener plus diode) is in parallel to the load. Any resistive element must have low inductance. This is restrictive given the power levels involved, and may result in only less effective wire wound elements being viable.

♣ By far the most common technique used to limit inductive switch-off voltage spikes in power circuits involves the use of a freewheel diode without Ropt, as shown in figure 6.5a and 6.7a. Typical switching waveforms for an inductive load clamped by a freewheel diode are shown in figure 6.7.

•

At turn-off, the switching device conducts the full load current as the collector voltage rises to the supply rail. When the collector voltage reaches the supply rail level the freewheel diode becomes forward-biased and begins to conduct. Only then can the switch current fall to zero. The freewheel diode conducts the load current.

•

At switch turn-on, assuming the diode is still freewheeling load current, the switch current increases, displacing freewheeling diode current, while the load is clamped to the rail voltage by the conducting freewheel diode. Only when the switch conducts the full load current can the freewheel diode recovered (and block), so that the switch voltage can fall to the low on-state level. Vs

Vg

V Vg

g

(V)

ON

OFF

di × c L stray dt

B A D

Won

Woff

Figure 6.7. Inductive load switching waveforms: (a) the circuit including the freewheel diode Df; (b) on-off gate drive voltage; (c) collector-to-emitter voltage; (d) collector and freewheel diode current; and (e) switch instantaneous power losses.


160

It will be seen in figure 6.7 that during both turn-on and turn-off the switch must support instantaneously a maximum voltage, Vs, and full load current, Im, condition. These severe electrical conditions are shown on the SOA characteristics in figure 6.8. In switching on from the operating point A to C, a maximum voltage and current condition (Vs, Im) occurs at point D. Because of freewheel diode current reverse recovery effects at turn-on, an SOA trajectory point B is reached. At turn-off, due to stray inductance, voltage over shoot occurs and the point E is reached. By comparison with figure 6.2, it is seen that power losses during the switching intervals are higher for an inductive load than a resistive load. diode recovery

I

Icmax c Voltage overshoot

tfv

on-state

E

trv

tfi

Rds(on) limit

tri

off-state

A VCES

Figure 6.8. I-V characteristics for an IGBT showing its safe operating area and switching trajectory for an inductive load (linear axes).

Switching losses can be calculated by using linear approximations to the switching transitions. It can be assumed that a silicon carbide Schottky freewheel diode is employed so as to allow reverse recovery effects to be neglected. Figure 6.9 shows the linearised switching waveforms for an inductive load, where maximum voltage Vs and current Im occur simultaneously during both turn-on and turn-off. The equations for the collector voltage and current at turn-on and turn-off are also shown in figure 6.9. The turn-on switching interval loss is given by the time integral over the current rise period plus the voltage fall period, t t t t Won = ∫ Vs Im dt + ∫ Vs (1- ) Im dt tri t fv 0 0 (6.9) ri

fv

= ½ Vs Im ton (J) where ton = tri + tfv, as shown in figure 6.9. The current rise time at turn-on is termed tri, while the switch voltage fall time at turn-on is termed tfv.

Similarly, from figure 6.9c, the turn-off loss is given by t t t t Wof f = ∫ Vs I m dt + ∫ Vs I m (1- ) dt tri 0 0 t fv rv

= ½ Vs I m toff

fi

(6.10) (J)

where toff = trv + tfi, as shown in figure 6.9c. The switch voltage rise time at turn-off is termed trv, while the switch current fall time is termed tfi. Comparison of switching losses for a resistive load, equations (6.3) and (6.4), and an inductive load, equations (6.9) and (6.10), shows that inductive switching losses are three times those for the resistive load case. The peak power experienced by the switch during switching of an inductive load, Vs Im, is four times greater than that experienced with a resistive load, ¼VsIm. As for the resistive load switching circuit, actual switch losses with an inductive load are higher than those predicted by equations (6.9) and (6.10). The effects of current tailing, voltage over-shoot, and freewheel diode reverse recovery can together produce losses of the same order as those predicted for theoretical switching by equations (6.3), (6.4), (6.9), and (6.10).

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iDf

Im = iDf + ic

ic

KCL

ic

Kirchhoff’s current law

iDf t

(a)

vDf

vce

Vs = vDf + vce

vDf

Vs

KVL

vce

KVL

Im

vDf

iDf ic

t

vce (b)

off

on

on

off

(c)

(d)

Figure 6.9. Linear approximations of transistor switching intervals for an inductive load: (a) Kirchhoff’s current law Im = iDf + ic; (b) Kirchhoff’s voltage law Vs = vDf + vce; (c) collector voltage and current waveforms with switching parameters defined; and (d) corresponding switching losses.

Example 6.4:

Inductive load switching losses

A power n-channel MOSFET switches a 10A, 100V dc, highly inductive load at 10kHz. Calculate the worse case switch losses if the switch turn-on time is ton = 1µs, switch turn-off time is toff = 2µs, and the MOSFET channel on-state resistance is 0.2Ω at 10A. Calculate the maximum instantaneous power dissipation in the switch, and determine when it occurs. Solution Maximum switch losses occur when the duty cycle approaches one (δ →1) such the both turn-on and turn-off still occur. The total switch losses PT are made up of three components PT = on-state loss + loss at switch-on + loss at switch-off 2 PT = δ × I L × Rds ( on ) + ½Vs I L ton f s + ½Vs I L toff f s = 1×10 2 ×0.2Ω + ½×100V×10A×1µs × 10kHz + ½×100V×10A×2µs × 10kHz =

20W

+

5W

+

10W

= 25W Since the off-state leakage current and gate power losses are not specified, it is assumed these are insignificant. The switching loss calculations should use a voltage of 98V, rather than 100V, since (10A×0.2Ω) 2V is dropped across the channel resistance of the MOSFET. The percentage error is small, and becomes insignificant at higher voltages.

Maximum switch loss occurs when during the switching transitions, the drain current is 10A and the drain voltage is 100V. The maximum instantaneous loss is 10A×100V=1000W, (IL ×Vs).

♣


6.1.3

162

Diode reverse recovery with an inductive load

When a bipolar diode conducts the pn junction scl region accumulates charges. When the diode turns off and the current falls to zero, the junction retains charge that must recovery before diode reverse voltage can be supported. Negative diode current flows. This phenomenon was considered in chapter 4.2.2 and is shown in figure 6.10a. The maximum collector current at turn-on is increased above the load current level Im by the reverse recovery current Irr, to Im+Irr. The diode begins to support reverse voltage once the peak reverse recovery current is reached. As a consequence the turn-on losses are increased as shown in figure 6.10c. The circuit current at peak recovery has a discontinuous derivative, and as a consequence, high circuit voltages are induced across circuit stray inductance due to v = Ldi/dt. High-frequency voltage ringing occurs as the stored energy in the stray inductance is dissipated and reverse voltages far in excess of Vs are experienced by the recovering diode. Im+Irr Im = iDf + ic

iDf

ic

iDf

Kirchhoff’s current law Schottky diode

ic t

bipolar diode

(a)

Irr

Vs = vDf + vce

vce

vDf

off

vce

Kirchhoff’s voltage law

on

vDf

off

on t

(b) (Im+Irr)Vs

Vs Im V s PD

vDf = Vload

Im iDf t

ic ton

vce

PD (c)

Figure 6.10. Linear approximations of transistor switching turn-on interval for an inductive load showing freewheel diode reverse recovery effects on the right: (a) Kirchhoff’s current law Im = iDf + ic; (b) Kirchhoff’s voltage law Vs = vDf + vce; and (c) corresponding switching losses.

Example 6.5:

Inductive load switching losses with device models

A MOSFET 340V dc chopper feeds an inductive dc motor load at 50kHz. In steady state the load current rises from 10A to 25A when the switch is on with a 75% on-state duty cycle (δ = ¾). The MOSFET switch turn-on time is ton = 100ns, switch turn-off time is toff = 200ns, and the channel on-state resistance is Rds on = 0.025Ω. The freewheel diode is modelled by a 1V on-state voltage and on-state resistance of 0.05 Ω. Neglecting diode recovery and diode turn-on losses, calculate i. ii. iii. iv.

the MOSFET total losses diode losses power delivered to the motor load, if the armature resistance is 1 Ω and back emf is 170V electromagnetic energy conversion efficiency and total circuit efficiency

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Solution i. The MOSFET losses comprise turn-on, turn-off, and conduction losses. The rms current in the MOSFET is given by I M − rms =

δ  2 ∨ ∨2  I + I ×I+ I 

3  0.75 = × ( 25A 2 +25A×10A+10A 2 ) = 15.6A 3 The MOSFET conduction losses are therefore 2 Pc = I rms Rds on = 324.75 × 0.025Ω = 8.1W

The switching losses are ∨

at turn-on Pt -on = ½ Vs I ton f s = ½×340V×10A×100ns×50kHz = 8.5W ∧

at turn-off Pt -off = ½ Vs I toff f s = ½×340V×25A×200ns×50kHz = 42.5W Total MOSFET losses are PMOSFET = Pc + Pt − on + Pt −off = 8.1W+8.5W+42.5W = 59.1W ii. The diode RMS current is 1− δ  2 ∨ ∨ 2  I + I × I+ I  3   0.25 = × ( 25A 2 +25A×10A+10A 2 ) = 9A 3 The average diode current is ∨ I d = ½ (1 − δ )  I + I  = ½× (1 - ¾ ) × ( 25A+10A ) = 4.375A   The total diode losses are Pdiode = I D2 −rms RD−on + I × VD−on I D−rms =

=81.25×0.05Ω + 4.375A×1V = 8.4W

iii.

The power delivered to the load comprises losses in the 1Ω armature resistance and the power delivered into the 170V dc back emf. The rms load current is given by 1  2 ∨ ∨2  I + I × I+ I  3   1 = × ( 25A 2 +25A×10A+10A 2 ) = 18A 3 The load resistor loss is PRa = I a2−rms Ra = 325 × 1Ω = 325W I M − rms =

The average load current is ∨ I a = ½  I + I  = ½× ( 25A+10A ) = 17.5A   The power delivered to the back emf is PE −a = I a Ea = 17.5A×170V = 2975W The total power delivered to the dc motor is Pmotor = PRa + PE −a = 325W+2975W = 3300W iv. The dc motor efficiency is power output 2975W η dc = = × 100 = 90.2% 3300W power input Including switch and diode losses yields total circuit efficiency, that is power output power output ηcircuit = = dc supply power input chopper circuit losses + dc motor power input 2975W = × 100 = 88.3% 59.1W+8.4W ( ) +3300W ♣


6.2

164

Switch characteristics

Having considered the switching of inductive and resistive loads, the following are the electrical and thermal characteristics desirable of commutable switching devices (as well as low cost): off-state (ideally open circuit): • Low, temperature independent leakage current in the off-state, to minimise off-state power loss, and to simplify resistive networks for device series connection. • High forward and reverse voltage blocking ratings to reduce the need for series device connection, which would otherwise complication control and protection circuitry requirements. Series connection increases the on-state voltage, hence on-state loss. When a diode is used in antiparallel across the switch to allow reverse principal current flow, the switch does not require a significant reverse voltage blocking rating. • High static off-state avalanche capability to absorb transient overvoltage stresses. • High static and re-applied dv/dt capability to withstand high applied off-state voltages without avalanche or false turn-on, with minimal displacement current. on-state (ideally short circuit): • Low on-state conducting voltage or low on-state resistance, in order to minimise onstate conduction power loss: with a slight positive temperature co-efficient at high current densities, to allow reliable parallel device connection. • High on-state current density capability so as to avoid need for and problems associated with parallel device current sharing and differential thermal coefficients. • Safe controlled switch off from a short circuit current condition. Switching (ideally instantaneous): • Low control power to produce switching between states, with no ‘Miller’ interaction. • Short, temperature independent, turn-on and turn-off times to result in low switching losses which will allow high frequency switching. • High initial di/dt capability at turn-on to allow rapid low loss build-up of the turn-on principal current. • High surge current capability to withstand transient over current fault conditions, resulting in better fault tolerance and nuisance tripping ride through. • Large switching safe operating area, being able to simultaneously, but briefly, support rated voltage and rated current, without the need for switch snubber circuits. Thermal/mechanical: • Easy to electrically connect and mechanically mount, with low thermal resistance and impedance for efficient heat removal. • Mechanically, electrically, and thermally robust, with the ability to operate at high (and low) junction temperatures in high (and low) ambient, pressure, humidity conditions. • Matching substrate structure and thermal properties to minimise stressing due to thermal, mechanical, and power stressing.

6.3

Switching classification

There are four principal I-V switching conditions during the commutation (turn-on or turn-off) of a switch, viz.:

• • • •

Hard switching; Soft switching; Resonant switching; and Naturally-commutated switching.

These four possibilities are classified in terms of the switching time ts and the commutation time tq, where tq ≤ ts. Figure 6.11 shows the four electrical cases and specifies the switching and commutation times for each.

• •

Switching time ts is the time for a switch to change from fully on (v = 0, i = IL) to fully off (v =Vs, i = 0), such that no further change occurs in the switch voltage or current due to the change of state. Commutation time tq is associated with the external circuitry and is defined as the time the switch takes to reach zero current at turn-off or to reach zero volts at turn-on. Alternatively, commutation time is the period of switch power loss at turn-on or turn-off, due to the switch changing states.

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Vs

Vs

vc

IL

W on

ic

t

tq

on

W off t

tq ts

Vs

vc

W on

IL

ic

t

tq

on

(b)

vc ic

off

W off t

tq

Soft Switching

ts

ts

t q < ts

Vs

vc

IL

W on

IL

ic

t

tq

on

(c)

vc ic

off

W off

ts

t q < ts

Vs

vc

W on = 0

IL

tq

IL

ic

vc

W off = 0 ic

tq

t

on

(d)

t

tq

Resonant Switching

ts

Vs

off

t q = ts

IL

Vs

(a)

ic

Hard Switching

ts

Vs

vc

IL

t

off

Naturally-commutated Switching

ts

tq = 0

ts

Figure 6.11. Switch voltage (vc), current (ic), and power loss (Won and Woff) of four switching classifications: (a) hard switching; (b) soft switching; (c) resonant switching; and (d) naturally-commutated switching.

Generally, the switch loss magnitude (stress) for a given set of electrical and thermal operating conditions, decreases when progressing from severe hard switching through to virtually lossless naturally-commutated switching. 6.3.1 Hard switching: tq = ts The turn-on and turn-off switching waveforms in figure 6.11a for an inductive load show that hard switching is characterised by tq = ts. The resistive and inductive switching considered in sections 6.1.1 and 6.1.2 are examples of hard switching. In figure 6.4 for a resistive load, the switching periods ton and toff (ts) correspond to the period of switch losses (tq) during each state transition. In figure 6.9 for the inductive load, the tq periods correspond to the power loss periods at switching (trv + tfi and tfv + tri).


166

6.3.2 Soft switching: tq < ts Figure 6.11b shows typical soft-switching waveforms for turn-on and turn-off. The switching losses are complete before the switch has reached its final steady-state condition. That is, ts > tq such that the periods ts and tq both commence at the same time. At turn-on, the switch voltage reaches zero before the switch current reaches the steady-state full-load value IL. Once the switch voltage reaches zero, the rising current no longer results in a power loss. This I-V characteristic at turn-on (usually involving inductance in series with the switch) is a form of quasi zero current switching, ZCS. The inverse occurs at turn-off. The switch current reaches zero before the switch voltage has settled at the supply voltage level Vs. (Usually involving capacitance in parallel with the switch.) This is a form of quasi zero voltage switching, ZVS. Soft-switching results when auxiliary stress diverting circuits, called snubber circuits, are used, as will be considered in chapters eight and nine. 6.3.3 Resonant switching: tq tq. Switching of the voltage when the switch current is zero, usually at turn-on, is called zero current resonant switching, ZCRS, while commutating the current while the switch voltage is zero, usually at turn-off, is called zero voltage resonant switching, ZVRS. Because the exact instant of zero may vary, being load circuit dependant, some control restriction is inevitable. Zero voltage or current switching can be readily attained with ac mains converter circuits since switching can be synchronised with supply zero voltage crossing, or zero current when the load current reverses due to the supply voltage reversal. 6.3.4 Naturally-commutated switching: W = 0, tq = 0 Figure 6.11d shows switching when the voltage and current are both zero, called naturally-commutated switching. This was a commonly used technique for force turn-off of thyristors before the exploitation of the GTO thyristor. Current from an auxiliary commutation circuit displaces (exceeds) the device principal current and reverse biases the device, at turn-off. The method was not used at turn-on. Commutated turn-on and turn-off occurs in inverter circuits where the switch has an anti-parallel connected diode. When the diode conducts and the switch is on but not conducting, if the load power factor causes the current to reverse, then the main switch automatically starts conducting with the switch voltage at zero because the diode was previously conducting, clamping the switch voltage slightly negative. Naturally-commutated switching occurs for ac mains zero crossing switching, with a purely resistive load such that the load V and I are in phase. Switching losses are virtually zero. 6.4

Switch configurations

Most semiconductor switches are unipolar, that is, allow current and/or voltage to be supported in one direction. The MOSFET allows uncontrolled reverse current flow; hence can not support reverse voltage because of its parasitic body diode. Some structures, like the RCT considered in chapter 3.3.3, integrate an anti-parallel diode with a thyristor. Generally, such integrated approaches sacrifice some electrical characteristics. Many applications require a bi-directional current and/or bi-directional supporting voltage switches, so the basic switches can be configured as shown in figure 6.12, to give the necessary I-V characteristics. The net effect of the bi-directional voltage arrangements is good dynamic electrical characteristics but poor static characteristics. Specifically, the switching performance is as for the principal switch but the on-state loss is that of two series connected devices. In the case of the bidirectional blocking thyristor, the on-state voltage is increased slightly because an n-buffer can not be used in its fabrication. The bi-directional conducting thyristor discussed in chapter 3.3.4 attempts to minimise the sacrificed on-state voltage limitation. A reverse blocking IGBT can also be realised. Die edge passivation of the diode region by a through the die p+ diffusion, plus guard rings, increase processing complexity, and hamper voltage ratings. A punch through IGBT version with reverse voltage blocking properties, is therefore problematic. On-state voltages are increased for a given switching speed and, as with the MOSFET body diode, the non-optimal diode recovery characteristics are a compromise because of the overriding n-substrate low resistivity requirements. See chapter 3.2.4. • Controllable switching devices with reverse blocking capability are usually required for ac to ac converters, half-wave resonant converters, and current fed inverters. • Voltage source inverters, full-wave resonant converters, and dc to dc converters usually do not require switching devices with reverse blocking properties, but may use an antiparallel connected diode.

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I V

P rin c ip a l C u rre n t u n id ir e c tio n a l b id ire c tio n a l

unidirectional

RCT

AS C R

AS C R

Voltage

IG B T

bidirectional

tria c

SSCR

¥ SSCR

SSCR

RB-IGBT

¥ Can be arranged so that emitters are at the same potential. Switches may be reverse blocking IGBTs. Figure 6.12. Switch configurations for uni-directional and bi-directional I-V characteristics.

Reading list Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978.


168

Problems 6.1.

During turn-on and turn-off of a power transistor the current-voltage relationships are as shown in figure 6.13. Calculate the energy loss during both turn-on and turn-off periods and the mean power loss if the transistor is being switched at a frequency of 10 kHz. What is the maximum instantaneous power dissipated? [1.66 mJ, 16.6 mJ, 183 W, 5kW]

Figure 6.13.

6.2.

The equivalent circuit in figure 2.4a involving parameters Eo and Ro can be extended to model a thyristor by replacing the ideal diode by an ideal thyristor. Derive general expressions for the thyristor mean power loss Pd and rms current io with a constant load current Io and switch ontime duty cycle δ. If Eo = 1 V and Ro = 0.01 Ohms, for Io = 50 A and a 25 per cent on-time duty cycle, calculate the thyristor: i. On-state voltage, VF ii. Mean power, Pd iii. rms current, io. [See example 2.1: 1.5 V, 18.75 W, 25 A]

6.3.

If the collector voltage at turn-on falls according to vc = ½Vs (1 + cos π t / To ) for 0 ≤ t ≤ To i. For a resistive load, RL, calculate transistor loss at turn-off. ii. Show that the switching trajectory across the SOA is as for the linear current fall case. iii. Calculate the peak power dissipation and when it occurs.

6.4.

A transistor is used to switch an inductive load with a current of Im. At transistor turn-off, the collector voltage rises to the supply rail Vs according to vce = ½Vs (1 - cos π t /Tov) for t ≤ Tov, then the collector current falls according to ic = ½Im(1 + cos π t /Toi) for t ≤ Toi. Using the same integration form as in equation (6.10), show that the turn-off loss is P = ½VsIm To where To = Tov + Toi.

7 Driving Transistors and Thyristors The thyristor, being a multiple (three) bipolar junction device, is essentially a current-controlled device. As illustrated in figure 7.1a, a current must be supplied between the gate and cathode terminals to produce cathode injection, hence anode current flow, provided the anode is forward biased. The magnitude of gate drive current determines the delay time and the anode current rise time. In gate commutated thyristors, a negative gate current must be produced, the magnitude determining the turnoff delay time and anode current fall time. The power MOSFET and IGBT are voltage controlled devices with turn-on and turn-off requirements fundamentally different to bipolar devices. With the n-channel enhancement-mode power MOSFET and IGBT, a positive voltage must be applied between the gate and source terminals to enhance a channel which allows a drain current, if the drain is positively biased with respect to the source, as shown in figure 7.1b. Generally the MOSFET and IGBT are easier to drive than the bipolar thyristor, and only a few basic considerations are required for MOSFET and IGBT gate circuit implementation. Gate current produces anode current

IA

+

iG

+

MOSFET

Figure 7.1. Thyristor and transistor drive requirements: (a) current drive for the bipolar junction thyristor and (b) voltage drive for the MOSFET and IGBT.

7.1

Application of the power MOSFET and IGBT

The MOSFET gate is isolated electrically from the source by a dielectric layer of silicon dioxide. Theoretically no current flows into the gate when a dc voltage is applied to it. In practice, gate current is required to charge device capacitances and a small leakage current of the order of nano-amps does flow in order to maintain the gate voltage. When no voltage is applied between the gate and source terminals (but with zero impedance), the drain-to-source impedance is very high and only a small leakage current of less than a milli-amp flows in the drain, until the applied voltage exceeds the drain-to-source avalanche voltage, VDSS. When a positive gate voltage is applied, an electric field is produced which modulates the drain-tosource resistance. When a gate voltage exceeds the threshold voltage level the channel resistance reduces to a low resistance and drain current flows. The maximum drain current depends on the gate voltage magnitude, assuming that the impedance of the external drain circuit is not current-limiting.

BWW

Driving Transistors and Thyristors

170

Turn off - reducing the drain current to the leakage current level - is achieved by reducing the gate voltage to below the gate threshold voltage level. The drain switching speeds are essentially determined by that speed at which the gate voltage can reach a level above the threshold voltage (for turn-on) or below the threshold voltage (for turn-off). Although the gate-to-source capacitance is an important parameter, the gate-to-drain capacitance is more significant because of the Miller effect, as considered in section 4.4.2. During switching, the dynamic gate-to-drain capacitance can be effectively much larger than the gate-to-source capacitance. The Miller capacitance typically requires more charge for switching than the gate-to-source capacitance.

74AC132

dv/dt=15kV/µs > td=0.1µs io =±2A 15V-30V

HCPL3210

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74AC132

Figure 7.2. Gate drive circuits for the MOSFET and IGBT: (a) driven from cmos; (b) driven from cmos and an emitter follower; (c) driven from ttl with pull-up resistor which increases sourcing capability; (d) driven from open collector ttl with an external current source; (e) driven from a high-current cmos clock driver; (f) opto-isolated driver circuit; (g) drive circuits for a totem pole connected p and n-channel MOSFET leg; (h) driven from a pulse transformer; and (i) fibre optic translation stage.

7.1.1

Gate drive circuits

The trench gate n-channel enhancement-mode power MOSFET (or IGBT) with a low threshold voltage interfaces easily with logic level integrated circuits. This allows low-power digital logic circuits to control directly high-power levels. Figure 7.2 shows a series of ttl and cmos circuits driving power MOSFETs, each circuit offering different levels of switching speed and performance. When driving a MOSFET directly from a cmos gate output, as shown in figure 7.2a, only modest rise and fall times can be expected because of the limited source and sink current available from a cmos gate. Figure 7.3a illustrates the output configuration of a typical cmos output stage, which consists of a seriesconnected p and n-channel MOSFET with the gates connected together. The cmos totem pole output stage is driven by a common signal, hence the name complementary mos - cmos - and when the input is high the n-channel device is on and the p-channel off, while when the input is low, the p-channel turns on and the n-channel turns off. However, cmos has a limited current output capability as shown in the 4049 source-to-sink output characteristics in figure 7.3b and c. The cmos gate output has to drive as a load the power MOSFET capacitive gate. In this configuration, the turn-on current is supplied from the pchannel fet, which has the poorer characteristics of the cmos pair. The turn-off current is sunk by the nchannel fet. Table 7.1 shows cmos typical current source and sink capabilities, switching speeds, and output impedance. It will be seen that the best performance, by far, is achieved from the 4049 and 4050 buffers. If shorter delays and faster drain rise and fall times are required there are several ways to obtain them. The simplest is to parallel a number of identical cmos inputs and outputs as shown dotted in figure 7.2a. The additional current capability, with the six parallel connected gates of the 4049, will significantly improve MOSFET switching performance. In figure 7.2b the gate drive current is the output current of the cmos gate multiplied by the gain β of the bipolar transistors. No bipolar saturation times are incurred since the transistors are operating as emitter followers, which cannot saturate. The operating frequency is no longer restricted by the cmos output current limitations.


172

MOSFETs can also be driven directly from ttl gates. Table 7.2 shows ttl typical current source and sink

capabilities and switching speeds. Low supply voltage, typically 5V, and high internal sourcing impedance characteristics, restrict MOSFET switch-on speed and gate voltage level. The ttl sink capability is significantly higher than source capability, hence a pull-up resistor as shown in figure 7.2c enables the sinking capability to be exploited at turn-on, as well as at turn off. A limitation of using ttl for driving MOSFETs is that the gate voltage is restricted to less than 5V, hence if the drain current is not to be restricted, low gate threshold voltage trench gate MOSFETs and IGBTs are used. An open collector ttl drive technique as shown in figure 7.2d overcomes the gate voltage limitation as well as improving the current source limit. Very fast switching speeds are attained with the capacitive driver shown in figure 7.2e. Such drivers can both source and sink typically 1.5 A in tens of nanoseconds. An isolated gate-to-source drive version is shown in figure 7.2f, where a floating 15 V rail is used and the gate control signal is optically transmitted with high dv/dt capability. The driver incorporates high current output, with modest propagation delays.

(a)

(b)

(c)

Figure 7.3. CMOS 4049 inverter output: (a) output cmos totem pole; (b) p-channel drain sourcing and (b) n-channel drain sinking, both at 25°C.

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Drive circuits for p-channel MOSFETs may be complicated by the reference signal voltage level, as shown in the series n and p-channel totem pole in figure 7.2g. This figure illustrates how the p-channel drive may be derived by means of a level shifter. The emitter follower, pnp transistor used for turn-on must have a breakdown voltage rating in excess of the totem pole rail voltage. Above 300 V the pnp transistor can be replaced by a diode as shown in figure 7.2d, or a low current high voltage MOSFET. Restricted charging of the translation MOSFET output capacitance can lead to increased delay times. The resistor divider, R1-R2, ensures that the p-channel gate voltage limit is not exceeded. In order to increase gate drive capability R2 can be decreased provided a 15 V Zener is used across the p-channel MOSFET gate to source. The low-voltage npn transistor in the p-channel driver stage is used for fast turn-off, shorting the p-channel source to its gate. A simple method of driving an n-channel MOSFET, with its source not referenced to ground, is shown in figure 7.2h. Electrical (galvanic) isolation is achieved by means of a pulse transformer. The internal parasitic diode in Q1 provides the path for the n-channel MOSFET gate to charge. When the pulse transformer saturates, Q1 blocks any discharge of the gate until turn-off, when a negative transformer pulse turns on Q1, thereby discharging the n-channel gate charge. An alternative translation method using a fibre optic stage is shown in figure 7.2i. The temperatureindependent, high threshold characteristics of 74AC technology is used for a simple detector comparator. A Schmitt input (hysteresis) gate (74AC132) improves noise immunity. In general, translation from ttl levels can be achieved with Zener diode bias circuits. From the circuits in figure 7.2 it is seen that there are two basic types of gate drives. • Low-side • High-side Essentially a low-side driver is one where the control signal and the power device gate are at almost the same potential. The lower switches in bridge legs normally use low-side drivers, while the upper switches require high-side drivers which translate the control signal and gate power to a different potential. The gate drive circuits 7.2a to 7.2e are basic low-side gate drive circuits. The high-side drivers in figures 7.2f to 7.2i translate the control signal to the gate level. Although the gate drive circuits in figures 7.2a to 7.2i translate the control signal to the device gate, these circuits do not address two important gate drive issues. • The derivation of the gate drive supply, particularly for floating gate drives as encountered in inverters. • The derivation of negative gate bias at turn-off for better immunity to false turn-on due to noise and induced Miller charging effects. 7.1.1i - Negative gate drive The gate drive circuits shown in figure 7.2 only clamp the gate to near zero volts during the off period. The lower bridge leg switch in figure 7.4 uses ±15V gate voltages. The complementary buffers drive the gate-source of the shown device in an H-bridge configuration. The buffers require an isolated 15V dc supply. Since the 15V dc supply is isolated, the complementary buffers can be used for high side gate drives, provided the control signal is isolated, as in figure 7.2i. Practically a negative gate bias of -5V is sufficient for noise immunity while any voltage in excess of this unnecessarily increases turn-on delay and increases gate power requirements. Manufacturers are continually improving power device properties and characteristics. Gate threshold voltage levels are constantly being decreased, and coupled with the fact that the threshold voltage decreases with temperature, negative voltage gate drive is necessary for high noise immunity to prevent false turn-on with high power devices. Gate capacitance improves noise immunity. 7.1.1ii - Floating power supplies There are three basic methods for deriving floating power supplies for gate drives. • A low inter-winding capacitance, high-frequency transformer • A capacitive coupled charge pump • A diode bootstrap The upper bridge leg switch Tu in figure 7.4 uses both a diode bootstrap via Dbs and a single ended capacitor charge pump via Ccp, in order to derive gate power. 1 - capacitive coupled charge pump By switching Tcp at high frequency the low-capacitance, high-voltage capacitor Ccp is successively charged through Dcp1 and discharged through Dcp. Discharge through Dcp involves charging Cgs, the gate voltage supply capacitor. The shown charge and discharge paths both rely on either the upper switch Tu or diode Du being in a conducting state.

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Vs

Dcp

Vgg

+15V wrt 0V

Dbs

+

Tu

on/off

Cgs

Du

bootstrap circiut Dcp1

off on

+ charge-pump circiut

output

Single rail floating supply

Ccp on/off

Tℓ

Q _ Q

Tcp

Dℓ

0V

Figure 7.4. Typical IGBT bridge leg showing ±15V gate drive on the leg lower switch and charge pump plus boot strap gate supply circuits for the leg upper switch.

2 - diode bootstrap When the lower switch Tℓ or diode Dℓ conduct, high voltage diode Dbs allows the upper gate supply capacitor Cgs to charge from a 15V dc supply which is referenced to the 0V dc rail. When the upper switch or diode conduct, the bootstrap diode is reverse bias and supports Vs + Vgg. Start-up is a problem since the gate of the upper switch Tu is in a high impedance state while its supply is being charged after the lower switch is turned on. For this reason, the boot strap is usually used in conjunction with a capacitor charge pump. The only foolproof method to ensure gate power at all times, particularly at start-up and during prolong on-state periods, is to use a high-frequency (power and/or signal) transformer approach. 7.1.2

Gate drive design procedure

The effective gate to source capacitance, Cin, can be calculated from Cin δ Qg / δVgs

(7.1)

The initial slope of the charge in figure 7.5a, 740 pF, is due to the gate source capacitance charging below the gate threshold level. The next charge section between Qg1 and Qg2 in figure 7.5c is due to the Miller effect. The horizontal charge portion is due to the very high drain-source depletion field capacitance as the drain falls below the gate voltage level. The drain switching times, similar to those derived in 4.4.2, can be calculated from the charge transfer characteristics in figure 7.5, using the following equations. (i) From figure 7.5c, for turn-on Qg 1 Vgg td on = Rg An ( ) (s) (7.2) Vg 1 Vgg - Vg 1 tr =

(ii)

Qg 2 - Qg 1 Vg 2 - Vg 1

Rg An (

Vgg - Vg 1 Vgg - Vg 2

)

From figure 7.5d, for turn-off Qg 2 - Qg 2 Vgg td off = Rg An Vg 2 - Vg 2 Vg 2 tf =

Qg 2 - Qg 1 Vg 2 - Vg 1

Rg An

Vg 2 Vg 1

where Rg is the gate equivalent series resistance and Vg1 = VTH.

(s)

(7.3)

(s)

(7.4)

(s)

(7.5)


176

Figure 7.5. Typical MOSFET charge transfer characteristics at: (a) turn-on; (b) turn-off; (c) turn-on showing switching parameters; and (d) turn-off showing switching parameters.

The energy required for switching is given by W = ½Qg 3Vgg

(J)

(7.6)

which will be dependent on the drain current and voltage. The gate drive power requirements are given by P = Qgs Vg 3 f s (W) (7.7) Obviously the faster the switching speed requirement, the higher and faster the gate drive current delivery necessary. If only 15 mA is available for gate drive then, based on figure 7.5, switching occurs in about 1 µs (from Q = I×t). This level of performance could be expected with circuit 7.2a, and slower switching for the circuit in figure 7.2c. By employing the gate drive in figure 7.2c, the gate voltage is limited to 5 V, hence the MOSFET represented by figure 7.5 could not be switched. The circuits in figures 7.2b and 7.2d are capable of delivering about 100 mA, which yields switching speeds of the order of 150 ns, with only 50 mW of drive power dissipation at 100 kHz. The drive circuit in figure 7.2e is capable of delivering ± 1.5 A. Hence the device characterised by figure 7.5 can be switched in only 10 ns. Switching times deteriorate slightly if reverse gate-to-source biasing is used for higher noise immunity in the off-state. Analysis of the increase in turn-on delay as a result of the use of negative gate drive is presented in Appendix 4.8.

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Example 7.1:

MOSFET input capacitance and switching times

A MOSFET switching a resistive load has the following circuit parameters: Rg = 47Ω, RL = 100Ω Vgg = 10 V,

Vds = 400 V

Based on the charge transfer characteristics in figure 7.5, calculate the gate input capacitance and switching times for MOSFET turn-on and turn-off. Solution The charge transfer characteristics shown in figure 7.5 are valid for a 100 Ω resistive load and a 0-10 V gate voltage. A 400 V drain switching characteristic is shown. At turn-on, from figure 7.5a and using equations (7.2) and (7.3) (i) Cin = Cgs = Qg1 / Vg1 = 4.4 nC / 6V = 740 pF td on = 740 pF × 47Ω ℓn (10V/10V-6V) = 31.9 ns (ii)

Cin = (Qg2 - Qg1) / (Vg2 - Vg1) = 5.6 nC / 1.5V = 3.7 nF tr = 3.7 nF × 47Ω ℓn 5.6V/2.5V = 141.3 ns

At turn-off, from figure 7.5b and using equations (7.4) and (7.5) (i) Cin = (Qg3 - Qg2) / (Vgg - Vg2) = 7.5 nC / 2.5V = 3 nF td off = 3 nF × 47Ω ℓn 10V/7.5V = 40 ns (ii) Cin = (Qg2 - Qg1) / (Vg2 - Vg1) = 7.5 nC / 0.9V = 8.3 nF = 8.33 nF × 47Ω ℓn 7.5V/6.6V = 50 ns tf An underestimate of the fall time results if figure 7.5a is used for both turn-on and turn-off calculations (Cin = 3.7 nF and tf = 39.1 ns).

♣

7.2

Application of the Thyristor

The basic gate requirements to trigger a thyristor into the conduction state are that the current supplied to the gate is • of adequate amplitude and sufficiently short rise time • of sufficient duration. The gate conditions are subject to the anode being forward-biased with respect to the cathode. Figure 7.6 illustrates a typical thyristor gate current waveform for turn-on. The initial high and rapid current quickly turns on the device so as to increase the anode initial di/dt capability. After a few microseconds the gate current can be decreased to a value in excess of the minimum gate requirement. After the thyristor has latched on, the gate drive may be removed in order to reduce gate power consumption, namely the losses. In some inductive load applications, where the load current lags, a continuous train of gate pulses is usually applied to ensure turn-on. Gate drives can be divided broadly into two types, either electrically isolated or non-isolated. To obtain electrical isolation usually involves the use of a pulse-transformer or an opto-coupler but above a few kilovolts fibre-optic techniques are applicable. fast rise-time for improved anode initial di/dt

slow fall to prevent unwanted turn-off

IG

continuous gate current to maintain all GTO cathode islands in conduction

minimum pulse length to ensure all GTO cathode islands conduct

Figure 7.6. Ideal thyristor gate current waveform for turn-on.


7.2.1

178

Thyristor gate drive circuits

Only low-power thyristors with amplifying gates can be triggered directly from ttl or cmos. Usually a power interface stage is employed to convert ttl current sink and source levels of a few milliamps up to the required gate power levels. Figure 7.7a and b shows two power interface circuits for triggering a triac. The triac could equally be another thyristor device. An important safety default feature of both these circuits is that no active device exists between the gate and Ml. During the off-state the gate is passively clamped by the resistor Rg to a voltage well below the minimum voltage level for turn-on. Bidirectional gate current can bring the triac into conduction. Figures 7.7c and d show how negative gate turn-on current can be derived.

(c)

(e)

(d)

(f)

Figure 7.7. Integrated circuit compatible triac gate drive circuits: (a) high level ttl activation;(b) low level ttl activation using an interfacing pnp transistor; (c) negative gate drive interface with high ttl output for triac activation;(d) negative gate drive interface with low ttl level for triac turn-on; (e) a triac opto-coupler isolated gate drive used to gate-drive a higher power triac and (f) a pulse transformer drive isolated gate drive for a thyristor.

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If electrical isolation between the control circuitry and the power thyristor circuit is required, a simple triac opto-coupler can be employed as shown in figure 7.7e. The photo-triac is optically turned on which allows bidirectional main triac gate current to flow, the magnitude of which is controlled by the highvoltage resistor Rg. If the main device is an SCR, an opto-coupled SCR can be used for isolation and unidirection gate triggering current. When suitable voltage rails are not available or isolation is required, a pulse transformer drive circuit can be employed as shown in figure 7.7f. The diode/Zener diode series combination across the pulse transformer primary provides a path for primary magnetising current decay at turn-off and prevents saturation. The resistor R limits the secondary current into the SCR gate. This resistor can be placed in the pulse transformer primary or secondary by transforming the resistance in the turns ratio squared. If R is in the primary circuit and transformer saturation inadvertently occurs, the resistor R limits the current and protects the switching transistor Ts. The transformer secondary resistor R2 is employed to decrease the gate to cathode impedance, thereby improving dv/dt capability, while the gate diode Dr prevents possible reverse gate voltage breakdown after Ts is turned off and the output voltage reverses during core reset. The transformer duty cycle must satisfy toff Vz ≥ ton Vs, neglecting R. 7.2.2

Thyristor gate drive design

In order to design a thyristor gate interface circuit, both the logic and thyristor gate requirements must be specified. Consider interfacing a typical ttl-compatible microprocessor peripheral which offers the following specification I OH = 0.3mA @ VOH = 2.4V I OL = 1.8mA @ VOL = 0.4V Vcc = 5V

These specifications are inadequate for turning on a power thyristor or an optical interfacing device. If the power thyristor gate, worst case requirements are I GT = 75 mA, VGT = 3 V @ - 65°C then a power interfacing circuit is necessary. Figure 7.8 shows an interfacing circuit utilising a p-channel MOSFET with the following characteristics Cgs = 400 pf VTH = 3.0V Rds ( on ) = 10 ohms

I d = 0.5A

Figure 7.8. Interfacing a microprocessor to a power thyristor.

The resistor R1 limits the MOSFET Cgs capacitance-charging current and also specifies the MOSFET turnon time. If the charging current is to be limited to 1.8 mA when VOL = 0.4 V, then R1 = (Vcc - VOL ) / I OL (ohms)

= (5V - 0.4V) /1.8mA = 2.7 kilohms A smaller resistance could be used but this would not preserve the microprocessor low-voltage output level integrity if it were also being used as input to ttl logic. The MOSFET will not turn on until Cgs has charged to 3 V or, with a 5 V rail, approximately one R-C time constant. That is


tdelay =

Ri Cgs

180

(s)

= 2.7 kilohms × 400 pF = 1 µs The MOSFET must provide the thyristor gate current and the current through resistor R3 when the gate is at 3 V. The maximum value of resistor R2 is when R3 = ∞ and is given by Vcc - VGT - I GT × Rds ( on ) R2 = I GT =

5V - 3V - 75 mA x 10Ω 75 mA

= 16.6 ohms

Use R2 = 10 ohms. The resistor R3 provides a low cathode-to-cathode impedance in the off-state, thus improving SCR noise immunity. When VGT = 3 V V - VGT I d = cc (A) Rds ( on ) + R2 5V-3V = 100 mA 10Ω+10Ω of which 75 mA must flow into the gate, while 25 mA can flow through R3. That is R3 = VGT /( I d - I GT ) (ohms) =

= 3 V/25 mA = 120 ohms After turn-on the gate voltage will be about 1 V, hence the MOSFET current will be 200 mA. Assuming 100 per cent on-state duty cycle, the I2R power loss in the MOSFET and resistor R2 will each be 0.4 W. A 1 W power dissipation 10 ohm resistor should be used for R2. Example 7.2:

A light dimmer

A diac with a breakdown voltage of ±30 V is used in a light dimming circuit as shown in figure 7.9. If R is variable from 1 kΩ to 22 kΩ and C = 47 nF, what are the maximum and minimum firing delays? What is the controllable output power range with a 10Ω load resistor?

Figure 7.9. Light dimmer.

Solution The capacitor voltage vc is given by - j / ωC vc = × 240∠0° R - j / ωC 1 = × 240∠0° 1 + jωCR i. For R = 1 kΩ vc = 237.36 ∟-8.4° that is, vc = 335.8 sin (ωt - 8.4°) The diac conducts when vc = 30V, that is minimum delay = ωt = 8.4° + sin-1 (30V/335.8V) = 13.5° ii.

For R = 22 kΩ vc = 70.6 ∟-72.8° that is, vc = 99.8 sin (ωt – 72.8°) The diac conducts when vc = 30V, that is minimum delay = ωt = 72.8° + sin-1 (30V/99.8V) = 92°

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The maximum power output, if continuous conduction were possible, is Plo = 240V 2 /10Ω = 5760W. From equation (12.16), the output power for a resistive load is given by 2 2 2α −sin2α V (W) Po = rms = V 1 − 2π R R 2402 × 1 − 2×92°−sin2×92° = 2862W Minimum power at α = 92° (1.6 rad) is Po = 2π 10Ω

{

}

{

Maximum power at α =13½° (0.24 rad) is Po =

}

{

}

2402 × 1 − 2×13½°−sin2×13½° = 5536W 2π 10Ω

♣

7.3

Drive design for GCT and GTO thyristors

The gate turn-off thyristor is not only turned on from the gate but, as its name implies, is turned off from its gate with negative gate current. Basic GTO thyristor gate current requirements are very similar to those for the power bipolar transistor (now virtually obsolete) when reverse base current is used for fast BJT turn-off.

R3 Tt

Ron

DDbb DDasas R1

R4

Ls Tn

X Tp

R2

Roff

Figure 7.10. Gate drive circuit and anode snubber circuits for a GTO thyristor.

Figure 7.10 shows a gate drive circuit for a GTO thyristor which is similar to that historically used for power bipolar junction transistor base drives. The inductor L, in figure 7.10, is the key turn-off component since it controls the di/dt of the reverse gate current. The smaller the value of L, the larger the reverse di/dt and the shorter the turn-off time. But with a shorter turn-off time the turn-off gain decreases, eventually to unity. That is, if the GTO thyristor is switched off rapidly, the reverse gate current must be of the same magnitude as the anode current to be extinguished. A slowly applied reverse gate current di/dt can produce a turn-off gain of over 20 but at the expense of increased turn-off saturation delay and switching losses. For the GTO thyristor L is finite to get a turn-off gain of more than one, while to achieve unity gain turn-off for the GCT, L is minimised. The GTO thyristor cathode-to-gate breakdown voltage rating VRGM specifies the maximum negative rail voltage. A level of -15 to -20V is common, and for supply rail simplicity a ± 15 V rail may be selected. Resistor R4 limits the base current of Tt. If an open collector ttl driver is employed, the current through R4 is given by I OL = (Vcc − VbeT − VDb − VOL ) / R4 (A) t


182

For the open collector 74 ttl series, IOL = 40 mA when VOL = 0.5 V whence R4 can be specified. The resistor R3 speeds up turn-off of Tt. It is as large as possible to ensure that minimal base current is diverted from Tt. Diodes Db and Das form a Baker’s clamp, preventing Tt from saturating thereby minimising its turn-off delay time. The two driver transistor Tn and Tp should

• • •

have high gains be fast switching have collector voltage ratings in excess of Vcc + VEE.

The GTO thyristor gate turn-on current is determined by resistor Ron, which is specified by V − V − VGC Ron = cc ceT (Ohms) IG The power rating of Ron is given by PR = δ (Vcc − VceT − VGC ) I G (W) n

on

n

where δ is the maximum on-state duty cycle. The capacitor Con, in parallel with Ron, provides a short current boost at turn-on, as shown in figure 7.6, thereby speeding up turn-on, increasing turn-on initial di/dt capability, and reducing turn-on losses. The series resistors R1 and R2 bias the bases of the totem pole level shift driver and, for an on-condition, the potential of point X in figure 7.10 is given by VX = VbeT + VGC (V) n

The total current flow through R1 is made up of the transistor Tn base current and that current flowing through R2, that is I V + VEE (A) I R1 = G + X βT R2 n

from which The power rating of R1 is

R1 = (Vcc - VX ) / I R1

(ohms)

PR1 = δ (Vcc − VX ) I R1

(W)

For fast turn-off, if the reverse gate current at turn-off is to be of the same magnitude as the maximum anode current, then R2 must allow sufficient base current to drive Tp. That is VX + VbeT (ohms) R2 = I c / ββ p p

Once the gate-to-cathode junction of the GTO has recovered, the reverse gate current decays to the leakage level. The power rating of R2 can be low at lower switching frequencies. The small inductor L in the turn-off circuit is of the order of microhenrys and it limits the rate of rise of reverse gate current, while Roff damps any inductor current oscillation. The turn-on and turn-off BJT output totem pole in figure 7.10 can be replaced by suitable n-channel MOSFET circuitry in high power GCT and GTO thyristor applications. In high power IGCT applications, MOSFETs and rail decoupling electrolytic capacitors are extensively parallel connected. Typically 21 capacitors and 42 MOSFETs are parallel connected to provide a low impedance path for unity anode current extraction from the GCT gate. The gate inductance (including the GCT internal package inductance) is minimised, whence L is zero. Typically, the IGCT gate drive, gate connection, and internal package inductance are each about 2 nH. This is achieved by minimising lengths, capacitive decoupling, and using parallel go and return paths. As a result, gate reverse di/dt’s of over 5kA/µs are attainable with a -15V dc negative gate supply. Table 7.3 Gate drive isolation techniques summary Technique

data transfer

power transfer

Transformer

direct signal coupling

direct magnetic transfer

opto-coupler

slow, with capacitive effects

n/a

fibre optics

fast, virtually no voltage limit

n/a

charge couple

n/a

requires switching

bootstrap

n/a

requires switching

comments duty cycle limited corona breakdown limit voltage and dv/dt limit best signal transmission at MV and HV induced effects between ground level and gate level, LV application

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Reading list International Rectifier, HEXFET Data Book, HDB-5, 1987. Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978. Siliconix Inc., Mospower Design Catalog, January 1983. Grafham, D. R. et al., SCR Manual, General Electric Company, 6th Edition, 1979.

Problems 7.1.

Calculate suitable resistor values for the triac gate drive circuit in figure 7.7a, assuming a minimum gate current requirement of 50 mA and the gain of Q1 is 50 at 50 mA.

7.2.

Repeat problem 7.1 for the circuits in figures • 7.7b • 7.7c • 7.7d.

7.3.

Repeat example 7.3 assuming a 2V triac gate threshold voltage for turn-on.


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184

8 Protecting Diodes, Transistors, and Thyristors

All power switching devices attain better switching performance if some form of switching aid circuit, called snubber, is employed. Snubber activation may be either passive or active which involves extra power switches. Only passive snubbers, which are based on passive electrical components, are considered in this chapter, while active snubbers are considered in Chapter 9. Fundamentally, the MOSFET and IGBT do not require switching aid circuits, but circuit imperfections, such as stray inductance and diode recovery, can necessitate the need for some form of switch snubber protection. Protection in the form of switching aid circuits performs three main functions: • • •

Divert switching losses from the switch thereby allowing a lower operating temperature, or higher electrical operating conditions for a given junction temperature. Prevent transient electrical stressing that may exceed I-V ratings thereby causing device failure. Reduce conducted and radiated electromagnetic interference

Every semiconductor switching device can benefit from switching protection circuits, but extra circuit component costs and physical constraints may dictate otherwise. The bipolar diode suffers from reverse recovery current and voltage snap which induces high but short duration circuit voltages. These voltage transients may cause interference to the associated circuit and to nearby equipment. A simple series non-polarised R-C circuit connected in parallel to the stressed or offending device is often used to help suppress the voltage oscillation at diode turn-off. Such a suppression circuit can be effectively used on simple mains rectifying circuits when rectification causes conducted and radiated interference. Although the MOSFET and IGBT can usually be reliably and safely operated without external protection circuitry, stringent EMC application emission restrictions may dictate the use of snubbers. In specific applications, the IGBT is extensively current derated as its operating frequency increases. In order to attain better device current utilization, at higher frequencies, various forms of switching aid circuits can be used to divert switching losses from the stressed semiconductor switch. Generally, all thyristor devices benefit from a polarised turn-on switching aid circuit, which is based on a series connected inductor that is active at thyristor turn-on. Such an inductive turn-on snubber is obligatory for the high-power GCT and GTO thyristor. In order to fully utilise the GTO thyristor, it is usually used in conjunction with a parallel-connected capacitive turn-off snubber, which decreases device stressing during the turn-off transient. Triacs and rectifier grade SCRs and diodes tend to use a simple R-C snubber connected in parallel to the switch to reduce interference. The design procedure of the RC snubber for a diode is different to that for the R-C snubber design for a thyristor device, because the protection objectives and initial conditions are different. In the case of a thyristor or rectifier diode, the objective is to control both the voltage rise at turn-off and recovery overshoot effects. For the fast recovery diode or any high-speed switch, the principal objectives are to control the voltage overshoot magnitude at diode snap recovery or at turn-off respectively, which are both exacerbated because of stray circuit inductance carrying current.

BWW

Protecting Diodes, Transistors, and Thyristors

8.1

186

The non-polarised R-C snubber

The series R-C snubber is the simplest switching aid circuit and is connected in parallel to the device being aided. It is characterized by having low series inductance and a high transient current rating. These requirements necessitate carbon type resistors for low inductance, below a few watts, and metal film resistors at higher powers. The high current and low inductance requirements are also provided by using metallised, polypropylene capacitors with high dv/dt ratings of typically hundreds of V/µs. Theoretically a purely capacitive snubber would achieve the required protection objectives, but series resistance is added to decrease the current magnitude when the capacitor is discharging and to damp any voltage oscillation by dissipating the oscillatory energy generated at turn-off when an over-voltage tends to occur.

L O A D s t r a y

s n u b b e r

Figure 8.1. MOSFET drain to source R-C snubber protection: (a) MOSFET circuit showing stray inductance, Ls, and R-C protection circuit and (b) R-C snubber optimal design curves.

8.1.1

R-C switching aid circuit for the GCT, the MOSFET, and the diode

In figure 8.1a, at switch turn-off, stray inductance Ls unclamped by the load freewheel diode, Df, produces an over voltage Vˆ on the MOSFET or IGBT. The energy associated with the inductor can be absorbed in the shown drain to source connected R-C circuit, thereby containing the voltage overshoot to a controlled safe level. Such an R-C snubber circuit is used extensively in thyristor circuits, 8.1.2, for dv/dt protection, but in such cases the initial current in the stray inductance is assumed zero. Here the initial inductor current is equal to the maximum load current magnitude, Iℓ. The design curves in figure 8.1b allow selection of R and C values based on the maximum voltage overshoot Vˆ and an initial current factor χ, defined in figure 8.1b. The C and R values are given by C = Ls ( IA / χ Vs ) 2 (F) (8.1) χ R = 2 ξ Vs / IA (Ω) (8.2) If the R-C circuit time constant, τ = RC, is significantly less than the MOSFET voltage rise and fall times, trv and tfv, at reset (when the capacitor is discharged through the resistor and switch at turned on), a portion of the capacitor energy ½CV , is dissipated in the switch, as well as in R. The switch appears as a variable resistor in series with the R-C snubber. Under these conditions (tfv and trv > RC) the resistor power loss is approximately by PR = PRon + PRoff 2

s

=

τ τ P + ( P + PL 0 ) τ + t fv C 0 τ + trv C 0

(W)

(8.3)

where PC 0 = ½CVs 2 f s and PL 0 = ½ Ls I A2 f s otherwise (tfv and trv < RC) the resistor losses are the energy to charge and discharge the snubber capacitor, plus the energy stored in the stray inductance, that is 2PC0 + PL0. Note the total losses are independent of snubber resistance. The snubber resistor determines the time over which the energy is dissipated, not the amount of energy dissipated. When the R-C snubber is employed across a fast recovery diode, the peak reverse recovery current is used for Iℓ in the design procedure.

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Example 8.1: R-C snubber design for MOSFETs A MOSFET switches a 40 A inductive load on a 200 V dc rail, at 10 kHz. The unclamped drain circuit inductance is 20 nH and the MOSFET voltage rise and fall times are both 100 ns. Design a suitable R-C snubber if the MOSFET voltage overshoot is to be restricted to 240 V (that is, 40V overshoot, viz. 20%). Solution From figure 8.1b, for 20 per cent voltage overshoot

ξ = 1.02, χ = 0.52 Using equations (8.1) and (8.2) for evaluating C and R respectively, 2

40A   C = Ls ( I A / χ Vs ) 2 = 20nH   = 3nF 0.52×200V   0.52×200V R = 2 ξ Vs χ / I A = 2 × 1.02 × = 5.3Ω 40A Use C = 3.3 nF, 450V dc, metallised polypropylene capacitor and R = 5.6 Ω.

Since the RC time constant, 18.5ns, is short compared with the MOSFET voltage transient times, 100ns, the resistor power rating is given by equation (8.3). PC 0 = ½CVs2 f s = ½×3.3nF ×200 2 ×10kHz = 2.64W PL 0 = ½ Ls I A2 f s = ½×20nH × 402 × 10kHz = 0.16W PR =

18.5ns 100ns + 18.5ns

×2.64W +

18.5ns 100ns + 18.5ns

× (2.64W + 0.16W) = 0.85W

Use a 5.6 Ω, 1 W carbon composition resistor for low self inductance, with a working voltage of at least 250V dc. Parallel connection of two 12Ω ½W, carbon composition resistors may be necessary since resistance values below 10Ω are uncommon. The MOSFET switching losses are 2WC 0 + PL 0 − 0.85W = 4.95W higher than those incurred by switching un-aided at 200V and 40A. From equations 6.9 and 6.10, the switching losses would be at least 8W, (4W+4W).

♣

8.1.2

Non-polarised R-C snubber circuit for a converter grade thyristor and a triac

The snubber circuit for a low switching frequency thyristor is an anode-to-cathode parallel connected RC series circuit for off-state voltage transient suppression. Thyristor series inductance may be necessary (forming a turn-on snubber) to control anode di/dt at turn-on. This inductive snubber is essential for the GCT and the GTO thyristor, and will be considered in section 8.3.3. Off-state dv/dt suppression snubber Thyristors, other than the GCT and the GTO thyristor, normally employ a simple R-C snubber circuit as shown in figure 8.2. The purpose of the R-C snubber circuit is not primarily to reduce turn-off switching loss but rather to prevent false triggering (turn on) from applied or reapplied anode dv/dt, when the switch is in a forward voltage blocking off-state. Any thyristor rate of rise of forward-voltage anode dv/dt produces a central junction charging current which may cause the thyristor to inadvertently turn on. The critical dv/dt is defined as the minimum value of dv/dt which will cause switching from the off-state to the on-state. In applications as shown in figure 8.2, an occasional false turn-on is generally not harmful to the triac or the load, since the device and the load only have to survive the surge associated with a half-a-cycle of the ac mains voltage supply. In other applications, such as reversible converters, a false dv/dt turn-on may prove catastrophic. A correctly designed snubber circuit is therefore essential to control the rate of rise of anode voltage. The action of this R-C snubber circuit relies on the presence of inductance in the main current path. The inductance may be stray, from transformer leakage or a supply, or deliberately introduced. Zero inductor current is the initial condition, since the device is in the off-state when experiencing the anode positive dv/dt. Analysis is based on the response of the R-C portion of an L-C-R circuit with a step input voltage and zero initial inductor current. Figure 8.3 shows an L-C-R circuit with a step input voltage and the typical resultant voltage across the SCR or R-C components. The circuit resistor R damps (by dissipating power) any oscillation and limits the capacitor discharge current through the SCR at subsequent SCR device turn-on initiated from the gate. The snubber resistor dissipates power even if the triac is not switching, since the snubber capacitor voltage alternates, tracking the ac voltage supply.


188

R-C snubber

Figure 8.2. Thyristor (triac) ac circuit with an R-C snubber circuit.

Figure 8.3. Non-polarised R-C snubber equivalent circuit showing the second-order output response eo to a step input voltage es.

1

(0.265, 0.81)

∧

Figure 8.4. Variation of snubber peak voltage, eo, maximum deo /dt, S ; and peak current, Ip; with L-C-R damping factor ξ.

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Based on the snubber∧ circuit analysis presented in the appendix in section 8.5 at the end of this chapter, the maximum dv/dt, S , which is usually specified for a given device, seen by the SCR for a step input of magnitude es, is given by ∧

S = es R / L (V/s) for a damping factor of ξ > ½. That is, after rearranging, the snubber resistance is given by ∧

R = L S / es while the snubber capacitance is given by 4ξ 2 es C= ∧ RS

(8.4)

(ohms)

(8.5)

(F)

(8.6)

and the peak snubber current is approximated by e 2ξ Iˆ = s for ξ < 1. (A) R 1−ξ 2

(8.7)

Figure 8.4 shows the variation of the different normalised design factors, with damping factor ξ.

Example 8.2:

Non-polarised R-C snubber design for a converter grade thyristor

Design an R-C snubber for the SCRs in a circuit where the SCRs experience an induced dv/dt due to a complementary SCR turning on, given • peak switching voltage, es = 200 V • operating frequency, fs = 1 kHz • dv/dt limit, S = 200 V/µs. Assume • stray circuit L = 10 µH • 22 per cent voltage overshoot across the SCR • an L-C-R snubber is appropriate. Solution From equation (8.5) the snubber resistance is given by ∧

R = L S / es 10µH×200V/µs = 10Ω 200V At turn-on the additional anode current from the snubber capacitor will be 200V/10Ω = 20A, which decays exponentially to zero, with a 1.8µs (10Ω×180nF) RC time constant. ∧ Figure 8.4 shows the R-C snubber circuit overshoot magnitude, e 0 / es for a range of damping factors ξ. The normal range of damping factors is between 0.5 and 1. Thus from figure 8.4, allowing 22 per cent overshoot, implies ξ = 0.65. From equation (8.6) 4ξ 2 es 4 × (0.65) 2 × 200V C= = ∧ 10Ω × 200 × 106 RS =

= 180 nF (preferred value) rated at 244 V peak.

From equation (8.7) the peak snubber current during the applied dv/dt is e 2ξ Iˆ = s R 1−ξ 2 200V 2×0.65 = 34 A 10Ω 1-0.652 The 10 ohm snubber resistor losses are given by P10 Ω = C e02 f s =

= 180×10-9 ×2442 ×1×103 = 11W Resistor current flows to both charge (maximum 34A) and discharge (initially 20A) the capacitor. The necessary 10Ω, 11W resistor must have lower inductance, hence two 22 Ω, 7W, 500V dc working voltage, metal oxide film resistors can be parallel connected to achieve the necessary ratings. ♣


190

Variations of the basic R-C snubber circuit are shown in figure 8.5. These circuits use extra components in an attempt to control SCR initial di/dt arising from snubber discharge through RL at thyristor turn-on. Figure 8.5a has the disadvantage that three series devices (C-Rs-D) provide turn-off protection. The parasitic series inductance can be decreased by using a turn-off snubber with two series components (C-D), as shown in figure 8.5b. An R-C snubber can be used across a diode in order to control voltage overshoot at diode snap-off during reverse recovery, as a result of stray circuit inductance, as considered in 8.1.1. The R-C snubber can provide decoupling and transient overvoltage protection on both ac and dc supply rails, although other forms of R-C snubber circuit may be more applicable, specifically the soft voltage clamp.

D

D C

Figure 8.5. Polarised variations of the basic thyristor R-C snubber: (a) Rs 2

Example 8.3:

Soft voltage clamp design

A 5 µH inductor turn-on snubber is used to control diode reverse recovery current and switch turn-on loss, as shown in figure 8.6a. The maximum collector current is 25 A, while the switch minimum off-time is 5 µs and the maximum operating frequency is 50 kHz. i.

Assuming an independent L-C resonant transfer from L to C and a subsequent R-C discharge cycle, calculate soft voltage clamp R and C requirements. ii. Use figure 8.7 to determine the voltage clamp requirements if the discharge (reset) resistor inductance LR is (a) 0 (b) 1.0µH.

In each case, the maximum switch overshoot is to be restricted to 50 V.


192

Figure 8.7. Voltage clamp capacitor normalised peak over-voltage, VCp' , versus damping factor, ξ, for different resistor normalised inductances, L’, and voltage and current normalised settling times, tvr' , tir' = Vcp /{I m L / C } , tvr' = trv / ω0 , tir' = tir / ω0 .

Solution i. Assuming all the inductor energy is transferred to the clamp capacitor, before any discharge through R occurs, then from equation (8.11), for a 50 V capacitor voltage rise 50 = I m L C that is, C = 5 µH/(50V/25A)2 = 1.25 µF (use 1.2 µF, rated at, at least 50V above the dc supply Vs). From equation (8.9), for R = 0, the energy transfer time (from L to C) is tir = ½π LC = ½π 5µH×1.25µF = 4µs which, as required, is less than the switch minimum off-time of 5 µs. If the maximum operating frequency is 50 kHz, the capacitor must discharge in 20 - 4 = 16 µs. Assuming five RC time constants for capacitor discharge 5 × RC = 16µs R = 16µs/(5×1.2µF) = 2 2 3 Ω (use 2.4Ω) The resistor power rating is PR = ½ LI m2 f s = ½×5µH×252 ×50kHz = 78W Obviously with a 2.4 Ω discharge resistor and 50V overshoot, discharge current would flow as the capacitor charges above the voltage rail. A smaller value of C could be used. A more accurate estimate of C and R values is possible, as follows. ii. (a) LR = 0, that is L′ = LR /L = 0 From figure 8.7, for the minimum voltage reset time, as indicated Vcp' = 0.46, tir' = 2.90, trv' = 4.34, and ξ = 0.70 From Vcp' = Vcp / I m L

C

0.46 = 50V/25A 5µH

From

C

gives C = 0.27µF

1 5µ H ξ = 1 2 R L C , R = 1 2ξ L C = = 3.2Ω 0.27µ F 2×0.7

(Use 3.3 Ω, 78 W)

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The reset times are given by tvr = tvr' LC = 4.34 ×1.16 = 5µs (< 20µs) tir = tir' LC = 2.9 ×1.16 = 3.4µs (< 5µs) It is seen that smaller capacitance (0.27 µF vs 1.2 µF) can be employed if simultaneous L-C transfer and R-C discharge are accounted for. The stray inductance of the resistor discharge path has been neglected. Any inductance decreases the effectiveness of the R-C discharge. Larger C than 0.27 µF and R < 3.3Ω are needed, as is now shown.

ii. (b) LR = 1µH, that is, L′ = LR /L = 0.2 In figure 8.7, for a minimum voltage reset time, ξ = 0.7, Vcp' = 0.54 when the L′ = 0.2 curve is used. The normalised reset times are unchanged, that is tir' = 2.9 and tvr' = 4.34. Using the same procedure as in part ii b 0.54 = 50V/25A 5µH gives C = 0.37µF (use 0.39µF) C 5µH L = 1 R= 1 = 2.6Ω (use 2.7Ω, 78W) 2ξ C 2×0.7 0.39µF Since resistor inductance has been accounted for, parallel connection of four 10Ω, 25W wire-wound aluminium clad resistors can be used. tvr = 4.34×1.4 = 6µs (< 20µs)

tir = 2.90 × 1.4 = 4µs (< 5µs) Note that circuit supply voltage Vs is not a necessary design parameter, other than to specify the capacitor absolute dc voltage rating. This supply independence is expected since in ac circuit analysis, as is applicable here, dc voltage sources are shorted.

♣

8.3

Polarised switching-aid circuits

Optimal gate drive electrical conditions minimize collector (or drain or anode) switching times, thus minimizing switch electrical stresses and power losses. Proper gate drive techniques greatly enhance the switching robustness and reliability of a power switching device. Switching-aid circuits, commonly called snubber circuits, can be employed to further reduce device switching stresses and losses. Optimal gate drive conditions minimise the amount of snubbering needed. Vs

Im

Vs

Im

Figure 8.8. Idealised collector (anode) switching waveforms for an inductive load.

During both the switch-on and the switch-off transition intervals, for an inductive load as considered in chapter 6.2, an instant exists when the switch simultaneously supports the supply voltage Vs and conducts the full load current Im, as shown in figure 8.8. The gate drive conditions cannot alter this peak power loss but can vary the duration of the switching periods (ton and toff). From chapter 6, for an inductive load, the switching losses, W, dissipated as heat in the switch, are given by Won = ½Vs I mton (J) (8.13) for turn-on: for turn-off: Woff = ½Vs I mtoff (J) (8.14) In order to reduce switching losses, two snubber circuits can be employed on a power switching device, one operational during switch turn-on, the other effective during turn-off. In the case of the turn-off snubber, energy (current) is diverted from the switch turning off into a parallel capacitor as shown in figure 8.9a. The turn-on snubber utilises an inductor in series with the collector as shown in figure 8.9b in order to support part of the dc voltage supply as the collector (anode) voltage falls. The inductor therefore controls the rate of rise of collector (anode) current during the collector voltage fall time. For both snubbers, the I-V SOA trajectory is modified to be within that area shown in figure 6.8.


194

A series inductive turn-on snubber is essential for the GCT and the GTO thyristor in order to control the anode initial di/dt current to safe levels at switch turn-on. In large area thyristor devices, the inductor controlled current increase at turn-on allows sufficient time for the silicon active area to spread uniformly so as to conduct safely the prospective load current. Special thyristor gate structures such as the amplifying gate, as shown in figure 3.24, allow initial anode di/dt values of up to 1000 A/us. Use of an inductive turn-on snubber with the MOSFET and the IGBT is limited but may be used because of freewheel diode imposed limitations rather than an intrinsic need by the switch. The shunt capacitive turn-off snubber is used extensively on the GTO thyristor. The R-D-C circuit is necessary to ensure that GTO turn-off occurs at a low anode-to-cathode voltage, preventing excessive power loss at the central GTO junction during reverse recovery. Larger area GTOs employ 1 to 8 µF in an R-D-C turn-off snubber and at high voltages and frequencies the associated losses, ½CsVs2 f s , tend to be high. To reduce this loss, GTOs with an increased SOA, namely GCTs, for use without a turn-off snubber are available. These devices under utilise their voltage and current density capabilities as compared with when used with a turn-off snubber.

While the switching performance of IGBTs and MOSFETs can be enhanced by using the turn-off snubber, it is not a prerequisite for safe, reliable switch operation.

Df Df

Vind Vg

Vg

T

T

Vsw

Figure 8.9. Basic switching-aid circuits comprising: (a) a parallel capacitor for current shunting at switch turn-off and (b) a series inductor for supporting voltage, thus limiting the rate of rise of principal current at turn-on.

8.3.1

The polarised turn-off snubber circuit - assuming a linear current fall

Figure 8.10 shows a complete turn-off snubber circuit comprising a capacitor-diode plus resistor combination across the anode-to-cathode/collector-to-emitter terminals of the switching device. At switch turn-off, load current is diverted into the snubber capacitor C via the diode D, while the switch principal current decreases. The anode/collector voltage is clamped to the capacitor voltage, which is initially zero. The larger the capacitor, the slower the anode/collector voltage rises for a given load current and, most importantly, turn-off occurs without a condition of simultaneous supply voltage and maximum load current (Vs, Im). Figure 8.11 shows the anode/collector turn-off waveforms for different magnitudes of snubber capacitance. The GTO/IGBT tail current has been neglected, thus the switching device is analysed without any tail current. For clarity, the terminology to be henceforth used, refers to an IGBT, viz., collector, emitter, and gate. Circuit operational explanations equally apply to thyristors. Figure 8.11a shows turn-off waveforms for a switch without a snubber, where it has been assumed that the collector voltage rise time is short compared with the collector current fall time, which is given by ic (t ) = I m (1 − t / t fi ) . For low capacitance values, the snubber capacitor (whence collector voltage) may charge to the rail voltage before the collector current has fallen to zero, as seen in figure 8.11b. For larger capacitance, the collector current reaches zero before the capacitor (whence collector voltage) has charged to the rail voltage level, as shown in figure 8.11c.

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Df

Vg

Figure 8.10. Practical capacitive turn-off snubber showing capacitor charging and discharging paths during device switching.

Vs

Im

trv Vs

Im

increasing C

Vs Im

increasing C

(d)

vc× ic

increasing C

t

Figure 8.11. Switch turn-off waveforms: (a) unaided turn-off; (b) turn off with small snubber capacitance; (c) turn-off with large snubber capacitance; (d) and switch power losses.


196

For analysis, the collector voltage rise time for an unaided switch is assumed zero. The device switch-off energy losses without a snubber, as shown in figure 8.11a, are given by W = ½Vs I mt fi (J) (8.15) With a snubber circuit, switch losses are decreased as shown in figure 8.11d, but snubber (resistor) losses are incurred. After turn-off the capacitor is charged to the rail voltage. This stored energy, ½CsVs 2 , is subsequently dissipated as heat in the snubber circuit resistor at subsequent switch turn-on, when an R-C discharge current flows. If the snubber RC time constant is significantly shorter than the switch voltage fall time at turn-on, the capacitor energy dissipated in the resistor is less than ½CsVs 2 and switch losses are increased as considered in 8.1.1. A range of capacitance values exists where the total losses - snubber plus switch - are less than those losses incurred if the same device is switched unaided, when losses as given by equation (8.14) result. Two distinct snubber design cases exist, depending on capacitance magnitude, as indicated by figures 8.11b and 8.11c. The two possibilities and the associated circuit voltage and current waveforms in each case are shown in detail in figure 8.12. The waveforms are based on satisfying Kirchhoff’s voltage and current laws for each case. Vs

(a) τ t fi

(b) τ

=k ≤1

Im

vDf

t fi

=k ≥1

iDf Vs Im

io = Im -

Ic

Vs

ic vce

2I m Vs Cs

Im

icap Cs

Vce

Ic

t fi

vo = ½I m t f i /Cs v o

on

Vce

io

off

switch voltage and current

on

off

t

tfi

Im

t

tfi

Im

Im

Ic

Im Ic

IDf

IDf


Icap

Icap

Im = iDf + ic + icap

t

t

Vs

Vs

Vs

Vs vDf = vload

vDf = vload

Vsw


vce = vcap

vce = vcap

Vs = vload + vcap τ

t

τ

Figure 8.12. Switch turn-off waveforms satisfying Kirchhoff’s laws: (a) turn-off with small snubber capacitance and (b) turn-off with large snubber capacitance.

t

197

Power Electronics

From i = C dv/dt, the snubber capacitor charges according to vc(t) = Vs (t / τ)2, to Vs before the collector current has reached zero, thus the switch losses are given by Wt = ½Vs I m t fi (1 − 4 3 k + ½ k 2 ) (J) (8.16) for k ≤ 1, where k = τ/tfi, as defined in figures 8.12a and 8.13. Alternatively, with larger capacitance, if the snubber capacitor charges to vo < Vs, according to vc(t) = vo (t / tfi)2 , thus not charging to Vs until after the collector current reaches zero, that is k ≥ 1, then the switch losses are given by ½Vs I m t fi (8.17) Wt = (J) 6 ( 2k − 1) for k ≥ 1 as defined in figures 8.12b and 8.13. Initially the capacitor voltage increase is quadratic, then when the collector current reaches the load current level, the capacitor voltage increase becomes linear. These losses, normalised with respect to the unaided switch losses given by equation (8.15), are plotted in figure 8.13. The switch and capacitor (subsequently resistor) components contributing to the total losses are also shown. A number of points arise concerning turn-off snubbers and snubber losses. (a) Because of current tailing, voltage overshoot, and the assumption that the voltage rise time trv is insignificantly short, practical unaided switch losses, equation (8.14), are approximately twice those indicated by equation (8.15). (b) As the snubber capacitance increases, that is, k increases, the switch loss is progressively reduced but at the expense of increased snubber associated loss. (c) If k ≤ 1.41 the total losses (switch and reset resistor) are less than those for an unaided switch. In the practical case k ≤ 2.70 would yield the same condition.

Figure 8.13. Loss components for a switch at turn-off when employing a capacitance-type snubber and assuming the collector current falls according to ic = I m (1−t / t fi ).


198

(d) A minimum total loss (switch plus reset resistor) condition exists. When k = ⅔ the total losses are only 5/9 those of an unaided switch. The snubber capacitance for this optimal case is given by 2 I m t fi (F) (8.18) Cs = 9 Vs (e) Losses are usually minimised at the maximum loss condition, that is maximum load current Im. At lower currents, the capacitor charging time is increased, increasing the output voltage distortion. (f) Snubbers not only reduce total losses, but because the loss is distributed between the switch and resistor, more effective heat dispersion can be achieved. (g) High switch current occurs at turn-on and incorporates the load current Im, the snubber −t capacitor exponential discharge Vs R 1 − e CR , and any freewheel diode reverse recovery current.

(

)

The capacitor energy ½CsVs2 is removed at turn-on and is exponentially dissipated mainly in the snubber circuit resistor R. The power rating of this resistor is independent of resistance but dependent on the maximum switching frequency. The reset resistor power rating is given by PR = ½CsVs2 f s (W) (8.19) s

Two factors specify the snubber circuit resistance value. •

•

The snubber circuit RC time constant period must ensure that after turn-on the capacitor ∨ discharges before the next switch turn-off is required. If ton is the minimum switch on-time, ∨ then t on =5RsCs , is sufficient to ensure the correct snubber circuit initial conditions, namely, zero capacitor volts. The resistor initial current at capacitor discharge is Vs / Rs. This component is added to the load current at switch turn-on, hence adding to the turn-on stresses. The maximum collector current rating must not be exceeded. In order to reduce the initial discharge current, a low valued inductor can be added in series with the resistor, (or a wire-wound resistor used), thus producing an overdamped L-C-R discharge current oscillation at turn-on. Note that the resistor power loss in equation (8.19) is independent of resistance value. The resistance determines the period of time over which the capacitor stored energy is dissipated at switch turn-on.

Figure 8.14. The collector I-V trajectory at turn-off with a capacitive switching-aid circuit.

As a result of utilising a capacitive turn-off snubber, the collector trajectory across the SOA is modified as shown in figure 8.14. It is seen that the undesired unaided condition of simultaneous supply voltage Vs and load current Im is avoided. Typical trajectory conditions for a turn-off snubbered device are shown for three situations, depending on the relative magnitudes of tfi and τ (the magnitude of Cs). A brief mathematical derivation describing the turn-off switching-aid circuit action is presented in the appendix in section 8.6 at the end of this chapter.

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see Table 8.1

Figure 8.15. Loss components for a switch at switch-off when employing a capacitance-type snubber and assuming a collector fall current according to ic = ½Im{1 + cos(πt/T)}.

8.3.2

The turn-off snubber circuit - assuming a cosinusoidal current fall

As an alternative to a linear current fall at turn-off, it may be more realistic to assume that the current falls cosinusoidally according to ic (t ) = ½ I m (1 + cos π t / T ) (A) (8.20) for 0 ≤ t ≤ T, as shown in figure 8.15. As with a linear current fall, two cases exist. (i) (ii)

τ ≤ T (k ≤ 1), that is the snubber capacitor charges to Vs in time τ, before the switch current reaches zero, at time T. τ ≥ T (k ≥ 1), that is the snubber capacitor charges to the supply Vs after the switch current has fallen to zero.

These two cases are shown in figure 8.15 where k is defined as τ /T. Using a similar analysis as presented in the appendix (section 8.6), expressions can be derived for switch and snubber resistor losses. These and the total losses for each case are summarised in table 8.1. Figure 8.15 shows that a minimum total loss occurs, namely Wtotal = 0.41× ½Vs I mT at k = 0.62 I T Cs = 0.16 m when (F) (8.21) Vs For tfi < 0.85T, a cosinusoidal fall current predicts lower total losses than a linear fall current, with losses shown in figure 8.13.


200

Table 8.1. Normalised switching loss components at turn-off with a cosinusoidal current fall of half period T

Example 8.4:

Capacitive turn-off snubber design

A 600V, 100A machine field winding is switched at 10kHz. In maintaining a constant field current, the switch operates with an on-state duty cycle ranging between 5% and 95% (5% ≤ δ ≤ 95%) and has a turn-off linear current fall time of 100ns, that is, ic (t ) = 100 × (1 − t /100ns) . i. Estimate the turn-off loss in the switch. ii. Design a capacitive turn-off snubber using the dimensionally correct identity i = Cdv/dt. What is the capacitor voltage when the collector current reaches zero. iii. Design a capacitive turn-off snubber such that the switch voltage reaches 600V at the same time the conducting current reaches zero. In each snubber case calculate the percentage decrease in un-aided switch turn-off power dissipation. Solution i. The switch un-aided turn-off losses are given by equation (8.14). The turn-off time is greater than the current fall time (since the voltage rise time trv has been neglected), thus the turn-off switching losses will be greater than Woff = ½Vs I m toff = ½ × 600V × 100A × 100ns = 3mJ Poff = Woff × f s = 3mJ × 10kHz = 30W

ii. Use of the equation i = Cdv/dt results in a switch voltage that reaches the rail voltage after the collector current has fallen to zero. From k = ½ + C V / I t in figure 8.13, k = 3/2 satisfies the dimensionally correct capacitor charging equation. Substitution into i = Cdv/dt gives the necessary snubber capacitance 600V 100A = C 100ns that is C = 16 2 3 nF Use an 18nF, 1000V dc, metallised polypropylene, high dv/dt capacitor. The snubber capacitor discharges at switch turn-on, and must discharge during the switch minimum ontime. That is s

s

m fi

∨

t on = 5 CR 5% of 1/10kHz = 5 × R × 18nF that is R = 55.5Ω Use 56Ω The discharge resistor power rating is independent of resistance and is given by P56 Ω = ½CVs 2 f s = ½ × 18nF × 600V 2 × 10kHz = 32.4W Use 50W. The resistor can be wire-wound, the internal inductance of which reduces the initial peak current when the capacitor discharges at switch turn-on. The maximum discharge current into the switch during reset, which is added to the 100A load current and any diode reverse recover current, is I 56 Ω = Vs / R = 600V / 56Ω = 10.7A

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which decays exponential to zero in five time constants, 5µs. The peak switch current (neglecting freewheel diode recovery) is 100A+10.7A=110.7A, at turn-on. At switch turn-off, when the switch current reduces to zero, the snubber capacitor has charged to a voltage less than the 600V rail voltage, specifically 1 v0 = ∫ icap dt C 100 ns 1  t  = 100A ×   dt = 300V (277V with 18nF) ∫ 2 16 3 nF 0  100ns  The switch turn-off losses are reduced from 30W to 100ns

Poff = f s

∫ 0

100ns

= fs

∫ 0

100ns

ic vce dt = f s

∫ 0

2

t    t  I m  1× v0    dt  100 ns   100ns  2

t    t  100A  1× 300V    dt = 2.5W  100 ns   100ns 

( 2.3W with 18nF )

The total turn-off losses (switch plus snubber resistor) are 2.5W+32.4W=34.9W, which is more than the 30W for the unaided switch. Since the voltage rise time has been neglected in calculating the un-aided losses, 34.9W would be expected to be less than the practical un-aided switch losses. The switch losses have been reduced by 91⅔%, from 30W to 2.5W. iii. As the current in the switch falls linearly to zero, the capacitor current increases linearly to 100A (k = 1), such that the load current remains constant, 100A. The capacitor voltage increases in a quadratic function according to 1 vcap (t ) = ∫ icap dt C The capacitor charges quadratically to 600V in 100ns, as its current increases linearly from zero to 100A, that is 100 ns 1 t 600V = 100A dt ∫ C 0 100ns that is C = 8 1 3 nF Use a 10nF, 1000V dc, metallised polypropylene, high dv/dt capacitor.

600V

600V

ic=100(1-t/tfi)

ic=100(1-t/tfi) 100A

100A 300V

vc=600(t/tfi)

vc=300(t/tfi)

2

2

P(t)

P(t)

t

icap

t

icap 100A

100A

IDf

IDf 600V=Area/C 600V=Area/C 0

tfi

Example 8.4. part (b)

1.5tfi

t

0

Example 8.4. part (c)

tfi

tt


202

The necessary reset resistance to discharge the 10nF capacitor in 5µs is 5µs = 5 × R × 10nF that is R = 100Ω The power dissipated in the reset resistor is P100 Ω = ½CVs 2 f s = ½ × 10nF × 600V 2 × 10kHz = 18W Use a 100Ω, 25W, wire-wound, 600V dc withstand voltage, metal clad resistor. The resistance determines the current magnitude and the period over which the capacitor energy is dissipated. The resistance does not determine the amount of energy dissipated. The capacitor exponentially discharges with an initial current of 600V/100Ω = 6A, which adds to the 100A load current at switch turn-on. The peak switch current is therefore 100A+6A = 106A, at turn-on. The energy dissipated in the switch at turn-off is reduced from 30W when un-aided to 100 ns

Poff = f s

∫ 0

100 ns

ic vc dt = f s

∫ 0

2

t    t  I m  1 × Vs  100ns  dt 100 ns     2

100ns

t    t  1 100A  1 × 600V  100ns  dt = 5W (using 8 3 nF) 100 ns     0 The total losses (switch plus snubber resistor) with a turn-off snubber are 5W+18W =23W, which is less than the 30W for the unaided switch. The switch loss has been decreased by 83⅓%, (30W to 5W). = fs

∫

Note that the losses predicted by the equations in figure 8.13 amount to 5W + 15W = 20W. The discrepancy is due to the fact that the preferred value of 10nF with k = 1.2 giving 5W + 18W = 23W (rather that the calculated 8⅓nF, k =1) has been used for the resistor loss calculation.

♣

8.3.3

The polarised turn-on snubber circuit – with air-core (non-saturable) inductance

A series turn-on snubber comprises an inductor-diode combination in the collector circuit as shown in figure 8.16. At turn-on the inductor controls the rate of rise (from zero) of collector current and supports a portion of the supply voltage while the collector voltage falls. At switch turn-off the energy stored in the inductor, ½ Ls I m2 , is transferred in the form of current through the diode and dissipated in the diode Ds and any added series resistance R, and in the resistance of the inductor.

Df

Im

Im

R

Figure 8.16. Turn-on switching-aid circuit incorporating series inductance, Ls.

Figure 8.17 shows collector turn-on waveforms with and without a turn-on snubber circuit. The turn-on loss associated with an unaided switch, figure 8.17a, neglecting the current rise time, is given by (8.22) W = ½Vs I m t fv (J) where it is assumed that the collector current rise time is zero and that the collector voltage falls linearly, according to vc (t ) = Vs (1 − t / t fv ) . When an inductive turn-on snubber circuit is employed, collector waveforms as in figure 8.17b or 8.17c result. The two possibilities and the associated circuit voltage and current waveforms in each case are shown in detail in figure 8.18. The waveforms are based on satisfying Kirchhoff’s voltage and current laws for each case.

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For low inductance the collector current reaches its maximum value Im (the load current) before the collector voltage has reached zero. As shown in figure 8.17b, from v = L di/dt, the collector current increases quadratically ic(t) = Im (t/τ)2 and the switch turn-on loss is given by Wt = ½Vs I m t fv (½ k 2 - 43 k + 1) (J) (8.23) for k ≤ 1, where k = τ / tfv as defined in figure 8.17.

Vs

tri

Vs Im increasing Ls

vo

Vs Im io

(d)

vc× ic

increasing Ls

increasing Ls

t

Figure 8.17. Switch voltage and current collector waveforms at turn-on: (a) without a snubber; (b) and (c) with an inductive snubber; and (d) switch power losses.

These losses include both switch losses and stored inductor energy subsequently dissipated. For higher snubber inductance, the collector voltage reaches zero before the collector current reaches the load current level. Initially the inductor current increases quadratically iLs(t) = io (t/tfv)2, then when the collector voltage has reached zero, the current increases linearly. The switch loss is given by 1 (J) Wt = ½Vs I m t fv (8.24) 6 × ( 2k -1) Note that these equations are similar to those for the turn-off snubber, except that the current fall time tfi is replace by the voltage fall time, tfv. The normalised loss components for the capacitive snubber in figure 8.13 are valid for the inductive turn-on snubber.


204

Vs

vDf = Vload Vs vind

Im

Im iDf ic = iind

Vs Im

vce

vce

Ic

vce ic

off

vo

on switch voltage and current

t

tfv

Vs

Vs vce

VDf =Vload

VDf =Vload


Vind

Vs = vload + vind + vc

t

Im

t

Im

Im

iDf

iDf


ic = iind

τ

t

Vs

Vind

Im

on

tfv

Vs vce

io io = ½Vs t f v /Ls

off

ic = iind

Im = iDf + ic

t

t

τ

Figure 8.18. Turn-on snubber waveforms satisfying Kirchhoff’s laws: (a) turn-on with small snubber inductance and (b) turn-on with large snubber inductance.

Minimum total turn-on losses of 5/9 those of the un-aided case, occur at k = ⅔ when 2 Vs t fv Ls = (H) 9 Im

(8.25)

At switch turn-off, the snubber inductance stored energy is dissipated as heat in the snubber freewheeling diode path. The maximum power loss magnitude is dependent on the operating frequency and is given by PL = ½ Ls I m2 f s (W) (8.26) s

This power is dissipated in the inductor ∨winding resistance,∨ resistance R, and freewheeling diode Ds. The time constant is designed such that t off = 5Ls / R where t off is the minimum device off-time, where R is the effective total series resistance. The time constant can be reduced either by increasing the series resistance or by inserting a Zener diode as shown in figure 8.19. A disadvantage of series resistance R as in figure 8.19a is that the switch collector voltage at turn-off is increased from Vs to Vs + ImR. The resistor must also have low self-inductance in order to allow the collector current to rapidly transfer from the switch to the resistor/diode reset circuit. The advantage of using a Zener diode as in figure 8.19b is that the maximum overvoltage is fixed, independent of the load

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current magnitude. For a given maximum overvoltage, the Zener diode absorbs the inductor-stored energy quicker than would a resistor (see example 6.3 and problem 8.9). The advantages of using resistive dissipation are lower costs and more robust heat dissipation properties. Alternatively the Zener diode can be placed across the switch as shown in figure 8.19c. The power dissipated is increased because of the energy drawn from the supply, through the inductor, during reset. At higher power, the soft voltage clamp shown in figure 8.19d, and considered in section 8.2, can be used. At switch turn-off, the energy stored in Ls, along with energy from the supply, is transferred and stored in a clamp capacitor. Simultaneously energy is dissipated in R and returned to the supply as the capacitor voltage rises. The advantage of this circuit is that the capacitor affords protection directly across the switch, but with lower loss than a Zener diode as in figure 8.19c. The energy loss equation for each circuit is also shown in figure 8.19. In high-voltage applications, the combined features of the soft clamp in figure 8.19d and the low loss Zener clamp in figure 8.19b can be realised by inserting a series Zener as shown in the figure 8.19d insert. This avoids the need to series connect Zener diodes, which would be necessary if the circuit in figure 8.19c were used at voltages above a few hundred volts. Figure 8.20 shows how a switch turn-on snubber circuit modifies the SOA trajectory during switch-on, avoiding a condition of simultaneous maximum voltage Vs and current Im.

Df

Df

Df

Df

Dc Dc

Dz

Dc

Figure 8.19. Four turn-on snubber modifications for increasing the rate of release of inductor Ls stored energy: (a) using a power resistor; (b) using a power Zener diode; (c) parallel switch Zener diode, VZ > Vs; and (d) using a soft voltage clamp.


206

vo

io

Figure 8.20. The collector I-V trajectory at turn-on with a switching-aid circuit.

Example 8.5:

Turn-on air-core inductor snubber design

A 600V, 100A machine field winding is switched at 10kHz. In maintaining a constant field current, the switch operates with an on-state duty cycle between 5% and 95% (5% ≤ δ ≤ 95%) and has a turn-on voltage fall time of 100ns, that is, vc (t ) = 600V(1 − t /100ns) . Estimate the turn-on loss of the switch. Design an inductive turn-on snubber using the dimensionally correct identity v = Ldi/dt. What is the current magnitude in the turn-on inductor when the switch voltage reaches zero. iii. Design an inductive turn-on snubber such that the switch current reaches 100A at the same time the switch collector voltage reaches zero. In each snubber case, using first a resistor and second a Zener diode for inductor reset, calculate the percentage decrease in switch power dissipation at turn-on, compared to the un-aided case. i. ii.

Solution i. The switch un-aided turn-on losses are given by equation (8.13). The turn-on time is greater than the voltage fall time (since the current rise time tri has been neglected), thus the turn-on switching losses will be greater than Won = ½Vs I m ton = ½ × 600V × 100A × 100ns = 3mJ Pon = Won × f s = 3mJ × 10kHz = 30W

ii. Use of the equation v = Ldi/dt results in a switch current that reaches the load current magnitude after the collector voltage has fallen to zero. From k = ½ + L I / V t in figure 8.20, k = 3/2 satisfies the dimensionally correct inductor equation. Substitution into v = Ldi/dt gives the necessary snubber inductance 100A 600V = L 100ns that is L = 600 nH The snubber inductor releases its stored energy at switch turn-off, and must discharge (demagnetise) ∨ during the switch minimum off-time, t off . That is s

m

s fv

∨

t off = 5 L / R 5% of 1/10kHz = 5 × 0.6µH / R that is R = 0.6 Ω Use the preferred value 0.68Ω (nearest higher preferred value), which reduces the L/R time constant.

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The discharge resistor power rating is independent of resistance and is given by P0.68Ω = ½ LI m2 f s = ½ × 600nH × 100A 2 × 10kHz = 30W The resistor in the circuit in figure 8.19a must have low inductance to minimise voltage overshoot at switch turn-off. Parallel connection of metal oxide resistors may be necessary to fulfil both resistance and power rating requirements. The maximum switch over-voltage at turn-off, (assuming zero resistor inductance), at the commencement of core reset, which is added to the supply voltage, 600V, is V0.68Ω = I m R = 100A × 0.68Ω = 68V which decays exponential to zero volts in five time constants, 5µs. The maximum switch voltage is 600V + 68V = 668V, at turn-off. The reset resistor should be rated at 0.68Ω, 30W, metal film, 750V dc working voltage. ∨ A Zener diode, as in figure 8.19b, of Vz = L I m / t off = 0.6µH×100A/5µs = 12V , will reset the inductor in the same time as 5 L/R time constants. The switch voltage is clamped to 612V during the 5µs inductor reset time at switch turn-off. At turn-on when the switch voltage reduces to zero, the snubber inductor current (hence switch current) is less than the load current, 100A, specifically 1 i0 = vind dt L 100ns 1  t  = 600V ×   dt = 50A 600nH 0  100ns 

∫

∫

The switch turn-on loss is reduced from 30W to 100 ns

Pon = f s

∫

100 ns

ic vc dt = f s

0

100ns

= fs

∫ 0

∫ 0

2

t    t  Vs  1× i0    dt  100 ns   100ns  2

t    t  600V  1× 50A    dt = 2.5W  100 ns   100ns 

The total turn-on losses (switch plus snubber resistor) are 2.5W + 30W = 32.5W, which is more than the 30W for the unaided switch. Since the current rise time tri has been neglected in calculating the 30W un-aided turn-on losses, it would be expected that 32.5W would be less than the practical un-aided case. The switch loss is decreased by 92⅔%, from 30W down to 2.5W.

600V

600V

vc=600(1-t/tfv)

vc=600(1-t/tfv) 100A

100A

ic=50(t/tfv)2

P(t)

50A

P(t)

ic=100(t/tfv)2

t

vind

t

vind 600V

600V

VDf

100A=Area/L

VDf=Vload 100A=Area/L

0

tfv

Example 8.5. part (b)

1.5tfv

t

0

tfv

Example 8.5. part (c)

t


208

iii. As the voltage across the switch falls linearly to zero from 600V, the series inductor voltage increases linearly to 600V (k = 1), such that the voltage sum of each component adds to 600V. The inductor current increases in a quadratic function according to 1 iind (t ) = ∫ vind dt L The inductor current increases quadratically to 100A in 100ns, as its voltage increases linearly from zero to 600V, that is 100 ns 1 dt 100A = 600V t 100ns L ∫ 0

that is L = 300nH The necessary reset resistance to reduce the 300nH inductor current to zero in 5µs is ∨

t off = 5µs = 5 × 0.3µH / R that is R = 0.3Ω Use the preferred value 0.33Ω in order to reduce the time constant. The power dissipated in the 0.33Ω reset resistor, which is independent of resistance, is P0.33Ω = ½ LI m2 f s = ½ × 300nH × 100A 2 × 10kHz = 15W The resistance determines the voltage magnitude and the period over which the inductor energy is dissipated, not the amount of inductor energy to be dissipated. The inductor peak reset voltage is 100A×0.33Ω = 33V, which is added to the supply voltage of 600V, giving 633V across the switch at turnoff. That is, use a 0.33Ω, 15W metal film (for low inductance), 750V dc working voltage resistor. ∨ A Zener diode, as in figure 8.19b, of Vz = L I m / t off = 0.3µH×100A/5µs = 6V (use 6.8V), will reset the inductor in the same time as 5 L/R time constants. The switch voltage is clamped to 606.8V during the ∨ t off = 5µs inductor reset time at turn-off. The energy dissipated in the switch at turn-on is reduced from 30W to 100 ns

∫

Pon = f s

100 ns

ic vc dt = f s

0

0

100ns

= fs

∫ 0

∫

2

t    t  × Im  Vs  1  dt  100ns   100 ns  2

t    t  × 100A  600V  1  dt = 5W  100ns   100 ns 

The total turn-on snubber losses (switch plus snubber resistor) are 5W+15W = 20W, which is less than the 30W for the unaided switch. The switch losses, with an inductive turn-on snubber, are decreased by 83⅓%, from 30W to 5W.

♣

8.3.4

The polarised turn-on snubber circuit - with saturable ferrite inductance

The purpose of a turn-on snubber circuit is to allow the switch collector voltage to fall to zero while the collector current is low. Device turn-on losses are thus reduced, particularly for inductive loads, where during switching the locus point (Vs, Im) occurs in the un-aided transition case. This turn-on loss reduction effect can be achieved with a saturable inductor in the circuit shown in figure 8.21a, rather than using a non-saturable (air core) inductor as previously considered in section 8.3.3. The saturable inductor in the snubber circuit is designed to saturate after the collector voltage has fallen to zero, at point Y in figure 8.21. Before saturation the saturable inductor presents high reactance and only a low magnetising current flows. Once the collector voltage has reached zero, the inductance can saturate since the switch-on loss period is finished. From Faraday’s equation, assuming the collector voltage fall to be linear, Vs (1 − t / t fv ) , the saturable inductor ℓs must satisfy dφ dB = NA (8.27) vA = N dt dt Rearranging, using an inductor voltage vA (t ) = Vs − vc (t ) = Vs t / t fv , and integrating gives Bs =

1 NA

t fv

∫

t fv

vA (t ) dt =

0

1 t Vs dt NA 0 t fv

∫

(8.28)

(V)

(8.29)

which yields the identity Vs =

2 NA Bs t fv

where N is the number of turns, A is the core area, and Bs is the core ferro-magnetic material saturation flux density.

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The inductor magnetising current IM should be much less than the load current magnitude Im, IM Cs, in which case the diode Dc across Cs conducts, clamping Cs to zero volts. The final voltage on Co is

VCo = VCs

Co L = Im s Cs Co

(9.8)

During the transfer of energy from Cs to Co the circuit voltage and current waveforms are given by equations (9.11) to (9.14). The voltage on Co given by (9.8) is retained until subsequent switch turn-off. The final stage of recovery is shown in figure 9.3d where the capacitor Co dumps its charge at a constant rate into the load as its voltage falls linearly to zero in a time, independent of the load current

t Co = C o

VCo = Ls C o Im

(9.9)

during which time the capacitor Co voltage falls according to

VCo (ωt ) = VCot =0 −

L Im I t = Im s − m t Co Co Co

The load freewheel diode Df then conducts the full load current Im.

(9.10)

Switching Aid Circuits with Energy Recovery

224

Vs

Im Df

L O A D

Im

Co Dr + +

Co>Cs

Co

Lr T

D

Co Dc

Cs

Lr

+

+

Cs +

Im

Ls

Dr

+

Cs

Ls

Ds

Dc

Ds

0

(a)

(b)

(c)

(d)

Figure 9.3. Inductive turn-on snubber with snubber energy recovery intermediate capacitors: (a) circuit diagram; and successive (b) turn-off; (c) turn-on; and (d) turn-off.

9.1.2

Active recovery

i. Recovery into the dc supply Figure 9.4 shows an inductive turn-on snubber energy recovery scheme which utilises a switched-mode power supply (smps) based on the boost converter in 15.4, and shown in figure 9.26a. At switch turn-off the energy stored in the snubber inductor Ls is transferred to the large intermediate storage capacitor Co via the blocking diode, Db. The inductor current falls linearly to zero in time Ls Im / VCo. The smps is then used to boost the relatively low capacitor voltage into a higher voltage suitable for feeding energy back into a dc supply. The capacitor charging rate is dependent on load current magnitude. The smps can be controlled so as to maintain the capacitor voltage constant, thereby fixing the maximum switch collector off-state voltage, or varied with current so as to maintain a constant snubber inductor reset time. One smps and storage capacitor can be utilised by a number of switching circuits, each with a blocking/directing diode as indicated in figure 9.4. The diode and switch are rated at Vs+VCo. The smps is operated in a discontinuous inductor current mode in order to reduce switch and diode losses and stresses. If the load and inductive turn-on snubber are re-arranged to be in the cathode circuit, then the complementary smps in figure 9.26b can be used to recover the snubber energy from capacitor Co.

Co

Lsmps

VCo

on Tsmps

off

Db see figure 9.26a

fsmps Dsmps

fsmps > fT 0V

0V

Figure 9.4. Turn-on snubber with active snubber inductor energy recovery.

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225

Df

OFF

ON

+

+

Figure 9.5. Conventional capacitive turn-off snubber showing currents at IGBT transistor: (a) turn-off and (b) turn-on.

9.2

Energy recovery for capacitive turn-off snubber circuits – single ended

Figure 9.5 shows the conventional capacitive turn-off snubber circuit used with both the GTO thyristor and the IGBT transistor. At turn-off, collector current is diverted into the snubber capacitor C via D. The switch turns off clamped to the capacitor voltage which increases quadratically from zero. At the subsequent switch turn-on the energy stored in C, ½CVs2 is dissipated as heat, mainly in the resistor R. A full functional description and design procedure for the capacitive turn-off snubber circuit is to be found in chapter 8.3.1. At high voltages and switching frequencies, with slow switching devices, snubber losses ( ½CVs2 f s ) may be too high to be readily dissipated. An alternative is to recover this energy (either into the load or back into the dc supply), using either passive or active recovery techniques.

+ +

Do

Co

T

Rs

L

+

Ds

Cs

+

(a)

(b)

Figure 9.6. A capacitive turn-off snubber with passive capacitor energy recovery into the load: (a) with a capacitive turn-off snubber and (b) with an RC turn-off snubber.


9.2.1

226

Passive recovery

i. Recovery into the load Figure 9.6 illustrates a passive, lossless, capacitive turn-off snubber energy recovery scheme which dumps the snubber energy, ½CVs2 f s , into the load. The switch turn-off protection is that with a conventional capacitive snubber circuit. At turn-off the snubber capacitor Cs charges to the voltage rail Vs as shown in figure 9.7a. At subsequent switch turn-on, the load current diverts from the freewheeling diode Df to the switch T. Simultaneously the snubber capacitor Cs resonates its charge to capacitor Co through the path shown in figure 9.7b, T - Cs - L - Do - Co. When the switch next turns off, the snubber capacitor Cs charges and the capacitor Co discharges into the load. When Co is discharged, the freewheeling diode conducts. During turn-off Co and Cs act effectively in parallel across the switching device. A convenient starting point for the analysis of the recovery scheme is at switch turn-on when snubber energy is transferred from Cs to Co.

T

T

+

+

Figure 9.7. Energy recovery turn-off snubber showing the energy recovery stages: (a) conventional snubber action at turn-off; (b) intermediate energy transfer at subsequent switch turn-on; and (c) transferred energy dumped into the load at subsequent switch turn-off.

At switch turn-on The active equivalent circuit portions of figure 9.7b are shown in figure 9.8a. Analysis of the L-C resonant circuit with the initial conditions shown yields the following capacitor voltage and current equations. The resonant current is given by V i (ωt ) = s sin ωt (A) (9.11) Z As 1 n + 1 where Z = ω A s = = Zo (ohms) Zo = (ohms)

ωC o

ω = ωo n =

n + 1 n

n

Co

(rad/s)

ωo =

1 AsC o

(rad/s)

Cs Co

The snubber capacitor voltage decreases from Vs according to 1  VCs = Vs 1 − (V) (1 − cos ωt )  1+ n  while the transfer capacitor voltage charges from zero according to n VCo = Vs (V) (1 − cos ωt ) 1+ n

(9.12)

(9.13)

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227

Figure 9.8. Equivalent circuit for the intermediate energy transfer phase of snubber energy recovery, occurring via: (a) the main switch T and (b) then via the snubber diode Ds.

equation (9.11) equation (9.14)

equation (9.12)

equation (9.13)

Figure 9.9. Circuit waveforms during intermediate energy transfer phase of snubber energy recovery: (a) transfer capacitor C0 current; (b) snubber capacitor voltage; and (c) transfer capacitor voltage.

Examination of equation (9.12) shows that if n > 1, the final snubber capacitor Cs voltage at ωt = π will be positive. It is required that Cs retains no charge, ready for subsequent switch turn-off; thus n ≤ 1, that is Co ≥ Cs. If Co is greater than Cs equation (9.12) predicts Cs will retain a negative voltage. Within the practical circuit of figure 9.6, Cs will be clamped to zero volts by diode Ds conducting and allowing the remaining stored energy in L to be transferred to Co. The new equivalent circuit for ωt = cos −1 ( − n ) is shown in figure 9.8b. The resonant current, hence transfer capacitor voltage are given by V i (ωt ) = s sin (ωo t + φ ) (A) Z (9.14) VCo = n Vs cos (ωo t + φ ) (V) 2

where t ≥ 0 and φ = − tan −1 1−nn . In maintaining energy balance, from equation (9.14) when the inductor L current i(ωt) = 0, the final voltage on Co is n Vs and Cs retains no charge, VCs = 0. The voltage and current waveforms for the resonant energy transfer stage are shown in figure 9.9.


228

At switch turn-off Energy dumping from Co into the load and snubber action occur in parallel and commence when the switch is turned off. As the collector current falls to zero in time tfi a number of serial phases occur. These phases, depicted by capacitor voltage and current waveforms, are shown in figure 9.10. Phase one Capacitor Co is charged to n Vs , so until the snubber capacitor Cs charges to 1 − n Vs , Co is inactive. Conventional snubber turn-off action occurs as discussed in chapter 8.3.1. The snubber capacitor voltage increases according to I VCs = ½ m t 2 (V) (9.15) Cs t fi

(

)

while Co remains charged with a constant voltage of n Vs . This first phase is complete at to when I t2 VCs = vo = ½ m o = 1 − n Vs (V) (9.16) Cs t fi

(

)

whence

to =

and the collector current

(

2 1 − n Vs Cs t fi

)

(s)

Im

(

I o = I m 1 − to t

fi

)

(A)

(9.17)

(9.18)

Figure 9.10. Circuit waveforms at switch turn-off with turn-off snubber energy recovery when: (a) the snubber Cs is fully charged before the switch current at turn-off reaches zero and (b) the switch collector current has fallen to zero before the snubber capacitor has charged to Vs.

Phase two When Cs charges to 1 − n Vs , the capacitor Co begins to discharge into the load. The equivalent circuit is shown in figure 9.11a, where the load current is assumed constant while the collector current fall is assumed linear. The following Kirchhoff conditions must be satisfied

(

)

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229

Vs = VCs + VCo (V) I m = iCo + iCs + I o (1 − t / t fi ) (A)

(9.19) (9.20)

for 0 ≤ t ≤ tfi – to Under these conditions, the snubber capacitor voltage increases according to n 1  ( I m − I o ) t + ½t 2 / to  + 1 − n Vs VCs = (V) 1 + n Cs  with a current 1 (A) iCs = {I m − I o (1 − t / to )} 1+ n

(

)

(9.21)

(9.22)

The transfer dump capacitor Co discharges with a current given by iCo = iCs / n

(9.23)

+

+

+

+

Figure 9.11. Turn-off snubber equivalent circuit during energy recovery into the load when: (a) Co begins to conduct and (b) after the switch has turned off.

Phase three If the snubber capacitor has not charged to the supply rail voltage before the switch collector current has reached zero, phase three will occur as shown in figure 9.10b. The equivalent circuit to be analysed is shown in figure 9.11b. The Kirchhoff equations describing this phase are similar to equations (9.19) and (9.20) except that in equation (9.20) the component Io(1- t/t0) is zero. The capacitor Cs, charging current is given by n (9.24) (A) iCs = Im 1+ n while the dumping capacitor Co current is iCo = iCs / n (A) (9.25) The snubber capacitor charges linearly, according to n Im (9.26) (V) VCs = vio + t 1 + n Cs When Cs is charged to the rail voltage Vs, Co is discharged and the load freewheeling diode conducts the full load current Im. Since the snubber capacitor energy is recovered there is no energy loss penalty for using a large snubber capacitance and the larger the capacitance, the lower the switch turn-off switching loss. The energy to be recovered into the load is fixed, ½CsVs2 and at low load current levels the long discharge time of Co may inhibit proper snubber circuit action. This is generally not critical since switching losses are small at low load current levels. Output voltage regulation is reduced, since the amount of energy recovered into the load is independent of the load current. ii. Recovery into the dc supply Figure 9.12 show two turn-off snubber circuits where the energy is recovered back into the dc supply. The ac circuit operational mechanisms are the same for both circuits. When the switch T is turned off the snubber capacitor Cs charges to the dc rail voltage Vs.

Switching Aid Circuits with Energy Recovery Vs

Df Im

230

Vs

L O A D

Df

Df/b Lr

Im

L O A D

Df/b

1:N on on Lp

Ls

N>2

Ds T

+ Cs

0

Do

+

Do

Cs Ds

T

on

on Lp

Ls

Lr

0 (a)

1:N

(b)

Figure 9.12. A capacitive turn-off snubber with passive energy recovery into the supply: (a) basic capacitive turn-off snubber and (b) an alternative configuration.

At switch T turn-on, the snubber capacitor Cs resonates with inductor Lr through the coupled transformer primary Lp, in the loop Cs - Do – Lp - Lr - T, returning energy to the dc supply through the coupled secondary circuit. The primary voltage is Vs /N, and provided this referred voltage is less than a half Vs, all the energy on Cs is transferred back to the dc supply through the transformer. The snubber diode Ds clamps the capacitor Cs voltage to zero, and excess energy in Lr is transferred to the dc supply, in the loop Do – Lp - Lr – Ds, as the inductor Lr current falls linearly to zero when opposed by the referred dc link voltage via the transformer. Once the energy transfer is complete, the transformer core magnetising current resets to zero in the same Kirchhoff loop, but at a low voltage. Reset must be complete in one complete period of switch T. iii RC snubber recovery The IGCThyristor is commonly used and characterised with an RC snubber. The figure 9.6b shows how the snubber diode Ds in figure 9.6a can be replaced by a resistor to form an RC snubber, provided diode Ds is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. The snubber capacitor stored energy after turn-off, ½CsV2, can be recovered at switch turn-on, provided the RsCs time constant is at least comparable with the LC resonant period – an unlikely condition. 9.2.2

Active recovery

i. Recovery into the dc supply Active energy recovery methods for the turn-off snubber are simpler than the technique needed for active recovery of turn-on snubber circuit stored energy. This is because the energy to be recovered from the turn-off snubber is fixed at ½CsVs2 and is independent of load current. In the case of the turn-on snubber, the energy to be recovered is load current magnitude dependent ( α IL2 ) which complicates active recovery. Active turn-off snubber energy recovery usually involves the production of an intermediate capacitive energy storage stage involving a positive or negative voltage rail (with respect to the emitter of the principal switch). a Negative intermediate voltage rail At switch T turn-on the snubber capacitor stored energy is resonated into a large intermediate storage capacitor Co as shown in figure 9.13a. Recovery from Cs to Co at switch T turn-on occurs through the following loops: at switch T turn-on when VCs > 0: Cs -T- Co - L- Da (as shown in figure 9.8a and equations (9.12) - (9.13)) then when VCs = 0: Ds - Co - L- Da (as shown in figure 9.8b and equation (9.14)) The switch current is increased by the resonant current, which has a maximum of VCo / L / C s . It is possible to use the energy in Co as a negative low-voltage rail supply. This passive recovery technique suffers from the problem that the recovered energy ½CsVs2 may represent more energy than the lowvoltage supply requires. An independent buck-boost smps can convert excess energy stored in Co to a more useful voltage level. Producing the gate drive for the smps switch Tsmps presents few difficulties since the gate-emitter has a low dc offset and does not experience any dv/dt relative to the emitter reference voltage of the main switch T.

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231

The basic recovery circuit, with the buck-boost smps, can form the basis of an active turn-off snubber energy recovery circuit when switches are series connected, as considered in section 9.4. It may be noticed that the ‘Cuk’ converter in chapter 17.6 is in fact the snubber energy recovery circuit in figure 9.13a, controlled in a different mode. Dc

Da Cs

T

Rs

SMPS

L

Dsmps

Tsmps

off

Lsmps on

on

(a) Vs SMPS

Df

L O A D

Vs

Im

Dsmps

off

+

Cs

Da

T Ds

Lsmps

Trev

off

+

on

Co

L

Tsmps 0V

on

(b) Figure 9.13. Switching circuit for recovering turn-off snubber capacitor energy, and for providing either (a) a negative voltage rail and/or transferring to Vs, via a buck-boost smps or (b) a positive voltage rail and/or transferring to Vs, via a boost smps.

b Positive intermediate voltage rail A positive voltage source, with respect to the main switch emitter, can be produced with the recovery circuit in figure 9.13b. Practically, an extra switch, Trev, is needed in order to minimise the time of current decay in the loop L - Ds, after the switch T is turned on and the voltage on the snubber capacitor Cs has resonated to zero. A passive resistor-capacitor network can be used to synchronise the turn-on (due to the main switch T turning on) and turn-off (due to diode Ds becoming forward biased) of the low-voltage switching device Trev. Recovery from Cs to Co at switch T turn-on occurs through the following Kirchhoff current loops: at switch T turn-on when Trev is on and VCs > 0: Cs -T - L- Trev for a period ½π√LCs then when Trev is off and VCs = 0: Co - L- Da for a period Vs /ωoVCo A boost smps controls and transfers the energy on Co to the dc rail through diode Dsmsp. The basic recovery circuit, with the boost smps, when cascade connected, can form the basis of an active turn-off snubber energy recovery circuit for series connected switches, as considered in 9.4. ii. RC snubber recovery The IGCThyristor is commonly used and characterised with an R-C snubber (as opposed to a parallel connected series capacitor-diode turn-off snubber). The insert in figure 9.13a, for use in figures 9.13a and b, shows how the snubber diode Ds can be replaced by a resistor to form an R-C snubber, provided diode Dc is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. Most of the snubber capacitor stored energy after turn-off, ½CsV2 at switch turn-off, (depending on the Rs-Cs time constant), can be recovered using either of the basic circuits in figure 9.13, or the circuits in figures 9.6 and 9.14, provided the RsCs time constant is greater than the LC resonant period.


232

Whether a positive or negative intermediate voltage is produced on Co, (typically a few tens of volts, but much higher if part of a turn-on snubber recovery circuit), the energy on Co is usually smps converted to stable gate voltage levels of the order of ±15V. Since a dual rail polarity gate level supply is needed, the polarity of the voltage on Co (viz., positive or negative) is inconsequential. 9.3

Unified turn-on and turn-off snubber circuit energy recovery – single ended

9.3.1

Passive recovery

Conventional inductive turn-on and capacitive turn-off snubber circuits can both be incorporated around a switching device as shown in figure 8.20 where the stored energy is dissipated as heat in the reset resistor. Figure 9.14 shows unified turn-on and turn-off snubber circuits which allow energy recovery from both the snubber capacitor Cs and inductor ℓs. i. Recovery into the load The snubber capacitor energy is recovered by the transfer process outlined in section 9.2.1. Figure 9.14a shows the energy transfer (recovery) paths at switch turn-off. The capacitor Co and inductor ℓs transfer their stored energy to the load in parallel, such that the inductor voltage is clamped to the capacitor voltage VCo. As Co discharges, the voltage across ℓs decreases to zero, at which time the load freewheel diode Df conducts. Any remaining inductor energy is dissipated as unwanted heat in circuit resistance. Proper selection of ℓs and Cs ( ½ Ls I m2 ≤ ½CsVs2 ) can minimise the energy that is lost although all the snubber capacitor energy is recovered, neglecting diode and stray resistance losses. The energy (controlled by and transferred to the turn-on snubber inductor ℓs) associated with freewheel diode reverse recovery current, is also recovered.

Df

Co L

Ds

Df

Do

T

Co

Vs

Da

Dc

+ Lo

Rs Cs

+

DR

Df/b

1:N

on

D1

Do Do

+

(c)

(a)

on

(b)

Figure 9.14. Switching circuits incorporating unified turn-on and turn-off snubber, showing recovery path of energy (a) in Co and ℓs; (b) in Cs and ℓs through Dr.; and (c) recovery circuit when an RC snubber is employed.

At switch turn-on When the switch is off, the freewheel diode Df conducts the load current Im, capacitor voltage VCs = Vs and VCo = 0. Phase one: t P 1 When the switch is turned on, the series inductor ℓs performs the usual turn-on snubber function of controlling the switch di/dt according to (assuming the switch voltage fall time is relatively short) on

i (t ) =

Vs

As

t

(9.27)

The switch current rises linearly to the load current level Im and then continues to a level IRR higher as the freewheel diode Df recovers with currents in the paths shown in figure 9.15a. This diode reverse recovery current IRR is included in the analysis since the associated energy transferred to the turn-on inductor is subsequently recovered.

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233

on The peak switch current Im + IRR is reached after the duration t P 1 A t Pon1 = ( I m + I RR ) s

(9.28)

Vs

As long as the freewheel-diode conducts, the load is clamped to near zero volts, thus Cs remains charged to Vs. Vs

Df

Vs

Vs

L

L

Im O

Im O

A D

Im

A D

Co

L O A D

Co

+

+ IRR ℓs

ℓs

T

+

T

0V

ℓs

Do

0V

Ds

T

Cs

Do

0V

0V

(a)

(b)

(c)

Figure 9.15. Unified turn-on and turn-off snubber at switch turn-on, showing (a) current build-up in ℓs; (b) energy resonant transfer from Cs to Co; and (c) energy transfer from ℓs to Co through Ds.

Phase two: t P 2 The turn-off snubber capacitor Cs charge resonates in the path Cs - Do - Co - ℓs and through the switch T, as shown in figure 9.15b. The capacitor voltages and resonant current are given by (n = Cs / Co) on

Vs sin ωt + I RR cos ωt Z ω Z 1  VCs (ωt ) = V s  1 − (1 − cos ωt )  + o I RR sin ωt 1+n   ω n ω n VCo (ωt ) = V s (1 − cos ωt ) + o Z I RR sin ωt 1+n ω i Cs (ωt ) = i Co (ωt ) =

where Z = ω A s =

ω = ωo

1

ωC o

= Zo

n + 1 n

n + 1 n

(ohms)

Zo =

(rad/s)

ωo =

The freewheel diode Df voltage is V Df (ωt ) = V s + VCo −VCs = V s (1 − cos ωt ) + I RR Z sin ωt

(9.29) (9.30) (9.31) As

Co 1 AsC o

(ohms)

n =

Cs Co

(rad/s)

(9.32)

When the freewheel-diode current reaches its peak recovery level, IRR, it is able to support a voltage which from equation (9.32) sinusoidally increases from zero. Specifically the freewheel-diode reverse bias VDf is controlled such that zero voltage turn-off occurs resulting in low recovery power losses. Stray or inductance deliberately introduced in series with Do (to decrease the resonant peak current given by equation (9.29) as approximately Vs / Z) produces a freewheel-diode recovery step voltage Vs ℓs /( ℓs + Lstray), but the step is always less than Vs. The resonant period prematurely ends (since n < 1) when the snubber capacitor Cs voltage reduces to zero and is clamped to zero by conduction of the snubber diode Ds, as shown in figure 9.15c. Assuming on IRR = 0 (to obtain a tractable solution), equating equation (9.30) to zero yields the time for period 2, t P 2 , that is cos −1 ( −n ) (9.33) t Pon2 =

ω

at which time

i Co (t Pon2 ) =

Vs (1 − n 2 ) Z

(9.34)


and

234

VCo (t Pon2 ) = nV s

(9.35)

Phase three: t P 3 The remaining energy stored in ℓs is resonantly transferred into Co in the path Do - Co - ℓs - Ds, with initial conditions given by equations (9.34) and (9.35), according to on

VCo (ωo t ) = n V s sin (ωo t + φ )

(9.36)

Vs cos (ωo t + φ ) Zo

(9.37)

and

i (ωo t ) = n

The resonant current reaches zero and energy transfer to Co is complete, after a period ½π − φ t Pon3 =

(9.38)

ωo

If the diode reverse recovery energy is reintroduced, based on energy transfer balance, the final voltage on Co is

VCo (t Pon3 ) = nV s2 + ( Z o I RR )

2

(9.39)

The turn-on equations (9.29) to (9.37) are essentially the same as equations (9.11) to (9.14) for the turn-off snubber energy recovery circuit considered in section 9.2.1, except free-wheel diode reverse recovery has now been included. The circuit turn-on voltage and current waveforms shown in figure 9.9 are also applicable. At switch turn-off When the switch is on, it conducts the load current Im and the snubber capacitor Cs voltage is zero, on while the transfer capacitor voltage VCo( t P 3 ) = √n Vs = Vo (neglecting the IRR component) is a result of the previous switch turn-on. When the switch T is turned off, the collector current decreases linearly from Im towards zero in time tfi. Vs

L

L

Df Im O

Df Im O

A D

Vs

Vs

Vs

L

L Df Im O

DR

A D

DR

A D

Co

+

0V

+ Cs

Ds

T

+ Cs

(b)

DR Co

+

Do

Ds

T

T 0V

0V

0V

(a)

ℓs

ℓs

Ds

T

A D

Co

+ ℓs

Df Im O

(c)

(d)

Figure 9.16. Unified turn-on and turn-off snubber at switch turn-off, showing (a) current diversion to snubber capacitor Cs; (b) transfer capacitor Co releasing energy (c) energy transfer to the load simultaneously from ℓs and Co through DR; and (d) energy transfer from Co into the load through DR.

Phase 1: t P 1 The load current is progressively diverted to the snubber capacitor as the collector current decreases, giving a capacitor (and collector) voltage of I t2 t 1 t 1 t v ce = VCs (t ) = (9.40) 0 ≤ t ≤ t fi ( I m − i c ) dt = ∫ I m dt = m ∫ Cs 0 C s 0 t fi C s 2t fi If the collector current reaches zero before any other associated recovery processes occurs, then after the collector current has reached zero, the collector and snubber voltages rise linearly (being clamped in parallel), with currents in the paths shown in figure 9,16a, according to off

Power Electronics

235

v ce = VCs (t ) = ½

I m t fi I m t + Cs Cs

provided ½

I m t fi ≤ V s −V o Cs

(9.41)

The collector voltage reaches Vs at a time given from equation (9.41) when VCs = Vs – VCo as

Cs (V −Vo ) + ½t fi Im s

t Poff1 =

(9.42)

where Vo is given by equation (9.39) and the period duration includes the collector linear fall period tfi. Phase 2: t P 2 When the collector (and snubber) voltage VCs reaches Vs -Vo capacitor Co begins to discharge into the load providing the load current Im. Simultaneously Cs charges to Vs through ℓs, as shown in figure 9.16b. The relevant circuit capacitor voltages and current are n  1  (9.43) i As (ωt ) = I m 1 + cos ωt  1 + n  n  off

 (9.44)  + V s −V o   1  1 VCo (ωt ) = I m Z o (9.45) sin ωt − ωo t  + Vo  n +1 n +1  This phase is complete when the snubber capacitor Cs is charged to the supply voltage, Vs, assuming the inductor current is greater than zero at that time. Let the inductor current be I2 at the end of the offoff period t P 2 and the capacitor Co voltage be V2.

VCs (ωt ) = I m Z o

1  1 sin ωt + ωo t  n +1 n +1

Phase 3: t P 3 The snubber capacitor is clamped to the rail voltage. The transfer capacitor Co and snubber inductor ℓs both release energy in parallel into the load through the paths shown in figure 9.16c. The inductor voltage is clamped to the capacitor Co voltage. The snubber inductor current is off

i As (ωo t ) = I m +

V2 sin ωo t + ( I 2 − I m ) cos ωo t Zo

while the transfer capacitor voltage is VCo (ωo t ) = V 2 cos ωo t + Z o ( I 2 − I m ) sin ωo t

(9.46) (9.47)

One of two conditions form the completion of this phase • •

the transfer capacitor voltage reaches zero before the snubber inductor current reaches zero the snubber inductor current reaches zero before the transfer capacitor voltage reaches zero

The first condition represents the case where the remaining inductor current associated energy is lost as it freewheels to zero in the low voltage path ℓs - Do - DR and the load. In the second case, the inductor current given by equation (9.46) reaches zero, while the transfer capacitor Co continues to discharge into the load as shown in figure 9.16d. The inductor current is prevented from reversing by diode Ds. Once the inductor current has fallen to zero, the transfer capacitor voltage falls linearly to zero as it provides the load current Im. This second case represents the situation when 100% of all snubber (inductor ℓs and capacitor Cs) and diode reverse recovery energy is recovered, that is ½A s ( I m + I RR ) ≤ ½C sV s2 2

(9.48)

Snubber reset and recovery is complete when the snubber inductor current and transfer capacitor voltage are both zero, the collector voltage has ramped to Vs, and the free-diode conducts the full load current Im. From equation (9.47), this stage is complete when VCo( t Poff3 ) = 0, that is   V2 tan−1   Z ( I − I )  ωo m   o 2 Now the switch can be turned on.

t Poff3 =

1

(9.49)

ii. RC-L dual snubber recovery The IGCThyristor is commonly used and characterised with an RC snubber and an inductive turn-on snubber. Figure 9.14c shows how the snubber diode Ds in figure 9.14a can be replaced by a resistor to form an RC snubber, provided diode combination Da - Ds is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. The snubber capacitor stored energy after turn-off, ½CsV2, can be recovered at switch turn-on, while the inductive turn-on energy ½LsI2 is recovered at switch turn-off, provided the RsCs time constant is greater than the LC resonant period.


236

iii. Recovery into the load and supply Figure 9.14b shows a dual snubber energy recovery technique where a portion of the resonance energy is transferred back to the dc supply (as opposed to the load) at switch turn-on, through a magnetically coupled circuit where it is required of the turns ratio that N > 2. This reduces the energy transferred from the snubbers to the load, giving better load regulation under light load conditions. Load regulation with light loads is poor since the snubber capacitor energy is fixed, ½C sV s2 , independent of the load, Im. In the analysis to follow, the recovery contribution of the freewheel diode reverse recovery energy is neglected. At switch turn-on The turn-on phase is essentially the same as the circuit considered in figure 9.14a, except the transformer is seen as an opposing emf voltage source Vs /N. Phase one: t P 1 The switch current fall period is described by equation (9.27) and the time of the first turn-on period is given by equation (9.28). on

Phase two: t P 2 The equations (9.29) to (9.35) are modified to account for the transformer referred voltage Vs /N N − 1 Vs × sin ωt (9.50) i As (ωt ) = i Cs (ωt ) = i Co (ωt ) = on

N

Z

1 VCs (ωt ) = V s × × 1 + Nn + (N − 1) cos ωt  N (1 + n ) 

(9.51)

n (N − 1) (1 − cos ωt ) N ( n + 1)

(9.52)

VCo (ωt ) = V s

The instantaneous power being returned to the supply through the transformer is given by

p (ωt ) =

Vs V N − 1 Vs N − 1 Vs × i As (ωt ) = s × × sin ωt = × sin ωt N N N Z N2 Z 2

(9.53)

The time for this period is given by equation (9.51), when the snubber capacitor voltage is zero 1  nN + 1  t Pon2 = × cos −1  − (9.54)  ω  N −1  The energy returned to the supply is 1 n + 1 V s2 × = × C sV s2 < ½C sV s2 since N > 2 (9.55) w Trans t Pon2 = ( J)

( )

N

ωZ

N

on Phase three: t P 3 Energy continues to be recovered back into the supply Vs through the transformer when the resonant current transfers to the diode Ds. Capacitor Cs charges to Vs and is clamped to Vs by diode Dc. The final voltage on the transfer capacitor Co is

VCo (t Pon3 ) =

Vs  1 + nN 2 − 1  N 

(9.56)

The total energy transferred to the supply through the transformer is the difference between the initial energy in ℓs and Cs and the final energy in Co.

w Trans (t P 2 + t P 3 ) = ½C sV s + ½A s I m − ½C o

V s2

2

 1 + nN 2 − 1 (9.57)  N  If the turn-on inductor current reaches zero before the third phase can commence (due to N being too small), then the turn-off snubber does not fully discharge, and will act as a soft clamp in the subsequent switch turn-off cycle. The capacitors retain the following voltages 2 + Nn − N 2 =Vs − VCs = V s V (9.58) N ( n − 1) N ( n − 1) s on

on

2

VCo = V s

2

2n (N − 1)

N ( n + 1)

2

(9.59)

At switch turn-off The circuit recovery operation at turn-off is essentially the same as when no transformer is used (N→∞), except that the voltage on Co at the begin of turn-off is given by equation (9.59) or equation (9.56), as appropriate.

Power Electronics

237

Operating regions of the dual energy recovery circuits Both the passive unified recovery circuits analysed can be assessed simultaneously for their operational bounds, since the bounds for the transformerless version in figure 9.14a are obtained by setting N to infinitely in the appropriate equations for the recovery circuit in figure 9.14b. Figure 9.17 shows various operational boundaries for the two unified passive energy recovery circuits analysed. The various boundaries are determined from the operating equations for the circuits. The boundaries in figure 9.17a show the regions of full snubbering and for soft snubbering where the capacitor Cs is not reset to zero voltage during the resonant cycles at turn-on. The boundaries are summarised as follows N −2 (9.60) n
1

normalised current

8 full snubbering

6 4

soft snubbering

2

Fig 9.14a

N infinite

100% energy recovery

0.8 N=10 0.6

∨

I

N=4

0.4 0.2

N=2

< 100% recovery

0

(a) 0

2

Co / Cs

normalised reset time

I

1

0

1/n

(c)

max

3

N=2

2

N=100

max min

1 min

0 2

4

capacitance ratio

6

8

Co / Cs

10

1/n

2

4

capacitance ratio

(d)

4

0

0

(b)

4

normalised recovery range

transformer turns ratio N:1

10

0.8

6

8

Co / Cs

10

1/n

Independent of N

0.6 0.4

∨

I − I

all N

I

0.2 0 0

2

4

capacitance ratio

6

8

Co / Cs

10

1/n

Figure 9.17. Unified, passive snubbering characteristics: (a) operating regions with recovery transformer; (b) 100% recovery regions with different transformer turns ratios; (c) normalised circuit reset limits; and (d) normalised recovery range independent of transformer turns ratio.


238

9.3.2 Active recovery i. Recovery into the dc supply Both turn-on and turn-off snubber energy can be recovered into the dc supply using a dedicated buckboost smps formed by Tsmps, Dsmps and Lsmps, shown in figure 9.18. Both snubbers (capacitor Cs and inductor Ls) transfer their energy to the intermediated storage capacitor, Co, from which the energy is smps transferred to the dc supply Vs. The buck-boost smps also maintains a fixed voltage on Co, which facilitates rapid energy transfer of the turn-on snubber inductor Ls energy to Co at switch T turn-off, in time LsIm / VCo. The maximum switch off-state voltage is Vs+VCo. At switch T turn-on, the turn-off snubber capacitor Cs energy is resonated to Co through the loop Cs - T - Co - ℓ - Do, as considered in detail in section 9.3.1. The smps is operated in a discontinuous inductor current mode in order to minimise smps switch and diode losses and stresses. The maximum smps switch and diode voltages are Vs+VCo. Figures 9.18b and c show circuit versions with a reduced component count. With the inductor ℓ removed, the resonant reset current magnitude and period is now only controlled by the turn-on snubber inductor. A further diode can be removed as shown in figure 9.18c, but the number of series components in the turn-on inductor reset path is increase as is the loop inductance associated with the path. Vs

Vs

Vs

Df

Cs T

T Tsmps

off

Lsmps

Ls

T Ds Tsmps

Do Co

+ 0

Lsmps Ls

Dsmps

+ Df

+

Ds Do Co

Tsmps

Lsmps +

0

0

(a)

Cs

+ Df

on Co

Ls

Dsmps

Cs

ℓ Ds

Im

Im

Dsmps

Do

+ Df

Df

Df

Im

(b)

(c)

Figure 9.18. Unified, active turn-on and turn-off snubber energy recovery circuits: (a) basic circuit and (b) and (c) reduced component variations.

9.4

Inverter bridge legs

Capacitive turn-off snubbers (without any turn-on snubber circuit inductance), both active and passive are not normally viable on bridge legs because of unwanted capacitor discharging and subsequent uncontrolled charging current, as considered in chapter 8.4. At best capacitive soft turn-off voltage clamps (operational at >Vs) can be employed to reduce turn-off losses, as shown in figure 8.24. 9.4.1 Turn-on snubbers i. Active recovery - recovery into the dc supply Figure 9.19 shows inverter bridge legs where both switches benefit from inductor turn-on snubbers and active energy recovery circuits. The circuits also recover the energy associated with freewheel diode reverse recovery current. The turn-on energy and diode recovery energies are both recovered back into the dc supply, Vs, via a buck-boost smps. At switch turn-off, the energy stored in Ls is transferred to capacitor Co via diode Ds. For given turn-on snubber inductance Ls, both circuits give the same di/dt in the switches. The capacitor voltages determine the snubber reset time. When both circuits result in the same switch maximum voltages, the reset times are the same. But the capacitor voltages in figure 18.9a are half those for the circuit in figure 9.19b. The main operational difference between the two configurations is the periods when the capacitors are charged. In figure 9.19a, both capacitors are charged at both switch turn-on and turn-off. In figure 9.19b, each capacitor charges once per cycle, one capacitor is charged at turn-on, the other at turn-off. Coupling of the turn-on inductors results in virtual identical waveforms as to when the inductors are not coupled. No net energy savings or gains result. Close coupling is therefore not necessary.

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Vs Ls

Vs

Ds

Co +

T Df

T

Lsmps

Tsmps

Dsmps

Tsmps

Dsmps

Co

Df

+

Ls

Ds

Ls

Ds

Tsmps

Df T Ds Ls

T

Lsmps

Co

Tsmps

Df

Co

+

Dsmps

Lsmps

+ 0

0

(a)

(b)

Im

Im

IDf

IDf

0

t

Irr

0

Im+Irr Im

IT

t

Irr

Im+Irr

Im

IT

0

t

0

Vs+2VC

t Vs+VC

Vs VDf

Vs

VDf

0

t

0

t

Vs+2VC Vs

V

Vs + VC

V

VT

Vs

VT

off

on

off

0

off

on

off

t Vs + VC

t Vs+½VC

Vs

Vo/p

Vs

Vo/p ½Vs

0

Dsmps

o/p

o/p

0

Lsmps

½Vs -VC

(c)

t

0

-½VC

t

(d)

Figure 9.19. Active inductive turn-on snubber energy recovery circuits: (a) multiple single-ended circuit; (b) cross-coupled high frequency circuit; and (c) and (d) respectively circuit waveforms.

9.4.2 Turn-on and turn-off snubbers i. Passive recovery - recovery into the dc supply Figure 9.20 shows an inverter bridge leg where both switches have inductor turn-on and capacitor turnoff snubbers and passive energy recovery circuits. The circuit also recovers the energy associated with freewheel diode reverse recovery current. Both the turn-on energy and turn-off energy are recovered back into the dc supply, Vs. Although this decreases the energy transfer efficiency, recovery into the


240

load gives poor regulation at low load current levels where the capacitor turn-off energy, which is fixed, may exceed the load requirements. Energy recovery involves a coupled magnetic circuit which can induce high voltage stresses across semiconductor devices. Such conditions can be readily avoided if a split capacitor (multilevel) voltage rail, fed from multiple secondaries, is used, as shown in figure 9.2c. Dual snubber (inductor and capacitor) energy recovery occurs as follows. For switch S1, the turn-off snubber is formed by CS1 and DS1, and the turn-on snubber comprises LS1. 1. 2. 3. 4. 5.

The energy stored in CS1 is resonantly transferred to Co1 when switch S1 is switched on, in the path CS1 - Dt1 - Co1 - LS2 - LS1 - S1. The energy stored on Co1 is resonantly transferred to the dc supply Vs through transformer T1 when switch S1 is turned off and (after an underlap period) S2 is turned on (in the path Co1 Lr1 - T1 - S2). When S2 is turned on, the turn-on snubber inductor LS1 releases its energy in parallel with capacitor Co1 (in the path LS1 - Ds1 – Dt1 - Lr1 - T1 - S2 - LS2). The diode Dr1 prevents (by clamping) the transfer capacitor Co1 from reverse charging, by providing an alternate path for the remaining energy in the resonant inductor Lr1 to be returned to Vs via the coupling transformer T1. The transformer T1 magnetising current is also returned to the dc supply Vs, thereby magnetically resetting the coupling transformer T1.

The numerical subscripts ‘1’ and ‘2’ are interchanged when considering the recovery processes associated with switch S2. The recovery circuit can operate at switching frequencies far in excess of those applicable to the IGCThyristor and the high power IGBT. The limiting operational factor tends to be associated with the various snubber reset periods which specify the switch minimum on and off times. Although adequate for IGCThyristor requirements, minimum on and off times are a restriction with the IGBT.

+

+

+

+

Figure 9.20. Unified, passive snubber energy recovery circuits for GTO and GCT inverter bridge legs.

ii. Active recovery - recovery into the dc supply Figure 9.21 shows two similar turn-on and turn-off snubber, active energy recovery circuits, which are particularly suitable for bridge leg configurations. In figure 9.21a, the turn-on snubber section is similar in operation to that shown in figure 9.4 while the turn-off snubber section is similar in operation to that shown in figure 9.13a. A common buck-boost smps is used for each turn-on and turn-off snubber pair. This arrangement is particularly useful when the two power switches and associated freewheel diodes are available in a single isolated module package. The active recovery circuit in figure 9.21b shows the inductive turn-on snubbers relocated. The buckboost smps inputs are cross-coupled, serving the turn-on snubber of one switch and the turn-off snubber of the other switch.

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The interaction of turn-off snubbers in both circuits can create high L-C resonant currents as discussed in section 8.4. In each case, two buck-boost smps and intermediate storage capacitors Co can serve numerous bridge legs, as in a three phase inverter bridge. Theoretically the recovery smps diodes Dr can be series connected, thereby eliminating a diode, as shown in figure 9.21c. But to do so assumes the two inductor recovery currents are both synchronised and equal in magnitude. Extra diodes, Di are needed to divert any inductor current magnitude imbalance, as shown in figure 9.21c, which negates the diode saving in having series connected the recovery diodes Dr. Alternatively, the single inductor recovery circuit in figure 9.21d may be used provided the smps switches are not conducting simultaneously. Synchronisation of the smps switch to its associated main switch avoids such simultaneous operation. The recovery circuits in figure 9.21 parts c and d are applicable to both the bridge leg circuits in figure 9.21 parts a and b. The circuit in figure 9.21a is readily reduced for single-ended operation, as shown in figure 9.18.

Co

Co

+

Dr

x

Tsmps

x

Dr

Cs

see figure 9.4

Lsmps

y

Tsmps

y

Dr

Dr

Co

Co

+ (d)

Lsmps Tsmps

Co

Co +

x

Dr

x

Di see see figure figure 9.3 9.4

Dr Di

Dr y Co

Tsmps

y Co

+

Lsmps (c)

Figure 9.21. Unified, active snubber energy recovery circuits: (a) multiple single-ended circuit; (b) cross-coupled high frequency circuit; and (c) and (d) coupled smps variations.

9.5

Snubbers for multi-level inverters

The multi-level inverter introduced in Chapter 15.3 utilises series connected switching elements with each switch operated in a voltage clamped mode. Three multi-level inverter configurations are commonly presented • the diode clamped multi-level inverter – see figure 15.38 • the flying capacitor multi-level inverter – see figure 15.40 and • the cascaded H-bridge multi-level inverter – see figure 15.41


242

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter Since the cascade multilevel inverter (see figure 15.38) is comprised of identical H-bridge modules, any of the snubbers for bridge legs considered in section 9.4 are applicable. Snubbers can be active or passive, incorporating only an inductive turn-on snubber or a capacitive soft turn-off snubber or both turn-on and turn-off snubbers. When the cascaded H-bridge approach is used for three-phase VAr compensation, real power must be returned to the ac system if the recovered energy is in excess of the inverter losses. 9.5.2 Snubbers for the diode-clamped multi-level inverter Various snubbers have been proposed for the neutral point clamped inverter which involves a split dc rail composed of two series connected capacitors, as shown in figure 15.38. Generally devices are asymmetrically stressed or indirectly snubbered. Indirect snubbering approaches should be avoided since the main problem with high power multilevel inverters is the decoupling of circuit inductance. For levels higher than three, only the outer switches have a fixed dc reference, viz., 0V or Vdc, hence recovery circuits on these switches can return energy to the outer link capacitors. Energy recovery from snubbers on the inner switches is hampered by the clamping diodes. Thus recovery of snubber energy in a three-level inverter is viable since the two link capacitors are in fact two outer capacitors, referenced to the dc rails. Recovery must be into the associated level capacitor of a given switch, if recovery circuit component voltage ratings are to be limited to that of the main switching elements. 9.5.3 Snubbers for the flying-capacitor multi-level inverter Turn-off snubbers for the flying capacitor inverter are problematic since the switch clamping principle is based on indirect clamping and the level clamping capacitors support multiple-voltages in excess of the individual device operating voltage ratings. As seen in figure 15.40, the flying capacitors associated with inner switches support lower voltages than the outer capacitors. As a general rule, if snubbering is being considered, then a series connection approach as in section 9.6 is viable, provided device switching delays are minimised. The turn-off delay of the GCThyristor can be reduced to less than 400ns if high di/dt reverse gate current drive is employed. The key limitation in reverting to series connected device operation is the loss of amplitude modulation offered by multi-level circuits. As a consequence, series connected devices produce higher output dv/dt voltages. The diode clamped inverter with numerous series connected devices is a favoured medium voltage compromise. 9.6

Snubbers for series connected devices

Two basic approaches are adopted when power-switching devices are series connected in order to operate circuits at voltages in excess of individual device voltage ratings. • Use a multilevel structure as considered in Chapter 15.3, where individual switches are effectively soft clamped or • series connect devices with fast turn-on and turn-off, minimising device switching delays thereby improving transient voltage sharing; possibly using simple R-C snubbers The use of turn-on and turn-off snubbers greatly increases system complexity and size but does offer a method for reliably operating series connected devices, a modular structure, and the possibility of obtaining gate drive power for individual series connected cells. Fast, noise free, isolated uni/bidirectional signal transmission, without any isolation or dv/dt problems, to virtual any voltage potential is possible with fibre optics. The production of isolated gate drive supply power at tens, possibly hundreds of kilovolts is problematic. The usual approach for deriving emitter level supplies involves tapping energy from static voltage sharing resistors, resulting in high resistor losses, or tapping energy from the R-C snubber during switching transitions. Both methods do not provide fail-safe device operation (in the off-state, with static dv/dt capability) at the application of the HV dc link voltage. The use of inductive and capacitive switching snubbers offers two advantages, other than enforcing transient voltage sharing of series connected devices, which may mitigate the associated increased cost and complexity • Better device I-V utilisation and a higher switching frequency • The derivation of cell level gate power supplies from snubber recovered energy Many of the previously presented active snubber energy recovery circuits in this chapter are directly transferable to multilevel inverter configurations, thereby extending the current and frequency capabilities of the main switching devices, particularly the GCThyristor, and freewheel diodes. Once

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snubbers are employed, traditional series device connection with snubbers is simpler than a multilevel approach, but does not offer the multilevel output voltage features (amplitude modulation and reduced dv/dt) of multi-level inverter configurations. The snubber recovered energy is usually far in excess of that that can be utilised for gate drive power. The topological nature of series connected devices precludes any form of relatively simple snubber energy recovery (active or passive) other than recovery back into the dc link supply. 9.6.1

Turn-off snubber circuit, active energy recovery for series connected devices

i. Recovery into the dc supply Series connection of switches and diodes requires static voltage sharing (resistors) and transient voltage sharing circuitry, viz., capacitive turn-off snubbers for voltage sharing during turn-off and inductive turnon snubbers for voltage sharing during turn-on. Figure 9.22 shows series connected devices, each modular cell level incorporating a main switch and inverse parallel connected freewheel diode, plus a turn-off snubber Cs - Ds, a resonant circuit L - Do, an intermediate energy storage capacitor Co, and buckboost smps recovery circuitry Tsmps - Lsmps - Dsmps, as shown in figure 9.13a and considered in 9.2.2. The recovery smps is operated so as to maintain a near constant voltage on the intermediate storage capacitor Co. The cell energy recovery switches Tsmps are synchronised, all being turned on for up to the switch minimum on-time (immediately before the switches T are turned off), and turned off when the main switches T are turned off. The timing sequence for the control signal, switch T and recovery switch Tsmps is shown in figure 9.22b. Note that the transmitted control signal is truncated at the switch T turnoff edge, by the switch minimum on-time, tdelay, which is approximately ½π√LCs. When Tsmps are turned off, the inductive stored energy in each Lsmps is returned to the dc link through each corresponding diode Dsmps as shown in figure 9.22a. Any imbalance in the individual inductor current magnitudes, involves currents in excess of the minimum of all the inductor currents being diverted to the cell snubber capacitor Cs through Dsmps - Cs - Ds - Lsmps. The inductor recovery current differentials are minimal compared to the principal current in the switches, hence do not unduly affect capacitive turn-off snubber charging, hence transient turn-off voltage balancing action. Vs Ls

T

Df DC rail

Io

Dsmps

+ T

Df

Cs

Da

L

Ds

Tsmps Co

+

Lsmps tdelay

signal

on

T

Df

t

Dsmps

+

T

Cs

Da

L

Ds

on

Tsmps Co

+

t

Lsmps Tsmps

on t

Dsmps

+ T

Df

Cs

Da

L

Ds

Tsmps Co

Co >>Cs

ILsmps

+

t

Lsmps

0V rail

(a)

(b)

Figure 9.22. Active turn-off snubber energy recovery for series GCT connected, inverter bridge legs: (a) modular cell circuit and (b) timing diagram.


244

The turn-on snubber Ls in figure 9.22 is indirectly clamped, with the stored energy released into the series string of turn-off snubber capacitors. Link inductance is mandatory in order to control recharging of the turn-off snubber capacitors as considered in section 8.4. Although the smps switch Tsmps and diode Dsmps are high voltage devices, rated at the cell voltage level, both are not particularly stressed during energy recovery switching, since the recovery buck-boost smps are operated in a discontinuous inductor current mode. The switch Tsmps turns on with zero current, without any diode reverse recovery effects, while the diode Dsmps suffers minimal reverse recovery, since its principal current reduces to zero controlled by Lsmps, with recovery di/dt current (or voltage) controlled (or supported) by the smps inductors Lsmps. A static voltage-sharing resistor across each cell (not shown in figure 9.22) compensates for various static voltage and current imbalance conditions on both the main switch T and smps diode Dsmps network, particular during converter start-up and shutdown sequencing. System start-up The intermediate transfer stage capacitor Co can be used to provide a source of gate level power, via a dedicated smps. One of two start-up sequences are used to build-up gate power and cell voltages before normal switching operation can commence. In both cases, an ac to dc single or three phase halfcontrolled converter is used to ramp charge the intermediate capacitor Co associated with the lowest potential cell (typically Co operates at about 50V to 100V). This capacitor Co in turn provides gate power, via a dedicate 100V dc to ±15Vdc smps, for the lowest level switch T. By using series blocking/directing diodes, rated at the cell voltage rating, one ac to dc converter can supply the lowest potential cell of all bridge legs, as shown in figure 9.23a. Proprietary pre-charging sequences are used to charge Co on higher cell levels, depending on whether the dc link voltage is established or not. As each Co is progressively charged, its associated gate supply smps is self-activated, enabling external control of that switching cell. Inverter start-up can involve the application of the dc link voltage before gate level power has been established. This does not present a problem for GCThyristors, but in the case of the IGBT, a low passive impedance gate to emitter circuit is needed to avoid inadvertent device turn-on due to Miller capacitor dv/dt effects. (a) Start-up with an established dc link voltage In the case of an inverter with an established dc link voltage, each level switch, hence cell, supports half its normal operating voltage, and each snubber capacitor Cs is charged to the cell voltage level. All the intermediate energy storage capacitors Co are discharged, except for the lowest potential cell capacitor, which has been ramp charged by the ac to dc converter. The recovery smps (and main switch) of the lowest potential cell is operable. Tsmps of the lowest potential cell is turned on, then off and the current in the associated Lsmps tends to overcharge Cs of the lowest potential cell. This forces current to increase through the Co - L - Ds combinations of the higher potential cells as each Cs is forced to decrease its charge, therein charging higher-level capacitors Co. The voltage on Cs of the lowest potential cell can be doubled before the cell reaches it normal operating voltage level. Thus for n series connected cells, the operating limit of the intermediate capacitor Co voltage satisfies (n-1)VCo < 2Vs /n. That is, any smps sourcing from Co used to provide gate supply voltage rails for the main switch T, must be able to function (convert) down to a voltage level satisfied by this inequality equation. When a cell voltage reaches its operating voltage limit, the associated main switch is turned on briefly to resonantly discharge the snubber capacitor Cs. The supported voltage is redistributed among the other cells, which typically, are only supporting half the normal cell operating voltage. (b) Start-up with no pre-existing dc link voltage In the case where the dc link voltage has not been established, a similar charging process is used as for the case of a pre-existing dc link voltage. The dc link capacitance must be on the inverter side of the isolation. The dc link capacitor is initially charged through series diodes Df to the maximum cell voltage as capacitor Cs of the lowest potential cell is parallel charged from Co by its associated recovery smps. The lowest potential recovery smps is commutated numerous time in order to charge the dc link capacitance which is usually significantly larger in capacitance than Cs. Once the link capacitor is charged to the maximum allowable cell voltage, the main switch T of the lowest potential cell is turned on to reset its associated snubber Cs voltage to zero. The start-up mechanism used with a pre-existing dc link voltage can then be used. Once Co in each cell is charged sufficiently to enable its gate voltage smps to become operational, synchronised use of the recovery smps at each level allows charging of the dc link capacitor to the operational voltage level (in fact slightly in excess of the rectified peak level). Then the vacuum circuit breakers before the rectifier, feeding the series connected device circuit, can be closed, which results in zero line current in-rush. Connection of the load and an interfacing filter may be problematic without dedicated contactors, as is the influence of the output filter on the cell charging mechanism previously outlined. Other gate power derivation methods Gate power derived from switching recovered energy cannot be maintained during prolonged standby periods. Using dropper resistors (as for static voltage sharing) to provide all gate level power

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requirements results in high dissipation losses, particularly during continuous standby periods (that is, 100% dissipation duty cycle). Although resistors are used for steady-state series voltage sharing, the current associated with this mechanism (≈10mA, depending of the degree of device matching and operating temperature range) is well below that needed for gate power (≈50W for IGCThyristors but much less for IGBTs). But this level of sharing resistor current (≈10mA) may be sufficient to trickle maintain gate level supplies of cells in the off-state during prolong standby periods, using variations on the circuits shown in figure 9.23c. Depending on the load and output filter, it may be possible during prolong standby periods to sequence the inverter between 000 and 111 states, thereby producing zero average voltage output between phases but activating the snubbers hence resonant recovery circuits that charge each Co. Provided sufficient switch voltage redundancy is available, sequential bootstrapping is possible where each level is boot strapped supplied from the immediate next lower level, as shown in figure 9.23b. (See figure 7.4). In the case of a positive voltage as shown in figure 9.23b, each switch, starting from the lowest level is sequentially turned on and off, thereby transferring gate energy from the lowest level to the highest level. (An expanding repetitive simultaneous on-state sequence is used, progressively involving higher potential cells.) This approach is viable in single-ending series connected switch applications. Although each bootstrap diode Dbs is rated at the cell level voltage, in the case of inverter legs, only half the inverter leg devices can be supplied, since any bootstrap diode bridging the pole centre take-off node must be rated at the full dc link voltage (actually ½n-1 levels can be charged since the lowest level cell is not bootstrapped). If the bootstrapping voltage is referenced with respect to the high potential terminal of the cell, then the supply voltage on Co is bootstrap by transferring energy from the highest potential cell down to the lowest potential cell. A similar approach can be used with transformer isolated smps’s transferring power between adjacent levels, which need only be rated at the cell level voltage. Again, this approach is viable in single-ended applications, but in the case of inverter legs, the pole output take-off node cannot be readily bridged by an smps because of the high dc link voltage blocking and isolation requirement. Also, each smps experiences dv/dt stresses when the level switches are commutated. hv

+

Db3

Co3 Db2

+

+

Co2

Co1 +

Vo

+

+

Cell 2

+ +

Co1

(b)

15V 0

Dbs 0V

(a)

15V

0 +

Co2

+

Dbs Db1

Co3

hv

Cell 3

15V

Cell 1 (c)

Figure 9.23. Gate supply derivation methods: (a) ac to dc half-controlled converter for ramp precharging of all lowest leg level capacitors Co; (b) bootstrapping a positive voltage supply; and (c) Zener diode based sources using static voltage sharing resistors or/and R-C snubber resistors.

9.6.2

Turn-on snubber circuit active energy recovery for series connected devices

i. Recovery into the dc supply An active energy recovery, inductive turn-on snubber as shown in figure 9.4 (usually with an R-C turn-off snubber), can be adapted and used at each series cell level, therein providing gate level power possibilities from Co and energy recovery through series connect buck-boost smps recovery circuitry, as shown in figure 9.24a. The capacitor Co is configured to be connected to the emitter of switch Tsmps. Energy stored in the turn-on snubber inductor Ls is transferred to the intermediate storage capacitor Co via diode Ds at switch T turn-off. The switching sequence is shown in figure 9.24b. Each recovery smps maintains the voltage near constant on its associated Co and the higher this voltage the faster the inductor Ls current is linearly reset to zero, in time treset = LsIm / VCo. Excess energy on Co is transfer (recovered) to the dc link by synchronised switching of Tsmps. Mismatched inductor Lsmps current


246

magnitudes and durations are diverted to charge Co of any cell attempting to recover a lower current magnitude, by turning off all Tsmps just before all the main switches T are turned off, as shown in figure 9.24b. This balancing effect is minimal (but does eliminate any smps diode forward recovery effects) and any current imbalance subsequently tends to overcharge the output capacitance of the main switch of the cells with recovery current in excess of the minimum of all the smps recovery currents. Some form of turn-off snubbering is therefore necessary in order to avoid excessive main switch T voltages at turn-off. The voltage rating of the various cell circuit semiconductors is increased by the voltage on Co. A cell static voltage sharing resistor helps maintain steady-state voltage balance of both the main switch T and the smps diode Dsmps. a Start-up One ac to dc converter can be used to pre-charge each lowest level capacitor Co of each inverter leg, as shown in figure 9.23a, provided the path to each inverter leg incorporates a series blocking/directing diode, rated at the cell voltage level. The start-up sequence, using the lowest level smps to charge higher level Co and the dc link to the sum of all Co voltages, is straightforward. Synchronised operation of all the smps can then gradually fully charge the dc rail, if it is not already pre-charged.

Vs tdelay

signal

Io

on T

Df

t

Dsmps T

Ds

on

Tsmps

t

Ls +

Co

Tsmps

Lsmps

on t

T

Df

Ds

ILsmps

Dsmps

t

Tsmps

Ls

0

+

Co

Lsmps

(a)

(b)

Figure 9.24. Active turn-on snubber energy recovery for series GCT connected, inverter bridge legs: (a) modular cell circuit and (b) timing diagram.

9.6.3

Turn-on and turn-off snubber circuit active energy recovery for series connected devices

i. Recovery into the dc supply If a single inductive turn-on snubber Ls is used in the dc link as in figure 9.22a, its stored inductor energy at switch turn-off is transferred to the capacitive turn-off snubbers of cells supporting off-state voltage. During switching, this causes voltage ringing between the cells and the link inductor. This inductor is rated at the full dc link voltage and cannot be clamped by the usual resistor-diode parallel connected reset circuit as in figure 8.19a. This is because any reset components (R-D) need high voltage ratings – in excess of the dc link voltage during diode Df reverse recovery. For this reason, an inductor snubber (possibly saturable) may be used at each cell level, giving a complete modular cell structure. Active snubber energy recovery of both inductive and capacitive energy is possible, although it may be convenient to resistively dissipated the turn-on inductive snubber energy, which is load current dependant, ½LsI2. Dual, unified active snubber energy recovery can be achieved by using the recovery circuits shown in figure 9.21b, but with the smps diodes series connected as shown in figure 9.25a. For a modular cell structure, all the cells are configured as for the lower switch in figure 9.21a. This switch configuration in figure 9.21a is preferred since capacitor Co can be readily pre-charged to initiate the start-up sequence

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for charging higher level Co, which can be used to derive gate level power for the associated cell. A relatively low voltage on capacitor Co (if Co operates at about 5 to 10% of the cell operating voltage) may necessitate a long switch T minimum off-time in order to ensure reset of the turn-on inductor current to zero. This is not a problem for GTO type devices which have minimum on and off time limitations. Higher operating voltages for Co necessitates a more complicated smps to derive gate level power for switch T. At higher cell operating voltages, the intermediate storage capacitor Co can be modified to the circuit in figure 9.25b. The low voltage output lv can be used to power cell start-up circuitry. The resonance inductor ℓ (in series with the turn-on snubber inductance Ls) is used to control the magnitude and duration of the resonant period of Cs transferring its charge to Co. The minimum value of inductor ℓ can be zero if Ls is large enough to satisfactorily control resonant reset circuit conditions without ℓ. A further simplification can be made by removing a resonant circuit diode as shown in figure 9.25c, which is derived from the circuits in figure 9.18. The timing sequence in figure 9.22b for turn-off snubbers is used. One functional design constraint should be observed. At switch turn-on, current builds up in Lsmps because of the voltage on Ls, during the later part of the cycle when Cs resonates its charge to Co. This relatively small current magnitude linearly increases to a magnitude dependant on the relative magnitudes of Ls to ℓ and Lsmps, and the magnitude of the voltage retained on Co. Once established, a near constant, slowly decreasing current flows in a zero voltage loop, Lsmps - Dsmps - T - Ls, and is recovered during recovery smps action at switch turn-off. 0

Vs

Co1 +

lv

Io

Cs T

+

ℓ

Df

Dsmps

(b) Co2

Tsmps

Ds

+

hv Do Co

Ls

Co1 >> Co2

Lsmps +

Cs

Cs T

+ Df

Ls

ℓ

Dsmps

T

Tsmps

Df

Tsmps

Ds

Dsmps +

Ds

Do Co

Lsmps +

Ls

Co

Lsmps +

0

(a)

(c)

Figure 9.25. Active turn-on and turn-off snubber energy recovery: (a) circuit for series GCT and IGBT inverter bridge legs; (b) high voltage replacement circuit for Co; and (c) reduced component variation of part a.

(a) Start-up The capacitor Co of the lowest potential cell (in each bridge leg) is negatively ramp charged by a dedicated ac to dc converter as shown in figure 9.23a. This establishes cell internally generated gate supply power and hence external control of both switches of the lowest potential cell. The recovery smps of the lowest potential cell is operated in a discontinuous mode, which charges up the turn-off snubber capacitor Cs of that cell. Simultaneously current flows in three other parallel paths, tending to charge up the dc link capacitor, viz. • the series connected Lsmps - Dsmps • the series connected Ls - Df • the series connected Co - Do - Df Thus provided the smps of the lowest cell delivers a high current, each Co receives charge before the current is diverted and built up in inductors Lsmps and Ls. The dc link capacitor simultaneously receives charge. The switch Tsmps on-time, hence its current, is not restricted during the start-up procedure. Once gate power, hence external control is established on each cell, judicious operation of each smps and main switch T can facilitate charging of the dc link capacitor and contains all cell voltages to within the rated cell voltage. The start up mechanism may necessitate a suitable diode connected in series or anti-parallel with Tsmps.


248

(b) Shut down After the dc link has been isolated, under zero inverter output current conditions, using a vacuum circuit breaker on the ac side, the intermediate capacitor of the lowest potential cell (in each bridge leg) is maintained in a partially discharged state by a resistive load which is switch connected to the capacitor Co of the lowest potential cell. The auxiliary ac to dc converter used to initially charge Co is disabled during normal operation and shut-down, with all the ac to dc converter thyristors off, therefore blocking current in both directions. Alternatively, if this ac to dc converter has suitable two quadrant operational modes, then the energy continually being transferred to Co from other cells, can be recovered into the low voltage ac source. The various smps and main switches are operated so as to maintain equal voltage across all cells (by sequentially commutating each main switch on then off), gradually decreasing the dc link voltage as energy is continually, but controlled, being transferred to and removed from the lowest potential cell capacitor Co. 9.6.4

General active recovery concepts for series connected devices

In each of the three snubber circuits considered for series connected devices, the common key recovery mechanism is performed by a buck-boost smps, with components rated at the cell voltage level. Figure 9.26 shows two basic underlying recovery techniques for transferring energy from Co through an inductor, into the dc supply at a higher potential. The key difference between the two techniques is the polarity orientation of the energy source Co and the dc supply Vs, with respect to their common node. • Figure 9.26 parts a and b show boost converters, where energy is drawn from Co when energy is being delivered to the supply Vs, via an inductor. • Figure 9.26 parts c and b show buck-boost converters, which do not involve Co during the period when energy is being delivered to the supply Vs, via an inductor. A common requirement is that an smps output (whether inductor-diode for buck-boost and inductordiode-Co for boost) span a cell, thereby inherently interconnecting in series any number of cells. Each intermediate storage capacitor Co must therefore be connected to one cell terminal. To confine further the possibilities, it is unlikely that Co referenced with respect to the cell collector will yield a useful active recovery circuit. If the capacitor Co is referenced with respect to the switch collector/anode, Co undergoes high dv/dt voltages with respect to the switch gate. This complicates any smps using the stored capacitor Co energy for gate drive purposes. The polarity orientation of Co and the recovery smps components are therefore restricted to the four possibilities shown in figure 9.27. Series recovery assumes the smps inductors conduct an identical instantaneous maximum magnitude and same duration current. +

D

Vs

Co Ls

+

+

ON

T

OFF

OFF

T Vs

Ls

Co

D

+ ON (a)

+

(b)

Co

Vs Ls R

Ls

+

Co

Vs

(c)

(d)

Figure 9.26. Underlying energy recovery circuits when energy in Co is stored at different potentials: (a) and (b) boost smps recovery and (c) and (d) buck-boost smps recovery.

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249

(a) Start up The general cell structures and their recovery smps can inherently be used to charge other series connected cells and the dc link, and to provide a dc source (the intermediate storage capacitor Co) from which to derive cell level power supplies for the gate level circuitry. Specific proprietary switching sequences are required at start-up, depending on the cell circuit arrangement, the output filter and load, the dc link and ac rectifier input arrangement and initial conditions. (b) Shut down At shut down, once the inverter is in standby, the dc link supply is isolated (by opening the ac side vacuum circuit breakers) under zero current conditions, then the dc link voltage is cyclically discharged into the load via the series connected cells. Such link discharge using cell switching sequences is problematic when • each cell voltage reaches a level where Co falls below a level to maintain operation of the smps used to provide gate level voltage which allows the cell switches to operate; or • cells in another inverter legs cease to operate sooner. Such limitations are mitigated by ensuring the smps that operates across Co has a wide (low minimum bounds) input voltage operating range. If the load is isolated at shut down, then the dc link energy can be sequentially transferred to Co of the lowest potential cell in each leg and dissipated in a single ended resistive dumping circuit or recovery from Co via the ac to dc converter (fully controlled) used during the start-up sequence, as shown in figure 9.23a. The sequence involves progressively, but sequentially, not using higher-level recovery smps. Fail-safe start-up and shut down sequencing, so as not to over-volt any cell, usually require cell operational coordination. The fibre optic communications link for cell level on/off control of the main switch T, is therefore bidirectional.

+ Co

Co +

(a)

(c)

(b)

(d)

+ Co

Co +

Figure 9.27. Cell active energy recovery from Co with: (a) and (b) a boost converter and (c) and (d) a buck-boost converter.

9.7

Snubber energy recovery for magnetically-coupled based switching circuits

Coupled circuits can induced circuit and in particular switch voltages that exceed the supply voltage. These increased voltages are associated with two factors: • leakage or uncoupled inductance energy release • time-displaced energy-transfer coupled-circuits, as with the buck-boost converter or coupled voltages as with push-pull centre tapped transformer circuits Both factors come into operation with the two buck-boost isolated output converters shown in figure 9.28. When energy is drawn by the coupled circuit secondary, a voltage is induced into the primary, increasing the voltage experience by the switch in the off-state. Energy associated with leakage


250

inductance further increases the switch T voltage. If a basic R-C-D turn-off snubber is used, the capacitor stored energy is increased from ½C sV s2 , if the switch voltage were to be limited to Vs, to in 2 excess of ½C s (V s + v o /N ) , where N is the transformer turns ratio as defined in figure 9.28. The leakage energy adds to the voltage component. 9.7.1 Passive recovery Figure 9.28a show the circuit of a passive turn-off snubber energy recovery configuration for an isolated buck-boost converter. It is based on the circuit in figure 9.31j, where the transformer leakage inductance is effectively the turn-on snubber inductance. When the switch T is turned off, the snubber capacitor Cs charges from - Vs to a voltage vo /N, controlled by the leakage inductance which causes the capacitor Cs to charge to a higher voltage. Turn-off capacitor Cs snubbering of the switch is achieved indirectly, through the dc supply Vs. At switch T turn-on, the charge on Cs resonates in the loop Cs - T - Ls - Dr, reversing the polarity of the charge on Cs. This reverse voltage is clamped to Vs, as the diode Ds conducts and the remaining energy in Ls is transferred (recovered) to the dc supply Vs. Tr

+

Cs

1:N

Vs

Lr

Do

Ds

Lp

+

Ls Co

R

Ds

vo Vs

Dr

+

+ R

vo

1:N

T

(a)

Ls Co

Lp

Dr

Cs

L

Do

T

(b)

Figure 9.28. Recovery of leakage inductance energy: (a) passive and (b) active recovery.

9.7.2 Active recovery Figure 9.28b show the circuit of an active turn-off soft snubber energy recovery configuration. Coupled circuit leakage inductance energy is transferred to the intermediate storage capacitor Cs via Ds at switch turn-off. The voltage on Cs is maintained at a voltage related to vo /N by the buck-boost smps formed by Tr, Lr and Dr, which returns leakage energy to the dc supply Vs. The circuit function is to clamp the switch voltage rather than to perform a turn-off snubber action. The maximum switch voltage is near constant, where as the voltage experience by the switch at turn-off in figure 9.28a, although variable, is snubbered, but dependant on the output voltage vo. In both circuits, an R-C snubber may be required across the switch T since the recovery snubber circuits do not decouple stray inductance not associated with the coupled magnetic circuit. Similar snubber or clamping circuits can be use with push-pull converters which utilise a centre-tapped transformer, as in figure 17.16.

9.8

General passive snubber energy recovery concepts for single-ended circuits

Snubbers are used for stress reduction at • switch turn-on - involving series inductance • switch turn-off – involving shunt capacitance • freewheel diode recovery - involving series inductance and the snubber may incorporate more than one of these stress arresting functions. A single ended switching circuit usually incorporates a switch T, a freewheel diode Df and an inductive load, where the load may be configured to be in • the emitter/cathode circuit of T or • the collector/anode circuit of T. The input energy source, the switch, diode and load may be configured to perform any of the following functions

251

Power Electronics

• forward converter • buck converter • boost converter or • buck-boost converter The differentiation between the forward converter and the buck converter is that the inductive element is part of the active load in the case of the forward converter. Figure 9.29a shows a switch-diode and inductor circuit combination, assuming a collector load circuit, which can be configured as any type of converter viz., forward, buck, boost, etc. Equivalent emitter load circuits, as well as collector loadings, are shown in figures 9.30 and 9.31, which present systematically a more complete range of circuit possibilities, in each case, all with exactly the same functional snubber circuit. Energy recovery into the load is usually associated with a parallel connected capacitor discharging (instantaneous change in capacitor current to match the load current is possible) while recovery back into the source is usually associated with a parallel connected inductor or magnetically coupled circuit releasing its energy (instantaneous change in inductor terminal voltage to equal the supply voltage is possible). Ac and dc circuit theory allows all these circuit configuration combinations to be generalised. This is because a snubber is an ac circuit – performing a transient function - while the source and load tend to be dc components (constant voltage and constant current sources respectively). Therefore it is possible to interchange the connections of the snubber (an ac circuit) with the connections to the dc voltage source, since ac-wise, a dc source appears as a short circuit. The snubber function can be achieved directly or indirectly. An operational mechanism to be appreciated is the topological relative orientation within the principal circuit of the turn-on snubber inductor or turn-off snubber capacitor. Turn-off snubber - capacitor: Circuits in figure 9.29c and d show the turn-off snubber Ds - Cs combination parallel to the switch (direct snubbering) or alternatively connected across the freewheel diode to the dc rail (indirect snubbering). AC circuit wise these are the same connection since the dc source can be considered as a short circuit at high frequency. When Ds - Cs are parallel connected to the switch (direct snubbering), the capacitor charges as the switch voltage rises at turn-off, while in the case of the snubber being across the freewheel diode (indirect snubbering), the capacitor discharges, and by Kirchhoff’s voltage law, the switch voltage is indirectly controlled to be the difference between the capacitor voltage and the source voltage. Practically it is preferred to place the Ds - Cs snubber directly across the element to be protected, the switch, since the source may not be well decoupled. Turn-on and diode reverse recovery snubber - inductor: Circuits in figure 9.29a and b show the inductor L configured such that the snubber turn-on inductor is in series with the switch (direct snubbering) or alternatively in series with the freewheel diode (indirect snubbering). Both arrangements perform the same function at switch turn-on. Assuming a constant current in the inductor L, by Kirchhoff’s current law, whether the turn-on inductor controls the rate of rise of current in the collector (direct snubbering) or rate of current fall in the diode (indirect snubbering), the complementary element has its current inversely controlled. Figure 9.30 shows variations of a snubber for recovering the energy associated with freewheel diode reverse recovery. All twelve circuits have the same functional operating mechanism, although a number have been published – even patented - as different. US patent 5633579, 1997, according to the three claims, explicitly covers the boost converter snubber circuit in figure 9.30a. In protecting the specific boost converter circuit, all the other topological variations are inadvertently and unwittingly implicitly precluded. Although a highly skilled expert in the art, Irving, IEEE APEC, 2002, published the next recovery circuit, figure 9.30b, as a new diode recovery snubber for the boost converter. Passive inductive turn-on snubber energy recovery circuit variations are shown in figure 9.31, for collector and emitter connected buck, boost, forward and buck boost converters. Six versions exist with the circuitry in each of the switch emitter and collector circuit. Figure 9.32 shows turn-off and turn-off plus turn-on passive recovery circuit variations. The circuitry can be in the emitter or collector (as shown) circuit.


252

Reading list Boehringer, A. et al., ‘Transistorschatter im Bereich hoher Leistungen und Frequenzen’, ETZ, Bd. 100 (1979) pp. 664-670. Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978. Williams, B. W., et al., ‘Passive snubber energy recovery for a GTO thyristor inverter bridge leg’, Trans. IE lEEE, Vol. 47, No. 1, Feb. (2000) pp. 2-8. Williams, B. W., ‘High-voltage high-frequency power-switching transistor module with switching-aidcircuit energy recovery’, Proc. lEE, Part B, Vol. 131, No. 1, (1984) pp. 7-12. Finney, S. J. et al., ‘High-power GTO thyristor chopper applications with passive snubber energy recovery’, Proc. lEE, EPA, Vol. 144, No. 6, (1997) pp. 381-388.

Problems 9.1.

For the circuit in Figure 9.14a show that the upper current limit for total energy recovery is given by ½ Ls I m2 ≤ ½CsVs2 .

9.2.

Derive capacitor Cs voltage and current equations which describe the operation of the turn-off snubber energy recovery circuit in figure 9.13. Assume the storage capacitor Co to be an ideal voltage source with polarity as shown.

Power Electronics

253 +

inductive freewheel diode reverse recovery snubber - passive energy recovery

+

Dr

Df Ls

Cs Ds

L

inductive turn-on and capacitive turn-off snubber - passive energy recovery

T 0 + +

+

Df

Dr

Cs

L

Cs Ds

Ls

Dr Co

Df

Do

Ls

+

T

Df

C

L

(d) T

+

Dr Do

Ds

(a)

+

Ls

Ds

L

Cs

T

0

0

0 +

+ x

Cs

Df

Generalised switched-mode circuit

B

+

T

Df

Ds

+

Do

+

Df

Dr

L

C Ls

Ls

Ds

Ds

L +

+

L

Do

y

A

Df

Dr Co

0

C

T

Cs

T

0

z Ls

0V

Cs L

+

Dr T

ℓ

(b)

+

Ds

L

Cs

T 0

Ls

Dr

+

ℓ

T 0

inductive turn-on snubber - passive energy recovery

capacitive turn-off snubber - passive energy recovery

Co

L

Cs

Df

ℓ

+

Df

Ds

Do

(c)

0

+

Dr

Ds

ℓ

Df

Co Dr Do

+

L

Cs T 0

converter

ports

transfer function

nodes

forward /buck

B/A

δ

xy/xz

boost

A/C

1 / (1- δ)

xz/yz

buckboost

-B/C

-δ/ (1- δ)

yx/yz

Figure 9.29. Snubber energy recovery circuits for generalised switch-diode-inductive element circuit.


+

Df Ls

+

Cs

+

Dr

L

Vi

Ds

Vo

T Vi Ds Cs

Ls

Dr

0

0

(a)

(b)

+

+

Dr

+

Df

0

Dr

(c)

(d)

+

+

Df

Cs Vi

L

Cs Ls

Ds

Vi

+

Ds

Vo

Df

T

Dr

T

0

0

(e)

(f)

+

Df

Dr

Df

buck/forward

Ls

(h)

T

Vo

L T

+

Vi

+ Vo

Df

Vi

Dr

T

0

0

(i)

(j)

T

buck-boost

Vi

Ls

Ds

Ls

Cs

Vi

Vo

+

+

L Ds

+

Df

(g)

+

Ls

Ds

L

Cs Dr 0

L+

Cs

Ls

Ds

0

Vo

Cs Ds

Vi

Ls

Cs

L

Dr

T

L Vi

Ds

+

T

Vo

Vo

Ls

Dr

Df

0

boost

Vo

Cs L

T

T

Ds

Ls

Vo

Df

Vi

+

+

L

Vi

+ L

+

T

Cs Ls

Vo

Ds

+

Df

Dr

254

L

Cs

Df

Dr

0

0

(k)

(l)

+ Vo

Figure 9.30. Passive energy recovery of freewheel diode recovery energy: (a)-(d) a boost converter; (e)-(h) a buck/forward converter; and (i)-(l) a buck-boost converter.

Power Electronics

255

+

Df Ls

+

Cs

+

Df

Ds

Vi

Cs

Ls

Vo

Dr

T

T

ℓ

0

(a)

(b)

+

+ Df

Ds

Vo

Vo

L T

ℓ

Ls

(c)

(d)

(f)

+

buck/forward

Df

Ds

+

T

+ Vi

Vo

Df

T

Vi

Ls

Cs

L

Ds

0

(g)

(h)

T

Vo

Ls

Vi

+ Vo

Ds

ℓ

Df

Dr T

ℓ

Ls

Vi

Dr

0

(i)

(j)

0

buck-boost

Vi

Ls

Cs

L

Ds

Df

T

0

Vo

+

+

L

Cs

+

Df

0

L+

Cs

Cs L

Ls

ℓ

Ls

Dr

ℓ +

Dr

Vo

Dr

L

Cs

0

Df

+

T

Dr

T

(e)

ℓ

0

Ds

ℓ

0

Ds

Vi

Dr

Dr

Ds

0

L

Cs

Vo

Cs

L

Ds

ℓ Vi

Cs

Vi

+

+

Df

Ds

Ls

Ls

Vo

Cs

Df

boost

+

ℓ

Vi

ℓ

0

Dr T

ℓ

Df

+

+

Dr

Ls

Vi Dr

+

T L

L

Vo

+ L Vi

+

Ds

+ Vo

0

(k)

(l)

Figure 9.31. Passive energy recovery for inductive turn-on snubber: (a)-(d) a boost converter; (e)-(h) a buck/forward converter; and (i)-(l) a buck-boost converter.

Switching Aid Circuits with Energy Recovery Df

256

+

Dr

Df

+

Dr

Cs

Ls

L

Co

+

Df

Dr

Df

Dr

Co ℓ

L +

Do

+ L

Ds

Vi

Do

Vo

Df +

+

Dr

L

Co

Ls

(b)

Vi

Vi

+

+

Dr

ℓ

Vo

ℓ

Do

Vi

T

Df

Turn-off snubber

Dr Co

Df

Do

Ls

Ds

L

Cs

T

Cs

Do

L

Ds

T

C

Ls

+ Vo

Ds

L

Cs

T

Vi

+ Vo

+ Do

L

Vo

L

C Ls

Vi

Ls

+

Df

Dr

Ds T

Cs

T 0

0

Turn-on and off snubber

Dr

ℓ

0

Df

Dr Co

Df

Do

L

L

Vo

Co

+ Vo

Ds

+

T

Dr Do

+ Vi

Ds

L

Cs

T

Df

+ Vo

C

L

Ds

L

Cs

T

0

+ Vi

0

+ Vi Cs

0

Df

Dr Co

L

Do

(e) buck/boost

Df

Dr Co

(d)

Vi

Turn-off snubber

Df

Vi

Ds

Do

+

Do

Vo

Dr

0

(c)

+

ℓ

+

L

Do

Cs

Vo

+

0 +

buck/forward

Cs

Cs

0

T

0

Df

Ds

Vo

Vo

C

0

Dr Co

Do

T

+

Do

L

Ds

Co

Ls

Vi

Ds

Df

L

Vo

0

Cs

Dr Co

+

Do

Turn-on and off snubber

+

Cs

+

Dr

T

(a)

boost

+

Df

Ds

Vi

0

Turn-off snubber

T

Cs

T

0

Vo

Cs

0

Cs

Ds

Vi

T

Vo

Do

Ds

Vi

0

ℓ

Co

Co

+ L

T

+

Cs

Ls

Vo

Ds

Vi +

Do

(f)

+ Vo +

Do

L

C

Vi T

Turn-on and off snubber 0

Vo

+

L

L

Ds

+

Df

Dr

Vi

Ds T

Cs 0

Figure 9.32. Passive energy recovery circuits for the capacitive turn-off snubber and both turn-on and turn-off snubber circuits, for the different types of switched mode converters.

10 Series and Parallel Device Operation, Protection, and Interference This chapter considers various areas of power device application that are often overlooked, or at best, underestimated. Such areas include parallel and series device utilisation, overcurrent and overvoltage protection, radio frequency interference (rfi) noise, filtering, and interactive noise effects. 10.1

Parallel and series connection and operation of power semiconductor devices

The power-handling capabilities of power semiconductor devices are generally limited by device area utilisation, encapsulation, and cooling efficiency. Many high-power applications exist where a single device is inadequate and, in order to increase power capability, devices are paralleled to increase current capability or series-connected to increase voltage ratings. Extensive series connection of devices is utilised in HVDC transmission thyristor and IGBT modules while extensive paralleling of IGBTs is common in inverter applications. Devices are also series connected in multilevel converters. When devices are connected in series for high-voltage operation, both steady-state and transient voltages must be shared equally by each individual series device. If power devices are connected in parallel to obtain higher current capability, the current sharing during both switching and conduction is achieved either by matching appropriate device electrical and thermal characteristics or by using external forced sharing techniques. 10.1.1 Series semiconductor device operation Owing to variations in blocking currents, junction capacitances, delay times, on-state voltage drops, and reverse recovery for individual power devices, external voltage equalisation networks and special gate circuits are required if devices are to be reliably connected and operated in series (or parallel). 10.1.1i - Steady-state voltage sharing Figure 10.1 shows the forward off-state voltage-current characteristics of two power switching devices, such as SCRs or IGBTs. Both series devices conduct the same off-state leakage current but, as shown, each supports a different voltage. The total voltage blocked is V1 + V2 which can be significantly less than the sum of the individual voltage capabilities. Forced voltage sharing can be achieved by connecting a resistor of suitable value in parallel with each series device as shown in figure 10.2. These equal value sharing resistors will consume power and it is therefore desirable to use as large resistance as possible. For worst case analysis consider n cells in series, where all the cells pass the maximum leakage current except cell D1 which has the lowest leakage. Cell D1 will support a larger blocking voltage than the remaining n - 1 which share voltage equally. Let VD be the maximum blocking voltage for any cell which in the worst case analysis is supported by ∨ ∧ D1. If the range of maximum rated leakage or blocking currents is from I b to I b then the maximum ∨ ∧ imbalance occurs when member D1 has a leakage current of I b whilst all the remainder conduct I b .

BWW

Series and Parallel Device Operation and Protection

258

V1 Ileakage V2

Figure 10.1. Collector (transistor) or anode (thyristor) forward blocking I-V characteristics showing voltage sharing imbalance for two devices in series.

∨

Ib VD a ∧

Ib

∧

Ib I2

Figure 10.2. Series IGBT string with resistive shunting for sustaining voltage equalisation in the off-state.

From figure 10.2, Kirchhoff’s current law at node ‘a’, gives ∧

∨

∆I = I b − I b

= I1 − I 2 where I1 > I2. The voltage across cell D1 is VD = I1 R

(A) (A) (V)

(10.1) (10.2) (10.3)

By symmetry and Kirchhoff’s voltage law, the total string voltage to be supported, Vs, is given by Vs = (n - 1) I 2 R + VD (V) (10.4) Eliminating ∆I, I1, and I2 from equations (10.1) to (10.4) yields nVD − Vs l≤ R (10.5) ( ohms ) ∧ ∨ ( n − 1)  I b − I b    for n ≥ 2. Generally only the maximum leakage current at rated voltage and maximum junction temperature is ∨ specified. By assuming I b = 0, a conservative value of the maximum allowable resistance is obtained, namely

Power Electronics

259

l ≤ nVD − Vs = n (1 − k s )VD R ∧ ∧ ( n − 1) I b ( n − 1) I b

( ohms )

(10.6)

The extent to which nVD is greater than Vs, is termed the voltage sharing factor, namely V (10.7) ks = s ≤1 nVD As the number of devices is minimized the sharing factor approaches one, but equation (10.5) shows that undesirably the resistance for sharing decreases, hence losses increase. The power dissipation of the resistor experiencing the highest voltage is given by l =V2 / R l P (W) (10.8) d D If resistors of ± l00a per cent resistance tolerance are used, the worst case occurs when cell D1 has a parallel resistance at the upper tolerance while all the other devices have parallel resistance at the lower limit. After using VD = (1+a)I1R and Vs = (n-1)×(1-a)I2R + VD for equations (10.3) and (10.4), the maximum resistance is given by l ≤ n (1 - a ) VD - (1 + a ) Vs R (ohms) (10.9) ∧ ( n - 1) (1 − a 2 ) I b for n ≥ 2. The maximum loss in a resistor is l =V2 / R l (1 - a ) P (10.10) D D If the dc supply toleration is incorporated, then Vs in equations (10.6) and (10.9) is replaced by (1+b)×Vs where +100b is the supply percentage upper tolerance. This leads to a decreased resistance requirement, hence increased resistor power losses. l ≤ n (1 − a ) VD - (1 + a )(1 + b ) Vs (10.11) R (ohms) ∧ ( n - 1) (1 − a 2 ) I b The effects and importance of just a few per cent resistance or supply voltage tolerance on the maximum value for the sharing resistors and their power losses, are illustrated by example 10.1.

Example 10.1: Series device connection – static voltage balancing Ten, 200 V reverse-blocking, ultra fast 35 ns reverse recovery diodes are to be employed in series in a 1500 V dc peak, string voltage application. If the maximum device reverse leakage current is 10 mA (at maximum junction temperature) calculate the voltage sharing factor, and for worst case conditions, the maximum value of sharing resistance and power dissipation. i. ii.

If 10 per cent tolerance resistors are employed, what is the maximum sharing resistance and its associated power rating? If a further allowance for supply voltage tolerance of ±5% is incorporated, what is the maximum sharing resistance and its associated power rating?

Solution ∧

When n = 10, VD = 200 V dc, Vs = 1500 V dc, and I b = 10 mA, the voltage sharing factor is k s = 1500V/10×200V = 0.75. Equation (10.6) yields the maximum allowable sharing resistance l ≤ nVD − Vs = 10×200V - 1500V = 5.55kΩ R ∧ ( n − 1) I b (10 - 1) ×10mA The nearest (lower) preferred value, 4.7 kilohms, would be used. Maximum resistor power losses occur when the diodes are continuously blocking. The maximum individual supporting voltage appears across the diode which conducts the least leakage current. Under worst case conditions this diode therefore supports voltage VD, hence maximum power loss lD is P l = V2 /R l P D D = 200V 2 /4700Ω = 8.5 W Since the worse device, (in terms of sharing has lowest leakage current), is randomly located in the string, each 4.7kΩ resistor must be capable of dissipating 8.5W. The maximum 1500V dc supply leakage current is 42.5mA (10mA+1500V/10×4.7kΩ) giving 63.8W total losses (1500V×42.5mA), of which 15W (10mA×1500V) is lost in the diodes.


260

i. If 10% resistance tolerance is incorporated, equation (10.9) is employed with a = +0.1, that is l ≤ n (1 - a ) VD - (1 + a ) Vs R ∧ ( n - 1) (1 − a 2 ) I b l ≤ 10 × (10 - 0.1) × 200V - (1 + 0.1) × 1500V R (10 - 1) × (1 - 0.12 ) × 10mA = 2.13 kΩ The nearest (lower) preferred value is 1.8 kilohms, which is much lower resistance (higher losses) than if closely matched resistors were to be used. Worst case resistor power dissipation is l =V2 / R l (1 - a ) P D

D

= 200V 2 /1800Ω × (1 - 0.1) = 27.7 W The maximum total module losses are 165W (1500V×103mA) arising from 103 mA (10mA + 1500V/1.8kΩ×(1- 0.1)) of leakage current.

ii. If the device with the lowest leakage is associated with the worse case resistance (upper tolerance band limit), and simultaneously the supply is at its upper tolerance limit, then worse case resistance is given by equation (10.11), that is l ≤ n (1 − a ) VD - (1 + a )(1 + b ) Vs R ∧ (n - 1) (1 − a 2 ) I b =

10 × (1 - 0.1) × 200V - (1 + 0.1) × (1 + 0.05 ) × 1500V (10 - 1) × (1 - 0.12 ) × 10mA

= 758Ω

Each resistor (preferred value 680Ω) needs to be rated in excess of 200V 2 /680Ω × (1 - 0.1) = 68.6 W ♣

When resistance tolerances are considered, sharing resistors of lower value must be used and the wider the tolerance, the lower will be the resistance and the higher the power losses. A number of solutions exist for reducing power losses and economic considerations dictate the acceptable trade-off level. Matched semiconductor devices would allow a minimum number of string devices (voltage sharing factor ks → 1) or, for a given string device number, a maximum value of sharing resistance (lowest losses). But matching is complicated by the fact that semiconductor leakage current varies significantly with temperature. Alternatively, by increasing the string device number (decreasing the sharing factor ks) the sharing resistance is increased, thereby decreasing losses. By increasing the string device number from 10 (ks = ¾) to 11 (ks = 0.68) in example 10.1, the sharing resistance requirement increases from 4.7 kilohms to 6.8 kilohms and resistor losses are reduced from a total of 50.8 W to 31 W. Another method of minimising sharing resistance losses is to minimise resistance tolerances. A tolerance reduction from 10 per cent to 5 per cent in example 10.1 increases the sharing resistance requirements from 1.8 kilohms to 3.9 kilohms, while total power losses are reduced from 140 W to 64 W. These worse case losses assume a near 100% off-state duty cycle. 10.1.1ii - Transient voltage sharing During steady-state or at very low frequencies, sharing resistors as shown in figure 10.2 are sufficient to prevent individual device overvoltage. Mismatching of turn-on delay times of thyristors and transistors can be minimised by supplying high enough turn-on drive with very fast rise times. A higher initial di/dt is then allowable. Before a conducting string of diodes or thyristors can reverse-block, reverse recovery charge must flow. Those elements with least recovery charge requirements recover first and support the reverse bias. The un-recovered devices recover slowly, since recovery now occurs as a result of the low leakage current though the recovered devices, and natural recombination. The transient reverse-blocking voltage can be shared more equally by placing capacitance across each string element as shown in figure 10.3. The capacitor action is to provide a transient current path bypassing a recovered device to allow a slower device to recover and to support volts. In the case of thyristors, low value resistance is connected in series with each capacitor to avoid high capacitor discharge through the thyristors at turn-on. Figure 10.4 shows the I-V characteristics of two unmatched thyristors or diodes during reverse recovery.

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ℓ ∆Q

Figure 10.3. A series diode string with shunting capacitance for transient reverse blocking voltage sharing.

Figure 10.4. Reverse recovery current and voltage for two mismatched series connected diodes.

The worst∨ case assumptions for the analysis of figure 10.3 are that element D1 has minimum stored ∧ charged Q while all other devices have the maximum requirement, Q . The charge difference is ∧

∨

∆Q = Q − Q (C) (10.12) The total string dc voltage Vs, comprises the voltage across the fast-recovery device VD plus the sum of each of the voltages across the slow n - 1 devices, Vslow. That is Vs = VD + ( n - 1) Vslow (V) The voltage across each slow device is given by ∧ Vslow = 1n  Vs − ∆ V  (V)   ∧ ∧ where ∆ V = ∆ Q/ C . Eliminating Vslow from equations (10.13) and (10.14) yields ∨ ( n − 1) ∆Q = ( n − 1) ∆Q C≥ (F) nVD − Vs n (1 − k s )VD

(10.13) (10.14)

(10.15)

This equation shows that as the number of devices is minimized, the sharing factor, ks, which is in the denominator of equation (10.15), tends to one and the capacitance requirement undesirably increases. Manufacturers do not specify the minimum reverse recovery charge but specify the maximum reverse recovery charge for a ∨given initial forward current, reverse recovery di/dt, and temperature. For worst case design, assume Q = 0, thus ∧

∨

C≥

( n − 1) Q nVD − Vs

∧

=

( n − 1) Q n (1 − k ) V s

(F)

(10.16)

D

Voltage sharing circuit design is complicated if the effects of reverse steady-state leakage current in ac thyristor blocking are taken into account. Supply and sharing capacitance tolerances significantly affect the minimum capacitance requirement. Worst case assumptions for capacitance tolerances involve the case when the fastest recovering diode is in parallel with capacitance at its lower tolerance limit while all the other sharing capacitances are at their upper tolerance limit. Assuming the minimum reverse recovery charge is zero, then the minimum sharing capacitance requirement is

Series and Parallel Device Operation and Protection ∧

( n − 1) Q C≥ (1 − a )( nV − V ) ∨

D

262

∧

=

s

( n − 1) Q n (1 − a )(1 − k ) V s

(F)

(10.17)

D

where -100a is the capacitor negative percentage tolerance and n ≥ 2. Voltage sharing resistors help minimise capacitor static voltage variation due to capacitance variations. If the supply tolerance is incorporated, then Vs in equations (10.16) and (10.17) are replaced by (1+b)×Vs where +100b is the supply percentage upper tolerance. This leads to an increased capacitance requirement, hence increased energy losses, ½CVD2 . ∧

( n − 1) Q C≥ (1 − a ) ( nV − (1 + b )V ) ∨

D

(10.18)

(F)

s

Example 10.2: Series device connection – dynamic voltage balancing The string of ten, 200 V diodes in worked example 10.1 is to incorporate capacitive reverse recovery transient sharing. Using the data in chapter 5, figure 5.9, specify a suitable sharing capacitance based on zero capacitance and supply tolerances (a = b = 0), ± 10 per cent capacitance tolerances (a = 0.1, b = 0), ± 5 per cent supply tolerance (a = 0, b = 0.05), then both tolerances (a = 0.1, b = 0.05). Estimate in each case the capacitor energy loss at capacitor discharge. Solution Figure 5.9 shows that worst case reverse recovery conditions occur at maximum junction ∧ temperature, di/dt, and IF, and a value of Q = 6µC is appropriate. The minimum possible sharing capacitance occurs when the capacitance and dc rail voltage are tightly specified. From equation (10.16) ∧

( n − 1) Q C≥ ∨

(10-1) ×6µC

=

= 108nF @ 200Vdc nVD − Vs 10×200V - 1500V The sharing capacitance requirement with 10% tolerance capacitors, is given by equation (10.17) ∧

( n − 1) Q C≥ (1 − a )( nV − V ) ∨

D

=

s

(10 - 1) × 6µC (1 - 0.1) × (10×200V-1500V )

= 0.12µF @ 200Vdc

A further increase in capacitance requirements results if the upper tolerance dc rail voltage is used. From equation (10.18) ∧

( n − 1) Q C≥ (1 − a ) ( nV − (1 + b )V ) (10 - 1) × 6µC = (1 - 0.1) × (10×200V - (1+0.05) ×1500V ) ∨

D

s

= 0.14µF @ 200Vdc

In each tolerance case the next larger preferred capacitance value should be used, namely, 120nF, 120nF, and 150nF respectively, all rated at 200V dc. The total series capacitance, using the upper tolerance limit is ∨

CT

(1 + a ) C = n

The stored energy with a 1500V dc rail in the 10 series connect 120nF capacitors, and subsequently loss when the string voltages reduces to zero at diode forward bias, is therefore ∨

2 (1 + a ) C 2 2 WT = ½CT Vl = ½ Vs (1 + b ) n (1 + 0.1) ×120nF 2 =½ ×1500V 2 × (1 + 0.05 ) = 16.4mJ 10 The energy stored in the 10 series connect 150nF capacitors, and subsequently loss when the string voltage reduces to zero at diode forward bias, is (1 + 0.1) ×150nF WT =½ × ×1500V 2 × (1 + 0.05) 2 = 20.5mJ 10 ♣ s

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When capacitive sharing is used with switching devices, at turn-on the transient sharing capacitor discharges into the switching device. The discharge current magnitude is controlled by the turn-on voltage fall characteristics. If a linear voltage fall at turn-on is assumed, then the transient sharing capacitor maximum discharge current idis is a constant current pulse for the fall duration, of magnitude V ∆V idis = C D = C D (A) (10.19) ttv ∆t The discharge current can be of the order of hundreds of amperes, incurring initial di/dt values beyond the capabilities of the switching device. In example 10.2 the discharge current for a switch rather than a diode is approximately 150nF×200V/1µs =30A, assuming a 1µs voltage fall time. This 30A may not be insignificant compared to the switches current rating. But, advantageously, the sharing capacitors do act as turn-off snubbers, reducing switch turn-off stressing. In the case of the thyristor, the addition of low-valued, low inductance, resistance in series with the transient capacitor can control the capacitor discharge current, yet not significantly affect the transient sharing properties. The resultant R-C discharge current can provide thyristor latching current while still offering transient recovery sharing, dv/dt, and voltage spike suppression. Thyristor snubber operation and design are considered in chapter 8.1.2. Figure 10.5 shows the complete steady-state and transient-sharing networks used for diodes, thyristors, and transistors. Transient voltage sharing for transistors involves the use of the conventional R-D-C snubber shown in figure 10.5c and considered in chapter 8. The series inductor used with thyristor and transistor strings provides transient turn-on voltage protection. The inductor supports the main voltage while each individual element switches on. Such an inductive turn-on snubber is mandatory for the GCT and the GTO thyristor. No one device is voltage-stressed as a consequence of having a longer turn-on delay time, although gate overdrive at turn-on minimises delay variations.

ℓ

R

R

R

R

Figure 10.5. Transient and steady-state voltage sharing circuits for series connected: (a) diodes; (b) thyristors; and (c) igbt transistors.

10.1.2 Parallel semiconductor device operation It is common practice to parallel power devices in order to achieve higher current ratings or lower conducting voltages than are attainable with a single device. Although devices in parallel complicate layout and interconnections, better cooling distribution is obtained. Also, built-in redundancy can give improved equipment reliability. A cost saving may arise with extensive parallel connection of smaller, cheaper, high production volume devices. The main design consideration for parallel device operation is that all devices share both the steadystate and transient currents. Any bipolar device carrying a disproportionately high current will heat up and conduct more current, eventually leading to thermal runaway as considered in section 4.1. The problem of current sharing is less severe with diodes because diode characteristics are more uniform (because of their simpler structure and manufacturing) than those of thyristors and transistors. Two basic sharing solutions exist • •

matched devices external forced current sharing.


264

10.1.2i - Matched devices Figure 10.6 shows the static I-V on-state characteristics of two SCR’s. If these two devices are connected in parallel, for the same on-state voltage, the resultant current flow is I1 + I2 where I1 and I2 can be very different in value. The total current rating of the pair is not the sum of the maximum current rating for each but rather a value which can be just larger than the rating of one device alone. The percentage parallel derating pd for n parallel connected devices is defined as  I  (10.20) pd =  1 − T  × 100 = (1- k p ) × 100 per cent  nI m  where IT = total current through the parallel arrangement Im = maximum allowable single device current rating n = number of parallel devices kp = current parallel sharing factor = IT /nIm ≤ 1 Parallel connection of IGBT die within a module is made possible by using die from the same wafer/batch. On-state voltage matching for single large area wafers is expensive and complicated by the high temperature dependence of both static and dynamic electrical device characteristics. Derating does not account for effects such as layout and electrical and thermal impedance imbalance. The amount of derating is traded off against the extra cost involved in selecting devices with closer (matched) static characteristics.

Im = 100A

Figure 10.6. Forward conduction characteristics of two unmatched devices.

10.1.2ii - External forced current sharing Forced current sharing is applicable to both steady-state and transient conditions. For a current derating of less than 5 per cent it is usually cheaper to use forced sharing techniques rather than matched devices. Figure 10.6 shows the maximum variation of I-V characteristics in devices of the same type. When parallel connected the maximum current is restricted to Im+I2, (= 100A+70A = 170A at 1.6V). The maximum current rating for each device is Im, (100A); hence with suitable forced sharing a combination in excess of Im + I2 (170A) should be possible. The resistive network in figure 10.7 is used for forced current sharing and in example 10.3 it is required that Im, 100A, flows through D1 and (1-2×pd)×Im > I2, (90A) flows through D2, for a pd (5%) overall derating. From Kirchhoff’s voltage law in figure 10.7 V1 + V3 = V2 + V4 (10.21) VD1 + I m R = VD2 + ( IT − I m ) R From equation (10.20), rearranged for two devices, n = 2

IT = 2 × (1 − pd ) I m = 2k p I m Substituting for IT in equation (10.21) gives VD − VD1 R= 2 2 pd I m

(ohms)

(10.22)

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Im IT Figure 10.7. Forced current sharing network for parallel connected devices.

For n devices connected in parallel, equation (10.21) becomes (I − I ) VD1 + I m R = VD2 + T m R n −1

(10.23)

which after substituting for IT from equation (10.20), for maximum device voltage variation, gives V − VD ( n − 1) R= D (ohms) (10.24) Im n × pd Although steady-state sharing is effective, sharing resistor losses can be high. The total resistor losses in general terms for n parallel connected devices and a conduction duty cycle δ, are given by 2   n   × pd   Im2 R (W) (10.25) Pt = δ 1 + 1 −     n − 1 Since the devices are random in characteristics, each resistor must have a power rating of I m2 R . ∧

∨

Example 10.3: Resistive parallel current sharing – static current balancing For the two diodes shown in figure 10.6, with I = 100A , what derating results when they are parallel connected, without any external sharing circuits? The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A combination should be possible. Using the network in figure 10.7 for current sharing, it is required that 100A flows through D1 and 90A through D2. Specify the per cent overall derating, the necessary sharing resistors, their worse case losses and diode average, rms, and ac currents at a 50% duty cycle and worse case. Solution The derating for the parallel situation depicted in figure 10.6, without external sharing, is 170A  100A+70A  pd =  1 ×100 = 15 per cent (k p = =0.85)  2×100A  2 × 100A  With forced resistive sharing, the objective derating is reduced from 15% to 190A  100A+90A  pd = 1 (k p = = 0.95)  ×100 = 5 per cent 2×100A 2 × 100A   From figure 10.6 1.6V + 100A×R = 1.7V + 90A×R

that is R = 10 milliohm

Equation (10.22), being based on the same procedure, gives the same result. The cell voltage drop is increased to 1.6V+100A×0.01Ω = 1.7V+90A×0.01Ω = 2.6V . Thus, for an on-state duty cycle δ, the total losses are δ×2.6V×190A = δ×494W.


For δ = ½ I D1 = δ × I D1 = ½ × 100 A = 50 A

δ × I D1 =

I D 1 rm s =

I D 2 = δ × I D 2 = ½ × 90A = 45A

½ × 1 0 0 A = 7 0 .7 A 2

I D 1 ac =

I D2 1 rm s − I D 1 =

266

δ × ID2 =

I D 2 rm s =

7 0 .7 2 − 5 0 2 = 5 0 A

½ × 9 0 A = 6 3 .6 A 2

I D 2 ac =

I D2 2 rm s − I D 2 =

6 3 .6 2 − 4 5 2 = 4 5 A

PR 1 = I D2 1 rm s R 1 = 7 0 .7 2 × 0 .0 1m Ω = 5 0 W

PR 2 = I D2 2 rm s R 2 = 6 3 .6 2 × 0 .0 1m Ω = 4 0 .5 W

PD 1 = I D 1 V D 1 = 5 0 A × 1 .6 V = 8 0 W

PR 2 = I D 2 V D 2 = 4 5 A × 1 .7 V = 7 6 .5 W

Pto ta l = PR + PD = ( 5 0 W + 4 0 .5 W ) + ( 8 0 W + 7 6 .5 W

For worse case losses, δ →1 I D1 = δ × I D1 = 1 × 1 0 0 A = 1 0 0 A

δ × I D1 =

I D 1 rm s = I D 1ac =

I D2 1 r m s − I D 1 =

+ 1 5 6 .5 W = 2 4 7 W

I D2 = δ × I D2 = 1× 90A = 90A

1 × 100A = 100A 2

) = 9 0 .5 W

I D 2 rm s =

1002 − 1002 = 0A

I D 2 ac =

δ × ID2 =

1 × 90A = 90A 2

I D2 2 r m s − I D 2 =

902 − 902 = 0A

PR 1 = I D2 1 r m s R 1 = 1 0 0 2 × 0 .0 1m Ω = 1 0 0 W

PR 2 = I D2 2 r m s R 2 = 9 0 2 × 0 .0 1m Ω = 8 1 W

PD 1 = I

PR 2 = I D 2 V D 2 = 9 0 A × 1 .7 V = 1 5 3 W

D1

V D 1 = 1 0 0 A × 1 .6 V = 1 6 0 W

P to ta l = P R + P D = (1 0 0 W + 8 1 W

) + (1 6 0 W

+ 153W

) = 181W

+ 313W = 494W

The general form in equation (10.25) gives the same total resistor losses for each conduction duty cycle case, namely for δ = ½: 50W+40.5W = 90.5W and for δ → 1: 100W+81W = 181W. ♣ A more efficient method of current sharing is to use coupled reactors as shown in figure 10.8. In these feedback arrangements, in figure 10.8a, if the current in D1 tends to increase above that through D2, the voltage across L1 increases to oppose current flow through D1. Simultaneously a negative voltage is induced across L2 thereby increasing the voltage across D2 thus increasing its current. This technique is most effective in ac circuits where the core is more readily designed to reset, not saturate. IF

X to X

Np Ns

Np Ns

Np Ns X to X

T1

T2

D2

D1

(c)

T3

D3

I n τ2 I F = F + × ∆VF n n − 1 2TLM

I τ2 I F = F + 0.016n 2 × ∆VF n 2TLM for n > 6

Figure 10.8. External forced current sharing networks using cross-coupled reactors: (a) for two devices; and (b) and (c) for many devices.

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Equalising reactor arrangements are possible for any number of devices in parallel, as shown in figures 10.8b and c, but size and cost become limiting constraints. The technique is applicable to steady-state and transient sharing. At high current densities, the forward I-V characteristic of diodes and thyristors (and some IGBTs) has a positive temperature dependence which provides feedback aiding sharing. The mean current in the device with the highest current, therefore lowest voltage, of n parallel connected devices in figure 10.8c (with one coupled circuit in series with each device), is given by I I I n −1 τ 2 n −1 δ2 × ∆VF = F + × ∆VF I F = F + ∆I F = F + (10.26) 2TLM 2 f s LM n n n n n where ∆VF is the maximum on-state voltage drop difference LM is the self-inductance (magnetising inductance) of the coupled inductor Τ is the cycle period, 1/fs and τ is the conduction period (τ < T) (a) current sharing analysis for two devices:– ro = 0 Consider two thyristors (n = 2) connected in parallel as show in figure 10.9. The coupled circuit magnetising current is modelled with the magnetising inductor LM. The transformer turns ratio is 1:1, hence the winding voltages and currents are equal, taking into account the relative winding flux orientation shown by the dots. Commutation inductance overlap is ignored. From Kirchhoff’s voltage law vT 1 + v1 = vT 2 − v1 (10.27) That is v1 = ½ × ( vT 1 - vT 2 ) = ½ × ∆v (10.28)

From Kirchhoff’s current law I M = i1 − i2

(10.29)

dI M dt

(10.30)

From Faraday’s equation v1 = LM

which after integrating both sides gives 1 τ 1 IM = v1 dt = ½ ∆VFτ (10.31) ∫ 0 LM LM As a condition it is assumed that the voltage difference ∆v does not decrease as the operating point moves along the I-V characteristics. That is, both devices are modelled by v = vo + i × ro, where the linear resistance ro, is zero, each have different zero current voltages that is different vo, ∆vo = ∆VF. Actually D1 moves further up the I-V characteristic with time as it conducts more current while D2 moves towards the origin, as shown in figure 10.9b. i

IT

IT

IM = i 1 - i2 i2

+ v1

i2

-

LM

t=0

+ T1 i1

IM

IM

+

+ VT1

VT2

-

-

t

T2 IF

t>0

i2 VF

IT

Im ½IT

IT2

v1

magnetising inductance

IT1

t>0

(a)

∆VF (b)

iF 1/ro ∆vo

vF

Figure 10.9. External forced current sharing network using cross-coupled reactors: (a) circuit (including magnetising inductance LM) for two devices and (b) I-V operating points.

(b) current sharing analysis for two devices:– ro ≠ 0 If static resistance is included into the device model for current sharing analysis, then equation (10.30), assuming both devices have the equal resistance, becomes

∆v o = LM

dI M + 2I M ro dt

(10.32)


268

The solution to this differential equation gives the magnetizing current as 2r −t o  ∆v o  L IM = 1 − e M  2ro  

(10.33)

The maximum magnetizing current increases from zero and reaches a maximum at the end of the current conduction period τ. Re-arranging equation (10.33) gives the magnetizing inductance as 2ro τ LM = (10.34)   ∆v o An   ∆v o − I M 2ro 

(c) current sharing analysis for n devices:– ro = 0 When more than two devices are parallel connected, sharing can be enforced with the multiple transformer technique shown in figure 10.8c, where the n transformer secondary windings are series connected. Each transformer has a turns ratio of η = Np:Ns, and the magnetising inductance is assumed to be on the primary side of each transformer. The semiconductor devices are assumed to have a constant on-state voltage vo. The total current is IT, and zero commutation inductance is assumed. Using Kirchhoff’s voltage law on the primary side: Since the secondary voltages sum to zero v s 1 + v s 2 + v s 3 + ... + v sn = 0 then the transformer primary voltages also sum to zero

v p 1 + v p 2 + v p 3 + ... + v pn =

(10.35)

Ns (v + v s 2 + v s 3 + ... + v sn ) = 0 N p s1

Since the legs are parallel connected VT 1 + v p 1 = VT 2 + v p 2 = ..... = VTn + v pn

(10.36)

∨

(10.37)

For worst case analysis, let one device (n = 1) operate at minimum on-state voltage, V T , while the other n - 1 devices have a maximum on-state voltage VlT , therefore potentially conduct less current than the device operating at minimum voltage. ∨ V + v = Vl + v = ..... = Vl + v (10.38) T

T

p1

p

T

p

These equations yield the following primary voltages ∨ ∨ n −1 l 1 l   v p1 = V T −V T  and v p 2 = v p 3 ... = v pn = − V T −V T  n  n  

(10.39)

Using Kirchhoff’s current law on the primary side: I T = I T 1 + I T 2 + ... + I TN (10.40) But a thyristor current, which is the transformer primary current, can be expressed in terms of the transformer secondary current plus the parallel magnetising current on the primary side. That is N 1 (10.41) I T i = i p i + iM i = s is + iM i = is + iM i

Np

η

where, because the secondary windings are series connected, the secondary current is the same for each transformer. The transformer magnetising current iMi is the same for transformers i = 2 to n, iM. Thus the total current n n 1  IT = ∑ IT i = ∑  i s + i m i  i =1 i =1  η  (10.42) 1 I T = n i s + i m 1 + ( n − 1) i m

η

Using Kirchhoff’s voltage law on the secondary side: Since the transformers are identical, each has the same value of magnetising inductance (selfinductance) LM. Because the secondary windings are series connected the sum of the secondary voltages, hence sum of primary voltages, are zero.

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v p1

v p2

+

+ v p 3 + ...

+v pn

= 0

d iM n d iM1 d iM 2 + LM + ...... + LM =0 dt dt dt di  d i = LM  M 1 + ( n − 1) M  = 0 dt   dt d i + ( n − 1) i M  = 0 = LM dt  M 1 = LM

(10.43)

This component inside the square bracket must be a constant. i M 1 + ( n − 1) i M = c

(10.44)

Substituting the constant c into equation (10.42) gives the secondary current as 1 i s = η (IT − c )

(10.45)

n

In conjunction with Faraday’s Equation, the magnetising current is a linear function of time, starting from zero. Applying these conditions to the worst case device, T1, then as the magnetising current in transformer Tr1 increases and the associated thyristor current IT1 increases, from equation (10.44), the opposing magnetising current in the other transformers reduces the associated device principal current. At the maximum on-time, the current in device T1 should not exceed its permitted rated limit, Im. 1 ∆i M 1 (t ) = × v p 1t (10.46)

LM

From equation (10.39), when t = τ, the maximum magnetising current, in terms of the device voltage extremes, is ∨ 1 n −1 l  ∆i M 1 (t = τ ) = ∆iM 1 = × (10.47) V T −V T  × τ LM n   Re-arranging gives the necessary minimum transformer self-inductance with respect to the primary side.

LM =

1 ∆i

×

M1

∨ n −1 l 1 n −1  × ∆V F × τ V T −V T  × τ = × n  n  ∆i M 1

(10.48)

The maximum magnetising current ∆iM 1 can be expressed in terms of devices current rating Im and device percentage derating, pd, or device utilisation, kp =1 - pd. If the device current rating is Im, then n devices in parallel can theoretically conduct n×Im. When derated by pd to kp, the total current is kp×nIm where each device initially conducts kp×Im. The current in the worst case device increases from kpIm to Im ( ∆iM 1 = (1 − k p ) I m = pd × I m ) in the maximum period the device conducts, τ. I = k I + ∆i M = k I + (1 − k ) I = I (10.49) T

p

m

p

m

p

m

m

I n×Im

theoretical current limit

kpnIm

Derated current

pd×nIm

Device rating

Im

Im

IT1

pd×Im

kp Im Im

kp Im

 nk p − 1    n −1 

Im 

1 − kp

n −1

t o

τ

Figure 10.10. External forced current sharing network using series connected secondary windings.


270

The current in each of the remaining n -1 devices decreases from kp Im by (1-kp) Im /n -1 to ∨ 1 − kp  nk p − 1  = Im  (10.50) I T = kpIm − Im  n −1  n −1  such that the necessary total current is maintained: ∨  nk − 1  IT + ( n − 1) I T = I m + ( n − 1) I m  p  = nk p I m  n −1  These various current components are shown in figure 10.10. By assuming a current quadratic dependence on time, equations similar to equations (10.26) can be obtained. Example 10.4: Transformer current sharing – static and dynamic current balancing

Two thyristors with the same forward conduction characteristics as the diodes in figure 10.6 are parallel connected using the coupled circuit arrangement in figure 10.8a. The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A combination should be possible. Using the network in figure 10.9a for current sharing, it is required that no more than rated current flow through the lower conducting voltage device, D1. Specify the per cent overall derating and the necessary sharing transformer properties assuming a half-wave, 180º conduction, phase-controlled, 50Hz, highly inductive load application. What are the transformer core reset requirements? Estimate inductance requirements if the thyristors have a static on-state resistance of 1mΩ. Solution

As in example 10.3, the derating for the parallel situation depicted in figure 10.6, without external sharing, is 170A   pd =  1 ×100 = 15 per cent (k p = 0.85) 2×100A   With forced transformer sharing, the objective derating is reduced from 15% to 190A   pd =  1  ×100 = 5 per cent (k p = 0.95) 2×100A   When the two thyristors are turned on, the magnetizing current is assumed zero and transformer action will force each device to conduct 95A, giving 190A in total. From figure 10.6, the voltage difference between the thyristors, ∆VF is about 0.1V, thus the transformer winding voltages will be 0.05V each, with polarities as shown in figure 10.9a. In time the magnetizing current increases and the current in T1 increases above 95A due to the increasing magnetizing current, while the current in T2 decreases below 95A, such that the total load current is maintained at 190A. The worse case conduction period in this ac application, giving maximum magnetising current, is for 180º conduction, that is, 10ms. Thus it is required that T1 current rises to 100A and T2 current falls to 90A after τ =10ms, that is, the magnetising current is 100A - 90A = 10A. Substitution into equation (10.31) gives 1 10ms 1 LM = ½ ∆vdt = ½ × × 0.1V×10ms = 50µH ∫ 0 10A IM where it is assuming that the voltage differential ∆VF between the two devices is constant during the conduction period. In fact figure 10.9b shows that the voltage difference decreases, so assuming a constant value gives an under-estimate of requirements. The core volt-µs during conduction is 0.05V×10ms = 500 V-µs. That is, during core reset the reverse voltage time integral must be at least 500 V-µs to ensure the core flux is reset, (magnetising current reduced to zero). Using equation (10.34), with ro = 1mΩ, gives 2ro τ 2 × 1mΩ × 10ms LM = = = 90µH 0.1V     ∆v o An  A n  0.1V − 10A × 2 × 1mΩ     ∆v o − I M 2ro  The inductance, 50µH, given by equation (10.31) when neglecting model resistance, under-estimates requirements. ♣

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10.2

Protection

A fault can be caused by a device failure or noise which causes undesired device turn-on. This will cause semiconductor device and equipment failure unless protective measures are utilised. Protection against fault current effects usually involves fuses which clear in time to protect endangered devices, or voltage transient absorption devices which absorb spike energy and clamp the equipment voltage to a safe level. The crowbar fault protection technique can be employed to divert the fault from sensitive components to the crowbar which is a robust circuit. The crowbar clamps the sensitive circuit to zero volts and initiates an isolation breaker or fuse action. 10.2.1 Overcurrent

It is not economical to design a circuit where fault overloads are catered for by using devices and components which will withstand worst case faults. A fuse link is normally used for circuit fault current protection. A fuse link protecting a semi-conductor is required to carry normal and overload currents but to open the circuit under fault conditions before the semiconductor is damaged. The resultant circuit induced fuse arcing voltage must not cause damage to the circuit. Other fuse links or circuit breakers should be unaffected when the defective cell is disconnected. This non-interaction property is termed discrimination. The fuse element is one or more parallel conductors of pure silver rolled into thin bands, 0.04 to 0.25 mm thick. Each silver band has a number of traverse rows of punched holes (or notches) as shown in figure 10.11. The area between the holes determines the pre-arcing I2t integral of the fuse and, along with thermal aspects, is related to the fuse current rating. The number of rows of holes determines the fuse voltage rating. When fusing occurs the current is shared between the holes (the necks), while the arcing voltage is supported between the series of rows of holes. The arcing characteristics are enhanced by packing the silver element in sand or glassed sand. The sand and silver element are contained in a ceramic body and the end connector plates are copper flashed and tinned. During normal operation, the I2R heat generated by the element is absorbed by the sand and transferred through the fuse body to the surrounding air. When an overload current occurs, the element generates heat at a faster rate than the heat can be transferred to the sand. If the overload persists, the element reaches its melting point, melts and then open circuits. The action of a typical fuse link is shown in figure 10.12. Owing to the prospective fault current Ia the fuse melts at point A, time tm. Depending on the fuse design and the circuit, the current may continue to rise further to point B, termed the peak let-through current Ip. Beyond this point the impedance of the arcing fuse forces the fault current down to zero at the point C. Thus fuse-clearing or total interrupting time tc consists of a melting time tm and an arcing time ta. A series L-R circuit can be used to model the prospective fault. The current characteristic is given by

i sc (ωt ) = I a {sin (ωt − ψ − φ ) − sin (ψ − φ ) e −ωt / tanφ }

(10.51) where ψ is the angle of the short circuit, after the zero voltage cross-over. tan φ = ωL / R . The maximum peak fault current therefore occurs when the short appears at zero voltage cross-over, ψ = 0.

Figure 10.11. The current fuse link: (a) a 50 A 660 V ac fuse link and (b) a silver fuse link element.


272

supply voltage

Figure 10.12. Parameters of a fuse link operating: (a) current waveforms; (b) supply voltage; and (c) fuse arcing voltage.

Differentiation of equation (10.51) gives the current di/dt, and the maximum initial di/dt is l di = I a × sinψ sin φ dt t =o

(10.52)

This equation shows that the maximum initial di/dt occurs for a short circuit occurring at the peak of the ac supply, ψ = ½π , and is independent of the circuit R-L, that is independent of φ. The load fault energy, for a fuse link resistance R, is Wtot =

∫

tc 0

isc2 R dt

(J)

If the load current, shown in figure 10.11a, during fuse action is assumed to be triangular, then the clearing integral of the fuse is Wc = 13 I p2tc R (J) (10.53) If the resistance R is assumed constant (because of its low resistivity temperature co-efficient), the value of I2t ( 13 I p2tc ) is proportional to the energy fed to the protected circuit. The I2t term is called the total let-through energy or the virtual clearing integral of the fuse. The energy which melts the fuse is proportional to 13 I p2tm and is termed the pre-arcing or melting I2t.

10.2.1i - Pre-arcing I2t Before a fuse melts, the fuse is affected only by the current flowing. The pre-arcing or melting I2t characteristics of fuse links are therefore only a function of prospective fault current and are independent of voltage. For melting times longer than 5-10 ms, the time-current characteristics are usually used for design. Typical time-current characteristics for four different current rated fuses are

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shown in figure 10.13. For times less than a millisecond, the melting I2t reduces to a minimum and the pre-arcing I2t characteristics shown in figure 10.14 are most useful. The peak let-through current Ip, is a function of prospective fault current Ia for a given supply voltage. Typical current cut-off characteristics are shown in figure 10.15.

Figure 10.13. Fuse-link time-current characteristics for 4 fuses and symmetrical sinusoidal 50Hz currents.

Figure 10.14. Pre-arcing I2t characteristics of four fuse links.


274

Figure 10.15. Fuse-link cut-off characteristics at 660 V rms.

10.2.1ii - Total I2t let-through For fuse operating times of less than about 10 milliseconds the arcing I2t can be considerably larger than the pre-arcing I2t and it varies considerably with system voltage, fault level, power factor, and the point on the wave when the fault is initiated. The higher the voltage the more onerous is the duty of the fuse link because of the increase in energy absorbed by the fuse link during the arcing process. Under short-circuit conditions this leads to an increase in I2t let-through with voltage. The I2t let-through will decrease with increased supply frequency whereas the cut-off current will increase.

The peak arc voltage after melting is usually specified for a given fuse link type and is a function of supply voltage, as indicated by the typical arcing voltage characteristics in figure 10.16. The faster the fault is cleared, the higher the arc voltage Vp. Typical total I2t let-through values for total operating times of less than 10 ms, at a given voltage, are shown in figure 10.17. Derating factors for temperature, frequency, and power factor are shown in figure 10.18.

Figure 10.16. Typical peak arc voltage for two different fuse-link types.

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Figure 10.17. Total let-through current for total fuse-link operating times of less than 10 ms and at 660 V rms.

10.2.1iii - Fuse link and semiconductor I2t co-ordination Difficulties arise in matching fuses with semiconductors because each has very different thermal and electrical properties. Semiconductor manufacturers publish (mainly for diodes and thyristors) I2t withstand values for their devices for times less than 10 ms. To ensure fuse link protection the total I2t let-through by the fuse link under appropriate circuit conditions should be less than the I2t withstand ability of the semiconductor. Fuse link manufacturers usually give the data shown in figures 10.13 to 10.18. In ac applications the parameters on which the semiconductor withstand capability is normally compared to the fuse link are

• • •

Peak let-through current versus clearing time or clearing I2t Applied voltage Power factor

10.2.1iv – Fuse link derating and losses

The maximum permissible continuous fuse current I is dependant on the ambient temperature Tamb and the air flow velocity, according to (10.54) I ≤ I × (1 − 0.005 × (T − 20°C ) ) × (1 + 0.05v ) × K n

amb

b

where In is the fuse rated current and the air velocity, v, is limited to 5m/s. The fuse load constant Kb is assumed worse case, that is 100% conduction, Kb = 1. In the absence of manufacturer’s curves as in figure 10.18a, being a resistive element, fuse losses are related to the square of the current, that is 2

2

 n% of I rated   I load  Pn % =   × P100% =  I  × P100% I 100% of rated    n  where P100% is the fuse losses at rated current In in a 20°C ambient.

(10.55)


276

Figure 10.18. Fuse derating with: (a) ambient temperature; (b) ac supply voltage; and (c) power factor.

Example 10.5: AC circuit fuse link design

A fast acting fuse is connected in series with a thyristor in a 415 V ac, 50 Hz ac application. The average current in the thyristor is 30 A at a maximum ambient temperature of 45°C. The ratings of the thyristor are IT(AV) = 45 A @ Tc = 85°C ITRMS = 80 A I 2 t = 5 k A2s for 10 ms @ 125°C I 2 t = 20 k A2√s ITSM = 1000 A for 10 ms @ 125°C and VRRM= 0 The fault circuit inductance is 1.32 mH and the resistance is negligible. Using the figures 10.13 to 10.18, select a suitable fuse. Solution

From figure 10.18a, the 35 A rms No. 2 fuse is rated at 30 A rms in a 45°C ambient. From figure 10.16 the peak arc voltage for a type No. 2 fuse will be less than 1200 V, hence the thyristor voltage rating must be greater than 1200 V and possibly 1200V+√2×415V ac, depending on the point-on-wave of the fault and the particular circuit configuration. The short circuit or prospective rms symmetrical fault current is I V 415V I sc = a = s = = 100A 2 X L 2π × 50Hz×1.32mH

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Figure 10.14 gives a fuse peak let through current of 500 A, which is less than the thyristor peak current rating, ITRMS, of 1 kA. Figure 10.17 gives the fuse total I2t of 300 A2s and the total clearing time of tc =3.5 ms. Since the fuse clears in less than 10 ms (½ ac cycle), the thyristor re-applied VRRM will be zero and an ITSM = 1000 A rating is applicable. The total I2t is corrected for voltage (415V ac) and power factor (0 pu) with f = 0.6 and c = 1.2 from figures 10.18b and c. I 2t ' = f × c × I 2t = 0.6 × 1.2 × 300 A 2s = 216 A 2s which is significantly less than the thyristor I2t rating of 5 kA2s. Since tc is less than 10 ms, the I2√t rating of the thyristor is used. I 2t '' = ( I 2 t )

tc

= 20 kA s × 3.5 ms = 1.18 kA 2s which is significantly greater than the I2t (216 A2s) of the fuse. 2

Since the fuse peak let through current (500 A) is less than the thyristor peak surge current rating (1000 A), and the fuse I2t rating (216 A2s) is significantly less than that for the thyristor (1180 A2s), the proposed 35 A fast acting fuse should afford adequate protection for the thyristor. Generally, if the rms current rating of the fuse is less than the average current rating of the thyristor or diode, the fuse will provide adequate protection under fault conditions. ♣

10.2.1v – Fuse link dc operation Fuse link protection in dc circuits presents greater difficulty than for ac circuits. No natural ac period current zeros exist and faults can result in continuous arcing. The breaking capacity of a fuse link in a dc application depends on l • the maximum applied dc voltage, E

• the feed L /R time constant, τ • the prospective short circuit current of the circuit, Ia High-speed semiconductor ac fuses can be used in dc applications, after suitable derated. The longer the fault current L /R time constant, the lower the allowable operating voltage, since the fuse takes longer to melt due to the slower energy delivery rate. Conversely, the higher the prospective short-circuit current Ia, the faster the fuse operates hence it can operate at a higher dc voltage level. Typically, the fuse dc rating is 70% of its ac voltage rating for time constants between 10ms to 20ms, and the dc rating decreases as the time constant increases. No voltage derating is necessary for time constants less than 2½ms. The design monograph in figure 10.19 can be used to select a suitable ac high-speed fuse for dc application. The design requires the fault time constant τ = L R , which will specify the maximum l , whence the maximum dc arcing voltage Vl arc . The fault time constant also allowable dc voltage E ∨ specifies the pre-arcing I 2 t derating factor k, used to specify the minimum prospective fault current I a to ensure enough energy for the fuse to melt, thence clear. ∨

I a = k I 2t This minimum current must be less than the prospective peak dc fault current given by E Ia = R ∨ That is, I a < I a is a fuse link requirement.

(10.56) (10.57)

10.2.1vi – Alternatives to dc fuse operation It may be possible in some applications to use an ac fuse in a dc circuit, before the rectification stage. Generally low voltage fuses are more effective than high voltage fuses. In high voltage transformer applications satisfactory protection may be afforded by transferring the fuse to the low voltage side. The fuse I2t rating is transferred as with impedance transferring, that is, in the turns ratio squared. 2

V  secondary primary =  s  × I 2 tsemiconductor (10.58) I 2 t fuse V   p Alternatively an mcb (miniature circuit breaker) may offer better protection in cases when the ac fault is more of an overload such that the current magnitude is limited. On overload, the mcb takes a longer time to clear than a fuse, thus the mcb is less prone to nuisance tripping. Fuse protection is mainly applicable to more robust devices such as thyristors and diodes. Transistors (MOSFETs more readily than IGBTs) usually fail as a result of overcurrent before any fuse link can clear the fault.


700V ac 3

2

80

1

1

2 3

1300V ac 1

278

ac voltage rating

2

3

fuse cross section 1 – 53mm×53mm 2 – 61mm×61mm 3 – 76mm×76mm

60 τ 40

L/R ms

20 k = 36

100

80

60

40

20

300

400

l E

k

l E I a = R

L

1400

R

1600

600

700

800

maximum dc voltage 700V ac

1200

l E

500

l V arc

1300V ac

2000

L τ = R

V arc = 2250V

Figure 10.19. Design curves for an ac fused used in dc applications.

Example 10.6: DC circuit fuse link design

A traction 600V dc supply has an equivalent source impedance of 20mΩ and 0.4mH, and a nominal dc load current of 600A. i. Validate the suitability of the following ac fuse in being able to safely clear a dc fault current. ii. Estimate the fuse losses at 20°C ambient. iii. What is the maximum nominal current allowable in an air still 80°C ambient? iv. Estimate the fuse losses in the 80°C ambient. FUSE: High speed 900A, 1300V ac, with a pre-acing I2t of 505,00A2s at room temperature, in a case size 3 of cross section 75mm×76mm, giving 125W of losses at 20°C. Figure 10.19 is applicable to this fuse link element. Solution l = 600V dc The maximum applied voltage is E = 20ms The short circuit fault time constant is τ = L = 0.4mH R 20mΩ i. From figure 10.19, a size 3 fuse will offer better voltage and current overheads than a type 2 fuse. The data yields k = 36, an arcing voltage maximum of 1920V dc, and would allow fault time constants of up to 36ms or peak dc supply voltages of up to 700V dc. The prospective short circuit fault current from equation (10.57) is = 30kA . I a = E = 600V 20mΩ R From equation (10.56), the minimum allowable fault current to ensure enough energy to melt and clear the fuse is ∨

I a = k × I 2t = 36 × 505, 00 = 25.6kA ∨ Since I a < I a , that is, 25.6kA < 30kA, the fuse will reliably and predictably melt, thence clear. .

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ii. The 125W fuse loss at rated current of 900A is reduced if the nominal load current is 600A. From equation (10.55): 2

I  Pn % =  load  × P100%  In  2

 600A  =  × 125W = 55½W  900A 

iii. At ambient temperatures above 20°C, the fuse nominal current rating is decreased according to equation (10.54): I ≤ I n × (1 − 0.005 × (Tamb − 20°C ) ) × (1 + 0.05v ) × K b ≤ 900A × (1 − 0.005 × ( 80°C − 20°C ) ) × (1 + 0.05 × 0 ) × 1 ≤ 900A × (1 − 0.005 × 60°C ) = 630A Thus the fuse would be satisfactory at 80°C with the nominal load current of 600A dc.

iv.

The fuse losses at 600A in an 80°C would be approximately 2

 I @80°C  × P100% P =  load  I @80°C    2

 600A  =  × 125W = 113W  630A  ♣

10.2.2 Overvoltage

Voltage transients in electrical circuits result from the sudden release of previously stored energy, such as with insulation breakdown arcing, fuses, contactors, freewheeling diode current snap, switches, and transformer energising and de-energising. These induced transients may be repetitive or random impulses. Repetitive voltage spikes are observable but random transients are elusively, unpredictable in time and location. A spike is usually brief but may result in high instantaneous power dissipation. A voltage spike in excess of a semiconductor rating for just a few microseconds usually results in catastrophic device failure. Extensive noise may be injected into low-level control logic causing spurious faults. Generally, high-frequency noise components can be filtered, but low-frequency noise is difficult to attenuate. Effective transient overvoltage protection requires that the impulse energy be dissipated in the added transient absorption circuit at a voltage low enough to afford circuit survival. 10.2.2i - Transient voltage suppression devices

Two voltage transient suppression techniques can be employed. • Transient voltage attenuation Low pass filters, such as an L-C filter, can be used to attenuate high frequencies and allow the low-frequency power to flow. • Diverter (to limit the residual voltage) Voltage clamps such as crowbars or snubbers are usually slow to respond. The crowbar is considered in section 10.2.3 while the snubber, which is for low-energy applications, is considered in sections 8.2 and 8.3. The voltage-limiting function may be performed by a number of non-linear impedance devices such as reverse selenium rectifiers, avalanche (commonly called Zener) diodes, and varistors made of various materials such as silicon carbide or zinc oxide. The relationship between the current in the non-linear device, I, and the voltage across its terminals, V, is typically described by the power law I = kV α (A) (10.59) k is an element constant dependent on device geometry in the case of the varistor, and the non-linear exponent α is defined as  log I 2 - log I1 log I 2 / I1  1 = α= (10.60) =  log V2 - log V1 log V2 / V1  log V2 / V1 


280

where I1 and I2 are taken a decade apart. The term alpha (α) represents the degree of non-linearity of the conduction. The higher the value of alpha, the better the clamp and therefore alpha may be used as a figure of merit. Linear resistance has an alpha of 1 and a conductance of k = 1/R ( I = 1 R V +1 ). The non-linear voltage-dependent resistance is given by V V R = = = 1k V 1-α (Ω) (10.61) I kV α and the power dissipation is P = VI = V kV α = kV α +1 (W) (10.62) The most useful transient suppressors are the Zener diode and the varistor. They are compact devices which offer nanosecond response time and high energy absorption capability.

1 - The Zener diode is an effective clamp and comes the closest to being a constant voltage clamp, having an alpha of 35. Since the avalanche junction area is small and not highly uniform, substantial heating occurs in a small volume. The energy dissipation of the Zener diode is limited, although transient absorption Zener devices with peak instantaneous powers of 50 kW are available. These peak power levels are obtained by: • Using diffusion technology, which leads to low metallisation contact resistance, narrow base width, and minimises the temperature coefficient. • Achieving void-free soldering and thermal matching of the chip and the large area electrodes of copper or silver. Molybdenum buffer electrodes are used. • Using bulk silicon compatible glass passivation which is alkali metal contamination free, and is cut without glass cracking. Voltage ratings are limited to 280 V but devices can be series connected for higher voltage application. This high-voltage clamping function is unipolar and back-to-back series connected Zener diodes can provide high-voltage bipolar symmetrical or asymmetrical voltage clamping. 2 - The varistor is a ceramic, bipolar, non-linear semiconductor utilising silicon carbide for continuous transient suppression or sintered zinc oxide for intermittent dissipation. Approximately 90 per cent by weight of zinc oxide and suitable additives such as oxides of bismuth, cobalt, and manganese, can give varistors with alphas better than 25. The structure of the plate capacitor like body consists of a matrix of conductive zinc oxide grains separated by grain boundaries, providing pn junction semiconductor-type characteristics. The grain sizes vary from approximately 100 µm for low-voltage varistors down to 20 µm for high voltage components. The junctions block conduction at low voltage and provide non-linear electrical characteristics at high voltage. Effectively pn junctions are distributed throughout the structure volume, giving more uniformly distributed heat dissipation than the plane structure Zener diode. The diameter determines current capability, hence maximum power dissipation, while thickness specifies voltage. The structure gives high terminal capacitance values (which decreases with voltage rating according to V -1) depending on area, thickness, and material processing. The varistor may therefore be limited in high-frequency applications (>1kHz), due to CV 2 f related losses. Functionally the varistor is similar to two identical Zener diodes connected back-to-back, in series. 10.2.2ii - Comparison between Zener diodes and varistors

Figure 10.20a illustrates the I-V characteristics of various voltage clamping devices suitable for 240 V ac application. The resistor with alpha equal to 1 is shown for reference. It is seen that the higher the exponent alpha, the nearer an ideal constant voltage characteristic is attained, and that the Zener diode performs best on these grounds. When considering device energy absorption and peak current and voltage clamping level capabilities, the Zener diode loses significant ground to the varistor. The higher the alpha, the lower will be the standby power dissipated. Figure 10.20b shows the dependence of standby power dissipation variation on withstand voltage for various transient absorbers. A small increase in Zener diode withstand voltage produces a very large increase in standby power dissipation. Various device compromises are borne out by the comparison in table 10.1. The current, power, and energy ratings of varistors typically are rated values up to 85°C, then linearly derated to zero at a case temperature of 125°C. Voltage-limiting diodes are typically linearly derated from rated values at 75°C to zero at 175°C. Reliability depends on the ambient temperature and applied voltage, and lifetime decreases with increased voltage or temperature. In the case of the varistor, an 8 per cent increase in applied voltage halves the mean time between failures, mtbf, for applied voltages less than 0.71 times the nominal voltage. Below 40°C ambient, the mtbf for a varistor is better than 7 x 108 hours (0.7 fit). The voltage temperature coefficient for the varistor is - 0.05 per cent/K while +0.1 per cent/K is typical for the power Zener.

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Figure 10.20. (a) The I-V characteristics of four transient voltage suppressor devices, with resistance characteristics for reference and (b) standby power dissipation characteristics showing the higher the alpha the lower the standby power dissipation.

The following design points will specify whether a Zener diode or varistor clamp is applicable and the characteristics of the required device.

• • • • • •

Determine the necessary steady-state voltage rating. Establish the transient energy to be absorbed by the clamp. Calculate the peak transient current through the clamp. Determine power dissipation requirements. Determine the clamping voltage to which the transient is to be suppressed. Estimate the number of fault cycles during the lifetime.

In order to meet higher power ratings, higher voltage levels or intermediate voltage levels, Zener diodes or varistors can be series-connected. The only requirement is that each series device has the same peak current rating. In the case of the varistor this implies the same disc diameter. Then the I-V characteristics, energy rating, and maximum clamping voltages are all determined by summing the respective characteristics and ratings of the individual devices. Parallel operation is difficult and matched I-V characteristics are necessary. A feature of varistors often overlooked is deterioration. Figure 10.21a shows that at relatively low energy levels an infinite number of transients can be absorbed, while at rated absorbed energy only one fault is allowed. This single fault, lifetime, is defined as that energy level that causes a 10 per cent increase in clamping voltage level, for a specified current density.


282

I

tp Figure 10.21. Pulse lifetime ratings for a Zinc oxide varistor: (a) lifetime for fixed 10/100µs pulses and (b) lifetime number for variable-duration square-wave pulses.

Figure 10.21b shows that high currents can be tolerated for short intervals. The lower the pulse repetition number, the higher the allowable current. The absorbed energy rating is given by (10.63) W = k I Vc t p (J) where k = 1 for a rectangular pulse and k = √2 for impulse waveforms: 10µs/1000µs shown in figure 10.21a and 8µs/20µs. The maximum allowable energy pulse is usually based on a 2ms current pulse of magnitude such that a 10% variation in clamping voltage results. Varistors rated for 1000V ac, 1280V dc at 1mA standby, are capable of clamping once, 2870J associated with an 80kA, 2ms pulse, and have a typical capacitance of 2nF at 25°C and 1kHz. The failure mode of the Zener diode and varistor is a short circuit. Subsequent high current flow may cause an explosion and disintegration of contacts, forming an open circuit. This catastrophic condition can be avoided by fuse protection.

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Example 10.7: Non-linear voltage clamp

Evaluate the current of a 1mA @ 250V Zener diode when used to clamp at 340V dc. At 340V dc, calculate the percentage decrease in voltage-dependent resistance and the per unit increase in power dissipation, assuming α = 30. Solution i.

ii.

From I = kV α, equation (10.59) I2 = I1(V2 /V1)α = 1 mA (340V/250V) 30 = 10.14 A The Zener diode will conduct 10.14A when clamping at 340 V (a 10,140 increase on the standby current of 1mA) From equation (10.61), R=V1-α/ k therefore 1−α

-29

V  R 1− 2 = 1−  2  R1  V1 

 340V  =1-   = 0.99987  250V  The percentage decrease in resistance is 99.987 per cent. The dynamic resistance decreases from (250V / 1 mA) 250 kΩ to (340V / 10.1 A) 33.5Ω. By differentiating eqn (10.59), the incremental resistance (dv/di) reduces by 10,000:1. iii.

P = kV α+1 (equation (10.62)) 31

V  P2  340V  −1 =  2  - 1 =   − 1 = 13793.5 P1  250V   V1  The per unit power increase is 13,800. The power increases from (250V × 1 mA) 0.2 W at 250V standby to (340V ×10.14A) 3447.6 W when clamping at 340V dc. ♣ 31

10.2.3 The Crowbar

A crowbar can be used for overvoltage and/or overcurrent protection in both ac and dc circuits. Figure 10.22 illustrates how an SCR can be used to provide fault protection for sensitive dc power electronic circuits and loads. Whenever a fault condition occurs the crowbar SCR is triggered, shorting the supply. The resultant high supply current flowing blows the fuse, or initiates a fast-acting circuit breaker/mcb, thereby isolating the load from the supply. The diode Dc provides a current path for inductive load energy. The load current is measured by the voltage across the sense resistor R. When this voltage reaches a preset limit, that is the load current has reached the fault level, the SCR is triggered. The load or dc link voltage is measured from the resistor divider R2 - R3. When this voltage exceeds the pre-determined limit the SCR is triggered and the fuse is blown by the crowbar short-circuit current, isolating the sensitive load from the supply. The load voltage is safely clamped to zero by the conducting SCR or diode Dc.

Figure 10.22. An SCR crowbar for overvoltage and over-current protection.


284

A judiciously selected crowbar SCR can conduct many times its average current rating. For the few milliseconds in which the fuse is isolating, the SCR I2t surge current feature can be exploited. The SCR I2t rating must be larger than the fuse total I2t rating. If the SCR crowbar is fuse-link protected then the total I2t of the dc-link fuse link must be less than the pre-arcing I2t of the SCR crowbar fuse link. An ac crowbar can comprise two antiparallel-connected SCR’s across the fuse-protected ac line, or alternatively one SCR in a four-diode full-wave rectifying bridge.

10.3

Interference

Electromagnetic phenomenon, whether intentional or unintentional by-products, tend to result in undesirable consequences in power electronic circuits and equipment, in terms of generated noise and susceptibility. EMC - Electromagnetic Compatibility The ability of a component or its associated system to operate and function correctly in its intended electromagnetic environment. EMI - Electromagnetic Interference Electromagnetic emissions from a component or its associated system that interfere with the normal operation of another component or system, or the emitting component or system itself. 10.3.1 Noise

RFI noise (electromagnetic interference, EMI) and the resultant equipment interaction is an area of power electronic design that is often fraught, under-estimated or overlooked. EMI is due to the effects of undesired energy transfer caused by radiated electromagnetic fields or conducted voltages and currents. The interference is produced by a source emitter and is detected by a susceptible victim via a coupling path. The source itself may be a self-inflicted victim. The effects of this interference can vary from simple intermittent reset conditions to a catastrophic failure. The coupling path may involve one or more of the following four coupling mechanisms. • • • •

Conduction - electric current, I Radiation - electromagnetic field, Zo Capacitive coupling - electric field, E Inductive coupling - magnetic field, H

10.3.1i - Conducted noise is coupled between components through interconnecting wiring such as through power supply (both ac and dc supplies) and ground wiring. This common impedance coupling is caused when currents from two or more circuits flow through the same wiring impedance. Coupling can also result because of common mode and differential (symmetrical) currents, which are illustrated in figure 10.23. Two forms of common mode currents exist. When the conducting currents are equal such that Vcm1 = Vcm2, then the common mode currents are termed asymmetrical, while if Vcm1 ≠ Vcm2, then the currents are termed non-symmetrical. 10.3.1ii - Radiated electromagnetic field coupling can be considered as two cases, namely

• near field, r λ / 2π , where radiation due to electric fields, E, and magnetic fields, H, are considered separate • far field, r λ / 2π , where the coupling is treated as a plane wave.

The boundary between the near and far field is given by r = λ / 2π where λ is the noise wavelength and r is distance from the source. As a reference impedance, the characteristic impedance of free space in the far field Zo, is given by E / H, which is constant, µo / ε o = 120π = 377Ω . In the near field region, the r-3 (as opposed to r-2 and r-1) term dominates field strength. A wire currying current produces E α r-3 and H α r-2, o thus the electric field E dominates and the wave impedance Z > Zo. A wire loop carrying current produces H α r-3 and E α r-2, o thus the magnetic field H dominates and the wave impedance Z < Zo.

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In the near field, interference is dominated by the effective input impedance, Zin, of the susceptible equipment and the source impedance Rs of its input drive. Electric coupling increases with increased input impedance, while magnetic coupling decreases with increased input impedance. That is, electric fields, E, are a problem with high input impedance, because the current results in a high voltage similar to that given by equation (10.64) dv v = ic × Rs // Z in = Cc × Rs // Z in dt while magnetic fields, H, are a problem with low input impedance, because the voltage results in a high current similar to that given by equation (10.65) di M vc dt i= = Rs // Z in Rs // Z in

induced (10.64) induced

(10.65)

In the far field the r-1 term dominates. In the far field region both the E and H fields are in phase and at right angles. Importantly their magnitudes both decrease, inversely proportionally with distance r, so their magnitude ratio remains constant. That is, in the far field the characteristic impedance Z o = E / H = µo / ε o =120π = 377Ω is constant. The far field radiation wave with this constant impedance is termed a plane wave. The electric field component of the plane wave tends to dominate interference problems in the far field region.

I

+

I

differential

source

+

common mode

mode source

victim

I1 victim

Vcm1

parasitic C

Vdm (a)

+

I2

Vcm2

(b)

L

L Lcm

E N

N

(c)

L

L Ldm

N E

Lcm

Ldm

N

Ldm

E (d)

Figure 10.23. Common mode & differential mode mains supply noise filtering: (a) differential mode noise paths; (b) common mode noise paths; (c) simple L-C mains filter; and (d) high specification mains filter.


286

10.3.1iii - Electric field coupling is caused by changing voltage differences, dv/dt, between conductors. This coupling is usually modelled by capacitance. The changing electric field produces a current according to i = Cc dv/dt, where coupling capacitance Cc is dependant on distance of separation, area, and the permittivity of the media. The effect of the produced current is dependant on the source impedance Rs and the effective input impedance, Zin, of the victim equipment as given by equation (10.64). 10.3.1iv - Magnetic field coupling is due to changing currents, di/dt, flowing in conductors. This coupling mechanism is usually modelled by a magnetically coupled circuit, or a transformer, according to v = Mdi/dt, where the resultant current is given by equation (10.65). The mutual inductance M is related to loop area, orientation, separation distance, and screening and its permeability. This induced voltage is independent of any ground connection or electrical connection between the coupled circuits. Magnetic field problems tend to be at low frequencies. Below 100kHz effective screen materials (due to the skin effect) are steel, mu-metal (µr = 20,000), and permalloy, while at higher frequencies the good electrical conduction properties of copper and aluminium are more effective despite there much lower permeabilities. 10.3.2

Mains filters

The conducted ac mains borne noise can be attenuated to safe levels by filtering. The simplest type of filter is an inductor in series with the load in order to reduce any current di/dt changes. It is usual practice to use L-C filtering, which gives second-order attenuation. The typical circuit diagram of an ac mains voltage filter, with common mode noise filtering, is shown in figure 10.23c. The core inductance is only presented to any ampere turn imbalance (common mode current), not the much larger principle throughput (go and return) ac current, hence the core dimensional requirements can be modest. Extra non-coupled inductance is needed for differential mode filtering, as shown in figure 10.23d. Only the higher frequency noise components can be effectively attenuated since the filter must not attenuate the 50/60 Hz ac mains component. 10.3.3 Noise filtering precautions

For power electronics, circuit noise suppression and interaction is ultimately based on a try-it and see approach. Logic and experience do not necessarily prevail. The noise reduction precautions to follow are orientated towards power electronics applications. Good circuit layout and construction (incorporated at the initial design stage) can greatly reduce the radiated noise, both transmitted and received. Obvious starting points are minimising wire loop lengths, using ground planes, capacitor decoupling, twisted wire pairs, and judicious placement of magnetic components. Use opto-couplers, not only to isolate signals but to allow flexible signal grounding that can bypass ground power noise around sensitive circuitry. Sensitive electronic circuitry should be rfi radiation protected by copper (electric and high frequency magnetic) or mild steel (low frequency magnetic) sheeting, depending on the type of radiation and frequency. Shielding, including electrically isolated heatsinks, should be electrically connected to a point that minimises interference. This may involve connection to supply rails (one of positive, zero, negative) or ground. An R-C snubber across a diode decreases dv/dt while a series inductive snubber will limit di/dt. Mains ac supply series input inductors for bridge rectifiers (plus diode R-C snubbers) decrease the amount of diode recovery noise injected back into the mains and into the equipment. Most effective are common mode transformers in all input and output connection cabling. Although differential mode line inductors may be effective in decoupling input power lines, stability issues can arise when used in output cables. Figure 10.24 outlines the frequency bands where the various interference modes can be expected, and the techniques commonly used to suppression that interference. In ac circuit applications, zero-voltage turn-on and zero-current turn-off minimise any rapid changes in current, thus reducing radiation. To minimise freewheel diode recovery noise, slow down switch turn-on. To minimise interactive noise effects, high noise immune circuit designs can be employed which utilise mos technology. The high-voltage input thresholds of cmos logic (4000 series), 74AC (not ACT) logic series, and power MOSFETs and IGBTs (high gate threshold and capacitance), offer circuit noise immunity. Gates with Schmitt trigger (hysteresis) inputs are preferable, for example, 4093, 74A132, etc. Since noise possesses both magnitude and duration, the much slower response times (but with high input thresholds) of 4000 HEF series cmos may result in better noise immunity in applications requiring clock frequencies below a few megahertz. DSP core operating voltages below a few volts necessitate: the use of a multilayer pcbs with ground planes, carefully layout separating analogue and digital circuitry, low inductance ceramic chip decoupling, watchdog circuitry, etc. Do not avoid using analogue circuitry (±12V), if it is applicable.

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287

differential mode

commonmode mode common

coupling coupled

conducted

10

1

10

2

3

10

Interference type

radiated field

Propagation mode

emc field 4

5

10

frequency

X - type capacitance

Y - type capacitance

Fe powder chokes

current balanced chokes

6

10

10

(kHz)

grounding

f

shielding

Cu

Remedial actions

Figure 10.24. Expected interference types, mode of propagation, and remedial techniques depending on the interference frequency.

Reading list

General Electric Company, Transient Voltage Suppression, 400.3, 1982. Grafham, D.R. et al., SCR Manual, General Electric Company, 6th Edition, 1979. Williams, T., EMC for Product Designers, Newnes, 2nd Edition, 1998.

Problems

10.1.

Derive an expression for the worst case maximum allowable voltage-sharing resistance for n series devices each of voltage rating VD and maximum leakage Im across a supply Vs. The resistance tolerance is ± 100a per cent and the supply tolerance is ± 100b per cent. If Vs = 1500 V, VD = 200 V, Im = 10 mA, n = 10 and tolerances are ±10 per cent, calculate resistance and maximum total power losses if i. tolerances are neglected ii. only one tolerance is considered iii. both tolerances are included. [i. R 3 Z2 R Since the load resistance must be low enough to ensure continuous inductor current, then 2ω L > R such that Z 2 = R 2 + ( 2ω L )2 ≈ 2ω L . Equation (11.64) therefore gives the following load identity for continuous inductor current 1 2 1 1 > = that is L > 1 (11.65) 3ω R 3Z 3ω L R 2

The load and supply (peak) ac currents are I o , ac = I s , ac = I o , 2 . The output and supply rms currents are I o , rms = I s , rms =

2

2 I + ½ I o , ac = o

2

2 I + ½ Io, 2

(11.66)

o

and the power delivered to resistance R in the load is PR = I o2, rms R

(11.67)

B – with an output L-C filter and discontinuous inductor current If the inductor current reduces to zero, at angle β, all the load current is provided by the capacitor. Its voltage falls to Vo ( I o , 6 . The load and supply ac currents are I o , ac = I s , ac = I o , 6 . The output and supply rms currents are 2

2

I o , rms = I s , rms = I o + I o2, ac = I o + I o2, 6 and the power delivered to resistance R in the load is PR = I o2, rms R

(11.99) (11.100)

11.2.2ii Three-phase full-wave bridge circuit with highly inductive load – constant load current For a highly inductive load, that is a constant load current: • the mean diode current is I D = 1 n I o = 13 I o (A) • •

and the rms diode current is I D rms = 1 n I o rms ≈ 1 n I o = 1 3 I o

(A)

and the power factor for a constant load current is 3 pf = = 0.955

π

(11.101) (11.102) (11.103)

The rms input line currents are

I L rms =

2 I o rms 3

The diode current form factor is FFID = I D rms / I D = 3

(11.104) (11.105)

The diode current ripple factor is

RFID = FF ID2 − 1 = 2

(11.106)

A phase voltage and current are given by

v a = 2V sin ωt

sin ( n + 1) ωt  (11.108) n = 6, 12, 18, ..  π n −1 n +1   with phases b and c shifted by ⅔π. That is substitute ωt in equations (11.107) and (11.108) with ωt±⅔π.

ia =

2 3



I o sin ωt +

sin ( n − 1) ωt

(11.107)

+

Each load current harmonic n produces harmonics n+1 and n-1 on the input current. The total load instantaneous power is given by cos n ωt   p (ωt ) = 3 × 2V I o ×  ½ − 2 n − 1   The supply apparent power is

S = 3V L I s rms

(11.109)

(11.110)

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers

318

Table 11.3. Three-phase full-wave uncontrolled rectifier circuits Full-wave rectifier circuit load

average output current Io

(A)

(A)

(W)

2

Vo R

I o2, rms R

2

Vo − E R

I o2, rms R + Io E

Vo R

I o2, rms R = I o R

circuit

Vs

Vo

Is

output power

PR+PE

L

Io

(a) R-L

6th harmonic current Io, 6

R

Vo , 6 R + ( 6ω L ) 2

see section 11.2.2i

Io

L R

(b) Vs

Vo , 6

Is

Vo

E+

R-L-E

Io

L

R + ( 6ω L ) 2

Io,dc Io,ac

(c) Vs

Is

Vo , 6

Vo C

R-L-C

R

6ω L

2

Example 11.7: Three-phase full-wave rectifier The full-wave three-phase dc rectifier in figure 11.12a has a three-phase 415V 50Hz source (240V phase), and a 10Ω, 50mH, series load. During the problem solution, verify that the only harmonic that need be considered is the sixth. Determine i. the average output voltage and current ii. the rms load voltage and the ac output voltage iii. the rms load current hence power dissipated and supply power factor iv. the load power percentage error in assuming a constant load current v. the diode average and rms current requirements Solution i. From equation (11.93) the average output voltage and current are Vo = I o R = 1.35VL = 1.35 × 415V = 560.45V Io =

Vo 560.45V = = 56.045A R 10Ω

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319

ii. The rms load voltage is given by equation (11.96) Vrms = 1.352 VL = 1.352 × 415V = 560.94V The ac component across the load is 2 Vac = Vrms − Vo2 = 560.94V 2 − 560.447V 2 = 23.52V iii. The rms load current is calculated from the harmonic currents, which are calculated from the harmonic voltages given by equation (11.95). harmonic n

Vn =

6 VlL π ( n 2 − 1)

Z n = R 2 + ( nω L )

In =

2

Vn Zn

½ I n2

0

(560.45)

10.00

56.04

(3141.01)

6

32.03

94.78

0.34

0.06

7.84

188.76

12 th

Note the 12 harmonic current is not significant

0.04

I + 2 o

∑½I

0.00 2 n

=

3141.07

The rms load current is I rms = I o2 +

∑½I

2 n

= 3141.07 = 56.05A The power absorbed by the 10Ω load resistor is 2 PL = I rms R = 56.05A 2 × 10Ω = 31410.7W The supply power factor is PL PL 31410.7W = = = 0.955 pf = Vrms I rms 3 VL I L 2 × 56.05A 3 × 415V × 3 This power factor of 0.955 is as predicted by equation (11.103), 3 π , for a constant current load. .

iv. The percentage output power error in assuming the load current is constant is given by i I 2R P 56.045A 2 × 10Ω 31410.1W 1 − L = 1 − 2o = 1 − = 1− 0 oo 56.05A 2 × 10Ω 31410.7W PL I rms R v. The diode average and rms currents are given by equations (11.101) and (11.102) I D = 13 I o = 13 × 56.045 = 18.7A I D rms =

1

3 Io

rms

=

1

3 × 56.05

= 23.4A

Example 11.8: Rectifier average load voltage Derive a general expression for the average load voltage of an p-pulse rectifier. Solution Figure 11.13 defines the general output voltage waveform where p is the output pulse number per cycle of the ac supply. From the output voltage waveform π /n 1 Vo = 2 V cos ω t d ω t ∫ − 2π / p π / n =

2V

2π / p

( sin(π / p) − sin(−π / p) ) = Vo =

2V

π/p

sin(π / p)

2V

2π / p

2sin(π / p )

(V)

where for p = 2 for the single-phase (n = 1) full-wave rectifier in figure 11.7. for p = 3 for the three-phase (n = 3) half-wave rectifier in figure 11.10. for p = 6 for the three-phase (n = 3) full-wave rectifier in figure 11.12. ♣


V3

V2

V1

320

vo

− πp

Io

+ πp

0

i1

ωt Io

ωt

I2 I3

Io ωt

2π

p Figure 11.13. A half-wave n-phase uncontrolled rectifier: output voltage and current waveforms.

11.3

DC MMFs in converter transformers

Half-wave rectification – whether controlled, semi-controlled or uncontrolled, is notorious for producing a dc mmf in transformers and triplen harmonics in the ac supply neutral of three-phase circuits. Generally, a transformer based solution can minimise the problem. In order to simplify the underlying concepts, a constant dc load current Io is assumed, that is, the load inductance is assumed infinite. The transformer is assumed linear, no load excitation is ignored, and the ac supply is assumed sinusoidal. Independent of the transformer and its winding connection, the average output voltage from a rectifier, when the rectifier bridge input rms voltage is VB and there are q pulses in the output, is given by ∧

VB Vo = 2π / q

π /q

∫

∧

cos ωt d ωt = V B

−π / q

sin π / q π /q

(11.111)

The rectifier bridge rms voltage output is dominated by the dc component and is given by

Vo rms

q = 2π

+

π q

∫ 2V −

2

B

cos 2 (ωt ) d ωt = V B 1 +

π q

q 2π sin 2π q

(11.112)

The Fourier expression for the output voltage, which is also dominated by the dc component, is ∞

v o (ωt ) = Vo + Vo ∑ k =1

2 ( −1)

k +1

k 2n 2 − 1

cos kn ωt

(11.113)

Table 11.4 summarizes the various rectifier characteristics that are independent of the transformer winding configuration.

Power Electronics

321

Table 11.4: Rectifier characteristics with q phases (see section 11.6) q phases

Parallel connected secondary windings

Series connected secondary windings

Star, thus neutral always exists

Polygon, hence no neutral

v 1 = 2V sin ωt  

v 2 = 2V sin ωt − 

. .

2π  q 

 2π  v q = 2V sin ωt − (q − 1)  q  

Half-wave Vo

q π 2V sin π q

Load harmonics

n=q

Full-wave 2

q π 2V sin π q

n=q n=2q

q even q odd

2V

Vlo

2V cos

∨

Vo

n=q n=2q

2q 2V

2V

VlDR

2V cos

π 2q

q

even

2 2V

q

odd

2 2V cos

π 2q

q

even

q

odd

ID

q diodes

2V

Is = Io

Is Po = VoIo S = qVsIs

pf load =

Po S

2q diodes

ID =

I D rms 1

q

Is = Io

Io q

q even

π q

sin

2 sin

No of diodes

q odd

π 2q

2q diodes

I D rms = 2

q

Io q I s = ½I o I s = ½I o

q even q −1 q 2

2 2

2q

π

π sin q

2 q

π

q even q odd

π

2 2V cos

π q

q 2V π

π sin q

q even

π 2 2

π

q odd

q q2 −1

q odd

11.3.1 Effect of multiple coils on multiple limb transformers The transformer for a single-phase two-pulse half-wave rectifier has three windings, a primary and two secondary windings as shown in figure 11.13. Two possible transformer core and winding configurations are shown, namely shell and core. In each case the winding turns ratios are identical, as is the load voltage and current, but the physical transformer limb arrangements are different. One transformer, figure 11.13a, has three limbs (made up from E and I laminations), while the second, figure 11.13b, is made from a circular core (shown as a square core). The reason for the two possibilities is related to the fact that the circular core can use a single strip of wound cold-rolled grain-orientated silicon steel as lamination material. Such steels offer better magnetic properties than the non-oriented steel that must be used for E core laminations. Single-phase toroidal core transformers are attractive because of the reduced size and weight but manufacturers do not highlight their inherent limitation and susceptibility to dc flux biasing, particularly in half-wave type applications. Although the solution is simple, the advantageous features of the toroidal transformer are lost, as will be shown.


i.

322

The E-I three-limb transformer (shell)

The key feature of the three-limb shell is that the three windings are on the centre limb, as shown in figure 11.13a. The area of each outer limb is half that of the central limb. Assuming a constant load current Io and equal secondary turns, Ns, excitation of only the central limb yields the following mmf equation mmf = i p N p + i s 1N s − i s 2N s (11.114) Thus the primary current ip is

Ns mmf (i − i ) + N p s 2 s1 Np

ip =

(11.115)

From the waveforms in figure 11.13a, since is2 – is1 is alternating, an average primary current of zero in equation (11.115) can only be satisfied by mmf = 0. The various transformer voltages and currents are

I s1 = I s 2 = I s = I p = Io

Io 2

Ns Np

(11.116)

Vs 1 =Vs 2 =Vs =V p

Ns π V = Np 2 2 o

Therefore the transformer input, output and average VA ratings are N  π  S s = V s 1I s 1 + V s 2 I s 2 = 2 s V p I o  = Po = 1.57Po  Np  2 

S p =Vp I p =

Ns V I Np p o

S = ½ (S s + S p ) =

  π Po = 1.11Po  =  2 2 

Np 1+ 2 V I Ns p o 2

The average output voltage, hence output power, are N 2 2 2 2 Ns Vo = Vs = V p = 0.9 s V p

π

(11.117)

π Np

Np

(11.118)

Po = I oVo Thus

1+ 2

π Po = 1.34Po 4 2 Since the transformer primary current is the line current, the supply power factor is 2 Vs I o Po Vo I o 2 2 π pf = = = = = 0.9 S =

S

ii.

Vp I p

Np Ns V I Ns s Np o

π

(11.119)

(11.120)

The two-limb strip core transformer

Figure 11.13b shows the windings equally split on each transformer leg. In practice the windings can all be on one leg and the primary is one coil, but separation as shown allows visual mmf analysis. The load and diode currents and voltages are the same as for the E-I core arrangement, as seen in the waveforms in figure 11.13b. The mmf analysis necessary to assess the primary currents and core flux, is based on analysing each limb. mmf 1 = −i p ½N p + i s 1N s

mmf 2 = +i p ½N p + i s 2N s mmf 1 = mmf 2 = mmf

(11.121)

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323

ip

ip

mmf1

ip Np

mmf2

½Np

½Np

Ns

Ns

Ns Ns

Io

is1

mmf

i s2

Vp Vp

+ipNp

ip

Np

-½ipNp

Vp1

½Np ip

D1

is1 Vs1

+is1Ns +is2Ns

+is1Ns

is2

mmf2

RL

Ns

Vs2

Ns

is1

RL LL Io D2

is2

LL

D1

D2

Io

Σ mmf1

Vo =

Vo

2 2

π

Vs

Σ mmf2

Vs1

Vo

Vo

ωt

ωt

Vs1

Vs1 ωt

VD1 2π

Io ωt

D1 Io D2

Ns ip

π

VD1

D1

is2

ωt VD1

π

is1

+is2Ns

Vo

mmf Vo

Vs1

+½ipNp

ip

mmf1

Vo

Ns

Vs2

Σ mmf Vs1

Ns

Vp2

½Np

Np

D2

ωt

is1

is2

Io

Ns

− mmf

(a)

Ns Np

D2

Np

ωt

Io ωt

−

Io ωt

ωt

D1

D2

ip

VD = 2 × V s

Io D1

Io ωt

VD1

2π

Ns Np

Io

½NsIo

mmf

(b)

Figure 11.13. Single-phase transformer core and winding arrangements: (a) E-I core with zero dc mmf bias and (b) square/circular core with dc mmf bias.

ωt


These equations yield

324

mmf = N s ½ ( i s 1 + i s 2 ) = N s ½I o ip =

Ns (i − i ) N p s1 s 2

(11.122)

These two equations are used every ac half cycle to obtain the plots in figure 11.13b. It will be noticed that the core has a magnetic mmf bias of ½NsIo associated with the half-wave rectification process. The various transformer ratings are

I s1 = I s 2 = I s = V p 1 = V p 2 = ½V p

Io

I p = Io

2

V s 1 = V s 2 = V s = ½V p Vp =

Ns Np Ns N =Vp s ½N p Np

(11.123)

Np π V Ns 2 2 o

Therefore the transformer VA ratings are

S s = V s 1I s 1 +V s 2 I s 2 = 2

Ns V I Np p o

S p = V p 1I p + V p 2 I p = S = ½ (S s + S p ) =

Ns V I Np p o

 π   = 2 Po = 1.57Po   

  π Po = 1.11Po  =  2 2 

(11.124)

Ns 1+ 2 Vp I o 2 Np

The average output voltage, hence output power, are 2 2 2 2 Ns 2 2 Ns Vo = Vs = V ½V p = π π ½N p π Np p

(11.125)

Po = I oVo Thus

S =π

1+ 2

Po = 1.34Po 4 2 and the supply power factor is pf = Po / S = 0.9.

(11.126)

The interpretation for equations (11.124) and (11.126) (and equations (11.117) and (11.119)) is that the transformer has to be oversized by 11% on the primary side and 57% on the secondary. From equation (11.126), in terms of the average VA, the transformer needs to be 34% larger than that implied by the rated dc load power. Further, the secondary is rated higher than the primary because of a dc component in the secondary. This core saturation aspect requires special attention when dimensioning the core size. Additionally, a component of the over rating requirement is due to circulating harmonics that do not contribute to real power output. This component is particularly relevant in three-phase delta primary or secondary connections when cophasal triplens circulate. This discussion on apparent power aspects is relevant to all the transformer connections considered. Generally the higher the phase number the better the transformer core utilisation, but the poor the secondary winding and rectifying diode utilisation since the percentage current conduction decreases with increased pulse number. The fundamental ripple in the output voltage, at twice the supply frequency, is ⅔Vo. The two cores give the same rated transformer apparent power and supply power factor, but importantly, undesirably, the toroidal core suffers an mmf magnetic bias. In each core case each diode conducts for 180º and

I D = ½I o

I D rms =

Io

2

VlD = 2 2

Ns V Np p

With a purely resistive load, a full-wave rectifier with a centre-tapped primary gives I D = ½I o I D rms = ¼π I o S s = 1.75Po S p = 1.23Po S = 1.49Po

(11.127)

(11.128)

Power Electronics

325

11.3.2 Single-phase toroidal core mmf imbalance cancellation – zig-zag winding In figure 11.14, each limb of the core has an extra secondary winding, of the same number of turns, Ns. MMF analysis of each limb in figure 11.14 yields limb1: mmf o = -i p N p - i s 2N s + i s 1N s (11.129) limb 2: mmf o = i p N p + i s 2N s − i s 1N s Adding the two mmf equations gives mmfo = 0 and the resulting alternating primary current is given by

ip =

Ns (i − i ) N p s1 s 2

(11.130)

The transformer apparent and real power are rated by the same equation as for the previous winding arrangements, namely  π π  S = ½ (S p + S s ) = ½  Po + Po  = 1.34Po 2  2 2 (11.131) Ns 2 2 where Po = Vo I o and Vo = Vp

Np π

Since the transformer primary current is the ac line current, the supply power factor is pf = Po / S = 0.9. The general rule to avoid any core dc mmf is, each core leg must be effectively excited by a net alternating current.

ip

ip

mmfo

Vo =

mmfo

Np

Np

Ns

Ns

Ns

Ns

4 2

π

Vs

Vs1

Vo

Vo ωt Vs1

2π

π

ωt VD1

Io

is1

i s2 VD1

VD1

VD = 4 × V s

Vp -ipNp

Vp1

Np

Np

ip

Vp2

+ipNp

is1

Io D1

ip mmf

mmf

Io

is2 -is2Ns

Vs1

Ns

Ns

Vs2

-is1Ns

D2

Ns +is1Ns

Vs1

Ns is1

Σmmfo

D1

ip

RL Vo LL Io

Ns

Vs2

D2

Np

D2

ωt

− Σmmfo

ωt

Io

+is2Ns

is2

ωt

D1

Ns Np

mmf o

Io ωt

Figure 11.14. Single-phase zig-zag transformer core and winding arrangement using square/circular core with zero dc mmf bias.

11.3.3 Single-phase transformer connection, with full-wave rectification The secondary current is ac with a zero average , thus no core mmf bias occurs. The average output voltage and peak diode reverse voltage, in terms of the transformer secondary rms voltage, are


Vo =

2 2

V Dr = 2V s

(11.132)

The rms output voltage is the bridge input rms voltage: Vo rms = V s

(11.133)

π

Vs

326

The various harmonic currents are 2 2 I s1 = I o = 0.9I o

Ish =

π

I s1 h

for h odd

(11.134)

The power factor angle of the fundamental is unity, while the THD is 48.43%. The transformer primary and secondary apparent powers are

Sp = Ss =

π

2 2 The transformer average VAr rating is

π

S =

Po = 1.11Po

(11.135)

Po

(11.136)

2 2 Since the line current is the primary current, the supply power factor is P 2 2 pf = o =

S

(11.137)

π

The fundamental ripple in the output voltage, at twice the supply frequency, is ⅔Vo. With a purely resistive load, a full-wave bridge rectifier gives

Io = I D = ½I o

I D rms = ¼π I o

Vo V I o rms = s R R S s = 1.23Po S p = 1.23Po

S = 1.23Po

(11.138)

11.3.4 Three-phase transformer connections Basic three-phase transformers can have a combination of star (wye) and delta, primary and secondary winding arrangements. i.

Y - y (WYE-wye) is avoided due to imbalance and third harmonic problems, but with an extra delta winding, triplen problems can be minimised. The arrangement is used to interconnect high voltage networks, 240kV/345kV or when two neutrals are needed for grounding.

ii.

Y - δ (WYE-delta) is commonly used for step-down voltage applications.

iii. ∆ – δ (DELTA-delta) is used in 11kV medium voltage applications where neither primary nor neutral connection is needed. iv. ∆ - y (DELTA-wye) is used as a step-up transformer at the point of generation, before transmission. Independent of the three-phase connection of the primary and secondary, for a balance three-phase load, the apparent power, VA, from the supply to the load is

S = 3V line I line = 3V phase I phase Also the sum of the primary and secondary line voltages is zero, that is V AB + VBC + VCA = 0

Vab +V bc + Vca = 0

(11.139)

(11.140)

where upper case subscripts refer to the primary and lower case subscripts refer to the secondary.

Power Electronics

327

Y-y (WYE-wye) connection Electrically, the Y-y transformer connection shown in figure 11.15, can be summarized as follows.

ηY − y =

N p V AN I a I a V BN I b VCN I c = = = = = = = N s V an I A I L1 V bn I B Vcn I C

(11.141)

V AB = V AN + V NB = V AN −VBN = 3VAN e j 30° = 3VAN ∠30° V BC = V BN + VNC = VBN −VCN VCA = VCN + V NA = VCN −V AN

(11.142)

V ab = V an −V bn = 3Van e j 30° = 3V an ∠30° V bc = V bn −Vcn Vca = Vcn −Van I N = I A + I B + IC

In = Ia + Ib + Ic

The output current rating is

(11.143)

S

IY =

3 = S V 3V 3

B

C

IB

N IC

A IN

b IA

c

Ib

n Ic

In

Ia

n

N

Vbn

VBN

VCA

a

-VBN

VCN

VAB

Vca

-Vbn

Vcn

Vab

VAN

VBN

Van

Vbn

VBC

Vbc

IC

Ic

IA

IB

Ia

Ib

(a) (b) Figure 11.15. Three-phase Y-y transformer: (a) winding arrangement and (b) phasor diagrams.


328

Y- δ (WYE-delta) connection The Y- δ transformer connection in figure 11.16 can be summarized as follows.

ηY −δ =

N p V AN I ba V BN I cb VCN I ac = = = = = = N s V ab I A V bc I B Vca IC

V AB = V AN −VBN = V AN −V AN e

− j 120°

= 3V AN e

(11.144)

j 30°

I a = I ba − I ac = I ba − I ba e − j 240° = 3 I ba e − j 30° Ia + Ib + Ic = 0 The output current rating is

I∆ =

B

C

IB

(11.145)

S

N IC

V

3 = S 3V

b

A IN

c

Ib

IA

Ic

Ia Ica

Vbc Ibc

N

Iab

VBN

VCA

a

VCN

VAB

-VBN

Vca

VAN

Vab

Vbc

VBN

Ic VBC Ica

IC

Iab IA

IB Ib

(a)

Ibc

-Ica

Ia

(b)

Figure 11.16. Three-phase Y- δ transformer: (a) winding arrangement and (b) phasor diagrams.

Power Electronics

329

∆-δ (DELTA-delta) connection In figure 11.17, the ∆ - δ transformer connection can be summarized as follows.

η ∆−δ =

N p V AB I a I ba V BC I b I cb VCA I c I cb = = = = = = = = = N s V ab I A I AB V bc I B I BC Vca I C I CA

(11.146)

I A = I AB − I CA = 3 I A B e − j 30° = 3I A B ∠ − 30° I B = I BC − I AB I C = I CA − I BC I A + IB + IC = 0

(11.147)

I a = I ab − I ca = 3 I ab e − j 30° = 3I ab ∠ − 30° I b = I cb − I ba I c = I ac − I cb Ic + Ib + Ic = 0 The output current rating is

S

IY =

B

C

IB

3 = S V 3V 3

(11.148)

b

A

IC

c

Ib

IA

Ic

ICA

VBC

a Ia Ica

Vbc Ibc

IBC

Iab

IAB VCA

Vca

VAB

Vab

VBC

Vbc Ic

IC

Ica

ICA

Iab

IAB

IB

IBC

-ICA

(a)

IA

Ib

Ibc

-Ica

Ia

(b)

Figure 11.17. Three-phase ∆-δ transformer: (a) winding arrangement and (b) phasor diagrams.


330

∆-y (DELTA-wye) connection The ∆-y transformer connection in figure 11.18 can be summarized as follows.

η ∆− y =

* V AB V AB e − j 30° V AN I a = = = * = V ab V ab V an I A 3

(

I a* 3 I AB e − j 30°

)

*

(11.149)

I A = I AB − I CA = I AB − I AB e − j 240° = 3 Ian e − j 30° The output current rating is

S

IY = B

C

IB

3 = S V 3V 3

(11.150)

A

IC

b

IA

c

Ib

n Ic

a In

Ia

ICA

VBC IBC

n IAB

Vbn Vca

Vcn

Vab

VCA

Van

VAB

VBC

Vbn IC

ICA

Ic

IAB Ia

IB

IBC

-ICA

IA

Ib

(a) (b) Figure 11.18. Three-phase ∆-y transformer: (a) winding arrangement and (b) phasor diagrams.

11.3.5 Three-phase transformer, half-wave rectifiers - core mmf imbalance Note that a delta secondary connection cannot be used for half-wave rectification as no physical neutral connection exists. i.

star connected primary Y-y (WYE-wye)

The three-phase half-wave rectifier with a star-star connected transformer in figure 11.19a is prone to magnetic mmf core bias. With a constant load current Io, each diode conducts for 120º. Each leg is analysed on an mmf basis, and the current and mmf waveforms in figure 11.19a are derived as follows.

Power Electronics

331

mmf o = N s i s 1 − N p i p 1 mmf o = N s i s 2 − N p i p 2

(11.151)

mmf o = N s i s 3 − N p i p 3 By symmetry and balance, the mmf in each leg must be equal. If iN is the neutral current then the equation for the currents is i p1 + i p 2 + i p 3 = i N

(11.152)

The same mmf equations are obtained if the load is purely resistive. Any triplens in the primary will add algebraically, while any other harmonics will vectorially cancel to zero. Therefore the neutral may only conduct primary side triplen currents. Any input current harmonics are due to the rectifier and the rectifier harmonics of the order h = cp ± 1 where c = 0,1,2,… and p is the pulse number, 3. No secondary-side third harmonics can exist hence h ≠ 3k for k = 1, 2, 3, . Therefore no primary-side triplen harmonic currents exist to flow in the neutral, that is iN = 0. In a balanced load condition, the neutral connection is redundant. The system equations resolve to N   i p1 = s  2 i s 1 − 1 i s 2 − 1 i s 3  3 3 3 Np  

i p2 = ip3

Ns  1  2 1 − is1 + is 2 − is 3   3 3 3 Np  

N  1  1 2 = s  − is1 − is 2 + is 3  3 3 3 Np  

(11.153)

 is1 + is 2 + is 3  1  = 3 Ns Io 3  

mmf o = N s 

Specifically, the core has an mmf dc bias of NsIo. Waveforms satisfying these equations are show plotted in figure 11.19a. The various transformer currents and voltages are

I s1 = I s 2 = I s 3 = I s = I p1 = I p 2 = I p 3 = I p = V p1 =V p 2 Vs 1 = Vs 2

Io 3 2 Ns Io 3 Np

N p 2π = V p 3 = V p = Vo Ns 3 6 V 2π = V s 3 = V s = Vo = o

3 6 1.17 The fundamental ripple in the output voltage, at three times the supply frequency, is ¼Vo. Therefore the various transformer VA ratings are π 2 S s = V s 1I s 1 +V s 2 I s 2 + V s 3I s 3 = 3V s I s = Po = 1.48Po 3 2 S p = V p 1I p + V p 2 I p + V p 3I p = 3V p I p = Po = 1.21Po 3 3

S = ½ ( S s + S p ) = Po The average output power is

2+π 6 3 3

(11.154)

(11.155)

= 1.34Po

Po = I oVo

(11.156)

Since with a wye connected transformer primary, the transformer primary phase current is the line current, the supply power factor is 3

3

I 2V s P V I 2 o = 0.827 pf = o = o o = π N S 3V p I p 3 Ns I 3 p Vs Ns 2 Np o

(11.157)

Although the neutral connection is redundant for a constant load current, the situation is different if the load current has ripple at the three times the rectified ac frequency, as with a resistive load. Equations in (11.153) remain valid for the untapped neutral case. In such a case, when triplens exist in the load current, how they are reflected into the primary depends on whether or not the neutral is connected:


• •

ii.

332

No neutral connection – a triplen mmf is superimposed on the mmf dc bias of ⅓NsIo. Neutral connected – a dc current (zero sequence) flows in the neutral and the associated zero sequence line currents in the primary, oppose the generation of any triplen mmf onto the dc mmf bias of ⅓NsIo.

delta connected primary ∆-y (DELTA-wye)

The three-phase half-wave rectifier with a delta-star connected transformer in figure 11.15b is prone to magnetic mmf core bias. With a constant load current Io each diode conducts for 120º. Each leg is analysed on an mmf basis, and the current and mmf waveforms in figure 11.19b are derived as follows. mmf o = N s i s 1 − N p i p 1

mmf o = N s i s 2 − N p i p 2

(11.158)

mmf o = N s i s 3 − N p i p 3 i L1 = i p 1 − i p 3

i L 2 = i p 2 − i p1

iL3 = i p 3 − i p 2

The line-side currents have average values of zero and if it is assumed that the core mmf has only a dc component, that is no alternating component, then based on these assumptions  is1 + is 2 + is 3  1  = 3 Ns Io 3  

mmf o = N s 

The primary currents are then N  N i p1 =  i s 1 − 1 I o  s = s 3   Np Np  Ns



i p2 = is 2 − 1 Io  3



 Np

=

(11.159)

2  1 1  3 is1 − 3 is 2 − 3 is 3   

Ns  1  2 1 − i + i − i N p  3 s 1 3 s 2 3 s 3 

(11.160)

N   N  i p3 = is 3 − 1 Io  s = s  − 1 is1 − 1 is 2 + 2 is 3  3 3 3 3 N N   p  p  These line-side equations are the same as for the star connected primary, hence the same real and apparent power equations are also applicable to the delta connected primary transformer, viz. equations (11.155) and (11.156). The line currents are

i L1 =

Ns (i − i ) N p p1 p 3

i L2 =

Ns (i − i ) N p p 2 p1

i L3 =

Ns (i − i ) N p p3 p2

(11.161)

The waveforms for these equations are shown plotted in figure 11.19b, where

Ip =

Ns 3 N I o and I L = s Np 2 Np

3 Io 2

(11.162)

that is I L = 3 I p

The supply power factor is

pf =

S = 1.34Po

(11.163)

Vo I o

(11.164)

3V p I L

== 0.827

Although with a delta connected primary, the ac supply line currents are not the transformer primary currents, the supply power factor is the same as a star primary connection since the proportions of the input harmonics are the same. The rms output voltage is

Vo rms = 2V s Each diode conducts for 120º and

3 2π

π 3  +  4  3

(11.165)

Power Electronics

333

ID =

Io

I D rms =

Io

Vl D = 6

Ns V Np p

(11.166) 3 The primary connection, delta or wye, does not influence any dc mmf generated in the core, although the primary connection does influence if an ac mmf results. 1

3

A

B

C VL2

VL1

A Vp1

B

Np

Np

ip1

ip2

Vp2

Ns

N

iN

ip3

Ns

-ipNp

Vp3

Np

mmfo

mmfo

Vs1

C

mmfo

Vp1

N

IL2

Np

Np

ip1

ip2

IL3 Vp2

Vp3

Np ip3

mmfo

mmfo

n

n

mmfo

+isNs Vs1

Vs3 RL

Vs2 Ns

IL1

Ns

Ns

Vs2 Ns

Vs3 RL

is1

is2

is3

c

LL

D3

Io

Vo a

is1

is2

D1

b

is3

c

LL

D3

Io

D2

Vo

Vo = V

Vs1

Vs2

Vs3

a

Σ mmfo

Vs1

3 3 2π

b

D1

D2

Vs V

Vs1

Vs2

Vs3

Vs1

ωt π

ωt

2π

π

ωt

is1

VD1

Io D1

is2

D2

Io

√6Vs

D1

ωt

D1 Io D2

⅔Io

ip1

ip2 -⅓Io

ip1=is1-is2-is3

⅔Io

Ns Np

Np

ωt

-⅓Io

ωt

Ns Np

ip3

IL1

ωt

ωt

i L1 = i p 1 − i p 3

Io

Ns Np

ωt

Np

ip3

mmf

Ns

ωt

Ns

D3 ωt

ip2 D3 ωt

D3

ωt

Io D3

ωt

Io

is3

D2

is3

ip1

D2

Io

is2

Vs3 -Vs1

ωt

D1

Vs2 -Vs1

is1

2π

ωt

⅓NsIo

(a)

ωt

-Io mmf

Ns Np ⅓NsIo

(b)

Figure 11.19. Three-phase transformer winding arrangement with dc mmf bias: (a) star connected primary and (b) delta connected primary.

ωt


334

11.3.6 Three-phase transformer with hexa-phase rectification, mmf imbalance Figure 11.20 shown a tri-hexaphase half-wave rectifier, which can employ a wye or delta primary configuration, but only a star secondary connection is possible, since a neutral connection is required. The primary configuration can be shown to dictate core mmf bias conditions. i.

Y-y (WYE-wye) connection

The mmf balance for the wye primary connection in figure 11.20a is N s i s 1 − N s i s 4 − N p i p1 = 0

Ns is 3 − Nsis 6 − N pi p2 = 0 Ns is5 − Nsis 2 − N pi p3 = 0

(11.167)

i p1 + i p 2 + i p 3 = 0 The primary currents expressed in terms of the secondary current are

Ns 2 ( i + 1i − 1i − 2i − 1i + 1i ) N p 3 s1 3 s 2 3 s 3 3 s 4 3 s 5 3 s 6 N = s ( − 13 i s 1 + 13 i s 2 + 23 i s 3 + 13 i s 4 − 13 i s 5 − 23 i s 6 ) Np N = s ( − 13 i s 1 − 23 i s 2 − 13 i s 3 + 13 i s 4 − 23 i s 5 − 13 i s 6 ) Np

i p1 = i p2 i p3

(11.168)

1 (i s 1 − i s 2 + i s 3 − i s 4 + i s 5 − i s 6 ) 3 These line side equations are plotted in figure 11.20a. Notice that an alternating mmf exists in the core related to the pulse frequency, n = 2q = 6.

mmf = N s

The transformer primary currents and the line currents are 2 ip = Io 3 2 iL = Io 3 Note that because of the zero sequence current, triplens, in the delta primary that iL = 2 i p not

(11.169)

(11.170)

iL = 3 i p The transformer power ratings are  π  π  1 Ss = 6  Vo   Io  = Po 3  3 2  6   π  2  π Sp = 3 Vo   I o  = Po  3 2  3  3  π π  π S = ½ Po + Po  = 3 + 1 Po = 1.43Po 3  6  3

(

ii.

(11.171)

)

∆-y (DELTA-wye) connection

When the primary is delta connected, as shown in figure 11.20b, the mmf equations are the same as with a wye primary, namely N s i s 1 − N s i s 4 − N p i p1 = 0

Ns is 3 − Nsis 6 − N pi p2 = 0

(11.172)

Ns is5 − Nsis 2 − N pi p3 = 0 but Kirchhoff’s electrical current equation becomes of the following form for each phase: 1 2π mmf = N s ( i s 1 − i s 4 ) d ωt = 0 2π ∫0

(11.173)

Power Electronics

335

Thus since each limb experiences an alternating current, similar to is1-is4 for each limb, with an average value of zero, the line currents can be calculated from

i p1 =

Ns (i − i ) N p s1 s 4

i p2 =

Ns (i − i ) Np s3 s6

ip3 =


(11.174)

The line currents are

i L1 = i p 1 − i p 3 =

Ns (i + i − i − i ) N p s1 s 2 s 4 s 5

i L2 = i p 2 − i p1 =

Ns ( −i s 1 + i s 3 + i s 4 − i s 6 ) Np

i L3 = i p 3 − i p 2 =

Ns ( −i s 2 − i s 3 + i s 5 + i s 6 ) Np

The transformer primary currents and the line currents are 1 ip = Io 3 2 Io 3

iL =

(11.175)

(11.176)

The transformer power ratings (which are relatively poor) are  π I π Ss = 6  Vo  o = Po = 1.81Po 3 3 2  6  π

Sp = 3

3 2  π

S = ½

 3

 Io

Vo 

=

 3

Po +

π

π 6

Po = 1.28Po



6

Po  = ½ 

(11.177)

π 

1  1 +  Po = 1.55Po 3 2

The same primary and secondary apparent powers result for a purely resistive load. The supply power factor is pf = 3/π = 0.955. Independent of the primary connection, the average output voltage is 3 2 Vo = Vs

π

(11.178)

and the rms output voltage is

Vo rms = 2V s

6 2π

π 3  +  4  6

The diode average and rms currents are

ID =

Io 6

I D rms =

Io 6

(11.179)

(11.180)

The maximum diode reverse voltage is

V Dr = 2 2V s

(11.181)

The line currents are added to the waveforms in figure 11.20a and are also shown in figure 11.10b. The core mmf bias is zero, without any ac component associated with the 6-pulse rectification process. Zero sequence, triplen currents, can flow in the delta primary connection. A star connected primary is therefore not advisable. If a single-phase inter-wye transformer is used between the neutrals of the two star rectifier group, the transformer apparent power factors improve significantly, to S s = 1.48Po S p = 1.05Po giving S = 1.26Po (11.182)

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers A A Vp1 N

n RL Vo

B Np

Np

ip1

ip2

Vs4

Vs1

-ip1Np

ip3 mmfo

Np

Np

ip1

ip2

C

VL2

IL3 Vp2

ip3 mmfo

mmfo

mmfo

is6

is2

is4

is6

is2

D4

D6

D2

D4

D6

D2

Ns

Ns

Ns

Ns

Ns

Ns

Ns

Ns

D1

D3

D5

is1

is3

is5

Vs6

Vs3

Ns Ns

D3

D5

Io

is1

is3

is5

Vs1

Vs2

Vs3

Vs2

-is4Ns +is1Ns

Vs5

Vs4

n RL Vo

Vs1

LL

Σ mmf

Vs4

Vs5

Vs6

Vo = V

2

π

Io Vs1

Vs2

Vs3

Vp3

Np

is4

D1

LL

IL2

Vp1

Vp3

Np

mmfo

mmfo

IL1

C Vp2

B

VL1

336

Vs6

Vs3

Vs4

Vs2

Ns Ns

Vs5

Vs5

Vs6

Vs 1 V ωt

ωt π

2π

π

VD1

VD1

2√2Vs

Io

is1

D1

is2

Io

D3

Io

is4

ωt

D1 D2

is3

Io

Io

ωt

D2

D1 D6 D3

D4

D4

 Io

D1

ωt ωt

D1 D6

Io

IoNs/Np

 Io

ωt

ip2

ωt D4

Io

D3 D6

D3

ωt

D6

-Io Io

ip3

ωt

D5 D2

-Io ωt

o

IL1

mmf

(a)

D4

D1

D2

mmf

ωt

D3 D2

D4

ωt

D6

iL1

D5 D4

-Io

Io

Io D6

D3 D2

ωt ip1

D5

ωt

o

Io

is5 is6

2π

Io

-Io o

ωt ωt

(b)

Figure 11.20. Three-phase transformer winding arrangement with hexa-phase rectification: (a) star connected primary with dc mmf bias and (b) delta connected primary. (the transformer secondary and diode currents are the same in each case)

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337

11.3.7 Three-phase transformer mmf imbalance cancellation – zig-zag winding In figures 11.21a and 11.22a, for balanced input currents and equal turns number Ns in the six windings N s ( I aa ' + I nc ' ) = N s ( I an − I cn ) whence

(11.183)

N s ( I an − I cn ) = 3 N s I an ∠ − 30° If the same windings were connected in series in a Y configuration the mmf would be 2NIan. Therefore 1.15 times more turns (2/√3) are needed with the zig-zag arrangement in order to produce the same mmf. Similarly for the output voltage, when compared to the same windings used in series in a Y secondary configuration: V na = V na ' + V a ' a = −V a ' n + V a ' a

(11.184)

= 3V a ' a ∠30° That is, for a given line to neutral voltage, 1.15 times as many turns are needed as when Y connected. c Vc′c=Vb′n a′

Vna′

c′ Vna

n

a Vb′b=Va′n

Va′a=Vc′n

b′ Icn

a′ b

Ian a

c

c′

b′

Ibn

-Vbn

Ian-Icn

b (a)

(b)

Figure 11.21. Three-phase transformer secondary zig-zag winding arrangement: (a) secondary windings and (b) current and voltage phasors for the fork case.

i.

star connected primary Y-z (WYE-zigzag)

In figure 11.22, each limb of the core has an extra secondary winding, of the same number of secondary turns, Ns. MMF analysis of each of the three limbs yields limb1:- mmf o = -i p 1N p + i s 1N s − i s 3N s limb 2:-

mmf o = −i p 2N p + i s 2N s − i s 1N s

limb 3:-

mmf o = −i p 2N p + i s 3N s − i s 2N s

(11.185)

i p1 + i p 2 + i p 3 = 0 Adding the three mmf equations gives mmfo = 0 and the alternating primary (and line) currents are

i p1 =

Ns (i − i ) N p s1 s 3

i p2 =

Ns (i − i ) N p s 2 s1

These equations are plotted in figure 11.22a.

ip3 =


(11.186)

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers A

Vs31 A Vp1

B

Np

Np

ip1

ip2

Vp3

Np ip3

mmfo

mmfo

B

mmfo

Vp1

Vs11

Vs21

IL1

IL2

IL3

Np

Np

ip1

ip2

Vs2

N

C VL2

VL1

C Vp2

338

Vp2

Np ip3

mmfo

mmfo

Vp3

N

mmfo

-Vs3o Vs1o

Ns

Ns

Vs2o

Vs3o

Ns

Vs1o

-ip1Np

n

Vs2o

Ns

Ns

Vs3o

n

-is3Ns Vs1

Vs1 Vs11

Ns

Ns

Vs31

Vs21 Ns

RL

Vs11 Vo

a

is1

is2

D1

V

Ns

Vs1

b D2

Vs2

c

LL

D3

Io

is3

Vs3

a

Vs1

3 3 2π

Ns

Vs21 Ns

Vs31

RL

is1

is2

b

c

LL

D3

Io

D1

Σmmfo

Vo =

Ns

Vo

+is1Ns

Vs 1

V

Vs1

is3

D2

Vs2

Vs3

Vs1 ωt

ωt π

π

2π

ωt

VL-L

VCB

2π

VBA

VAC

VCB

VD1

ωt Vs2 -Vs1

π

2π

Vs3 -Vs1 Io

is1

√6Vs

D1

D1

ωt

D1

Io

is2

Io

is1

Io

is2

D2

Io

is3

Io N

Io

Ns

Io N

ip1 ωt

p

Ns

Io N

ip2

Ns

Io N

iL1

p

ωt

p

Ns

Io N

ip3

p

-2Io N

p

ωt

iL2

mmf o

p

ωt

p

ωt

mmf

Io N

ωt

p

Ns

-2Io N

o

(a)

p

Ns

p

Ns

-Io N

-Io N

Ns

Ns

-Io N

ωt

p

Ns

Ns

-Io N

ωt

D3

ωt

Ns

ωt

D2

is3

D3

ip1

D2

ωt

D2

ωt

D1

p

(b)

Figure 11.22. Three-phase transformer winding zig-zag arrangement with no dc mmf bias: (a) star connected primary and (b) delta connected primary.

ωt

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339

If a 1:1:1 turns ratio is assumed, the power ratings of the transformer (which is independent of the turns ratio) involves the vectorial addition of the winding voltages. G G G v s 1 = v s 11 − v s 2o G G G v s 2 = v s 21 − v s 3o (11.187) G G G v s 3 = v s 31 − v s 1o The various transformer ratings are 2 2π S s = 3I sV s 0 + 3I sV s 1 = 6I sV so = Po 3 3

S p = 3I pV p =

S = ½ ( S s + S p ) = Po

ii.

π 3 3

(

2π 3 3

Po

)

(11.188)

2 + 1 = 1.46Po

delta connected primary ∆-z (DELTA-zigzag)

Carrying out an mmf balancing exercise, assuming no alternating mmf component, and the mean line current is zero, yields

i L1 = i p 1 − i p 3 =

Ns (i + i − 2i s 3 ) N p s1 s 2

i L2 = i p 2 − i p1 =

Ns (i + i − 2i s 1 ) Np s2 s3

i L3 = i p 3 − i p 2 =

Ns (i + i − 2i s 2 ) N p s 3 s1

(11.189)

The primary and secondary currents are the same whether for a delta or star connected primary, therefore S = ½ ( S s + S p ) = 1.46Po (11.190) If a 1:1:1 turns ratio is assumed, the line, primary and load current are related according to 2 2 4 2 IL = I o + I o = 2I o 3 3

Ip =

2 Io 3

(11.191)

I L = 3I p

A zig-zag secondary can be a Y-type fork for a possible neutral connection or alternatively, a ∆-type polygon when the neutral is not required. Each diode conducts for 120º and

ID =

1

3

Io

I D rms =

Io 3

Vl D = 6

Ns V Np p

(11.192)

11.3.8 Three-phase transformer full-wave rectifiers – zero core mmf Full-wave rectification is common in single and three phase applications, since, unlike half-wave rectification, the core mmf bias tends to be zero. In three-phase, it is advisable that either the primary or secondary be a delta connection. Any non-linearity in the core characteristics, namely hysteresis, causes triplen fluxes. If a delta connection is used, triplen currents can circulate in the winding, thereby suppressing the creation of triplen core fluxes. If a Y-y connection is used, a third winding set, delta connected, is usually added to the transformer in high power applications. The extra winding can be used for auxiliary type supply applications, and in the limit only one turn per phase need be employed if the sole function of the tertiary delta winding is to suppress core flux triplens. The primary current harmonic content is the same for a given output winding configuration, independent of whether the primary is star or delta connected.


i.

340

star connected primary Y-y (Wye-wye)

The Y-y connection shown in figure 11.23a (with primary and secondary neutral nodes N, n respectively) is the simplest to analyse since each phase primary current is equal to a corresponding phase secondary current. mmf o = N s i s 1 − N p i p 1

mmf o = N s i s 2 − N p i p 2

(11.193)

mmf o = N s i s 2 − N p i p 2 Adding the three mmf equations gives 3

3

i =1

i =1

3 × mmf o = N p ∑ i pi − N s ∑ i si

(11.194)

i p1 + i p 2 + i p 3 = 0

(11.195)

but

and the secondary currents always sum to zero, then mmfo = 0. Additionally

i L1 = i p 1 =

Ns i N p s1

Ns i Np s2

iL2 = i p 2 =

iL3 = i p 3 =

Ns i Np s3

(11.196)

Generally

Ip =

Ns N Is = s Np Np

2 Io 3

(11.197)

whence

Sp =

2π 3 3

Po = 1.21Po

Ss =

2π Po = 1.48Po 3

 2π 2π  S = ½  Po + Po  = 1.35Po 3 3 3  The secondary harmonic currents are given by 1 1 6 I s h = I s1 = I o for h = 6n ± 1 ∀

h π

h

n >0

(11.198)

(11.199)

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, 1:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.200)

π

π

The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo. Since with a star primary the line currents are the primary currents, the supply power factor is P 3 pf = o = = 0.955 (11.201)

S

ii.

π

delta connected primary ∆-y (Delta-wye)

The secondary phase currents in figure 11.23b are the same as for the Y-y connection, but the line currents are composed as follows i L1 = i p 1 − i p 3 i L 2 = i p 2 − i p1 iL3 = i p 3 − i p 2 (11.202) Such that

Ip =

Ns N Is = s Np Np

N IL = 3 I p = s Np

2 Io 3

N 3 Is = s Np

The secondary harmonic currents are given by 1 1 6 I s h = I s1 = I o for h = 6n ± 1

h

h π

(11.203) 2 Io

∀

n >0

(11.204)

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341

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, √3:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.205)

π

π

The transformer apparent power components are S s = 1.05Po S p = 1.05Po hence

S = 1.05Po

(11.206)

The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo. The supply power factor is

pf =

iii.

3

π

= 0.955

(11.207)

star connected primary Y-δ (Wye-delta)

In the Y-δ configuration in figure 11.24a, there are no zero sequence currents hence no mmf bias arises, mmfo = 0, and both transformer sides have positive and negative sequence currents.

i p1 =

Ns i N p s1

i p2 =

Ns i Np s2

i p3 =

Ns i Np s3

(11.208)

and i s 1 + i s 2 + i s 3 = 0

where

i L1 =

Ns (i − i ) = i p 1 − i p 2 N p s1 s 2

i L2 =

Ns (i − i ) = i p 2 − i p 3 Np s2 s3

iL2 =

Ns (i − i ) = i p 3 − i p1 N p s 3 s1

(11.209)

Thus the transformer currents are related to the supply line currents by

i p1 =

Ns i s 1 = 2 i L1 − 2 i L 2 3 3 Np

i p2 =

Ns i s 2 = 2 iL2 − 2 iL3 3 3 Np

i p3 =

Ns 2 2 i = i − i N p s 3 3 L 3 3 L1

where

(11.210)

i L1 + i L 2 + i L 3 = 0

(11.211)

Ns N 2 2 Is = s ½I o Np Np 3

(11.212)

Generally

Ip =

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, √3:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.213)

π

π

The fundamental ripple in the output voltage, at six times the supply frequency, is 2/5×7 = 0.057Vo. The supply power factor is

pf = for an output power, Po = Vo Io,

3

π

(11.214)


iv.

342

delta connected primary ∆-δ (Delta-delta)

The phase primary and secondary voltages are in phase. As shown in figure 11.24b the line currents are composed as follows i L1 = i p 1 − i p 3 i L 2 = i p 2 − i p1 iL3 = i p 3 − i p 2 The transformer primary and secondary currents are

i p1 =

Ns i N p s1

i p2 =

and

Ns i Np s2

i p3 =

Ns i Np s3

(11.215) (11.216)

i p1 + i p 2 + i p 3 = 0 is1 + is 2 + is 3 = 0 i L1 + i L 2 + i L 3 = 0

Generally

Ip =

(11.217)

Ns I Np s

(11.218)

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, 1:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.219)

π

π

The rms output voltage is 3 9 3 + 2 4π The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo.

Vo rms = 2V s

(11.220)

The primary and secondary apparent powers are

Sp = Ss =

π 3

Po = 1.05Po

(11.221)

Thus the supply power factor is

pf =

3

(11.222)

π

for an output power, Po = Vo Io, In summary, when the primary and secondary winding configurations are the same (∆-δ or Y-y) the input and output line voltages are in phase, otherwise (∆-y or Y-δ) the input and output line voltages are shifted by 30º relative to one another. Independent of the transformer primary and secondary connection, for a specified input and output voltage, the following electrical equations hold.

Vo = ID =

1 Io 3

3 3

π

Vp =

3 Ns

π Np

I D rms =

1 3

VL Io

pf =

3

π

VlDR = 3 2V s

Power Electronics

343

A A Vp1

B Np

Np

ip1

ip2

C Vp2

ip3 mmfo

mmfo

Vp1

-ip1Np

Vp3

Np

N

mmfo

B

VL1 IL1

IL2

Np

Np

ip1

ip2

C

VL2 IL3 Vp2

ip3 mmfo

mmfo

Vp3

Np

mmfo

n

n Vs1

Ns

Vs1

Vs3

Vs2 Ns

Ns

Ns

Ns

is1

is2

Vs3

Vs2 Ns

+is1Ns

a

is1

b

is2

c

is3

D4

D1

D6

D3

D2

Σ mmf

D5 Io

LL

RL

a

V

ac

bc

ba

ca

cb

D1

D6

D3

D2

D5 Io

LL

RL Vo

ab

Vo =

ac

Van

Vbn

Vcn

Van

Vs1

Vs2

Vs3

Vs1

3 3

π

Vs 1

ab

V

ac

bc

ba

ca

cb

ab

ac

Van

Vbn

Vcn

Van

Vs1

Vs2

Vs3

Vs1 ωt

π

ωt π

c

D4

Vo

ab

is3

b

2π

2π

Io

ip1=is1

D1

ωt

D1 D4

D4

-Io VD4

ip2=is2

VD1

√6Vs

Io

Io Io

ip1=is1

D1 D4

Io

D5 ωt

D5 D2

D2

-Io 2Io

Io

D3

Io

iL1

ωt

D3

D6

ωt

D6

-Io ip1=is3

-Io

Io

-2Io

D5 ωt

D5 D2

mmf

-Io

D4

-Io ip2=is2

D6

ip1=is3

ωt

D1

ωt

D3

D6

ωt

o

Io

D3

D2

-Io

Io

iL2

ωt

o

(a)

(b)

mmf

-2Io o

ωt

ωt

Figure 11.23. Three-phase transformer wye connected secondary winding with full-wave rectification and no resultant dc mmf bias: (a) star connected primary Y-y and (b) delta connected primary ∆-y.

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers A A Vp1

B

Np

Np

ip1

ip2

C Vp2

ip3 mmfo

mmfo

a

Ns

Ns

is1

is2

+is1Ns

c

is3

D1

D6

D3

a

Σ mmf

D5 Io

LL

RL

IL1

IL2

Np

Np

ip1

ip2

Ns

Ns

is1

is2

IL3 Vp2

Vp3

Np ip3

mmfo

Vs3

Ns

b

c

is3

D4

D1

D6

D3

D2

LL

RL

Vo

V

C

VL2

mmfo

mmfo

Vs3

Ns

D4

D2

-ip1Np

N

mmfo

b

Vp1

Vp3

Np

B

VL1

344

D5 Io

Vo

Van

Vbn

Vcn

Van

Vs1

Vs2

Vs3

Vs1

Vo =

3 3

π

Vs 1

ωt π

2π

√2Vs

VD1 Io

Io

Io

ip1=is1

D1

ωt

D4

o

D1

ip2=is2

ωt

D1 D4

D6

ip1=is3

ωt

D3

D2

-Io ip1=is3 D2

Io

2Io

D2

-Io

D2

-Io

D5 ωt

D5

Io

D5 ωt

D5

D6

ωt

D3 D6

-Io

Io

D3

Io

D3 D6

D4

-Io

mmf

D4

-Io

Io

ip1=is1

ωt

D1

Io

iL1

ωt

ωt

o

-Io -2Io Io

iL2

(a)

(b)

mmf

-2Io o

ωt

ωt

Figure 11.24. Three-phase transformer with delta connected secondary winding with full-wave rectification and no resultant dc mmf bias: (a) star connected primary Y- δ and (b) delta connected primary ∆- δ.

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345

11.4

Voltage multipliers

Voltage multipliers are ac to dc power conversion circuits, comprised of diodes and capacitors that are interconnected so as to produce a high potential dc voltage from a lower voltage ac source. As in figure 11.25, multipliers are made up of cascaded stages each comprised of a diode and a capacitor. Voltage multipliers are a simple way to generate high voltages at relatively low currents. By using only capacitors and diodes, the voltage multipliers can step up relatively low voltages to extremely high values, while at the same time being far lighter and cheaper than transformers. The advantage of the circuit is that the voltage across each cascaded stage is only equal to twice the peak input voltage, so it requires relatively low cost components and is easy to insulate. One can also tap the output from any stage, like a multi-tapped transformer. The voltage multiplier has poor voltage regulation, that is, the voltage drops rapidly as a function the output current. The output I-V characteristic is approximately hyperbolic, so it is suitable for charging capacitor banks to high voltages at near constant charging power. Furthermore, the ripple on the output, particularly at high loads, is high. The output voltage is not isolated from the input voltage source, although transformer coupling provides general isolation. The most commonly used multiplier circuit is the half-wave series multiplier. Other multiplier circuits can be derived from its operating principles. ID3

ID2

C1

C3 +

+ D2

D4

Vac ID1

0V

D1

+ C2

D3

+ C4

Vout

+ hv dc

ID4

Figure 11.25. Charging sequence of a half-wave series positive output voltage multiplier.

The following description for a two-stage series voltage multiplier assumes no losses and represents sequential reversals of polarity of the source transformer Ts in the figure 11.25. The number of stages is equal to the number of smoothing capacitors between ground and Vout, which in this case is two, capacitors C2 and C4. • Vac = Negative Peak: C1 charges through D1 to Vpk by current ID1 • Vac = Positive Peak: Vpk of Ts adds arithmetically to existing potential C1, thus C2 charges to 2 Vpk thru D2 by current ID2 • Vac = Negative Peak: C3 is charged to 2Vpk through D3 by current ID3 • Vac = Positive Peak: C4 is charged to 2Vpk by current ID4 through D4 then Vpk. For N stages (series capacitors) the output voltage is N×Vpk. 11.4.1 Half-Wave Series Multipliers The capacitors are in series, so effectively capacitance is as for series connected capacitors, C/N, but voltage rating is the cumulative sum of the series capacitors between the output terminals. This multiplier is the most common, and is versatile, being used in high-voltage, low-current applications. The basic charging sequence in figure 11.26 is as for the circuit shown in figure 11.25, where the diodes conduct in the order D1 to D4, for both output polarity versions. Half-wave series voltage multiplier features include: • A wide range of multiplication stages • Low cost • Uniform stress per stage on diodes and capacitors, 2Vpk and Vpk Any one capacitor can be eliminated from the capacitor filter bank if the load is capacitive. Whether full wave or half-wave, the series diodes prevent the output voltage from swinging negative. At high discharges, part of the output current is also drawn via a diode, hampering rapid high current discharge.


346

Dual polarity output voltage is produced by connecting positive and negative multipliers as shown in the four stage circuit is shown in figure 11.26c, where an unlimited stage number can be cascaded. Since regulation is proportional to N³, a large number of stages eventually becomes ineffective. A centre tapped capacitor string connection reduces the maximum voltage potential with respect to ground. An odd number of stages can be produced as well as an even number of stages. The output voltage may be tapped at any point on the capacitor series filter bank.

Vout

Vout +

D4

+ hv dc

-

D4

C4

C4 +

- hv dc

-

D3

C3

D3

C3 +

D2

C2

+ C1

C2

C1

D1

Vac

-

D2

D1

Vac

0V

(a)

0V

(c)

(b)

Vac C1

+

-Vout

C6

+

+

+

+ C2

C5

C3

0V

+

+ C6

C4

+

+Vout

C8

Vac

Figure 11.26. Series half-wave voltage multipliers: (a) two stage positive hv output voltage; (b) two stage negative hv output voltage; and (c) four stage multiplier configured with ± output hv voltage.

Once a load is connected at the output, the output voltage decreases due to the voltage regulation. Also, any small fluctuation of load impedance causes a large fluctuation in the multiplier output voltage due to the number of stages involved. For this reason, voltage multipliers are used only in special applications where the load is constant and has a high impedance or where voltage stability is not critical. Half-wave Output Voltage The open-circuit output voltage Vo/c of each stage is nominally twice the peak input voltage Vpk. Assuming the ac input voltage and frequency are constant, for N cascaded stages, the output voltage is Vo /c = 2N ×V pk (11.223) In practice, several cycles are required to reach full output voltage. The output voltage follows an RC network exponential curve, where R is the output impedance of the ac source, whilst C is the effective dynamic capacitance of the voltage multiplier, N×C. This charging occurs only upon switch-on of the voltage multiplier from a discharged state, and does not repeat itself unless the output is short circuited. The most common input ac waveforms are sine waves and square waves.

Power Electronics

347

Output Voltage Regulation DC output voltage drops as the dc output current increases. Regulation is the drop in dc output voltage from the ideal at a specified dc output current (assuming the ac input voltage and ac input frequency are constant). The voltage drop under load is mostly reactive and is calculated as: 4N 3 + 3N 2 − N 4N 2 + 3N 2 − 1 = Io × V reg = I o × (11.224) 6f × C 6f × C

N

where:

Io is the load or output dc current (A) C is the stage capacitance (F) f is the ac frequency (Hz) N is the number of stages C/N is the effective output capacitance.

Regulation voltage droop is not a power losses in a multiplier. Power losses are primarily diode forward conduction and rarely result in excessive multiplier temperatures at the low current loadings. Substituting Vreg from equation (11.224): 4N 3 + 3N 2 − N Vout = Vo /c −V reg = 2NV pk − I o × (11.225) 6f × C Output Voltage Ripple Ripple voltage is the magnitude of fluctuation in dc output voltage at a specific output current. This assumes the ac input voltage and frequency are maintained constant. The ripple voltage in the case where all stage capacitances, C1 through C2N, are equal, is: N2 +N V ripple = I o × (11.226) 2f × C The ripple grows rapidly as the number of stages increases, with N squared. A common modification to the design is to make the stage capacitances larger at the input, with C1 = C2 = N×C, C3 = C4 = (N-1)×C, and so forth. Then the ripple is:

V ripple =

Io f ×C

(11.227)

For a large number of stages, N ≥ 5, the N3 term in the voltage drop equation dominates. Differentiating the Vout equation without the negligible terms, with respect to the number of stages and equating to zero, gives an equation for the optimum (integer) number of stages Nopt for the equal valued capacitor design: dVout Io d   = × 4N 3  = 0 2NV pk −  dN dN  6f × C  :  V pk f × C ½  (11.228) N opt = int      I o   Increasing the frequency can dramatically reduce the ripple, and the voltage drop under load, which accounts for the popularity driving a multiplier stack with a switching power supply. If the driving voltage Vpk and the required output voltage Vo/c are known, the optimum number of cascaded stages is:  3V  (11.229) N opt = int  out   4V pk  11.4.2 Half-Wave Parallel Multipliers Opposite polarity half-wave parallel voltage multipliers are shown in figure 11.27. The output capacitors share a common connection but must have a high voltage rating. The output is usually low voltage but with high currents. The basic charging sequence in figure 11.27 is the same as shown in figure 11.25, where the diodes conduct in the order D1 to D4, for both output polarity versions. Parallel multipliers offer the following features: • Uniform stress on diodes • compact • Voltage stress on capacitors increases with successive stages by Vpk • Highly efficient


Vout

Vout

+ hv dc

D4

C3

348

- hv dc

D4

C3 +

+

D3

C4

+

C4

D3

+

D2

C1

C1

+

+

D2

+

C2

C2 +

D1

D1

Vac

Vac

0V

0V

(a)

(b)

Figure 11.27. Parallel half-wave voltage multipliers: (a) two stage positive hv output voltage and (b) two stage negative hv output voltage.

11.4.3 Full-Wave Series Multipliers Increasing the frequency can dramatically reduce the ripple, and the voltage drop under load, which can be achieved by driving a multiplier stack with a switched mode power supply. Figure 11.28 shows a typical full-wave two-stage series voltage multiplier. It is comprised of two antiphase ac input half-wave multipliers sharing a common series output capacitor string. This effectively doubles the number of charging cycles per second, and thus reduces the voltage drop and ripple factor. The input is usually fed from a centre-tapped ac transformer or MOSFET H-bridge circuit. Vac

C1

C3

+

+

+ 0V

+

C5

C6 Vout

+ Vac

C2

+

C4

Figure 11.28. Two-stage series full-wave voltage multiplier.

The full-wave series voltage multiplier has the following general features: • Uniform stress on components • Highly efficient • High Voltage • High power capability • Easy to produce • Increased voltage stress on capacitors with successive stages • Wide range of multiplication stages

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349

Full-wave Output Voltage As with the half-wave voltage multiplier, the full wave voltage multiplier output voltage is given by: Vo /c = 2NV pk (11.230) Output Voltage Regulation DC output voltage decreases as dc output current increases. Regulation is the drop in dc output voltage from the ideal at a specified dc output current, assuming constant ac input voltage and frequency. The voltage drop under load is mostly reactive and is: N 3 + 2N N2 + 2 = Io × V reg = I o × (11.231) 6f × C 6f × C

N

where:

Io is the load or output dc current (A) C is the stage capacitance (F) f is the ac frequency (Hz) N is the number of stages C/N is the effective output capacitance.

Regulation voltage droop is not a power losses in a multiplier. Power losses are primarily diode forward conduction and rarely result in excessive multiplier temperatures at the low current loadings. Substituting equation (11.231) for Vreg: N 3 + 2N (11.232) Vout = Vo /c −V reg = 2N ×V pk − I o × 6f × C Output Voltage Ripple The ripple voltage, in the case where all stage capacitances are equal, is given by:

V ripple = I o ×

If the driving voltage Vpk cascaded stages is:

N

(11.233) 2f × C and the required output voltage Vo/c are known, the optimum number of  0.521Vout    V pk 

N opt = int 

(11.234)

Example 11.9: Half-wave voltage multiplier A three-stage half-wave series voltage multiplier, is driven by a 50kHz peak voltage of 10kV, with 1nF capacitances, and a load current of 10mA. i. Calculate the open circuit output voltage, regulated output voltage, ripple voltage, and optimal number of stages for the required voltage transfer function. ii. What is the capacitance and voltage rating of each stage of a parallel connected multiplier? iii. What is the output ripple if progressively smaller capacitance is used?. Solution i.

In a three-stage voltage multiplier, the no load voltage Vo/c = 2×N×Vpk = 2×3×10kV = 60kV 4N 3 + 3N 2 − N 33 + 3 × 32 − 3 = 10mA × = 1.7kV V reg = I o 6f × C 6 × 50kHz × 1nF Vout = 60kV - 1.7kV = 58.3kV So the output voltage will swing between 6kV and 58.3kV, depending on the load current. The output ripple voltage is N2 +N 32 + 3 = 10mA = 3kV V ripple = I o 2f × C 2 × 50kHz × 1nF The optimal number of stages, from equation (11.234), is  0.521 ×Vout   0.521 × 58.3kV  N opt = int   = int  =3 10kV V   pk  

ii.

An equivalent parallel multiplier would require each capacitor stage to equal the total series capacitance of the AC capacitor bank.


350

In this case, the three capacitors in the dc bank would equal 1000pF/3 or 330pF. The parallel equivalent would require 330pF capacitors in each stage. However, each successive stage, from the input, would require a higher voltage capacitor, 20kV, 40kV and 60kV, respectively. iii.

When C1 = C2 = N×C = 3nF, C3 = C4 = (N-1)×C = 2nF, C5 = C6 = (N-2)×C = 1nF. I 10mA V ripple = o = = 200V f × C 50kHz × 1nF This modification reduces the ripple voltage from 3kV to just 200V. ♣

Example 11.10: Full-wave voltage multiplier A three-stage full-wave parallel voltage multiplier, is driven by a 50kHz peak voltage of 10kV, with 1nF capacitances, and a load current of 10mA. Calculate the output voltage and ripple voltage. Solution In a three-stage voltage multiplier, the no load voltage Vo/c = 2×N×Vpk = 2×3×10kV = 60kV. N 3 + 2N 33 + 2 × 3 = 10mA = 1.1kV V reg = I o 6f × C 6 × 50kHz × 1nF Full-wave rectification reduces the regulation voltage drop from 1.7kV in example 11.19, to 1.1kV. The output voltage is increased by 600V, from 58.3kV in example 11.19, to Vout = 60kV - 1.1kV = 58.9kV. The ripple voltage reduces from 3kV for half-wave multiplication in example 11.19, to N 3 V ripple = I o = 10mA = 200V 2f × C 2 × 50kHz × 1nF ♣ 11.4.4 Three-phase voltage multipliers The full-wave multiplier in figure 11.28 is a special case of a poly-phase (0° and 180°) multiplier where more than one multiplier share a common series stack of load capacitors. In figure 11.28, the phase angle between phases is 0°, 120°, and 240°, respectively. The peak voltage supplied by each secondary winding is Vpk. The three-phase circuit in figure 11.28b can be modified by disconnecting the centre point of the Y configuration from ground and omitting the first capacitor in each charging stack, as shown in figure 11.29c. As a result, the open-circuit dc voltage per stage is reduced from 2×Vpk to √3×Vpk. The output impedance, however, decreases dramatically, so the output voltage under load may be even higher, depending on the load current. Therefore, this variant is preferred if the multiplier has to supply higher currents. 11.4.5 Series versus parallel voltage multipliers The theory of operation is the same for both series and parallel connected voltage multipliers. Parallel multipliers require less capacitance per cascaded stage than their series counterparts, however parallel multipliers require higher capacitor voltage ratings on successive cascaded stages. The parallel multiplier output is easier to RC filter in applications requiring low output ripple voltage. 11.5

Marx voltage generator

The Marx generator shown in figure 11.29, charges the energy storage capacitor of each stage in parallel with a relatively low voltage (1kV to 6kV), and then discharges them by means of active switches in series, into the load. The output voltage is then equal to the charging voltage multiplied by the number of stages. The series inductance of this type of generators is low, as a result the rise time and fall time of the output pulses can be less than 1µs. The pulse repetition rate can be more than 20kHz for short pulses, and the pulse length can be several ms.

Power Electronics

351

D1 (a)

C1

D4 C4

+

D5

D2 C2

C5

+

(b)

D6

Vpk

Vpk

+

C2

+

C1

+ D1

Vpk

C6

+

C3

D8

+

D3 C3

D7

+

D2

D3

Vout D9

+

D4

D5

D6 Vout

+

0V

2Vpk

C4

(c) C3 + Vpk

C2 +

C1 + Vpk

D1

Vpk

D2

D3

D4

D5

D6

D7

D8

+ 0V

D9

D11

D10

D12

Vout

+

C4

√3NVpk

C5

Figure 11.29. Three-phase Y configuration voltage multipliers (a) series diode output stage; (b) grounded centre point; and (b) floating centre point.

L

L

+

C

C

Vdc SG

L

+

L

L

SG

L

+

C

C SG

+

L

SG

L

Vout Figure 11.30. The hv Marx generator.

+


11.6

352

Definitions

Vo average output voltage I o average output current Vrms rms output voltage I rms rms output current l Vl peak output voltage I peak output current l V Load voltage form factor = FFv = rms Load voltage crest factor = CFv = V Vo Vrms I Load current form factor = FF i = rms Load current crest factor = CF i = I Irms Io Rectification efficiency = η =

dc load power ac load power + rectifier losses =

Vo I o

V rms I rms + Lossrectifier

Waveform smoothness = Ripple factor = RFv =

where





∞

VRi =  ∑ 12 (v an2 + v bn2 )  n =1

effective values of acV (or I ) VRi = average value of V (or I ) Vo 2 2 V −V = rms 2 o = FFv 2 − 1

Vo

½



similarly the current ripple factor is RF i =

I Ri = FF i 2 − 1 Io

RF i = RFv for a resistive load

11.7

Output pulse number

Output pulse number p is the number of pulses in the output voltage that occur during one ac input cycle, of frequency fs. The pulse number p therefore specifies the output harmonics, which occur at p x fs, and multiples of that frequency, m×p×fs, for m = 1, 2, 3, ... The pulse number p is specified in terms of q the number of elements in the commutation group r the number of parallel connected commutation groups s the number of series connected (phase displaced) commutating groups Parallel connected commutation groups, r, are usually associated with (and identified by) intergroup reactors (to reduce circulating current), with transformers where at least one secondary is effectively star connected while another is delta connected. The rectified output voltages associated with each transformer secondary, are connected in parallel. Series connected commutation groups, s, are usually associated with (and identified by) transformers where at least one secondary is effectively star while another is delta connected, with the rectified output associated with each transformer secondary, connected in series. q =3 r =2 s =2 p=qxrxs p = 12

The mean rectifier output voltage Vo can be specified by

Vo = s

q π

2Vφ × sin

π q

For a full-wave, single-phase rectifier, r = 1, q = 2, and s = 1, whence p = 2 π 2 2Vφ 2 Vo = 1 × 2Vφ × sin = π π 2 For a full-wave, three-phase rectifier, r = 1, q = 3, and s = 2, whence p = 6 π 3 2Vφ 3 Vo = 2 × 2Vφ × sin = π π 3

(11.235)

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353

11.8


Alternating sinusoidal voltages V1 = 2V sin ωt

(

V 2 = 2V sin ωt − .

2π

q

)

(

Vq = 2V sin ωt − (q − 1) 2qπ

)

where q is the number of phases (number of voltage sources) On the secondary or converter side of any transformer, if the load current is assumed constant I o then the power factor is determined by the load voltage harmonics. Voltage form factor

FFv =

V rms Vo

whence the voltage ripple factor is ½ ½ 1 2 RFv = V rms −Vo2  = FFv 2 − 1 V o

The power factor on the secondary side of any transformer is related to the voltage ripple factor by P V I 1 pf = d = o o = S qVI rms RFv 2 + 1 On the primary side of a transformer the power factor is related to the secondary power factor, but since the supply is assumed sinusoidal, the power factor is related to the primary current harmonics. Relationship between current ripple factor and power factor 1 ∞ 2 1 2 RFi = − I 12 ∑ I h = I rms

I1

I1

h =3

I1

pf =

I rms

=

1 1 + RFi 2

The supply power factor is related to the primary power factor and is dependent of the supply connection, star or delta, etc. Half-wave diode rectifiers [see figures 11.2, 11.10] Pulse number p=q. Pulse number is the number of sine crests in the output voltage during one input voltage cycle. There are q phases and q diodes and each diode conducts for 2π/q, with q crest (pulses) in the output voltage Mean voltage

Vo = =

q π

q 2π

∫

½π + π q

2V sin ωt d ωt

½π − π q

2V sin

π q

RMS voltage q V rms =   2π

∫

½π + π q

½π − π q

(

2V sin ωt

 2π  q = 2V ½ + sin q  4π  Normalised peak to peak ripple voltage

v p − p = 2V − 2V cos Vnp − p

v p −p = = Vo

π q

2V − 2V cos

q π

π 2V sin q

π q

)

2

 

½

=

½

d ωt 

π q

1 − cos sin

π q

π q


Voltage form factor

FFv =

V rms Vo

 q 2π  ½ + 4π sin q   =  q π sin

π

½

q

whence the voltage ripple factor is ½ ½ 1 2 −Vo2  = FFv 2 − 1 RFv = V rms V o

Diode reverse voltage

Vl DR = 2 2V

if q is even

π 2q

Vl DR = 2 2V cos

if q is odd

For a constant load current Io, diode currents are

ID = I o

ID =

Io q

Io

I D rms =

q

.

For a constant load current Io the output power is Pd = Vo I o The apparent power is S = qVI rms The power factor on the secondary side of any transformer is P V I 1 pf = d = o o = S qVI rms RFv 2 + 1 =

q π

2V sin

π × Io q 1

qV × I o

=

2q

π

sin

π q

q

The primary side power factor is supply connection and transformer construction dependant. For two-phase half-wave p=q=2

pf 1φ ,½ =

Vo I o 2 2 = = 0.90 V Io π

For three-phase half wave p=q=3

pf 3φ ,½ =

Vo I o 3 3 = = 0.827 3V I o 2π

For six-phase half-wave p=q=6

pf 6φ ,½ =

Vo I o

3V I o

==

3

π

= 0.995

(Y conection)

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is q 2V

K s/c =

ωLc

2 2V

ωLc

Commutation overlap angle 1 − cos µ =

sin

π q

q

=

2 sin

π q

ωLc I o 2V sin

π q

The commutation voltage drop

v com = q ωL I where 2Lc = Ls / c c o 2π

354

Power Electronics

355

p=q=

Isec rms

2

Io /√2

3

Io /√3

6

Io /√6

Vo

VlD

%Vp-p

Ks/c

pfsec

pfprim

0.90V

2√2 V

0.157

1

0.636

0.90

0.68

1.17V

√6 V

0.604

1.73

0.675

0.827

0.31

1.35V

2√2 V

0.140

6

0.55

0.995

RFv

For three-phase resistive load, with transformer turns ratio 1:N ½ 2V 3 3 V Io = I o rms =  13 + 4.3π  R 2π R ½ 2 2 π π FFi output =  27 + 6 .3  .

I p∆ =

N

1

.

×

V 1 + R 3

.3 4π

−

3

2π

2

 

½

I L∆ =

N

V = ×  29 + 1 R

I LY

.3  6π 

N

½

×

1

V 2 + R 3

.3  2π 

½

Time domain half-wave single phase R-L-E load E Z  − ωt −α E 2V  i o (ωt ) = − +  sin (ωt − φ ) +  − sin (ωt − φ )  e tanφ R Z   R 2V  k   ∞ −2 −1 ( ) cos kq ωt  v o (ωt ) = Vo 1 + ∑ 2 2 ( )   k =1 k q − 1  

Full-wave diode bridge rectifiers - star [see figures 11.7, 11.12] q phases and 2q diodes Mean voltage

q ½π + π q 2V sin ωt d ωt π ∫½π − π q π 2q 2V sin = π q

Vo =

Pulse number p=q p=2q

if q is even if q is odd

Diode reverse voltage

VlDR = 2 2V

if q is even

VlDR = 2 2V cos

π 2q

if q is odd

For a constant load current Io, diode currents are

ID = I o

ID =

Io q

I D rms =

Io q

.

The current and power factor are

I rms = I o pf =

=

2

q

Pd V I = o o S qVI rms 2q π 2 V sin × I o π q qV × I o

2

=

2 q

π

q

which is √2 larger than the half-wave case. For single-phase, full-wave p=q=2

pf 1φ =

Vo I o 2 2 = = 0.90 V Io π

sin

π q

   


For three-phase full-wave p=2 q=6 6

2V × ½I o

Vo I o = π 3VI o

pf 3φ =

2 3V × I 3 o

=

3

π

356

= 0.955

p, q

Isec

RFv

Vo

VlD

%Vp-p

Ks/c

pfY prim

pfsec

p=q=2

Io

0.483

1.80V

2√2 V

0.157

2/π

0.90

0.90

p=2 q=6

√⅔ Io

0.31

2.34V

√6 V

0.140

6/π

0.995

0.995

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is

K s/c =

q 2π sin

π q

which is smaller by a factor π than the half-wave case.

K s/c =

q π

for q = 2

Relationship between current ripple factor and supply side power factor on the primary

RFi =

1

∞

∑I

1

=

2

h

2 I rms − I 12

I 1 h =3 I1 I1 1 = pf = I rms 1 + RFi 2

For single phase p=2

RFi =

1

2 I rms − I 12

I1

 1 4

I o2 − 

 2π 1 4

=

2π

1 1 + RFi

2

2



.

.

pf =



Io 

π2 − 8

=

1

= 1+

= 0.483

8

Io

π −8 2

=

2 2 .

π

= 0.90

8

The rms of the fundamental component is 1 4 I1 = Io 2π The rms of the harmonic components are .

Ih =

I1 I1 = for k ≥ 1, 2, 3... h kp ± 1

For p-pulse

π2 p2

RFv =

pf =

sin2 1

1 + RFv

Commutation overlap angle 1 − cos µ =

2

π p =

−1

p π sin p π

ωLc I o 2V sin

π q

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357

The commutation voltage drop

v com = q ωL I where 2Lc = Ls / c π c o For p=q=2, only 1 − cos µ =

2ωLc I o

v com = 4 ωL I π c o

2V

Load characteristics

I o rms Current Form Factor = FF I = = Io

2

Io

q

=

Io

2

q

Full-wave diode bridge rectifiers – delta Same expression as for delta connected secondary, except supply voltages V are replaced by

V 2 sin

π q

For example in three-phase, V is replaced by V/√3, that is, V L −L = The mean output voltage is 2q π 2q 2V ∆ sin = Vo =

π

π

q

2

V π 2 sin q

sin

π q = q π

.

3V L −N =

2V

Pulse number p=q if q is even p=2q if q is odd diode reverse voltage and currents 2V if q is even VlDR = π sin

q 2V if q is odd VlDR = π 2 sin 2q I D = Io I D = Io /q I D rms = I o / q .

rms current and power factor

I rms even = I rms odd

Io

q 2V I o Vo I o 2 2 = = π = π qVI rms qV ½I o .

pf q even

2

2 I q − 1 = o  q 2

½

pf q odd =

.

Vo I o 2 2 q = π q 2 − 1½ qVI rms   .

Commutation angle and voltage 1 − cos µ =

ωLI o

v com = q ωL I c o 2π  1 v com = q ωL I 1 −  c o q  2π

2V .

1 − cos µ =

ωLI o 

1 1 −  q 2V  .

q even q odd

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is q π q −1 π K s/c even = sin K s/c odd = sin

π

q

π

q

.

3V phase


358

For single-phase resistive load, with transformer turns ratio 1:N 2V 4 2V Io = I o rms = .

R

FFi output =

π π

R

RFv = FF 2 − 1 =

2 2

π2 8

.

Ip =

N 1

I sec =

N 1

×

2V

R

pf =

1

RF + 1 2

=

−1

2 2 .

π

Reading list Dewan, S. B. and Straughen, A., Power Semiconductor Circuits, John Wiley and Sons, New York, 1975. Sen, P.C., Power Electronics, McGraw-Hill, 5th reprint, 1992. Shepherd, W et al. Power Electronics and motor control, Cambridge University Press, 2nd Edition 1995. http://www.ipes.ethz.ch/ http://www.celnav.de/hv/hv9.htm http://www.physiqueindustrie.com/custom_converter.php http://www.voltagemultipliers.com/html/multdesign.html

Problems 11.1.

Derive equations (11.33) and (11.34) for the circuit in figure 11.5.

11.2.

Assuming a constant load current, derive an expression for the mean and rms device current and the device form factor, for the circuits in figure 11.7.

11.3.

The single-phase full-wave uncontrolled rectifier is operated from the 415 V line-to-line voltage, 50 Hz supply, with a series load of 10 Ω + 5 mH + 40 V battery. Derive the load voltage expression in terms of a Fourier series. Determine the rms value of the fundamental of the load current.

11.4.

A single-phase uncontrolled rectifier has a 24Ω resistive load a 240V ac 50Hz supply. Determine the average, peak and rms current and peak reverse voltage across each rectifier diode for i. an isolating transformer with a 1:1 turns ratio ii. centre-tapped transformer with turns ratio 1:1:1.

11.5.

A single-phase bridge rectifier has an R-L of R = 20Ω and L = 50mH and a 240V ac 50Hz source voltage. Determine: i. the average and rms currents of the diodes and load ii. rms and average 50Hz source currents iii. the power absorbed by the load iv. the supply power factor

11.6.

A single-phase, full-wave uncontrolled rectifier has a back emf Eb in its load. If the supply is 240Vac 50Hz and the series load is R = 20Ω, L = 50mH, and Eb = 120V dc, determine: i. the power absorbed by the dc source in the load ii. the power absorbed by the load resistor iii. the power delivered from the ac source iv. the ac source power factor v. the peak-to-peak load current variation if only the first ac term of the Fourier series for the load current is considered.

359

Power Electronics

11.7.

A three-phase uncontrolled rectifier is supplied from a 50Hz 415V ac line-to-line voltage source. If the rectifier load is a 75 Ω resistor, determine i. the average load current ii. the rms load current iii. the rms source current iv. the supply power factor.

11.8.

A three-phase uncontrolled rectifier is supplied from a 50Hz 415V ac line-to-line voltage source. If the rectifier load is a series R-L circuit where R = 10Ω and L = 100mH, determine: i. the average and rms load currents ii. the average and rms diode currents iii. the rms source and power current iv. the supply power factor.


blank

360

12 Naturally Commutating AC to DC Converters

- Controlled Rectifiers The converter circuits considered in this chapter have in common an ac voltage supply input and a dc load output. The function of the converter circuit is to convert the ac source energy into controllable dc load power, mainly for highly inductive loads. Turn-off of converter semiconductor devices is brought about by the ac supply voltage reversal, a process called line commutation or natural commutation. Converter circuits employing only diodes are termed uncontrolled (or rectifiers) while the incorporation of only thyristors results in a (fully) controlled converter. The functional difference is that the diode conducts when forward-biased whereas the turn-on of the forward-biased thyristor can be controlled from its gate. An uncontrolled converter provides a fixed output voltage for a given ac supply and load. Converters employing a combination of both diodes and thyristors are generally termed half-controlled (or semi-controlled). Both fully controlled and half-controlled converters allow an adjustable output voltage by controlling the phase angle at which the forward biased thyristors are turned on. The polarity of the output (load) voltage of a fully controlled converter can reverse (but the current flow direction is not reversible), allowing power flow into the supply, a process called inversion. Thus a fully controlled converter can be described as a bidirectional converter as it facilitates power flow in either direction. The half-controlled converter, as well as the uncontrolled converter, contains diodes which prevent the output voltage from going negative. Such converters only allow power flow from the ac supply to the dc load, termed rectification, and can therefore be described as unidirectional converters. Although all these converter types provide a dc output, they differ in characteristics such as output ripple and mean voltage as well as efficiency and ac supply harmonics. An important converter characteristic is that of pulse number, which is defined as the repetition rate in the direct output voltage during one complete cycle of the input ac supply. A useful way to judge the quality of the required dc output, is by the contribution of its superimposed ac harmonics. The harmonic or ripple factor RF is defined by

RFv =

2 V rms −Vdc2 V2 = rms2 − 1 = FF 2 − 1 2 Vdc Vdc

where FF is termed the form factor. RFv is a measure of the voltage harmonics in the output voltage while if currents are used in the equation, RFi gives a measure of the current harmonics in the output current. Both FF and RF are applicable to the input and output, and are fully defined in section 12.8. The general analysis in this chapter is concerned with single and three phase ac supplies mainly feeding inductive dc loads. A load dc back emf is used in modelling the dc machine. Generally, uncontrolled rectifier equations can be derived from the corresponding controlled converter circuit equations by setting the controlled delay angle α to zero. Also purely resistive load equations generally can be derived by setting inductance L to zero in the L-R load equations and R-L load equations can be derived from R-L-E equations by setting E, the load back emf, to zero.

12.1

Single-phase full-wave half-controlled converter

When a converter contains both diodes and thyristors, for example as shown in figure 12.1 parts a to d, the converter is termed half-controlled (or semi-controlled). These four circuits produce identical load and supply waveforms, neglecting any differences in the number and type of semiconductor voltage drops. The power to the load is varied by controlling the angle α, shown in figure 12.1e, at which the bridge thyristors are triggered (after first becoming forward biased). The circuit diodes prevent the load voltage from going negative, extend the conduction period, and reduce the output ac ripple.

BWW

Naturally Commutating AC to DC Converters – Controlled Rectifiers

362

The particular application will determine which one of the four circuits should be employed. For example, circuit figure 12.1a contains five devices of which four are thyristors, whereas the other circuits contain fewer devices, of which only two are thyristors. The circuit in figure 12.1b uses the fewest semiconductors, but requires a transformer which introduces extra cost, weight, and size. Also the thyristors experience twice the voltage of the thyristors in the other circuits, 2√2 V rather than √2 V. The transformer does provide isolation and voltage matching.

T1 q =2 r =1 s =1 p=qxrxs p=2

T2

(a)

Df

D1

(b)

vo

vo

(c)

(d)

Circuit a

T1 and T4

D1

b

T1

D1

c

T1 and D2

T1 and D1

T2 and D1

T2 and D2

d

T1 and D2

D2 and D1

T2 and D1

D1 and D2

T2 and T3 T2

D1 D1

(e)

Figure 12.1. Full-wave half-controlled converters with freewheel diodes: (a), (b), (c), and (d) different circuit configurations producing the same output; and (e) circuit voltage and current waveforms and device conduction table.

The thyristor triggering requirements of the circuits in figures 12.1b and c are simple since both thyristors have a common cathode connection. Figure 12.1c may suffer from prolonged shut-down times with highly inductive loads. The diode in the freewheeling path will hold on the freewheeling thyristor, allowing conduction during that thyristors next positive cycle without any gate drive present. The extra diode Df in figure 12.1c bypasses the bridge thyristors allowing them to drop out of conduction. This is

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achieved at the expense of an extra device, but the freewheel path conduction losses are decreased since that series circuit now involves only one semiconductor voltage drop. This continued conduction problem does not occur in circuits 12.1a and d since freewheeling does not occur through the circuit thyristors, hence they will drop out of conduction at converter shut-down. The table in figure 12.1e shows which semiconductors are active in each circuit during the various periods of the load cycle. Circuit waveforms are shown in figure 12.1e. Since the load is a passive L-R circuit, independent of whether the load current is continuous or discontinuous, the mean output voltage and current (neglecting diode voltage drops) are Vo = I o R = I o = Vo R =

1

∫

π

2V

πR

π α

2

2

V sin(ωt ) d ωt =

(1 + cos α )

π

V

(1 + cos α )

(V)

(12.1)

(A)

where α is the delay angle from the point at which the associated thyristor first becomes forward-biased and is therefore able to be turned on and conduct current. The maximum mean output voltage, Vo = 2 2 V / π (also predicted by equation 11.54), occurs at α = 0. The normalised mean output voltage Vn is Vn = Vo / Vo = ½(1 + cos α ) (12.2) The Fourier coefficients of the 2-pulse output voltage are given by equation (12.92). For the singlephase, full-wave, half-controlled case, p = 2, thus the output voltage harmonics occur at n = 2, 4, 6, …

Equation (12.1) shows that the load voltage is independent of the passive load (because the diodes clamp the load to zero volts thereby preventing the load voltage from going negative), and is a function only of the phase delay angle for a given supply voltage. The rms value of the load circuit voltage vo is 2 1 π π − α + ½ sin 2α Vrms = (12.3) (V) ( 2 V sin ωt ) dωt = V

π

∫

π

α

From the load voltage definitions in section 12.7, the load voltage form factor is FFv =

π (π − α + ½ sin 2α ) Vrms = Vo 2 (1 + cos α )

(12.4)

2 Vrms − Vo2

(12.5)

VRi / Vo = FFv2 − 1

(12.6)

The ripple voltage is VRi

hence the voltage ripple factor RFv is

RFv

The load and supply waveforms and equations, for continuous and discontinuous load current, are the same for all the circuits in figure 12.1. The circuits differ in the device conduction paths as shown in the table in figure 12.1e. After deriving the general load current equations, the current equations applicable to the different circuit devices can be decoded. 12.1i - Discontinuous load current, with α < π and β – α < π, the load current (and supply current) is based on equation 11.14 namely i (ωt ) = is (ωt ) = 2 V

Z

(sin(ωt − φ ) − sin (α − φ ) e

− ωt +α

tanφ

)

(A)

(12.7)

α ≤ ωt ≤ π where Z = R 2 + (ω L ) and φ = tan −1 ω L 2

R After ωt = π the load current decreases exponentially to zero through the freewheel diode according to i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ (A) 0 ≤ ωt ≤ α (12.8)

where for ωt = π in equation (12.7) I o1π =

2V Z

sin(φ − α )(1 − e −π / tanφ )

The various semiconductor average current ratings can be determined from the average half-cycle freewheeling current, I ½ F , and the average half-cycle supply current, I ½ s . For discontinuous load current 2V α −π / tan φ I ½F = ½ sin φ sin φ − sin (α − φ ) e( ) (12.9) πR

(

I ½s = ½I o - I ½F = ½

(

)

2V α −π / tan φ cos 2 φ + cos α + sin φ sin (α − φ ) e( ) πR

)

(12.10)


364

12.1ii - Continuous load current, with α < φ and β − α ≥ π , the load current is given by equations similar to equations 11.20 and 11.21, specifically  sin φ e −α / tan φ − sin(α − φ ) −ωt +α tan φ  i (ω t ) = is (ω t ) = 2 V  sin(ωt − φ ) + e  Z (12.11) 1 − e −π / tan φ   α ≤ ωt ≤ π (A) while the load current when the freewheel diode conducts is i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ (A) (12.12) 0 ≤ ωt ≤ α where, for ωt = π in equation (12.11) sin φ − sin(α − φ )e −π +α / tanφ I 01π = 2 V (A) Z 1 − e −π / tanφ The various semiconductor average current ratings can be determined from the average half cycle freewheeling current, I ½ F , and the average half cycle supply current, I ½ s . For continuous load current sin φ − sin (α − φ ) e−π +α / tan φ 2V I ½F = ½ sin φ (12.13) (1 − e−α / tan φ ) 1 − e−π / tan φ πR I ½s = ½I o - I ½F =½

(

)

− π +α / tan φ −α   2V 1− e ( ) cos φ  tan φ e tanφ sin φ − sin (α − φ ) + cos φ + cos (α − φ )  −π / tan φ 1− e πR  

(12.14)

Table 12.1. Semiconductor average current ratings Bridge circuit figure 12.1

Number of devices

Average device current Thyristor Diode 1× I ½ s 2× I ½ F

a

4T+1D

b

2T+1D

1× I ½ s

2× I ½ F

c

2T+2D

½× I o

½× I o

d

2T+2D

1× I ½ s

1× I ½ s + 2× I ½ F

The device conduction table in figure 12.1e can be used to specify average devices currents, for both continuous and discontinuous load current for each of the circuits in figure 12.1, parts a to d. For a highly inductive load, constant load current, the supply power factor is pf = 2 π √2cosα. Critical load inductance The critical load inductance, to prevent the current falling to zero, is given by ω Lcrit α + sin α + π cos θ = θ − α − ½π + (12.15) 1 + cos α R for α ≤ θ where V 1 + cos α θ = sin −1 o = sin −1 (12.16) π 2V The minimum current occurs at the angle θ, where the mean output voltage Vo equals the instantaneous load voltage, vo. When the phase delay angle α is greater than the critical angle θ, θ = α in equation (12.16) yields (see figure 12.12) ω Lcrit α + sin α + π cos α = −½π + (12.17) R 1 + cos α It is important to note that converter circuits employing diodes cannot be used when inversion is required. Since the converter diodes prevent the output voltage from being negative, (and the current is unidirectional), regeneration from the load into the supply is not achievable. Figure 12.1a is a fully controlled converter with an R-L load and freewheel diode. In single-phase circuits, this converter essentially behaves as a half-controlled converter.

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12.2

Single-phase controlled thyristor converter circuits

12.2.1 Single-phase, half-wave controlled circuit with an R-L load The rectifying diode in the circuit of figure 11.1 can be replaced by a thyristor as shown in figure 12.2a to form a half-wave controlled rectifier circuit with an R-L load. The output voltage is now controlled by the thyristor trigger angle, α. The output voltage ripple is at the supply frequency. Circuit waveforms are shown in figure 12.2b, where the load inductor voltage equal areas are shaded. The output current, hence output voltage, for the series circuit are given by di L + Ri = 2V sin ωt (V) (12.18) dt α ≤ ωt ≤ β (rad) where phase delay angle α and current extinction angle β are shown in the waveform in figure 12.2b and are the zero load (and supply) current points. Solving equation (12.18) yields the load and supply current 2V i (ωt ) = {sin(ωt - φ ) - sin(α - φ )e(α - ωt ) / tan φ } Z where Z =

R 2 + (ω L) 2

(A)

α ≤ ωt ≤ β

(ohms)

(12.19)

tan φ = ω L / R and zero elsewhere.

q =1 r =1 s =1 p=qxrxs p=1

vo iL

vL 0

α

π

2π-α vL

ωt

vT

v (c)

Figure 12.2. Single-phase half-wave controlled converter: (a) circuit diagram; (b) circuit waveforms for an R-L load; and (c) purely inductive load.


366

The current extinction angle β is dependent on the load impedance and thyristor trigger angle α, and can be determined by solving equation (12.19) with ωt = β when i(β) = 0, that is sin( β - φ ) = sin(α - φ ) e(α -β )/ tanφ (12.20) This is a transcendental equation. A family of curves of current conduction angle versus delay angle, that is β - α versus α, is shown in figure 12.3a. The straight line plot for φ = ½π is for a purely inductive load, whereas ø = 0 is a straight line for a purely resistive load. The mean load voltage, whence the mean load current, is given by Vo =

1 2π

∫

β

2 V sin ωt d ωt

α

(12.21)

2V Vo = Io R = (cos α − cos β ) 2π

(V)

where the angle β can be extracted from figure 12.3a. The rms load voltage is Vrms =  12π ∫ α 

β

(

2V

) sin ωt dωt  2

½

2

(12.22)

= V  12π {( β − α ) − ½(sin 2 β − sin 2α )} The rms current involves integration of equation (12.19), squared, giving ½

½

sin ( β − α ) cos(α + φ + β )   I rms = (12.23)   ( β − α ) −   Z  2π  cos φ    Iterative solutions to equation (12.20) are shown in figure 12.3a, where it is seen that two straight-line relationships exist that relate α and β-α. Exact solutions to equation (12.20) exist for these two cases. That is, exact tractable solutions exist for the purely resistive load, Φ = 0, and the purely inductive load, Φ = ½π. V  1 

(a) (a) straight line β=π-α

straight line β = π

π

⅓π

½π

⅔π

(b) Eqn (12.31)

√2V × Io Z

1/π

Eqn (12.25)

π

⅓π

½π

π

Delay angle α (degrees)

Figure 12.3. Half-wave, controlled converter thyristor trigger delay angle α versus: (a) thyristor conduction angle, β-α, and (b) normalised mean load current.

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12.2.1i - Case 1: Purely resistive load. From equation (12.19), Z = R, φ = 0 , and the current is given by 2V i (ωt ) = sin(ωt ) (A) (12.24) R α ≤ ωt ≤ π and β = π ∀α The average load voltage, hence average load current, are Vo =

1 2π

∫

π

2V sin ωt d ωt

α

(12.25)

2V Vo = I o R = (1 + cos α ) 2π

(V)

where the maximum output voltage is 0.45V for zero delay angle. The rms output voltage is Vrms =  12π 

∫ ( π

α

2V

) sin ωt dωt  2

½

2

(12.26)

= V  2π {(π − α ) + ½ sin 2α )} Since the load is purely resistive, I rms = Vrms / R and the voltage and current factors (form and ripple) are 2 equal. The power delivered to the load is Po = Irms R. ½

1

The supply power factor, for a resistive load, is Pout /Vrms Irms, that is pf = ½ -

α sin 2α + 2π 4π

(12.27)

12.2.1ii - Case 2: Purely inductive load. Circuit waveforms showing equal inductor voltage areas are shown in figure 12.2c. From equation (12.19), Z = ωL, φ = ½π , and the output voltage and current ares given by  2V sin ωt α ≤ ωt ≤ 2π − α v o (ωt ) =  (12.28) elsewhere 0 2V ( sin(ωt − ½π ) - sin (α -½π ) ) (A) ωL 2V = α ≤ ωt ≤ β and β = 2π − α ( cos α - cos ωt ) ωL The average load voltage, based on the equal area criterion, is zero i (ωt ) =

1 2π

Vo =

∫

2π-α α

2V sin ωt d ωt = 0

(12.29)

(12.30)

The average output current is I o = 12π

∫

2π −α

2 V

ωL

α

{cos α - cos ωt} d ωt

(12.31)

 (π − α ) cos α + sin α  = πω L  The rms output current is derived from ½ 2π −α 2 2 V 1  α ω ω I rms = cos cos t d t ( ) 2π α  ω L  2 V

∫

3 V 1   =   (π − α )( 2 + cos 2α ) + sin 2α   2 X π   The rms output voltage is

∫ ( 2 V ) sin ωt dωt  = V 1π {(π − α ) + ½ sin 2α )}

Vrms =  12π 

2π −α

2



2

α

½

(12.32)

½

(12.33)

½

Since the load is purely inductive, Po = 0 and the load voltage ripple factor is undefined since Vo = 0. By setting α = 0, the equations (12.24) to (12.33) are valid for the uncontrolled rectifier considered in section 11.1.3, for a purely resistive and purely inductive load, respectively.


368

12.2.1iii - Case 3: Back emf E and R-L load. With a load back emf, current begins to flow when the supply instantaneous voltage exceeds the back emf magnitude E, that is when ∨

α = sin−1

E

(12.34)

2V When current flows, Kirchhoff’s voltage law gives

2V sin ωt = Ri + L

di +E dt

(12.35)

which yields

i (ωt ) =

2V

Z

sin (ωt − φ ) −

 2V −ωt E E − e tanφ  sin (α − φ ) −  Z R R 

 α tanφ  e 

(12.36) ∨

α ≤ ωt ≤ β and α ≥ α The extinction angle β is found from the boundary condition i(ωt) = i(β) = 0, for β > π. The load power is given by 2 PL = I rms R + I oR

(12.37)

while the supply power factor is given by

pf =

I 2 R + I oR PL = rms V I rms V I rms

(12.38) ∨

The solution for the uncontrolled converter (a half-wave rectifier) is found by setting α = α , eqn (12.34). Example 12.1: Single-phase, half-wave controlled rectifier The ac supply of the half-wave controlled single-phase converter in figure 12.2a is v = √2 240 sinωt. For the following loads Load #1: R = 10Ω, ωL = 0 Ω Load #2: R = 0 Ω, ωL = 10Ω Load #3: R = 7.1Ω, ωL = 7.1Ω Determine in each load case, for a firing delay angle α = π/6 • • • •

the conduction angle γ=β - α, hence the current extinction angle β the dc output voltage and the average output current the rms load current and voltage, load current and voltage ripple factor, and power dissipated in the load the supply power factor

Solution Load #1: Z = R = 10Ω, ωL = 0 Ω From equation (12.19), Z = 10Ω and φ = 0° . From equation (12.24), β = π for all α, thus for α = π/6, γ = β - α = 5π/6. From equation (12.25) Vo = I o R = =

2V (1 + cos α ) 2π

2V (1 + cos π / 6) = 100.9V 2π

The average load current is I o = Vo / R =

2V (1 + cos α ) = 100.9V/10Ω =10.1A. 2π R

The rms load voltage is given by equation (12.26), that is Vrms = V  12π {(π − α ) + ½ sin 2α )}

½

= 240V ×  12π {(π − π / 6 ) + ½ sin π / 3} = 167.2V ½

Since the load is purely resistive, the power delivered to the load is 2 Po = Irms R = Vrms2 / R = 167.2V 2 /10Ω = 2797.0W

I rms = Vrms / R = 167.9V /10Ω = 16.8A

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For a purely resistive load, the voltage and current factors are equal: 167.2V 16.8A = = 1.68 FFi = FFv = 100.9V 10.1A RFi = RFv = FF 2 − 1 = 1.32 The power factor is 2797W pf = = 0.70 240V × 16.7A Alternatively, use of equation (12.27) gives π /6 sin π /6 pf = ½ + = 0.70 2π 4π

Load #2: R = 0 Ω, Z = X = ωL = 10Ω From equation (12.19), Z = X =10Ω and φ = ½π . From equation (12.29), which is based on the equal area criterion, β = 2π - α, thus for α = π/6, β = 11π/6 whence the conduction period is γ = β – α = 5π/3. From equation (12.30) the average output voltage is Vo = 0V The average load current is Io = =

2 V

(π − α ) cos α + sin α 

π ωL 

2 240

π × 10

× ( 5π / 6 ) cos π / 6 + sin π / 6  = 14.9A

Using equations (12.32) and (12.33), the load rms voltage and current are ½ 1  Vrms = 240V  π − π + ½ sin π  = 236.5V 6 3  π

{

I rms =

240V  1 10Ω  π

}

{(π − π 6 ) ( 2 + cos 2α ) +

3

2 sin

π

 3}

½

= 37.9A

Since the load is purely inductive, the power delivered to the load is zero, as is the power factor, and the output voltage ripple factor is undefined. The output current ripple factor is I 37.9A FFi = rms = = 2.54 whence RFi = 2.542 − 1 = 2.34 14.9A Io Load #3: R = 7.1Ω, ωL = 7.1Ω From equation (12.19), Z = 10Ω and φ = ¼π . From figure 12.3a, for φ = ¼π and α = π / 6 , γ = β – α =195º whence β = 225º. Iteration of equation (12.20) gives β = 225.5º = 3.936 rad From equation (12.21) Vo = Io R = =

2V (cos α − cos β ) 2π

2 × 240 (cos 30° − cos 225°) = 85.0V 2π

The average load current is Io = Vo / R = 85.0V/7.1Ω = 12.0A Alternatively, the average current can be extracted from figure 12.3b, which for φ = ¼π and α = π / 6 gives the normalised current as 0.35, thus Io = 2V × 0.35 Z = 2×240V ×0.35 = 11.9A 10Ω

From equation (12.23), the rms current is


I rms

sin ( β − α ) cos(α + φ + β )   =   ( β − α ) −   cos φ Z  2π     V  1 

(

370

½

)

½

  sin 3.93 − π cos(π + ¼π + 3.93)   240V  1  6 6   = 18.18A π = × (3.93 − )−  6 10Ω 2π  cos¼π     The power delivered to the load resistor is 2 Po = Irms R = 18.18A 2 × 7.1Ω = 2346W The load rms voltage, from equation (12.22), is Vrms = V  12π {( β − α ) − ½(sin 2 β − sin 2α )} = 240V  12π 

½

{(3.94 − 16 π ) − ½ × (sin ( 2 × 3.94 ) − sin ( 2 × 16 π ))}

½

= 175.1V

The load current and voltage ripple factors are 18.18A FFi = RFi = FFi 2 − 1 = 1.138 = 1.515 12.0A 175.1V FFv = RFv = FFv2 − 1 = 1.8 = 2.06 85V The supply power factor is

2346W = 0.54 240V × 18.18A ♣

pf =

12.2.2 Single-phase, half-wave half-controlled The half-wave controlled converter waveform in figure 12.2b shows that when α < ωt < π, during the positive half of the supply cycle, energy is delivered to the load. But when π < ωt < 2π, the supply reverses and some energy in the load circuit is returned to the supply. More energy can be retained by the load if the load voltage is prevented from reversing. A load freewheel diode facilitates this objective. The single-phase half-wave converter can be controlled when a load commutating diode is incorporated as shown in figure 12.4a. The diode will prevent the instantaneous load voltage v0 from going negative, as with the single-phase half-controlled converters shown in figure 12.1. The load current is defined by equation 11.31 for α ≤ ωt ≤ π and equation 11.32 for π ≤ ωt ≤ 2π + α, namely: di L + Ri = 2 V sin ωt (A) α ≤ ωt ≤ π dt (12.39) di L + Ri = 0 (A) π ≤ ωt ≤ 2π + α dt At ωt = π the thyristor is line commutated and the load current, and hence freewheel diode current, is of the form of equation 11.33. As shown in figure 12.4b, depending on the delay angle α and R-L load time constant (L/R), the load current may fall to zero, producing discontinuous load current. The mean load voltage (hence mean output current) for all conduction cases, with a passive L-R load, is Vo =

1 2π

∫

π α

2 V sin ω t d ω t

2V Vo = Io R = (1 + cos α ) 2π

(12.40) (V)

which is half the mean voltage for a single-phase half-controlled converter, given by equation (12.1). ∧

The maximum mean output voltage, V o = 2V / π (equation 11.27), occurs at α = 0. The normalised mean output voltage Vn is ∧

Vn = Vo / V o = ½ (1 + cos α )

(12.41)

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is

i

q =1 r =1 s =1 p=qxrxs p=1

vo = 0 = vL+vR

vo = v = vL+vR

I o 1π R

vR

vL = vR v L for ωt > π

Figure 12.4. Half-wave half-controlled converter: (a) circuit diagram and (b) circuit waveforms for an inductive load.

The Fourier coefficients of the 1-pulse output voltage are given by equation (12.92). For the singlephase, half-wave, half-controlled case, p = 1, thus the output voltage harmonics occur at n = 1, 2, 3, … The rms output voltage for both continuous and discontinuous load current is  ∫ ( 2 V ) sin ωt dωt  = V  12π {(π − α ) + ½ sin 2α )}

Vrms =  12π 

π

2

½

2

α

(12.42) ½

12.2.2i - For discontinuous conduction the load current is defined by equation (12.19) during thyristor conduction i (ω t ) = is (ω t ) =

(

)

2 V × sin(ωt − φ ) − sin α − φ e −ωt +α tanφ ( ) Z α ≤ ωt ≤ π

(A)

i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ −π / tan φ   )  e −ωt +π / tan φ =  2 V × sin(φ − α ) (1 − e  Z   π ≤ ωt ≤ 2π + α The average thyristor current is V × ( cos 2 φ + cos α + sin φ × sin (α − φ ) × eα −π / tan φ ) IT = 2π R while the average freewheel diode current is V sin φ × ( sin φ − × sin (α − φ ) × eα −π / tan φ ) I Df = I o − I T = 2π R

(12.43) (A)

(12.44)

(12.45)


372

12.2.2ii - For continuous conduction the load current is defined by  sin φ e −α / tan φ − sin(α − φ ) −ωt +α tanφ  i (ω t ) = is (ω t ) = 2 V ×  sin(ωt − φ ) + ( )e  Z 1 − e −2π / tan φ  

α ≤ ωt ≤ π i (ω t ) = iDf (ω t ) = I 01π e

(A)

−ωt / tan φ

(12.46)

 sin φ − sin(α − φ ) e = 2V × Z 1 − e −π / tan φ 

−π −α / tan φ

 −ωt +π / tan φ e 

(A)

π ≤ ωt ≤ 2π + α The advantages of incorporating a load freewheel diode are • the input power factor is improved and • the load waveform is improved (less ripple) giving a better load performance

12.2.3 Single-phase, full-wave controlled rectifier circuit with an R-L load Full-wave voltage control is possible with the circuits shown in figures 12.5a and b. The circuit in figure 12.5a uses a centre-tapped transformer and two thyristors which experience a reverse bias of twice the supply. At high powers where a transformer may not be applicable, a four-thyristor configuration as in figure 12.5b is suitable. The voltage ratings of the thyristors in figure 12.5b are half those of the devices in figure 12.5a, for a given converter input voltage. Load voltage and current waveforms are shown in figure 12.5 parts c, d, and e for three different phase control angle conditions. The load current waveform becomes continuous when the phase control angle α is given by α = tan −1 ω L / R = φ (rad) (12.47) at which angle the output current is a rectified sine wave. For α > ø, discontinuous load current flows as shown in figure 12.5c. At α = ø the load current becomes continuous as shown in figure 12.5d, whence β = α + π. Further decrease in α, that is α < ø, results in continuous load current that is always greater than zero (no zero current periods), as shown in figure 12.5e. 12.2.3i - α > φ , β - α < π , discontinuous load current The load current waveform is the same as for the half-wave situation considered in section 12.2.1, given by equation (12.19). That is 2V

i (ωt ) =

[sin(ωt - φ ) - sin(α - φ ) e

{(α

- ωt ) / tan φ }

]

(A)

(12.48) (rad) The mean output voltage for this full-wave circuit will be twice that of the half-wave case in section 12.2.1, given by equation (12.21). That is Z

α ≤ ωt < β

Vo = Io R = =

2V

π

1

π

∫

β

2 V sin ωt

α

d ωt

(12.49)

(cos α - cos β )

(V)

where β can be extracted from figure 12.3. For a purely resistive load, β = π. The average output current is given by I o = Vo / R and the average and rms thyristor currents are ½ I o and I rms / 2 , respectively. The rms load voltage is Vrms =  π1 

∫

β α

2 V 2 sin 2 ωt d ωt  ½ 

= V  1 {( β − α ) − ½(sin 2β − sin 2α )}  π 

(12.50)

½

The rms load current is I rms

sin ( β − α ) cos(α + φ + β )   =   ( β − α ) −   Z π  cos φ    V 1 

2 R. The load power is therefore P = I rms

½

(12.51)

Power Electronics

373

Vo

q =2 r =1 s =1 p=qxrxs p=2

Figure 12.5. Full-wave controlled converter: (a) and (b) circuit diagrams; (c) discontinuous load current; (d) verge of continuous load current, when α = ø; and (e) continuous load current.

12.2.3ii - α = φ , β - α = π , verge of continuous load current When α = φ = tan -1 ω L / R , the load current given by equation (12.48) reduces to i (ωt ) =

2V

sin(ωt − φ ) (A) (12.52) Z (rad) for φ ≤ ωt ≤ φ + π and the mean output voltage, on reducing equation (12.49) using β = α+π, is given by 2 2V (12.53) Vo = cos α (V) π which is dependent on the load such that α = φ = tan -1 ω L / R . From equation (12.50), with β − α = π , the rms output voltage is V, Irms = V/Z, and power = VI rms cos φ .


374

12.2.3iii - α < φ , β - π = α, continuous load current (and also a purely inductive load) Under a continuous load current conduction condition, a thyristor is still conducting when another is forward-biased and is turned on. The first device is instantaneously reverse-biased by the second device which has been turned on. The first device is commutated and load current is instantaneously transferred to the oncoming device. The load current is given by i (ωt ) =

2V Z

2 sin(α - φ )

[sin(ωt - φ ) -

1− e

− π / tan φ

e

{(α

- ωt ) / tan φ }

(12.54)

]

This equation reduces to equation (12.52) for α = φ and equation 11.52 for α = 0. The mean output voltage, whence mean output current, are defined by equation (12.53) 2 2V cos α (V) π ∧ which is uniquely defined by α. The maximum mean output voltage, Vo = 2 2 V / π (equation 11.54), occurs at α = 0. Generally, for α > ½π, the average output voltage is negative, resulting in a net energy transfer from the load to the supply. Vo = Io R =

The normalised mean output voltage Vn is ∧

Vn = Vo / Vo = cos α The rms output voltage is equal to the rms input supply voltage and is given by Vrms =

( π∫ 1

π +α

α

2V

) sin ωt dωt 2

2

(12.55)

= V

(12.56)

The ac in the output voltage is 2 V ac = V rms −Vo2 = V 1 +

8

π

cos 2 α

(12.57)

The ac component harmonic magnitudes in the load are given by 2V  1 1 2 cos 2α  Vn = × + −  2 2 2π  ( n − 1) ( n + 1) ( n − 1)( n + 1)  for n even, namely n = 2, 4, 6… The load voltage form factor, (thence ripple factor), is FFv =

(12.58)

π

(12.59) 2 2 cos α The current harmonics are obtained by division of the voltage harmonic by its load impedance at that frequency, that is V Vn (12.60) In = n = n = 0, 2, 4, 6,.. 2 Zn R 2 + ( nω L ) Integration of equation (12.54), squared, yields the load rms current (or equation 11.53 for α = 0) I rms

2    2sin (α − φ )   2sin (α − φ )  V  1  −2π / tan φ − π / tan φ   = − − − φ α φ e e tan 1 4 sin sin 1    ( ) ( ) π +   − π / tan φ   1 − e −π / tan φ   Z π   1− e      

½

(12.61)

Thyristor average current is ½ I o , while thyristor rms current rating is I rms / 2 . The same thyristor current rating expressions are valid for both continuous and discontinuous load current conditions. For a highly inductive load, constant load current, the supply power factor is pf = 2 π (1 + cos α ) π π The harmonic factor or voltage ripple factor for the output voltage is

V 2 −Vo2  π 2  = − cos 2 α  RFv = rms Vo  8 

−α .

½

(12.62)

which is a minimum of 0.483 for α=0 and a maximum of 1.11 when α=½π. Critical load inductance (see figure 12.12) The critical load inductance, to prevent the load current falling to zero, is given by ω Lcrit π   2 2 =  cos θ + π sin α − π cos α (½π + α + θ )  R 2 cos α   for α ≤ θ where V 2 cos α θ = sin −1 o = sin −1 π 2V

(12.63)

(12.64)

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375

The minimum current occurs at the angle θ, where the mean output voltage Vo equals the instantaneous load voltage, vo. When the phase delay angle α is greater than the critical angle θ, substituting α = θ in equation (12.63) gives ω Lcrit = − tan α (12.65) R For a purely resistive load 2V Vo = (12.66) (1 + cos α ) .

π

Example 12.2: Controlled full-wave converter – continuous and discontinuous conduction The fully controlled full-wave, single-phase converter in figure 12.5a has a source of 240V rms, 50Hz, and a 10Ω 50mH series load. If the delay angle is 45°, determine i. the average output voltage and current, hence thyristor mean current ii. the rms load voltage and current, hence thyristor rms current and load ripple factors iii. the power absorbed by the load and the supply power factor If the delay angle is increased to 75° determine iv. v. vi. vii. viii.

the load current in the time domain numerically solve the load current equation for β, the current extinction angle the load average current and voltage the load rms voltage and current hence load ripple factors and power dissipated the supply power factor

Solution The load natural power factor angle is given by φ = tan -1 ω L / R = tan -1 ( 2π 50 × 50mH /10Ω ) = 57.5°=1 rad Continuous conduction Since α < φ ( 45° < 57.5° ) , continuous load current flows, which is given by equation (12.54). 2 × 240V 2 × sin(1.31 -1) e [sin(ωt - 1) 18.62Ω 1 − e −π / 1.56 = 18.2 × [sin(ωt - 1) - 1.62 × e - ωt / 1.56 ]

i (ωt ) =

{(1.31 - ωt ) / 1.56}

]

i. The average output current and voltage are given by equation (12.53) 2 2V 2 2V Vo = Io R = cos α = cos 45° = 152.8V π

π

Io = Vo / R = 152.8V /10Ω = 15.3A Each thyristor conducts for 180°, hence thyristor mean current is ½ of 15.3A = 7.65A.

ii. The rms load current is determined by harmonic analysis. The voltage harmonics (peak magnitude) are given by equation (12.58) 2V  1 1 2 cos 2α  Vn = × + − for n = 2, 4, 6,..  2 2  2π  ( n − 1) ( n + 1) ( n − 1)( n + 1)  and the corresponding current is given from equation (12.60) V Vn In = n = 2 Zn R 2 + ( nω L ) Vn Zn

harmonic n

Vn

Z n = R 2 + ( nω L )

0

(152.79)

10.00

15.28

(233.44)

2

55.65

32.97

1.69

1.42

4

8.16

63.62

0.13

0.01

6

3.03

94.78

In =

2

½ I n2

0.07

I + 2 o

∑½I

0.00 2 n

=

234.4


376

The dc output voltage component is given by equation (12.53). From the calculations in the table, the rms load current is I rms = I o2 + ½

∑I

2 n

= 234.4 = 15.3A

Since each thyristor conducts for 180°, the thyristor rms current is

1

2

of 15.3A = 10.8A

The rms load voltage is given by equation (12.56), that is 240V. I 15.3A = 1.0 FFi = rms = RFi = FFi 2 − 1 = 1.002 − 1 = 0.0 I o 15.3A V 240V = 1.57 FFv = rms = RFv = FFv2 − 1 = 1.57 2 − 1 = 1.21 V o 152.8V iii. The power absorbed by the load is 2 PL = I rms R = 15.3A 2 × 10Ω = 2344W The supply power factor is PL 2344W = = 0.64 pf = Vrms I rms 240V × 15.3A Discontinuous conduction iv. When the delay angle is increased to 75° (1.31 rad), discontinuous load current flows since the natural power factor angle φ = tan -1 ω L / R = tan -1 ( 2π 50 × 50mH /10Ω ) = 57.5° ≡ 1rad is exceeded. The load current is given by equation (12.48) 2 × 240V (1.31 - ωt ) / 1.56} [sin(ωt - 1) - sin(1.31 -1) e { ] i (ωt ) = 18.62Ω = 18.2 × [sin(ωt - 1) - 0.71× e - ωt / 1.56 ] v. Solving the equation in part iv for ωt = β and zero current, that is 0 = sin( β - 1) - 0.71× e - β / 1.56 gives β = 4.09 rad or 234.3°. vi. The average load voltage from equation (12.49) is 2 240V (cos 75° - cos 234.5°) = 90.8V Vo =

π

Io =

Vo 90.8V = = 9.08A 10Ω R

vii. The rms load voltage is given by equation (12.50) ½

Vrms = 240V ×  1 {(4.09 − 1.31) − ½(sin 8.18 − sin 2.62)} = 216.46V  π  The rms current from equation (12.51) is ½

1  sin ( 4.09 − 1.31) × cos(1.31 + 1 + 4.09)   I rms = ×   ( 4.09 − 1.31) −   = 13.55A  18.62Ω  π  cos1    The load voltage and current form and ripple factors are I 13.55A = 1.49 FFi = rms = RFi = FFi 2 − 1 = 1.492 − 1 = 1.11 9.08A Io V 216.46V FFv = rms = RFv = FFv2 − 1 = 2.382 − 1 = 2.16 = 2.38 90.8V Vo The power dissipated in the 10Ω load resistor is 2 P = I rms R = 13.552 × 10Ω = 1836W 240V

viii. The supply power factor is PL 1836W = = 0.56 pf = Vrms I rms 240V × 13.55A ♣

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12.2.4 Single-phase, full-wave, fully-controlled circuit with R-L and emf load, E

An emf source and R-L load can be encountered in dc machine modelling. The emf represents the machine speed back emf, defined by E = kφω . DC machines can be controlled by a fully controlled converter configuration as shown in figure 12.6a, where T1-T4 and T2-T3 are triggered alternately. If in each half sine period the thyristor firing delay angle occurs after the rectified sine supply has fallen below the emf level E, then no load current flows since the bridge thyristors will always be reversebiased. Thus the zero current firing angle α is:

(

α = sin −1 E / 2V

)

(rad)

for

∧

½π < α < π

(12.67)

where it has been assumed the emf has the polarity shown in figure 12.6a. With discontinuous output current, load current cannot flow until the supply voltage exceeds the back emf E. That is

(

∨

α = sin −1 E / 2V

)

for

(rad)

∨

0< α < ½π

(12.68)

Load current can always flow with a firing angle defined by ∨

α ≤α ≤α

(12.69)

(rad) The load circuit current can be evaluated by solving di 2 V sin ωt = L + Ri + E (V) dt The load voltage and current ripple are both at twice the supply frequency.

(12.70)

12.2.4i - Discontinuous load current

The load current is given by i (ωt ) =

2V R

[cos φ sin(ωt - φ ) - E + 2V

{

E 2V

}

- cos φ sin(α - φ ) e

{(α

- ωt ) / tan φ }

]

(12.71)

∨

α ≤ ωt ≤ β < π + α

(rad) For discontinuous load current conduction, the current extinction angle β, shown on figure 12.6b, is solved by iterative techniques for i(ωt=β) = 0 in equation (12.71). cos φ sin( β - φ ) - E + 2V

{

E 2V

}

- cos φ sin(α - φ ) e

{(α

- β ) / tan φ }

=0

(12.72)

The mean output voltage can be obtained from equation (12.49), which is valid for E = 0. For any E, including E = 0

∫ (

)

β

Vo = 1π

2 V sin ω t + E d ω t

α

 E  (V)  cos α − cos β + (π + α − β )  π 2V   0 < β −α < π (rad) The current extinction angle β is load-dependent, being a function of Z and E, as well as α. 2V

Vo =

(12.73)

Since Vo = E + I o R , the mean load current is given by Io =

V −E o

R

=

2V

πR

E   (β − α )   cos α − cos β − 2V   0 < β −α < π

(A)

(12.74)

(rad)

The rms output voltage is given by ½

2  2 β −α  β −α V 2 + − − V E (1 ) (sin 2 β − sin 2α )   π π 2π   The rms voltage across the R-L part of the load is given by

Vrms =

2 VRLrms = Vrms − E2

(V)

(12.75)

(12.76)

The total power delivered to the R-L-E load is 2 Po = I rms R + IoE (12.77) where the rms load current is found by integrating the current in equation (12.71), squared, etc.


q =2 r =1 s =1 p=qxrxs p=2

T1

T2

T3

T4

378

∨

α

α

α

Figure 12.6. A full-wave fully controlled converter with an inductive load which includes an emf source: (a) circuit diagram; (b) voltage waveforms with discontinuous load current; (c) verge of continuous load current; and (d) continuous load current.

12.2.4ii - Continuous load current With continuous load current conduction, the load rms voltage is V.

The load current is given by i (ωt ) =

2V Z

[sin(ωt - φ ) -

E

2V

cos φ

+2

sin(α - φ ) e e−π / tan φ − 1

{(α

- ωt ) / tan φ }

]

α ≤ ωt ≤ π + α The periodic minimum current is given by ∨ e −π / tan φ + 1 E 2V I= − sin (α − φ ) −π / tan φ Z e −1 R

=

 ½π  E 2V sin (α − φ ) tanh  − Z  tan φ  R

(12.78) (rad)

(12.79)

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379

For continuous load current conditions, as shown in figures 12.6c and 12.6d, the mean output voltage is given by equation (12.73) with β = π − α Vo = π1 =

∫

π +α

α

2 2V π

2 V sin ωt d ωt cosα

(= E + I R) o

(12.80)

(V)

  p π  = 2 V π sin p cos α    The average output voltage is dependent only on the phase delay angle α (independent of E), unlike the mean load current, which is given by V −E 2V  2 E  = (A) (12.81) Io =  cosα −  R R 2V  π The power absorbed by the emf source in the load is P = I o E , while the total power delivered to the R-L2 E load is Po = I rms R + IoE . The output current and voltage ripple is at multiples of twice the supply frequency. The output voltage harmonic magnitudes for continuous conduction, given by equation (12.58), are 2V  1 1 2 cos 2α  for n = 2, 4, 6, .. (12.82) Vn = × + −  2 2 2π  ( n − 1) ( n + 1) ( n − 1)( n + 1)  The dc component across the R-L (and just the resistor) part of the load is Vo R−L = Vo − E (12.83) 2 2V = × cos α − E o

.

π

The ac component of the output voltage is  2 2 cos α 2 2 −V o = 1−  Vac = Vrms  π  and the output voltage form factor is FFv =

  

2

(12.84)

π

(12.85) 2 2 cos α Thyristor average current is ½ I o , while thyristor rms current rating is I rms / 2 . These same two thyristor expressions are valid for both continuous and discontinuous load current conditions. Critical load inductance

From equation (12.79) set to zero (or i = 0 in equation (12.78)), the boundary between continuous and discontinuous inductor current must satisfy  ½π  R E (12.86) sin (α − φ ) tanh   > Z 2V  tan φ 

Inversion

If the polarity of the back emf E is reversed as shown in figure 12.7a, waveforms as in parts b and c of figure 12.7 result. The emf supply can provide a forward bias across the bridge thyristors even after the supply polarity has gone negative. The zero current angle α now satisfies π < α < 3π/2, as given by equation (12.67). Thus load and supply current can flow, even for α > π. The relationship between the mean output voltage and current is now given by p π sin cos α with p = 2 (12.87) Vo = − E + I o R = 2 V π p That is, the emf term E in equations (12.67) to (12.86) is appropriately changed to - E. The load current flows from the emf source and if α > ½π, the average load voltage is negative. Power is being delivered to the ac supply from the emf source in the load, which is an energy transfer process called power inversion. In general 0 < α < 90° → Vo > 0 Po > 0 io > 0 rectification 90° < α < 180° → Vo < 0 Po < 0 io > 0 inversion


T1

T2

T3

T4

380

q =2 r =1 s =1 p=qxrxs p=2

α

α

Figure 12.7. A full-wave controlled converter with an inductive load and negative emf source: (a) circuit diagram; (b) voltage waveforms for discontinuous load current; and (c) continuous load current.

Example 12.3: Single-phase, controlled converter – continuous conduction and back emf

The fully controlled full-wave converter in figure 12.5a has a source of 240V rms, 50Hz, and a 10Ω, 50mH, 50V emf opposing series load. The delay angle is 45°. Determine i. ii. iii. iv. v. vi.

the average output voltage and current the rms load voltage and the rms voltage across the R-L part of the load the power absorbed by the 50V load back emf the rms load current hence power dissipated in the resistive part of the load the load efficiency, that is percentage of energy into the back emf and power factor the load voltage and current form and ripple factors

Solution

From example 12.2, continuous conduction is possible since α < φ i. The average output voltage is given by equation (12.80) 2 2V Vo = cosα π

=

2 2 × 240 π

× cos45° = 152.8V

The average current, from equation (12.81) is

( 45° < 57.5° ) .

Power Electronics

381

Io =

V −E o

R

=

152.8V − 50V = 10.28A 10Ω

ii. From equation (12.56) the rms load voltage is 240V. The rms voltage across the R-L part of the load is 2 VRLrms = Vrms − E2 = 240V 2 − 50V 2 = 234.7V

iii. The power absorbed by the 50V back emf load is P = I o E = 10.28A × 50V = 514W iv. The R-L load voltage harmonics (which are even) are given by equations (12.82) and (12.83): 2 2V × cos α − E Vo R−L = .

π

Vn =

2V 2π

 1 1 2 cos 2α  × + −  2 2  ( n − 1) ( n + 1) ( n − 1)( n + 1)   

n = 2, 4, 6,..

for

The harmonic currents and voltages are shown in the table to follow.

Vn

n 0

Z n = R 2 + ( nω L ) (Ω )

102.79

2

harmonic

In =

2

Vn Zn

(A)

½ I n2

10.00

10.28

105.66

60.02

32.97

1.82

1.66

4

8.16

63.62

0.13

0.01

6

3.26

94.78

0.04 I + 2 o

∑½I

0.00 2 n

=

107.33

From the table the rms load current is given by I rms = I o2 + ½

∑I

2 n

= 107.33 = 10.36A

The power absorbed by the 10Ω load resistor is 2 PL = I rms R = 10.36A 2 × 10Ω = 1073.3W v. The load efficiency, that is, percentage energy into the back emf E is 514W η= × 100 o o = 32.4 o o 514W + 1073.3W The power factor is PL 514W+1073.3W pf = = = 0.64 240V × 10.36A Vrms I rms vi. The output performance factors are I 10.36A FFi = rms = RFi = FFi 2 − 1 = 1.0232 − 1 = 0.125 = 1.011 I o 10.28A V 240V FFv = rms = RFv = FFv2 − 1 = 1.57 2 − 1 = 1.211 = 1.57 V o 152.8V Note that the voltage form factor (hence voltage ripple factor) agrees with that obtained by substitution into equation (12.85), 1.57. ♣ Example 12.4: Controlled converter – constant load current, back emf, and overlap

The fully controlled single-phase full-wave converter in figure 12.5a has a source of 230V rms, 50Hz, and a series load composed of ½Ω, infinite inductance, 150V emf non-opposing. If the average load current is to be 200A, calculate the delay angle assuming the converter is operating in the inversion mode, taking into account 1mH of commutation inductance.


382

Solution

The mean load current is

Io = 200A =

V o (α ) − E R Vo (α ) − −150V

½Ω which implies a load voltage Vo(α) = -50V. The output voltage is given by equation (12.53) Vo = 2 π2 V cos α . Commutation of current from one rectifier to the other takes a finite time. The effect of commutation inductance is to reduce the output

voltage, thus according to equation (12.141), the output voltage becomes

Vo =

2V sin π n cos α − n ω Lc I o / 2π π /n

where n = 2

2 × 230V × cos α − 2 × 50Hz × 1mH × 200A π /2 = 207V × cos α − 20V which yields α = 98.3º. The commutation overlap causes the output voltage to reduce to zero volts and the overlap period γ is given by equation (12.142) −50V =

Io =

2V

2π f Lc

( cos α − cos (γ + α ) )

2 230V ( cos 93.8° − cos (γ + 93.8° ) ) 2π 50Hz × 1mH This gives an overlap angle of γ = 11.2º. ♣ 200A =

12.3

Three-phase half-controlled converter

Figure 12.8a illustrates a half-controlled (semi-controlled) converter where half the devices are thyristors, the remainder being diodes. As in the single-phase case, a freewheeling diode can be added across the load so as to allow the bridge thyristors to commutate and decrease freewheeling losses. The output voltage expression consists of √2V 3√3/2π due to the uncontrolled half of the bridge and √2V 3√3 × cos α /2π due to the controlled half which is phase-controlled. The half-controlled bridge mean output is given by the sum, that is 3 3 3 Vo = 2 V (1 + cos α ) = 2 VL (1 + cos α ) 2π 2π = 2.34 V (1 + cos α ) (V) (12.88) 0≤α ≤π (rad) Vo = I o R At α = 0, V o = √2 V 3√3/π = 1.35 VL, as in equation (11.93). The normalised mean output voltage Vn is Vn = Vo / V o = ½(1 + cos α )

(12.89)

The diodes prevent any negative output, hence inversion cannot occur. Typical output voltage and current waveforms for a highly inductive load (constant current) are shown in figure 12.8b. 12.3i - α ≤ ⅓π When the delay angle is less than ⅓π the output waveform contains six pulses per cycle, of alternating controlled and uncontrolled phases, as shown in figure 12.8b. The output current is always continuous (even for a resistive load) since no output voltage zeros occur. The rms output voltage is given by 2 2 α + 2π / 3 3 2π / 3 2VL sin 2 ωt d ωt + ∫ 2VL sin 2 ωt d ωt Vrms = ∫ π /3 2π α +π / 3

{

(

)

 3 3  = VL 1 + (1 + cos 2α )   4π  

(

)

}

½

(12.90) for α ≤ π / 3

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383

R-L

q =3 r =1 s =2 p=qxrxs p=6

Figure 12.8. Three-phase half-controlled bridge converter: (a) circuit connection; (b) voltage and current waveforms for a small firing delay angle α; and (c) waveforms for α large.

12.3ii - α ≥ ⅓π For delay angles greater than ⅓π the output voltage waveform is made up of three controlled pulses per cycle, as shown in figure 12.8c. Although output voltage zeros result, continuous load current can flow through a diode and the conducting thyristor, or through the commutating diode if employed. The rms output voltage is given by


Vrms =

3 2π

∫( π

α

2 VL

384

) sin ωt dωt 2

2

½

 3 = VL  (π − α + ½ sin 2α )  π 2  

(12.91) for α ≥ π / 3

The Fourier coefficients of the p-pulse output voltage are given by cos ( n + 1) α cos ( n − 1) α  2V  −2 an = − +  2  2π  n − 1 n +1 n −1   p 2V  sin ( n + 1) α sin ( n − 1) α  − bn =   2π  n +1 n −1  p

(12.92)

where n = mp and m = 1, 2, 3, .. For the three-phase, full-wave, half-controlled case, p = 6, thus the output voltage harmonics occur at n = 6, 12, …

12.4

Three-phase, fully controlled thyristor converter circuits

12.4.1 Three-phase, fully-controlled, half-wave circuit with an inductive load

When the diodes in the circuit of figure 11.10 are replaced by thyristors, as in figure 12.9a, a threephase fully controlled half-wave converter results. The output voltage is controlled by the delay angle α. This angle is specified from the thyristor commutation angle, which is the earliest point the associated thyristor becomes forward-biased, as shown in parts b, c, and d of figure 12.9. (The reference is not the phase zero voltage cross-over point). The thyristor with the highest instantaneous anode potential will conduct when fired and in turning on will reverse bias and turn off any previously conducting thyristor. The output voltage ripple is three times the supply frequency and the supply currents contain dc components. Each phase progressively conducts for periods of π, displaced by α, as shown in figure 12.9b. The mean output voltage for an n-phase half-wave controlled converter is given by (see example 12.7) 2 V α +π / n Vo = cos ωt d ωt 2π / n ∫ α −π / n (12.93) sin(π / n ) = 2V cos α (V) π /n which for the three-phase circuit considered with continuous or discontinuous (R) load current gives 3 3 0 ≤α ≤π /6 Vo = Io R = (12.94) 2 V cos α = 1.17 V cos α 2π For discontinuous conduction, and a resitive load, the mean output voltage is 3 Vo = Io R = 2 V (1 + cos (α + π / 6 ) ) π / 6 ≤ α ≤ 5π / 6 (12.95) 2π The mean output voltage is zero for α = ½π. For 0 < α < π, the instantaneous output voltage is always greater than zero. Negative average output voltage occurs when α > ½π as shown in figure 12.9d. Since the load current direction is unchanged, for α > ½π, power reversal occurs, with energy feeding from the load into the ac supply. Power inversion assumes a load with an emf to assist the current flow, as in figure 12.7. If α > π no reverse bias exists for natural commutation and continuous load current will freewheel. The maximum mean output voltage V o = √2V 3√3 /2π occurs at α = 0. The normalised mean output voltage Vn is Vn = Vo / Vˆo = cos α (12.96) With an R-L load, at Vo = 0, the load current falls to zero. Thus for α > ½π, continuous load current does not flow for an R-L load.

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q =3 r =1 s =1 p=qxrxs p=3

Figure 12.9. Three-phase half-wave controlled converter: (a) circuit connection; (b) voltage and current waveforms for a small firing delay angle α; (c) and (d) load voltage waveforms for progressively larger delay angles.

The rms output voltage is given by 3 α +π / 3 Vrms = 2π ∫ α −π / 3

(

2V

) sin (ωt ) dωt 2

2

(12.97)

½

1 3 = 3 2 V  + sin 2α   6 8π  From equations (12.94) and (12.97), the ac in the output voltage is

1 2 V ac = V rms −Vo2 = 3 2 V  + 6



3 8π

sin 2α −

3 2π

½

cos2 α  

(12.98)

The output voltage distortion ripple factor is

RFv =

12.4.2

2π 2 27

+

3π 18

sin 2α − cos2 α

(min ( at α =0 ) = 0.173; max ( at α =½π ) = 0.66)

(12.99)

Three-phase, half-wave converter with freewheel diode

Figure 12.10 shows a three-phase, half-wave controlled rectifier converter circuit with a load freewheel diode, Df. This diode prevents the load voltage from going negative, thus inversion is not possible.


386

q =3 r =1 s =1 p=qxrxs p=3

Df

Figure 12.10. A half-wave fully controlled three-phase converter with a load freewheel diode.

12.4.2i - α < π/6. The output is as in figure 12.9b, with no voltage zeros occurring. The mean output voltage (and current) is given by equation (12.94), that is 3 3 2V cos α = 1.17V cos α (V) 0 ≤α ≤π /6 (rad) Vo = Io R = (12.100) 2π

The maximum mean output Vo = √2V 3√3/2π occurs at α = 0. The normalised mean output voltage, Vn is given by Vn = Vo / V o = cos α (12.101) The Fourier coefficients of the 3-pulse output voltage are given by (12.92). For the three-phase, halfwave, half-controlled case, p = 3, thus the output voltage harmonics occur at n = 3, 6, 9, …

12.4.2ii - α > π/6. Because of the freewheel diode, voltage zeros occur and the negative portions in the waveforms in parts c and d of figure 12.9 do not occur. The mean output voltage is given by 2V π Vo = Io R = sin ωt d ωt 2π / 3 ∫ α −π / 6 2V (12.102) = (V) (1 + cos (α + π / 6 ) ) 2π / 3 π / 6 ≤ α ≤ 5π / 6

The normalised mean output voltage Vn is Vn = Vo / V o = [1 + cos(α + π / 6)]/ 3 The average load current (with an emf E in the load) is given by V −E Io = o R These equations assume continuous load current.

(12.103) (12.104)

12.4.2iii - α > 5π/6. A delay angle of greater than 5π/6 would imply a negative output voltage, clearly not possible with a freewheel load diode.

Example 12.5: Three-phase half-wave rectifier with freewheel diode

The half-wave three-phase rectifier in figure 12.10 has a three-phase 415V 50Hz source (240V phase), and a 10Ω resistor and infinite series inductance as a load. If the delay angle is 60º determine the load current and output voltage if: i. the phase commutation inductance is zero ii. the phase commutation reactance is¼Ω

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Solution i. The output voltage, without any line commutation inductance and a 60º phase delay angle, is given by equation (12.102)

Vo = I o R =

2V

2π / 3

(1 + cos (α + π / 6 ) )

2 240 V

(1 + cos ( 60° + π / 6 ) ) = 162V 2π / 3 The constant load current is therefore V 162V = 16.2A Io = o = 10Ω R =

ii. When the current changes paths, any inductance will control the rate at which the commutation from one path to the next occurs. The voltage drops across the commutating inductors modifies the output voltage. Since the voltage across the freewheel diode is not associated with commutation inductance, the output voltage is not effected when the current swaps from a phase to the freewheel diode. But when the current transfers from the diode to a phase, while the commutation inductance current in the phase is building up to the constant load current level, the output remains clamped at the diode voltage level, viz. zero. The average voltage across the load during this overlap period is therefore reduced. The commutation current is defined by

di c di c = Xc dt d ωt  2V  π  ic =  cos  α +  − cos ωt  Xc  6   Solving for when the current rises to the load current I oγ gives 2V  π π    I oγ =  cos  α +  − cos  α + + γ   Xc  6 6    2V sin ωt = Lc

but

I oγ =

Voγ 2V = (1 + cos (α + π / 6 + γ ) ) R R 2π / 3

Xc π  cos  α +  − π 6  R 2π / 3    = cos  α + + γ  Xc 6   +1 R 2π / 3 Xc   π   cos  α +  − π π / 3   R 6 2   −  α +  = 0.68° γ = cos −1  Xc    6 +1   π R 2 / 3   The load current and voltage are therefore 2V  π π 2 240V    I oγ = ( cos ( 90° ) − cos ( 90.68 ) ) = 16.11A  cos  α +  − cos  α + + γ   = Xc  ¼Ω 6 6    

Voγ = I oγ R = 16.11A × 10Ω = 161.1V ♣ 12.4.3 Three-phase, full-wave, fully-controlled circuit with an inductive load

A three-phase bridge is fully controlled when all six bridge devices are thyristors, as shown in figure 12.11a. The frequency of the output ripple voltage is six times the supply frequency and each thyristor always conducts for ⅔π. Circuit waveforms are shown in figure 12.11b. The output voltage is continuous, and the mean output voltage for both inductive and resistive loads is given by


Vo = =

3

π∫

α +½ π α +π / 6

3 3

π

388

3 2 V sin (ω t + π / 6 ) d ω t

2 V cos α = 2.34 V cos α

(V)

(12.105)

0 ≤ α ≤ 2π / 3 which is twice the voltage given by equation (12.94) for the half-wave circuit, but for a purely resistive load the output voltage is discontinuous and equation (12.105) becomes 3 3 (V) Vo = 2 V 1 + cos (α + π / 6 )  (12.106) π π / 3 ≤ α ≤ 2π / 3

The average output current is given by I o = Vo / R in each case. If a load back emf exists the average current becomes Vo − E Io = (12.107) R The maximum mean output voltage V o = √2V 3√3/π occurs at α = 0. The normalised mean output Vn is Vn = Vo / V o = cos α

q =3 r =1 s =2 p=qxrxs p=6

Figure 12.11. A three-phase fully controlled converter: (a) circuit connection and (b) load voltage waveform for four delay angles.

(12.108)

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For delay angles up to ⅓π, the output voltage is at all instances non-zero, hence the load current is continuous for any passive load (both resistive and inductive). Beyond ⅓π the load current may be discontinuous (always discontinuous for a resistive load). For α > ½π the current is always discontinuous for passive loads (no back emf, E) and the average output voltage is less than zero For continuous load current, the load current is given by 3 2V

i ( ωt ) =

Z

(

sin ωt + π

6

)

E

−φ −

R

+

3 2V

Z

sin (α − φ )

− ωt + π 6 + α

e e

− π 3 tan φ

tan φ

(12.109)

−1

The maximum and minimum ripple current magnitudes are 3 2V

I =

Z

(

sin α + π

2

)

−φ −

E R

3 2V

+

Z

e

sin (α − φ )

e

−

π 6

π 3

tan φ

(12.110) tan φ

−1

at ωt = α +nπ for n = 0, 6, 12, .. 3 2V

∨

I =

Z

(

sin α + π

3

)

−φ −

E R

3 2V

+

Z

1

sin (α − φ )

e

−

π 3

tan φ

(12.111) −1

at ωt = α - π +n π for n = 0, 6, 12, .. ∨

With a load back emf the critical inductance for continuous load current must satisfy I = 0 in equation (12.111), that is sin (α − φ )  R  E × sin (α − φ + 13 π ) + −π / 3 tan φ (12.112) ≥ −1 Z  e 3 2V where tan φ = ω L / R . The rms value of the output voltage for a purely resistive load is given by 3 Vrms =  π

∫

α +π / 2 α −π / 6

3

(

= 3 2 V 1+

)

2V 3 3 2π

2

½

 sin 2 (ωt ) d ω t  

0 ≤α ≤π /3

(12.113)

π / 3 ≤ α ≤ 2π / 3

(12.114)

cos 2α

and

Vrms = 3 2 V 1 −

3α 2π

−

3 4π

sin ( 2α − π / 3)

The output voltage ripple factor (with continuous current) is

RFv =

π2

18

3π

+

12

(min ( at α =0 ) = 0.025; max ( at α =½π ) = 0.3)

cos 2α − cos 2 α

(12.115)

The normalise voltage harmonic peak magnitudes in the output voltage, with continuous load current, are 1

VL n

2 3 3 1 1 2 cos 2α  = 2V + −   2 2 π  ( n − 1) ( n + 1) ( n − 1)( n + 1) 

(12.116)

.

.

for n = 6, 12, 18… The harmonics occur at multiples of six times the fundamental frequency. For discontinuous load current, at high delay angles, when the output current becomes discontinuous with an inductive load, the output current is given by

i (ωt ) =

(

3 2V  sin ωt + π

Z



6

)

(

− φ − sin α + π

3

)

−φ e

− ωt − π 6 + α

tan φ

−E  R

1 − e −ωt −π 6 +α tan φ    α ≤ ωt ≤ α + θc

(12.117)

where θc is the conduction period, which is found by solving the transcendental equation formed when in equation (12.117), i(ωt = α+π+θc) = 0. The average output voltage can then be found from

Vo =

(

3 3 2V  cos α + π

π



3

) − cos (α + π 3 + θ ) − 3πE π 3 − θ  c

c

(12.118)


390

fully-controlled converter delay angle α 0

20°

30°

¼π

60°

70°

80°

½π°

10 Single-phase 2 pulse

ω Lcrit / R

5

sing

le

se -p h a

fully

-con

tr oll

ed

single-phase 1

Semi-controlled

0.5

three-phase

1

0.1

0.8

0.05

thre e

0

30°

se - p ha

¼π

0.6

fully

-con

60°

trolle

0.4

0.2

←

d

0

per unit dc output voltage Vo

Three-phase 6 pulse

75°

½π

105°

120°

¾π

150°

π

delay angle α semi-controlled converter

Figure 12.12. Critical load inductance (reactance) of single-phase (two pulse) and three-phase (six pulse), semi-controlled and fully-controlled converters, as a function phase delay angle α whence dc output voltage Vo. For rectifier, α = 0.

12.4.3i - Resistive load

For a resistive load, the load voltage harmonics for p pulses per cycle, are given by cos ( n + 1) α cos ( n − 1) α  2V  −2 an = − −   2π  n 2 + 1 n +1 n −1  p 2V  sin ( n + 1) α sin ( n − 1) α  bn = −   2π  n +1 n −1   p

(12.119)

for n = pm and m = 1, 2, 3, .. The harmonics occur at multiples of six times the fundamental frequency, for a 6 - pulse (p = 6) per cycle output voltage. 12.4.3ii - Highly inductive load – constant load current

As with a continuous load current, with a constant load current the input current comprises ⅔π alternating polarity blocks of current, with each phase displaced relative to the others by ⅔π, independent of the thyristor triggering delay angle. At maximum voltage hence maximum power output, the delay angle is zero and the phase voltage and current fundamental are in phase. As the phase angle is increased, the inverter output voltage, hence power output is decreased, and the line current block of current (fundamental) shifts by α with respect to the line voltage. Reactive input power increases as the real power decreases. At α = ½π, the output voltage reduces to zero, the output power is zero, and the ⅔π current blocks in the ac input are shifted ½π with respect to the line voltage, producing only VAr’s from the ac input. When the delay angle is increased above ½π, the inverter dc output reverses polarity and energy transfers back into the ac supply (inversion), with maximum inverted power reached at α = π, where the reactive VAr is reduced to zero, from a maximum at α = ½π. For a highly inductive load, that is a constant load current: the mean diode current is I Th = 1n I o = 13 I o (A)

(12.120)

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391

and the rms diode current is ITh rms = 1 n I o rms ≈

1

=

n Io

1

3

Io

(A)

The diode current form factor is FFITh = ITh rms / I Th = 3

(12.121) (12.122)

The diode current ripple factor is

RFITh = FF ITh2 − 1 = 2

(12.123)

The rms input line currents are

2 I o rms 3

(12.124)

v a = 2V sin ωt

(12.125)

I L rms = A phase voltage is given by

with phases b and c shifted by ⅔π. That is substitute ωt with ωt±⅔π. From equation (14.34), the line current harmonics are 4 1 cos ½ ( 1 3 π ) n for n odd ii = I o

π n

(12.126)

The rms fundamental input current is

I 1rms = 3

2

π

Io

(12.127)

The supply fundamental apparent power, S1, active power P and reactive power Q, are given by

S 1 = 3VI 1rms = P 2 + Q 2 P = P1 = S 1 cos α

(12.128)

Q = Q1 = S 1 sin α The supply apparent power is constant for a given constant load current, independent of the thyristor turn-on delay angle. The power factor for a constant load current is 2 3 Vrms 3 I o cos α 3 Vrms I1rms cos α 3 π pf = = = cos α (12.129) π 2 2 Io Io 3 Vrms × 3 Vrms × 3 3 Undesirably, if triggering pulses to all the thyristors are removed, the dc current decays slowly and uncontrolled to zero through the last pair of thyristors that were triggered. Converter shut down is best achieved regeneratively by increasing (and controlling) the delay angle to greater than ½π such that the output voltage goes negative, which results in controlled power inversion back into the ac supply. Example 12.6: Three-phase full-wave controlled rectifier with constant output current

The full-wave three-phase controlled rectifier in figure 12.11a has a three-phase 415V 50Hz source (240V phase), and provides a 100A constant current load. Determine: i. the average and rms thyristor current ii. the rms and fundamental line current iii. the apparent fundamental power S1 If 25kW is delivered to the dc load, calculate: iv. iv. v. vi.

the supply power factor the dc output voltage, load resistance, hence the converter phase delay angle the real active and reactive Q1 ac supply power the delay angle range if the ac supply varies by ±5% (with 25kW and 100A dc).

Solution i.

From equations (12.120) and (12.121) the thyristor average and rms currents are I Th = 1 3 I o = 1 3 × 100A = 33 1 3 A

I Th rms =

1

3

Io =

1

3

× 100A = 57.7A


ii.

The rms and fundamental line currents are 2 2 I L rms = I o rms = × 100A = 81.6A 3 3 2 2 × 100A = 78.0A I1rms = 3 Io = 3

π

iii.

392

π

The apparent power is

S 1 = 3VI 1rms = 3 × 415V × 78A = 56.1kVA iv.

v.

The supply power factor, from equation (12.129), is PL 25kW  3  pf = = = 0.426  = π cos α  3 Vrms I rms 3 × 415V × 81.6A   The output voltage is Vo = power = 25kW = 250V dc 100A Io The load resistance is

RL =

Vo 250V = = 2.5Ω I o 100A

Thyristor delay angle is given by equation (12.105), that is Vo = 2.34 V cos α 250Vdc = 2.34 × 415V

× cos α 3 which yields a delay angle of α = 1.11rad = 63.5°

vi.

For a constant output power at 100A dc, the output voltage must be maintained at 250V dc independent of the ac input voltage magnitude, thus for equation (12.105) 250Vdc α = cos −1 2.34 × ( 415 ± 5% ) 3 ∨

α = cos −1

250Vdc 2.34 × ( 415 − 5% )

= 1.08 rad = 61.9°

3

α = cos −1

250Vdc 2.34 × ( 415 + 5% )

= 1.13 rad = 64.9°

3 ♣ q =3 r =1 s =2 p=qxrxs p=6

Figure 12.13. A full-wave three-phase controlled converter with a load freewheeling diode (half-controlled).

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12.4.4 Three-phase, full-wave converter with freewheel diode

Both half-controlled and fully controlled converters can employ a discrete load freewheel diode. These circuits have the voltage output characteristic that the output voltage can never go negative, hence power inversion is not possible. Figure 12.13 shows a fully controlled three-phase converter with a freewheel diode D.

•

The freewheel diode is active for α > ⅓π. The output is as in figure 12.11b for α < ⅓π. The mean output voltage is Vo = I o R =

3 3

π

2 V cos α = 2.34V cos α

0 ≤α ≤π /3

(V)

(12.130)

(rad)

The maximum mean output voltage V o = √2V 3√3/π occurs at α = 0. The normalised mean output voltage Vn is given by Vn = Vo / V o = cos α

•

(12.131)

while Vo = I o R =

3 3

π

(

2 V 1 + cos (α + π / 3)

)

π / 3 ≤ α ≤ 2π / 3

(V)

(12.132)

(rad)

The normalised mean output, Vn, is

Vn = Vo / V o = 1 + cos (α + π / 3)

•

(12.133)

while Vo = 0

(V)

(12.134) 2π / 3 ≤ α (rad) In each case the average output current is given by I o = Vo / R , which can be modified to include any load back emf, that is, I o = (Vo − E ) / R .

Example 12.7: Converter average load voltage

Derive a general expression for the average load voltage of an p-pulse controlled converter. Solution

Figure 12.14 defines the general output voltage waveform where p is the output pulse number per cycle of the ac supply. From the output voltage waveform π / n+α 1 Vo = 2 V cos ω t d ω t ∫ − 2π / p π / n+α =

2V ( sin(α + π / p) − sin(α − π / p) ) 2π / p

=

2V 2sin(π / p ) cos α 2π / p

Vo =

2V

π/p

sin(π / p ) cos α

= Vo cos α

(V)

where for p = 2 for the single-phase (n = 1) full-wave controlled converter in figure 12.5. for p = 3 for the three-phase (n = 3) half-wave controlled converter in figure 12.9. for p = 6 for the three-phase (n = 3) full-wave controlled converter in figure 12.11. ♣


− πp

+ πp

0

2π

(a)

p +

394

2V 2 V s i n n π n πsin p π

pπ

rectify

½

π

π

invert

−

2V2 V s i n n π sin p π p πn π

−

(b)

Figure 12.14. A half-wave n-phase controlled converter: (a) output voltage and current waveform and (b) transfer function of voltage versus delay angle α.

12.5

Overlap

In the previous sections of this chapter, impedance of the ac source has been neglected, such that current transfers or commutates instantly from one switch to the other with higher anode potential, when triggered. However, in practice the source has inductive reactance Xc and current takes a finite time to fall in the device turning off and rise in the device turning on. Consider the three-phase half-wave controlled rectifying converter in figure 12.9a, where it is assumed that a continuous dc load current, Io, flows. When thyristor T1 is conducting and T2 (which is forward biased) is turned on after delay α, the equivalent circuit is shown in figure 12.15a. The source reactances X1 and X2 limit the rate of change of current in T1 as i1 decreases from Io to 0 and in T2 as i2 increases from 0 to Io. These current transitions in T1 and T2 are shown in the waveforms of figure 12.15d. A circulating current, i, flows between the two thyristors. If the line reactances are identical, the output voltage during commutation, vγ, is mid-way between the conducting phase voltages v1 and v2, as shown in figure 12.15b. That is vγ = ½(v1 + v2), creating a series of notches in the output voltage waveform as shown in figure 12.15c. This interval during which both T1 and T2 conduct (i ≠ 0) is termed the overlap period and is defined by the overlap angle γ. Ignoring thyristor voltage drops, the overlap angle is calculated as follows: With reference t = 0 when T2 is triggered v2 − v1 = vL = 3 v phase = 3 2 V sin (ωt + α ) where V is the line to neutral rms voltage. Equating these two equations 2 L di / dt = 3 2 V sin (ωt + α )

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Rearranging and integrating gives i (ωt ) =

3 2V

2ω L

( cos α − cos (ωt + α ) )

(12.135)

Commutation from T1 to T2 is complete when i = Io, at ωt = γ, that is Io =

3 2V

( cos α − cos (γ + α ) ) = 23πωVL ( cos α − cos (γ + α ) )

o (A) (12.136) 2ω L Figure 12.15b shows that the load voltage comprises the phase voltage v2 when no source inductance exists minus the voltage due to circulating current vγ (= ½(v1 + v2)) during commutation.

The mean output voltage Voγ is therefore Voγ = Vo − v γ =

1  2π / 3 

α + 5π / 6

∫v

 

γ +α +π / 6

d ωt − ∫ vγ d ωt

2 α +π / 6

α +π / 6

where vγ = ½(v1 + v2)  α +5π / 6 3  ∫ α +π / 6 2 V sin (ωt + α ) d ωt Vo = γ +α +π / 6 2π  −∫ 2 V sin (ω t + 2π 3 ) + sin ωt d ω t  α +π / 6 γ

{

}

   

v2 − v1 = 2 L di / dt Voγ =

3 2π

3 2 V cos α −

3 3 2 V ( cos α − cos (α − γ ) ) 2π 2

(12.137)

3 3 (12.138) 2 V  cos α + cos (α + γ )  = ½Vo  cos α + cos (α + γ )  4π which reduces to equation (12.94) when γ = 0. Substituting cos α - cos (α + γ) from equation (12.136) into equation (12.137) yields 3 3 3 3 3 3 Voγ = ω LI o = Vo − ω LI o where Vo = (12.139) 2 V cos α − 2V 2π 2π 2π 2π Voγ =

The mean output voltage Vo is reduced or regulated by the commutation reactance Xc = ωL and this regulation varies with load current magnitude Io. Converter semiconductor voltage drops also regulate (decrease) the output voltage. The component 3ωL/2π is called the equivalent internal resistance. Being an inductive phenomenon, it does not represent a power loss component. As shown in figure 12.16, the overlap occurs immediately after the delay α. The commutation voltage, v2 - v1, is √3 √2 V sin α. The commutation time is inversely proportional to the commutation voltage v2 v1. For rectification, as α increases from zero to ½π, the commutation voltage increases from a minimum of zero volts to a maximum of √3 √2 V at ½π, whence the overlap angle γ decreases from a maximum of ∧ ∨ γ at α = 0 to a minimum of γ at ½π. ∨

∧

[For inversion, the overlap angle γ decreases from a minimum of γ at ½π to a maximum of γ at π, as the commutation voltage reduces from a maximum, back to zero volts.] From equation (12.136), with α = π ∨

γ = arc sin(2ω LI o / 2 3 V ) The general expressions for the mean load voltage Voγ of an n-pulse, fully-controlled converter, with underlap, are given by 2V Voγ = sin π n cos α + cos (α + γ )  (12.140) 2π / n and 2V Voγ = sin π n cos α ∓ nX c I o / 2π (12.141) π /n where V is the line voltage for a full-wave converter and the phase voltage for a half-wave converter and the plus sign in equation (12.141) accounts for inversion operation.


0º

396

α α+γ

Vγ = ½ (v1 + v2)

(b)

√2 VLL

VT3 v3-1

α+γ 0º

commutation voltage

α

(e)

π

δ

recovery angle = ωtq

(c)

commutation voltage

(d)

Figure 12.15. Overlap: (a) equivalent circuit during overlap; (b) angle relationships; (c) load voltage for different delay angles α (hatched areas equal to IoL; last overlap shows commutation failure); (d) thyristor currents showing eventual failure; and (e) voltage across a thyristor in the inversion mode, α >90°.

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Effectively, as shown in figure 12.17, during rectification, overlap reduces the mean output voltage by nfLIo or as if α were increased. The supply voltage is effectively distorted and the harmonic content of the output is increased. Equating equations (12.140) and (12.141) gives the mean output current 2V (12.142) Io = sin π n ( cos α − cos (γ + α ) ) (A) Xc which reduces to equation (12.136) when n = 3. Harmonic input current magnitudes are decreased by a factor sin (½ nγ ) / ½ nγ . In the three-phase case, for a constant dc link current Io, without commutation effects, the rms phase current and the magnitude of the nth current harmonic are 2I o 2 3 (12.143) I rms = Ihn = Io nπ 3 When accounting for commutation reactance effects the fundamental current is

I h1

2 2      2 3  cos 2α - cos 2 (α + γ )  + 2γ + sin 2α − sin 2 (α + γ )  = Io π 4  cos α − cos (α + γ ) 

½

(12.144)

The single-phase, full-wave, converter voltage drop is 2ωLIo /π and the overlap output voltage is zero. The general effects of line inductance, which causes current overlap are: • the average output voltage is reduced • the input voltage is distorted • the inversion safety angle to allow for thyristor commutation, is increased • the output voltage spectrum component frequencies are unchanged but there magnitudes are decreased slightly. 12.6

Overlap - inversion

A fully controlled converter operates in the inversion mode when α > 90° and the mean output voltage is negative and less than the load back emf shown in figure 12.15a. Since the direction of the load current Io is from the supply and the output voltage is negative, energy is being returned, regenerated into the supply from the load. Figure 12.18 shows the power flow differences between rectification and inversion. As α increases, the returned energy magnitude increases. If α plus the necessary overlap γ exceeds ωt = π, commutation failure occurs. The output goes positive and the load current builds up uncontrolled. The last commutation with α ≈ π in figures 12.15c and d results in a commutation failure of thyristor T1. Before the circulating inductor current i has reduced to zero, the incoming thyristor T2 experiences an anode potential which is less positive than that of the thyristor to be commutated T1, v1 - v2 < 0. The incoming device T2 fails to stay on and conduction continues through T1, impressing positive supply cycles across the load. This positive converter voltage aids the load back emf and the load current builds up uncontrolled. Equations (12.140) and (12.141) are valid provided a commutation failure does not occur. The controllable delay angle range is curtailed to 0 ≤ α ≤ π −γ ∧ ∧ The maximum allowable delay angle α occurs when α + γ = π and from equations (12.140) and (12.141) with α + γ = π gives XI o   − 1 < π α = cos−1  (rad) (12.145)  2V sin π / n  In practice commutation must be complete δ rad before ωt = π, in order to allow the outgoing thyristor to regain a forward blocking state. That is α + γ + δ ≤ π . δ is known as the recovery or extinction angle, and is shown in figure 12.23e. The thyristor recovery period increases with increased anode current and temperature, and decreases with increased voltage. The input power is equal to the dc power

P = 3VI cos φ = Vo I o

(12.146)

The input power factor is therefore

cos φ =

Vo I o

3V I

≈ ½ cos α + cos (α + γ ) 

(12.147)


398

v2 vo ½(v1+v2 )

v2-v1

v1

vγ

i(ωt) 2

δ

2 3V

ωL

i1

γ

Io

i2

Io

α = 135°

rectifying Vo > 0

Inverting Vo < 0 i1

Io

∨

γ

Io

i2

2 3V

ωL

α = 90° i1

Io

γ

Io

equation

(12.135) i2

α = 60° i1

γ

Io

Io

i2 ωt

α = 0°

π

½π

Figure 12.16. Overlap γ for current commutation from thyristor 1 to thyristor 2, at delay angle α.

nX/2π

Voγ

Io

Io=0, γ

=0

from equation (12.141)

Voγ = n 2½ V/π×sinπ/n×cosα rectification

Voγ n 2½ V/π×sinπ/n×cosα

Voγ=0, γ

Mean output voltage

=π

from equation (12.142) Io = 2×2½V/X×sinπ/n×cosα slope =

-nX/2π Io 0 Load current (a)

inversion

(b)

Figure 12.17. Overlap regulation model: (a) equivalent circuit and (b) load plot of overlap model.

Power Electronics

399

i

rectification

vs

i

vs

+ i>0 vs > 0

power in

0 < α < ½π

½π < α < π

+

power out

i>0 vs < 0

power in

+ inversion

power out

+

(a) (b) Figure 12.18. Controlled converter model showing: (a) rectification and (b) inversion.

Example 12.8:

Converter overlap

A three-phase full-wave converter is supplied from the 415 V ac, 50 Hz mains with phase source inductance of 0.1 mH. If the average load current is 100 A continuous, for phase delay angles of (i) 0º and (ii) 60º determine i. the supply reactance voltage drop, ii. mean output voltage (with and without commutation overlap), load resistance, and output power, and iii. the overlap angle Ignoring thyristor forward blocking recovery time requirements, determine the maximum allowable delay angle. Solution

Using equations (12.140) and (12.141) with n = 6 and V = 415 V ac, the mean supply reactance voltage n 6 vγ = 2π f LI o = × 2π 50 × 10−4 × 102 2π 2π = 3V (i) α = 0° - as for uncontrolled rectifiers. From equation (12.141), the maximum output voltage is 2V Voγ = sin π n cos α − nX c I o / 2π 2π / n 2 × 415 π sin 6 × cos 0 − 3V = 560.44V - 3V = 557.44V = 2π / 6 where the mean output voltage without commutation inductance effects is 560.4V. The power output for 100A is 560.4V×100A = 56.04kW and the load resistance is 560.4V/100A = 5.6Ω. From equation (12.140) 2V Voγ = sin π / n  cos α + cos (α + γ )  2π / n 2 × 415 × sin π / 6 × [1 + cos γ ] 557.44 = 2π / 6 that is γ = 8.4° (ii)

α = 60º

2V sin π n cos α − nX c I o / 2π 2π / n 2 × 415 sin π 6 × cos 60° − 3V = 280.22V - 3V = 277.22V = 2π / 6 where the mean output voltage without commutation inductance effects is 280.2V. The power output for 100A is 280.2V×100A = 28.02kW and the load resistance is 280.2V/100A = 2.8Ω.

Voγ =


400

2V

sin π / n cos α + cos (α + γ )  2π / n 2 × 415 277.22 = × ½ × cos 60° + cos ( 60° + γ )  2π / 6 that is γ = 0.71° Voγ =

Equation (12.145) gives the maximum allowable delay angle as 

 X Io − 1  2 V sin π / n 

α = cos −1 

 2π50×10-4 ×102  = cos-1  -1  2 ×415×½  = 171.56° and Voγ = −557.41V ♣

12.7

Summary

General expressions for n-phase converter mean output voltage, Vo (i) Half-wave and full-wave, fully-controlled converter sin(π / n ) Vo = 2 V cos α π /n where V is the rms line voltage for a full-wave converter or the rms phase voltage for a half-wave converter. cos α = cosψ , the supply displacement factor From L’Hopital’s rule, for n→∞, Vo = √2 V cosα (ii) Full-wave, half-controlled converter sin(π / n ) Vo = 2 V (1 + cos α ) π /n where V is the rms line voltage. (iii) Half-wave and full-wave controlled converter with load freewheel diode sin(π / n ) Vo = 2 V cos α 0 < α < ½π − π / n π /n 1 + cos (α + ½π − π / n ) Vo = 2 V ½π − π / n < α < ½π + π / n 2π / n the output rms voltage is given by cos 2α sin 2π / n α + π / n ≤ ½π Vrms = V 1 + 2π / n Vrms = V ½ +

cos ( 2α − 2π / n ) n α − − 4 2π / n 4π / n

α + π / n > ½π

where V is the rms line voltage for a full-wave converter or the rms phase voltage for a half-wave converter. n = 0 for single-phase and three-phase half-controlled converters = π for three-phase half-wave converters = ⅓π for three-phase fully controlled converters These voltage output characteristics are shown in figure 12.19 and the main converter circuit characteristics are shown in table 12.2.

Power Electronics

401

Figure 12.19. Converter normalised output voltage characteristics as a function of firing delay angle α.

12.8

Definitions average output voltage

Vo

Vrms rms output voltage

Io

average output current

Irms rms output current

peak output voltage I peak output current V Load voltage form factor = FFv = rms Load voltage crest factor = CFv = V Vo Vrms V

Load current form factor = FFi =

Irms

Load current crest factor = CFi = I

Io

Irms

dc load power Rectification efficiency = η = ac load power + rectifier losses Vo I o = Vrms I rms + Loss rectifier

Waveform smoothness = Ripple factor = RFv = = where

 ∞ VRi =   n=1

∑

1 2

( van2 + vbn2 ) 

effective values of ac V (or I ) VRi = average value of V (or I ) Vo

2 Vrms − Vo2 = FFv2 − 1 Vo2

½

similarly the current ripple factor is RFi =

I Ri

= FFi 2 − 1 Io RFi = RFv for a resistive load


12.9

402

Output pulse number

Output pulse number p is the number of pulses in the output voltage that occur during one ac input cycle, of frequency fs. The pulse number p therefore specifies the output harmonics, which occur at p x fs, and multiples of that frequency, m×p×fs, for m = 1, 2, 3, ... The pulse number p is specified in terms of q the number of elements in the commutation group r the number of parallel connected commutation groups s the number of series connected (phase displaced) commutating groups Parallel connected commutation groups, r, are usually associated with (and identified by) intergroup reactors (to reduce circulating current), with transformers where at least one secondary is effectively star connected while another is delta connected. The rectified output voltages associated with each transformer secondary, are connected in parallel. Series connected commutation groups, s, are usually associated with (and identified by) transformers where at least one secondary is effectively star while another is delta connected, with the rectified output associated with each transformer secondary, connected in series. q =3 r =2 s =2 p=qxrxs p = 12

The mean converter output voltage Vo can be specified by

Vo = s

q π

2Vφ × sin

π × cos α q

For a full-wave fully-controlled single-phase converter, r = 1, q = 2, and s = 1, whence p = 2 2 2 Vφ 2 π 2Vφ × sin × cos α = Vo = 1 × × cos α 2 π π For a full-wave, fully-controlled, three-phase converter, r = 1, q = 3, and s = 2, whence p = 6 3 2 Vφ 3 π Vo = 2 × × cos α 2Vφ × sin × cos α = 3 π π

(12.148)

Power Electronics

403

Table 12.2. Main characteristics of controllable converter circuits

12.2a

12.4a

12.5a

12.4b

12.1

12.1

12.9a

12.10a

12.10

12.13

12.8a

12.8a


404

12.10 AC-dc converter generalised equations

Alternating sinusoidal voltages V1 = 2V sin ωt

(

V 2 = 2V sin ωt − .

2π

q

)

(

Vq = 2V sin ωt − (q − 1) 2qπ

)

where q is the number of phases (number of voltage sources) On the secondary or converter side of any transformer, if the load current is assumed constant I o then the power factor is determined by the load voltage harmonics. Voltage form factor

FFv =

V rms Vo

whence the voltage ripple factor is ½ ½ 1 2 −Vo2  = FFv 2 − 1 RFv = V rms V o

The power factor on the secondary side of any transformer is related to the voltage ripple factor by P V I 1 pf = d = o o = S qVI rms RFv 2 + 1 On the primary side of a transformer the power factor is related to the secondary power factor, but since the supply is assumed sinusoidal, the power factor is related to the primary current harmonics. Relationship between current ripple factor and power factor 1 ∞ 2 1 2 RFi = − I 12 ∑ I h = I rms

I1

I1

h =3

pf =

I1 I rms

=

1 1 + RFi 2

The supply power factor is related to the primary power factor and is dependent of the supply connection, star or delta, etc. Half-wave controlled rectifiers – star connected secondary supply [see figures 12.2, 12.9]

q phases and q thyristors, and a phase delay angle of α. The pulse number is p (=q). Mean output voltage is

q ½ π + π q +α 2V sin ωt d ωt 2π ∫½π − π q +α q π = 2V sin cos α π q = Vo (α = 0 ) cos α

Vo =

The rms output voltage is

V rms =

q 2π

∫

½π + π q + α

½π − π q + α

(

2V sin ωt

)

2

d ωt

½

  2π q = 2V ½ + sin cos α  q 4π   The maximum and minimum voltages in the output are

v = 2V .

 π  = 2V cos  − + α  q   ∨ π  v = 2V cos  + α  q  .

.

= − 2V .

for 0 < α < for α >

π q

π q

3π π + 2 q 3π π + for α > 2 q for α
½π -

π p

Mean rectified output voltage is

p 2π p = 2π

Vo =

∫

½π

− π q +α

2V cos ωt d ωt

  π  2V 1 − sin  − + α   p   

RMS voltage

V rms

  p pα p 2π   = 2V ¼ − − + sin  2α − q   8 4π 8π  

The maximum ripple occurs at ωt = − π

v p − p = 2V cos 

p

Vnp − p =

v p −p Vo

=

p 2π

½

π + α , with zero volts during diode freewheeling, thus p

 −α −0 

π  π  2V cos  − α  cos  − α  p p 2π     = p  π  π  1 + sin  − α  2V 1 − sin  − α   p  p  

The freewheel diodes conduct for p periods of duration π/p+α, and the currents are pα   I Df = I o  ½ + - ¼p  2π   

½

I rms Df = I o  ½ +

pα  - ¼p  2π 

 The thyristor conductor for 2π/p without a load freewheel diode and 2π/p-(π/p+α+½π) when the diode is present. The thyristor rms current is

I rmsTh

I  pα  = o ½ + ¼p  2π q  

½

Full-wave fully controlled thyristor converters–star connected supply [see figures 12.5, 12.6, 12.7, 12.11] q phases 2q thyristors Pulse number, p p=q p=2q Mean voltage

if q is even if q is odd

Vo =

p π V sin cos α = Vo' cos α π p

The rms output voltage is



Vo rms = V ½ +

 p 2π sin cos α  p 4π 

½

 The maximum and minimum voltages in the output are

Power Electronics

407

for 0 < α

π p

π p

3π π + 2 p 3π π + for α > 2 p for α

539

Power Electronics

×1.155

Figure 15.21. Modulation reference waveforms: (a) sinusoidal reference, sin ωt; (b) third harmonic injection reference, sin ωt +  sin 3ωt; and (c) triplen injection reference, sin ωt + (1/√3π){9/8 sin3ωt 80/81 sin9ωt + . ..} where the near triangular waveform b is half the magnitude of the shaded area.

The spatial voltage vector technique injects the triplens according to r   1 ∞ ( −1) VRN = M ' sin ωt + (15.71)  sin  ( 2r + 1) 3ωt  ∑ 1 1 3π r =0 ( 2r + 1) − 3   ( 2r + 1) + 3     The Fourier triplen series represents half the magnitude of the shaded area in figure 15.21c (the waveform marked ‘b’), which is formed by the three-phase sinusoidal waveforms. The spatial voltage vector waveform is defined by 3 sin(ωt ) 0 ≤ ωt ≤ 16 π 2 (15.72) 3 1 1 sin(ωt + 6 π ) 6 π ≤ ωt ≤ ½π 2 The use of this reference increases the duration of the zero volt loops, thereby decreasing inverter output current ripple. The maximum modulation index is 1.155. Third harmonic injection, yielding M = 1.155, is a satisfactory approximation to spatial voltage vector injection. 2 - Voltage space vector pwm

When generating three-phase quasi-square output voltages, the inverter switches step progressively to each of the six switch output possibilities (states). In figure 15.10, when producing the quasi-square output, each of these six states is represented by an output voltage space vector. Each vector has a ⅓π displacement from its two adjacent states, and each has a length Vs which is the pole output voltage relative to the inverter 0V rail. Effectively, the quasi-square three-phase output is generated by a rotating vector of length Vs, jumping successively from one output state to the next in the sequence, and in so doing creating six voltage output sectors. The speed of rotation, in particular the time for one

DC to AC Inverters – Switched Mode

540

rotation, determines the inverter output frequency. The sequence of voltage vectors {v1, v3, v2, v6, v4, v5} is arranged such that stepping from one state to the next involves only one of the three poles changing state. Thus the number of inverter devices needing to change states (switch) at each transition, is minimised. [If the inverter switches are relabelled, upper switches T1, T2, T3 - right to left; and lower switches T4, T5, T6 - right to left: then the rotating voltage sequence becomes {v1, v2, v3, v4, v5, v6}] Rather than stepping ⅓π radians per step, from one voltage space vector position to the next, thereby producing a six-step quasi-square fixed magnitude voltage output, the rotating vector is rotated in smaller steps based on the position being updated at a constant rate (carrier frequency). Furthermore, the vector length can be varied, modulated, to a magnitude less than Vs. 2 V sin 1 π − θ (3 ) o/ p Va ta 3 = = Tc v1 Vs Vb tb = = Tc v3

2 Vo / p sin θ 3 Vs

where v1 = v3

#

(15.73)

#

Interval 4 T4 T5 T6 on leg state 010 πj v2 = V s e 

Interval 3 T3 T4 T5 on leg state 011 πj v3 = V s e  SECTOR

II

SECTOR

SECTOR

III

#

Interval 5 T1 T5 T6 on leg state 110 πj v6 = V s e

I

#

Interval 2 T2 T3 T4 on leg state 001 0j v1 = V s e

000 111 SECTOR

SECTOR

IV

VI

SECTOR

V

#

#

Interval 6 T1 T2 T6 on leg state 100 πj v4 = V s e 

Interval 1 T1 T2 T3 on leg state 101 - πj v5 = V s e 

001 v1

011 v3

010 v2

110 v6

100 v4

101 v5

111 v7

000 v0

Figure 15.22. Instantaneous output voltage states for the three legs of an inverter.

Power Electronics

541

To incorporate a variable rotating vector length (modulation depth), it is necessary to vary the average voltage in each carrier period. Hence pulse width modulation is used in the period between each finite step of the rotating vector. Pulse width modulation requires the introduction of zero voltage output states, namely all the top switches on (state 111, v7) or all the lower switches on (state 000, v0). These two extra states are shown in figure 15.22, at the centre of the hexagon. Now the pole-to-pole output voltage can be zero, which allows duty cycle variation to achieve variable average output voltage for each phase, within each carrier period, proportional to the magnitude of the position vector. To facilitate vector positions (angles) that do not lie on one of the six quasi-square output vectors, an intermediate vector Vo/p e jθ is resolved into the vector sum of the two quasi-square vectors adjacent to the rotating vector. This process is shown in figure 15.23 for a voltage vector Vo/p that lies in sector I, between output states v1 (001) and v3 (011). The voltage vector has been resolved into the two components Va and Vb as shown. The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in each case. Therefore the portion of Tc associated with va and vb is scaled proportionally to v1 and v3, giving ta and tb. The two sine terms in equation (15.73) generate two sine waves displaced by 120°, identical to that generated with standard carrier based sinusoidal pwm. The sum of ta and tb cannot be greater than the carrier period Tc, thus ta + tb ≤ Tc (15.74) ta + tb + to = Tc where the slack variable to has been included to form an equality. The equality dictates that vector v1 is used for a period ta, v3 is used for a period tb, and during period to, the null vector, v0 or v7, at the centre of the hexagon is used, which do not affect the average voltage during the carrier interval Tc. A further constraint is imposed in the time domain. The rotating voltage vector is a fixed length for all rotating angles, for a given inverter output voltage. Its length is restricted in both time and space. Obviously the resolved component lengths cannot exceed the pole vector length, Vs. Additionally, the two vector magnitudes are each a portion of the carrier period, where ta and tb could be both equal to Tc, that is, they both have a maximum length Vs. The anomaly is that voltages va and vb are added vectorially but their scalar durations (times ta and tb) are added linearly. The longest time ta + tb possible is when to is zero, as shown in figures 15.23a and 15.22a, by the hexagon boundary. The shortest vector to the boundary is where both resolving vectors have a length ½Vs, as shown in figure 15.23b. For such a condition, ta = tb = ½Tc, that is ta + tb = Tc. Thus for a constant inverter output voltage, when the rotating voltage vector has a constant length, Vlo /p , the locus of allowable rotating reference voltage vectors must be within the circle scribed by the maximum length vector shown in figure 15.23b. As shown, this vector has a length v1 cos30°, specifically 0.866Vs. Thus the full quasi-square vectors v1, v2, etc., which have a magnitude of 1×Vs, cannot be used for generating a sinusoidal output voltage. The excess length of each quasi-square voltage (which represents time) is accounted for by using zero state voltage vectors for a period corresponding to that extra length (1- cos 30° at maximum output voltage). Having calculated the necessary periods for the inverter poles (ta, tb, and to), the carrier period switching pattern can be assigned in two ways. • •

Minimised current ripple Minimised switching losses, using dead banding

Each approach is shown in figure 15.24, using single edged modulation. The waveforms are based on the equivalent of symmetrical modulation where the pulses are symmetrical about the carrier trough. By minimising the current ripple, seven switching states are used per carrier cycle, while for loss minimisation (dead banding) only five switching states occur, but at the expense of increased ripple current in the output current. When dead banding, the zero voltage state v0 is used in even numbered sextants and v7 is used in odd numbered sextants. Sideband and harmonic component magnitudes can be decreased if double-edged modulation placement of the states is used, which requires recalculation of ta, tb, and to at the carrier crest, as well as at the trough. Over-modulation is when the magnitude of the demanded rotating vector is greater than Vlo /p such that the zero voltage time reduces to zero, to = 0, during a portion of the time of one rotation of the output vector. Initially this occurs at 30° ( 16 π ( 2 N sector − 1) ) when the output vector length reaches Vlo /p , as shown in figure 15.23b. As the demand voltage magnitude increases further, the region around the 30° vector position where to ceases to occur, increases as shown in figure 15.23c. When the output rotational vector magnitude increases to Vs, the maximum possible, angle α reduces to zero, and to ceases to occur at any rotational angle. The values of ta, tb, and to (if greater than zero), are calculated as usual, but pulse times are assigned pro rata to fit within the carrier period Tc.

DC to AC Inverters – Switched Mode V 3 =V s e

j?π

V 3 =V s e

011

j?π

542 Tc

011

SECTOR I

SECTOR I

Tc

ωt ∧

Vo / p

tb Vb = 2 VO / P sin θ 3

V s cos30°

VoV/ pO/P e jθ

½v 3 = ½V s

θ

000 111

ta

Va = 2 VO / P sin ( 13 π − θ ) 3

000 111

v 1 =V s e

Tc

30° ½v 1 = ½V s

j0

v 1 =V s e

j0

001

001

(a)

(b) V 3 =V s e

j?π

tb + ta < T c reduced to

Tc

011

60°-α V o /p

tb + ta > T c no to

> Vo /p

TTcc

Vlo / p

α

000 111

Tc v 1 =V s e

tb + ta < T c reduced to

j0

001

(c)

Figure 15.23. First sector of inverter operational area involving pole outputs 001 and 011: (a) general rotating voltage vector; (b) maximum allowable voltage vector length for undistorted output voltages; and (c) over modulation. v0

v1

v3

0 00

0 01

011

¼ to

½ ta

½ tb

v7

v7

v3

v1

v0

111

1 11

01 1

001

0 00

¼ to ¼ to

½ tb

¼ ta

¼ to

ΦR

ΦY

ΦB

Tc (a )

v1

v3

v7

v7

v3

v1

001

01 1

111

111

011

001

½ ta

½ tb

¼ to

¼ to

½ tb

¼ ta

ΦR

ΦY

ΦB

Tc (b )

Figure 15.24. Assignment of pole periods ta and tb based on: (a) minimum current ripple and (b) minimum switching transitions per carrier cycle, Tc.

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15.2

dc-to-ac controlled current-source inverters

In the current source inverter, CSI, the dc supply is of high reactance, being inductive so as to maintain the required inverter output bidirectional current independent of the inverter load. 15.2.1 Single-phase current source inverter

A single-phase, controlled current-sourced bridge is shown in figure 15.25a and its near square-wave output current is shown in figure 15.25b. No freewheel diodes are required and the thyristors require forced commutation and have to withstand reverse voltages. An inverter current path must be maintained at all times for the source controlled current. Consider thyristors T1 and T2 on and conducting the constant load current. The capacitors are charged with plates X and Y positive as a result of the previous commutation cycle. • Phase I Thyristors T1 and T2 are commutated by triggering thyristors T3 and T4. The capacitors impress negative voltages across the respective thyristors to be commutated off, as shown in figure 15.26a. The load current is displaced from T1 and T2 via the path T3-C1-D1, the load and D2-C2-T4. The two capacitors discharge in series with the load, each capacitor reverse biasing the thyristor to be commutated, T1 and T2 as well as diodes D3 to D4. The capacitors discharge linearly (due to the constant current source).

Figure 15.25. Single-phase controlled-current sourced bridge inverter: (a) bridge circuit with a current source input and (b) load current waveform.

-

+

+

-

-

+

-

+

+

+

(a)

-

+

+

-

(b)

Figure 15.26. Controlled-current sourced bridge inverter showing commutation of T1 and T2 by T3 and T4: (a) capacitors C1 and C2 discharging and T1, T2, D3, and D4 reversed biased and (b) C1, C2, and the load in parallel with C1 and C2 charging.


544

• Phase II When both capacitors are discharged, the load current transfers from D1 to D2 and from D3 to D4, which connects the capacitors in parallel with the load via diodes D1 to D2. The plates X and Y now charge negative, ready for the next commutation cycle, as shown in figure 15.26b. Thyristors T1 and T2 are now forward biased and must have attained forward blocking ability before the start of phase 2.

The on-going thyristor automatically commutates the outgoing thyristor. This repeated commutation sequencing is a processed termed auto-sequential thyristor commutation. The load voltage is load dependent and usually has controlled voltage spikes during commutation. Since the GTO and GCT both can be commutated from the gate, the two commutation capacitors C1 and C2 are not necessary. Commutation overlap is still essential. Also, if the thyristors have reverse blocking capability, the four diodes D1 to D4 are not necessary. IGBTs require series blocking diodes, which increases on-state losses. In practice, the current source inverter is only used in very high-power applications (>1MVA), and the ratings of the self-commutating thyristor devices can be greatly extended if the simple external capacitive commutation circuits shown in figure 15.25 are used to reduce thyristor turn-off stresses. 15.2.2 Three-phase current source inverter

A three-phase controlled current-source inverter is shown in figure 15.27a. Only two thyristors can be on at any instant, that is, the 120° thyristor conduction principle shown in figure 15.11 is used. A quasisquare line current results, as illustrated in figure 15.27b. There is a 60° phase displacement between commutation of an upper device followed by commutation of a lower device. An upper device (T1, T3, T5) is turned on to commutate another upper device, and a lower device (T2, T4, T6) commutates another lower device. The three upper capacitors are all involved with each upper device commutation, whilst the same constraint applies to the lower capacitors. Thyristor commutation occurs in two distinct phases.

Figure 15.27. Three-phase controlled-current sourced bridge inverter: (a) bridge circuit with a current source input and (b) load current waveform for one phase showing 120° conduction.

• Phase I In figure 15.28a the capacitors C13, C35, C51 are charged with the shown polarities as a result of the earlier commutation of T5. T1 is commutated by turning on T3. During commutation, the capacitor between the two commutating switches is in parallel with the two remaining capacitors which are effectively connected in series. Capacitor C13 provides displacement current whilst in parallel, C35 and C151 in series also provide thyristor T1 displacement current, thereby reverse biasing T1.

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• Phase II When the capacitors have discharged, T1 becomes forward biased, as shown in figure 15.28b, and must have regained forward blocking capability before the applied positive dv/dt. The capacitor voltages reverse as shown in figure 15.28b and when fully charged, diode D1 ceases to conduct. Independent of this commutation, lower thyristor T2 is commutated by turning on T4, 60° later.

As with the single-phase current sourced inverter, assisted capacitor commutation can greatly improve the capabilities of self-commutating thyristors, such as the GTO thyristor and GCT. The output capacitors stiffen the output ac voltage. A typical application for a three-phase current-sourced inverter would be to feed and control a threephase induction motor. Varying load requirements are met by changing the source current level over a number of cycles by varying the link inductor input voltage. An important advantage of the controlled current source concept, as opposed to the constant voltage link, is good fault tolerance and protection. An output short circuit or simultaneous conduction in an inverter leg is controlled by the current source. Its time constant is usually longer than that of the input converter, hence converter shut-down can be initiated before the link current can rise to a catastrophic level.

+

Io +

-

-

-

C35

C13

D1

+ +

+

+

Io

-

+

C35

C13

-

C51

D1

-

+

D3

-

+ C51

Io

Io Io

Io

Io

(a)

Io

(b)

Figure 15.28. Controlled-current sourced bridge three-phase inverter showing commutation of T1 and T3: (a) capacitors C13 discharging in parallel with C35 and C51 discharging in series, with T1 and D3 reversed biased (b) C13, C35, and C51 charging in series with the load , with T1 forward biased.

PWM techniques are applicable to current source inverters in order to reduce current harmonics, thereby reducing load losses and pulsating motor shaft torques. Since current source inverters are most attractive in very high-power applications, inverter switching is minimised by using optimal pwm. The central 60° portion about the maximums of each phase cannot be modulated, since link current must flow and during such periods both the other phases require the opposite current direction. Attempts to over come such pwm restrictions include using a current sourced inverter with additional parallel current displacement paths as shown in figure 15.29. The auxiliary thyristors, Tupper and Tlower, and capacitors, CR, CY, and CB, provide alternative current paths (extra control states) and temporary energy storage. The auxiliary thyristor can be commutated by the extra capacitors. Characteristics and features of current source inverters • The inverter is simple and can utilise rectifier grade thyristors. The switching devices must have reverse blocking capability and experience high voltages (both forward and reverse) during commutation. • Commutation capability is load current dependent and a minimum load is required. This limits the operating frequency and precludes use in UPS systems. The limited operating frequency can result in torque pulsations. • The inverter can recover from an output short circuit hence the system is rugged and reliable – fault tolerant.


•

• • •

546

The converter-inverter configuration has inherent four quadrant capability without extra power components. Power inversion is achieved by reversing the converter average voltage output with a delay angle of α > ½π, as in the three-phase fully controlled converter shown in figure 12.11 (or 15.4.3). In the event of a power supply failure, mechanical braking is necessary. Dynamic braking is possible with voltage source systems. Current source inverter systems have sluggish performance and stability problems on light loads and at high frequency. On the other hand, voltage source systems have minimal stability problems and can operate open loop. Each machine must have its own controlled rectifier and inverter. The dc link of the voltage source scheme can be used by many inverters or many machines can utilise one inverter. A dc link offers limited ride-through. Current feed inverters tend to be larger in size and weight, because of the link inductor and filtering requirements. T1

T5

T3

T4

T2

T6

Tupper CR CY CB Tlower

(a)

IR

+Io ωt

-Io (b)

Figure 15.29. Three-phase controlled-current sourced bridge inverter with alternative commutation current paths: (a) bridge circuit with a current source input and two extra thyristors and (b) load current waveform for one phase showing 180° conduction involving pwm switching.

15.3

Multi-level voltage-source inverters

The conventional three-phase, six-switch dc to ac voltage-source inverter is shown in figure 15.7. Each of the three inverter legs has an output which can provide one of two voltage levels, Vs, when the upper switch (or diode) is on, and 0 when the lower switch (or diode) conducts. The quality of the output waveform is determined by the resolution and switching frequency of the pwm technique used. A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of the leg can be more than two discrete levels, as shown in figure 15.37 for a diode clamped multilevel inverter model. In this way, the output quality is improved because both pulse width modulation and amplitude modulation can be used. The output pole is made from more than two series connected, clamped switches, so the total dc voltage rail can be the sum of the voltage rating of the individual switches. Very high output voltages can be achieved, where each device does not experience a voltage in excess of its individual rating. A multilevel inverter allows higher output voltages with low distortion (due to the use of both pulse width and amplitude modulation) and reduced output dv/dt. There are three main types of multilevel converters • Diode clamped • Flying capacitor, and • Cascaded H-bridge

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½Vs

½Vs

½Vs Vs /N-1

½Vs a Vs

0 Va0

a

0 ½Vs

Va0

Vs /N-1

Va0

Vs /N-1 -½Vs

-½Vs

-½Vs

a

0

+½Vs +½Vs +½Vs

0V

t

+¼Vs 0V

t

t

-½Vs -½Vs (a)

(b)

-¼Vs (c)

-½Vs

Figure 15.37. One phase leg of a voltage-source bridge inverter with: (a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and waveform for five levels.

15.3.1 Diode clamped multilevel inverter

Figure 15.37 shows the basic principle of the diode clamped (or neutral point clamped, NPC) multilevel inverter, where only one dc supply, Vs, is used and N is the number levels present in the output voltage between the leg output and the inverter negative terminal, Va-neg. The capacitors split the dc rail voltage into a number of lower voltage levels, each of which can be tapped and connected to the leg output through switches (and diodes). Only one string of series connected capacitors is necessary for any number of output phase legs. The number of levels in the line-to-line voltage waveform will be k = 2N −1 (15.75) while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 (15.76) The number of capacitors required, independent of the number of phase, is N cap = N − 1 (15.77) while the number of clamping diodes per phase is Dclamp = 2 ( N − 2 ) but ( N − 1)( N − 2 ) if rated at switch voltage The number of possible switch states is nstates = N phases and the number of switches (and inverse parallel diodes) in each leg is Sn = 2 ( N − 1)

(15.78) (15.79) (15.80)

The basic three-level inverter (±½Vs, 0) is shown in figure 15.38, along with the basic three-level voltage from the leg output to centre tap of the capacitor string, R (neutral point). When switch T1 is on, its complement T1′ is off, and visa versa. Similarly for the pair of switches T2 and T2′. Specifically T1 and T2 on give the output +½Vs, T1′ and T2′ on give the output -½Vs, and T2 and T1′ on give the output 0. Essential to attaining these output levels, are the clamping diodes Du and Dℓ. These two diodes clamp the outer switches to the capacitor string mid-point, which is half the dc rail voltage. In this way, no switch experiences a voltage in excess of half the dc rail voltage. Inner switches must be turned on (or off) before outer switches are turned on (or off). The five-level inverter uses four capacitors, and eight switches in each inverter leg. A set of clamping diodes (three in total for each leg) clamp the complementary switches in each leg. The output is characterised by having five levels, ±½Vs, ±¼ Vs, and zero. Some of the clamping diodes experience voltages in excess of that experienced by the main switches. Series connection of some of the clamping diodes avoids this limitation, but at the expense of increasing the number of clamping diodes from 2× (N-2) to (N-1)×(N-2) per phase. Thus, depending on the diode position in the structure, two diodes have blocking requirements of


548

N −1− k Vs (15.81) N −1 where 1 ≤ k ≤ N-2. These diodes require series connection of diodes, if all devices in the structure are to support Vs /(N-1). For N > 2, capacitor imbalance occurs at high modulation indices. The general output voltage, to the centre of the capacitor string is given by V Van = s (T1 + T2 + .. .. + TN −1 − ½ ( N − 1)) (15.82) N −1 Common to all diode clamped inverter, each phase leg is identical in structure, and all legs share a common dc link capacitor string. Table 15.5 in combination with the six parts of figure 15.39, show the conducting devices for the six different output voltage and current combinations of the NPC inverter leg. The commercial inverter, HVDC Light, uses the NPC structure in figure 15.38, but uses extensive series connection of devices to achieve a high dc link voltage. The main problem in increasing the number of output voltage levels, other than increased circuit complexity, is voltage balancing the dc link series connected capacitors at higher modulation levels, M>½(N-1). This capacitor voltage balancing problem can be avoided when two multilevel inverters are used in an ac-dc-ac back to back converter arrangement, where the link capacitors are common to both converters. VRB =

Cu

½Vs

T1

D1

T2

D2

Dcu

Vs R

C Cℓ?

T1’

½Vs Dcℓ D c?

T2’

D1’

D2’

neg

ia

VaR

ib

ic

b

+½Vs t

o

Vba

0 -½Vs

c

Vao

a

Figure 15.38. Three-phase, voltage-source, three-level, diode-clamped (NPC) bridge inverter.

Table 15.5. Conduction paths in the diode clamped three-level inverter Vout

On switches

Output current and path + iL I - iL

½ Vs

T1 T2

T1 T2

Fig 15.39a

D1 D2

Fig 15.39d

none

0

T1 ′ T2

Dcu T2

Fig 15.39b

T1′ Dcℓ

Fig 15.39e

Dcu Dcℓ

-½ Vs

T1 ′ T2 ′

D1′ D2′

Fig 15.39c

T 1 ′ T2 ′

Fig 15.39f

none

Active clamping diodes

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+½Vs

D1

T2

D2

′ 1

′ 1

D

′

D2

0 T

T2

-½Vs iL > 0

+½Vs

′

T1

vo iL > 0

T2

D2

′ 1

′ 1

D

′

D2

T

T2

-½Vs

vo = ½Vs

iL > 0

(a)

vo iL > 0

D1

T2

D2 vo i >0

D

′

D2

T2

-½Vs

vo = 0

iL > 0

′ L 1

′ 1

T

′

′

vo = -½Vs (c)

+½Vs

′

′

T1

0

(b)

+½Vs

+½Vs

′

′

T1

D1

T1

D1

T1

D1

T2

D2

T2

D2

T2

D2

′ 1

′ 1

D

′ 1

′ 1

D

′ 1

′ 1

D

′

D2

′

D2

′

D2

0 T

T2

-½Vs

D1

0

′

+½Vs

′

T1

iL < 0

vo iL < 0

0 T

′

T2

-½Vs

vo = ½Vs (d)

iL < 0

vo = 0 (e)

vo iL < 0

0 T

′

T2

-½Vs iL < 0

vo iL < 0

′

vo = -½Vs (f)

Figure 15.39. The six output voltage and current combinations for the NPC bridge inverter: (a), (b), (c) output current iL > 0; and (d), (e), (f) output current iL < 0.

15.3.2 Flying capacitor multilevel inverter

One leg of a fly-capacitor clamped five-level voltage source inverter is shown in figure 15.40b, where capacitors are used to clamp the switch voltages to ¼Vs. The available output voltages are ±½Vs, ±¼Vs, and 0, where the output is connected to the dc link (Vs and 0) indirectly via capacitors. Figure 15.40 shows that in general, switches Tn and Tn+1 connect to capacitor Cn. The configuration offers more usable switch states than the clamped diode inverter, and this redundancy allows better, flexible control of capacitor voltages. For example, Table 15.5 shows that there are six states for obtaining 0V output, and four states for each of ±¼Vs. The output states ±½Vs do not involve the capacitors, hence they offer no redundant states. The basic switch restriction is that only one complementary switch (for example, T4 or T4′ ) is on at any time, so as to prevent shorting of a flying capacitor (e.g., T4 and T4′ would short C3). The number of levels in the line-to-line voltage waveform will be k = 2N −1 (15.83) while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 (15.84) The number of capacitors required, which is dependent of the number of phase, is for each phase N cap = ½ ( N − 1)( N − 2 ) (15.85) The number of possible switch states is nstates = N phases

(15.86)


550

and the number of switches in each leg is S n = 2 ( N − 1)

(15.87)

The current output paths in Table 15.6 are made up by the series (and parallel) connection of the flying capacitors through the turn-on of the appropriate switches. Capacitors shown as negative are discharging in the formed path, while those shown as positive are charging. Use of the shown redundant states allows control to maintain the necessary voltage level on all the flying capacitors, while providing the desired output voltages. A feature of the flying capacitor multilevel inverter is its ride through capability due to the large capacitance used. On the other hand, the capacitors have a high voltage rating and suffer from high current ripple, since they conduct the full load current when connected into an active output voltage state. Capacitor initial charging is also problematic, especially given the capacitors for each leg, and between the different legs, are independent.

VC1 T1 D1

Vs

VC1

VCu

T1 D1

Cu C1

VCu

R

T2 D2

VC2

Cℓ C ?

Cu

T2 D2

phase a

T2?D2?

VCℓ

VC?

VC3

T1?D1?

T3 D3

Vs C1 VCℓ V C?

C2

C3

T4 D4

R ¾Vs C Cℓ?

½Vs

¼Vs

phase a

(a)

′ D′4? T4? ′ D′3? T3?

′ D′2? T2?

(b)

′ D′1? T1?

Figure 15.40. One leg of a voltage-source: (a) three-level and (b) five-level, flying capacitor clamped bridge inverter.

If all the flying capacitors are to be voltage rated at the switch voltage level, then C2 comprises two series connect capacitors and C3 comprises three series capacitors, and all the same voltage rating as C1.

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Table 15.6. Five-level flying-capacitor inverter output states (phase A to R) mode

VAR

switching states T2 T3 T4 T1

capacitors C1 C2 C3

1

½Vs

1

1

1

1

=

=

=

½Vs

1

1

1

0

=

=

+

½Vs

-VC3

1

1

0

1

=

+

-

½Vs

-VC2+VC3

1

0

1

1

+

-

=

½Vs-VC1+VC2

0

1

1

1

-

=

=

-½Vs+VC1

1

1

0

0

=

+

=

½Vs

1

0

1

0

+

-

+

½Vs-VC1+VC2 -VC3

0

1

1

0

-

=

+

-½Vs+VC1-VC3

1

0

0

1

+

=

-

½Vs-VC1+-VC3

0

1

0

1

-

+

-

-½Vs+VC1-VC2+VC3

0

0

1

1

=

-

=

-½Vs

1

0

0

0

+

=

=

½Vs-VC1

0

1

0

0

-

+

=

-½Vs+VC1-VC2

0

0

1

0

=

-

+

-½Vs

-VC2 -VC3 +VC3

2 ¼Vs

N-1 states

3 0

2

N -4N+1 states

4 -¼Vs

N-1 states

5

-½Vs

paths

0

0

0

1

=

=

-

-½Vs

0

0

0

0

=

=

=

-½Vs

-VC2

+VC2

15.3.3 Cascaded H-bridge multilevel inverter The N-level cascaded H-bridge, multilevel inverter comprises ½(N-1) series connected single-phase Hbridges per phase, for which each H-bridge has its own isolated dc voltage source. For each bridge, as shown in table 15.7, three output voltages are possible, ±Vs, and zero, giving a total number of states of 3½( N −1) , where N is odd. Figure 15.41 shows one phase of a seven-level cascaded H-bridge inverter. The cascaded H-bridge multilevel inverter is based on multiple two level inverter outputs (each Hbridge), with the output of each phase shifted. Despite four diodes and switches, it achieves the greatest number of output voltage levels for the fewest switches. Its main limitation lies in the need for isolated power sources for each H-bridge and for each phase, although for VA compensation, capacitors replace the dc voltage supplies, and the necessary capacitor energy is only to replace losses due to inverter losses. Its modular structure of identical H-bridges is a positive design feature. The number of levels in the line-to-line voltage waveform will be k = 2N −1 while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 The number of capacitors or isolated supplies required per phase is N cap = ½ ( N − 1) The number of possible switch states is nstates = N phases and the number of switches in each leg is S n = 2 ( N − 1)

(15.89) (15.90) (15.91) (15.92)

Table 15.7. Three output states of H-bridges and their current paths. Bidirectional current paths + iL - iL T2 T3 D2 D3

Vs

On switches T2 T3

0

none

D4 D1

D2 D3

-Vs

T1 T4

T1 T4

D2 D3

Vℓ

(15.88)


Vs

552

D2 T2

T1 D1 V1

Vs

T3 D3

D4 T4

T1 D1

D2 T2 V1

Vs

T3 D3

D4 T4

T1 D1

D2 T2 V1 D4 T4

T3 D3

Figure 15.41. One leg of a voltage-source, seven-level, cascaded H-bridge inverter.

A comparison between the three basic multilevel inverters is possible from the numerical summary of component numbers for each inverter, as in Table 15.8. The diode clamped inverter requires many clamping diodes; the flying capacitor inverter requires many independent capacitors; while the cascaded inverter requires many isolated dc voltage power supplies. Table 15.8. Multilevel inverter component count, per phase. Inverter type

VA-0V

levels VA-B

VA-N

& // diodes

diodes clamping

flying capacitors

Level capacitors

Isolated supplies

switches

diode clamped

N

2N-1

4N-3

2(N-1)

(N-1)(N-2)

0

(N-1)

0

fly capacitor

N

2N-1

4N-3

2(N-1)

0

½(N-1)(N-2)

(N-1)

0

cascade

N

2N-1

4N-3

2(N-1)

0

0

½ (N-1)*

½(N-1)*

* either /or

15.3.4 PWM for multilevel inverters Two basic approaches can be used to generate the necessary pwm signals for multilevel inverters. Each approach is based on the extension of a two level equivalent. • Modulating waveform comparison with offset triangular carriers • Space vector modulation based on a rotating vector in multilevel space

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1.5

½Vs

1

¼Vs

0.5

0

Voltage(pu)

π 0 0

π

-¼Vs

-0.5

-½Vs

-1

0

1 -1.5

0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

½

1.5

1

0

Voltage(pu)

0.5

0

0 0

π -0.5

-½

π -1

-1 -1.5

0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

1.5

1

0 0.5

Voltage(pu)

0 0

0 -0.5

0 -1

-1.5

0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

Figure 15.42. Multi-carrier based pwm generation for a voltage-source, 5-level, inverter.

15.3.4i - Multiple offset triangular carriers

Various sinusoidal pwm techniques were considered in sections 15.1.3v and 15.1.3vi of this chapter. Figure 15.42 shows how a triangular carrier is associate with each complementary switch pair, four carriers (N-1) for the five-level inverter as illustrated. The parts of figure 15.42 show how the four individual carriers can be displaced with respect to one another. The figure also shows how triplen injection is incorporated. The appropriate five-level switch states, as in tables 15.4 to 15.6, can be used to decode the necessary switching sequences. To minimise losses, switching is restricted to only occur between adjacent levels. 15.3.4ii - Multilevel rotating voltage space vector

Space vector modulation for the two-level inverter was considered in section 15.1.3vi of this chapter. The basic hexagon shape for two levels is extended to higher levels as shown in figure 15.43, for three levels. The number of triangles, vectors, and states increases rapidly as the level number increases. Table 15.9. Properties of N-level vector spaces levels

states

triangles

vectors

N

N3

6(N-1)2

3N(N-1)+1

vectors in each hexagon

2

8

6

7

(1+6)

3

27

24

19

(1+6)+12

5

125

96

61

(1+6)+12+18+24


554

From table 15.9, the states for the two and three level inverters can be specified as follows.

The 2-level inverter The zero state matrix is [000 111] The first and only hexagon is shown in figure 15.22a. [100 110 010 011 001 101] The three level inverter The zero state matrix is [000 111 222] The first hexagon matrix is 100 110 010 011 001 101   211 221 121 122 112 212    The second hexagon matrix is [ 200 210 220 120 020 021 022 012 002 102 202 201] These pole states are shown figure 15.43. 120

020 010 121

021

110 221 000 111 222

011 122

022

001 112

012

002

220

210 100 211

101 212 102

200

201

202

Figure 15.43. Rotating voltage space vector approached applied to three phases of a voltage-source three-level, inverter.

A 0  represents the minimum voltage obtainable from the multilevel converter and N-1 represents the maximum value. For example, in a two-level converter, 0  is equivalent to 0V and 1  is equivalent to Vs, where Vs is the converter DC link voltage. In a three-level converter 0  is equivalent to -½Vs, 1  is equivalent to 0 V, and ‘2’ is equivalent to ½Vs where Vs is the dc link voltage of the multilevel converter. When the rotating vector is drawn in the vector space, it is decomposed into vectors bordering the triangle it lies in. When operating in the outer hexagon, the vectors states used in the inner most hexagon mean that that level of the converter is operating with a six-step quasi-square output voltage waveform, to which is added a modulated square waveform for the next higher level. 15.4

Reversible dc link converters

Power inversion by phase angle control is attained with a fully controlled single-phase converter as discussed in section 12.2.3. Power regeneration is also possible with the fully controlled three-phase converter shown in figure 12.11. If a fully controlled converter supplies a dc machine, two-quadrant control is possible (QI and QIV), motoring in one direction of rotation and generating in the other direction. Power regeneration into the supply is achieved by reversing the dc output voltage by controlling the converter phase delay angle. The converter current is uni-directional, that is, the converter output current can not reverse. The dual or double converter circuit in figure 15.44a and b will accommodate four-quadrant dc machine operation, where the circuit performs as two fully controlled converters in anti-parallel. Each converter is able to rectify and invert, but because of their inverse parallel connection, one converter (the positive converter P) operates in quadrants QI and QIV, while the other (the negative converter N) operates in quadrants QII and QIII, as shown in figure 15.45. The two converters can be operated synchronously, called simultaneous control or independently where one is always blocking, called independent control.

Power Electronics

555

α1

L

α2

P

(a )

N d c lin k

α1

L

α2 (b )

P

N

α1

α2

(c )

P

N (d ) d c lin k

in p u t L -C filte r

o u tp u t filte r re ctifier/ co n ve rter

3Φ in p u t

in verte r

3Φ o u tp u t

½L

Figure 15.44. Reversible converter allowing four-quadrant control of: (a) a dc machine with independent converters; (b) a dc machine with simultaneously controlled converters; and (c) voltage and (d) current fed induction machine.

15.4.1 Independent control Simultaneous converter control can be used if continuous load current can be guaranteed. Otherwise only one converter, depending on the quadrant, need operate at anyone time (the other is in a blocking state), as shown in figure 15.44a. No circulating currents arise due to possible mismatched N and P converter output voltages. The continuous current condition may be difficult to ensure at light load levels. Additional series armature inductance, L in figure 15.44a and b, helps with current smoothing and ensuring continuous machine current.


556

A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I, with 0° ≤ α1 ≤ 90° for the positive converter P. The negative converter, N, is in the fully blocking state, with all thyristors turned off. • The positive converter is put into the inverting mode with 90° ≤ α1 ≤ 180°, changing the average output voltage from positive to negative. The machine current rapidly falls to zero. The machine rotational speed slows, the rate depending on the load inertia. • After a dead time, the positive converter blocks and the negative converter N starts in a motor braking mode in quadrant II. The motor speed falls rapidly to zero. • The second converter operates in quadrant III and rapidly accelerates the motor in the opposite direction, with 0° ≤ α2 ≤ 90°. The dead time before turning on the negative converter N is to ensure the positive converter P is fully off, otherwise the three-phase input voltage lines may short through the two converters. Such a current condition cannot be controlled with line-commutated thyristors. Operation is characterised by transitions from QI to QII to QIII for reversal, and transitions from QIII to QIV to QI for returning to the original direction of rotation. sp eed vo

Ia

Ia +

N

P

E

α1

+ E

vo

vo

α2

N

rege nera tive brak in g /in vers io n

II

I

m o to r/rectification

to rq u e

m o to r/rectification

III

IV

rege nera tive brak in g /in versio n

Ia

Ia

P

E

vo

+

α2

Ia

α1

E

vo

+

Figure 15.45. Four quadrants of reversible converter operation.

15.4.2 Simultaneous control Simultaneous converter control, also called circulating current control, functions with both converters always in operation which gives a faster dynamic response than when the converters are used mutually exclusively. To avoid supply short circuits requires that the output voltage of both converters (rectifier Vr and inverter Vi) be the same in order to minimise circulating currents. Vr + Vi = 0 V cos α1 + V cos α 2 = 0 (15.93) cos α1 + cos α 2 = 0 that is α1 + α 2 = 180°

Equation (15.93) implies that both converters operate with firing angles that sum to 180°. Each converter produces the opposite polarity output voltage, which is cancelled by reversing the relative output connections. Under such conditions the load current can be maintained continuous. To minimize any circulating current due to ripple voltage produced by instantaneous voltage differences between the two converters, inductance is usually inserted between each converter and the dc machine load, as shown in figure 15.44b. Adversely the cost and weight are increased, and the supply power factor and drive efficiency are decreased, compared to that obtained with independently controlled converters.

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A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I for the rectifying, positive converter, with 0° ≤ α1 ≤ 90°. The other converter is operating in the inverting mode with 90° ≤ α2 ≤ 180°, such that α1 + α2 = 180°. The output voltage for both converters is the same, and the negative converter N carries only the circulating current. • For rotational direction reversal, α1 ≥ 90° and α2 ≤ 90°, such that α1 + α2 = 180°. The armature back emf voltage now exceeds the converter output voltages, and current diverts to the negative converter N and the machine regeneratively brakes, operating in quadrant II. The current rapidly falls to zero and the positive converter P carries only the ac circulating current. • The speed rapidly falls to zero, with α1 = α2 = 90° giving zero output voltage, so as to control the armature current since the back emf is zero. Then with α2 < 90° the machine rapidly accelerates in quadrant III, in the reverse direction to the original rotation. For reversing the direction of rotation from Q III the operation sequence is QIII to QIV to QI. Since no converter dead time is introduced, a fast dynamic response can be attained. A small dc circulating current is deliberately maintained, that is greater in magnitude than the peak of the ac ripple current. The ac current can then flow continuously in both converters, both of which can operate in the continuous conduction mode without the need for continuous converter current reversal operation.

15.4.3 Inverter regeneration The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link voltage from reversing. The dual or double converter circuit in figure 15.44c will allow inversion with a three-phase voltage source inverter. One converter rectifies, the other converter inverts, functioning as a selfcommutated inverter, transferring power from the dc link to the ac supply. Complete four-quadrant control of the three-phase ac machine on the inverter is achieved in conjunction with control of the dc to ac inverter. That is, motor reversal is achieved by effectively interchanging the pwm control signals associated with two phases. The real power flow back into the ac supply is controlled by the converter phase delay angle, while the reactive power flow is controlled by the voltage magnitude. The angle and voltage are not independent. In the case of a pwm controlled inverter fed ac machine, the ac to dc converter can be uncontrolled, using all diodes, since dc output voltage reversal is not utilised. Figure 15.44d shows a fully reversible current controlled converter/inverter configuration, using selfcommutating devices. The use of self-commutated switches (rather than mains commutated converter thyristors) offers the possibility to minimise the input current distortion and to reduce the inductor size hence improve the dynamic current response. The switch series diodes are essential since the shown IGBTs have no useable reverse blocking capability. The use of reverse blocking GCTs avoids the need for the series blocking diodes, which reduces the on-state voltage losses but increases gate drive complexity and power rating. Series connection of devices is necessary above a few kV, and above 1 MVA the GCT dominates. 15.5

Standby inverters and uninterruptible power supplies

Standby inverters and uninterruptible power supplies (UPS’s) provide a 50/60 Hz supply in the event of an ac mains failure. A UPS must provide ac output such that mains failure is undetected by the load. To achieve this, a UPS continually feeds the load from an inverter. A load that can tolerate a short interruption of the ac supply is fed from a standby inverter which becomes operational within 1-5 ms after the ac supply failure. In communications, computing, and automated production lines, UPS’s are essential for even brownouts (V and f outwith bounds for reliable equipment operation), while in lighting and heating applications, standby inverters are used since a few missing ac cycles (due to a blackout – total interruption of the mains power) may be tolerated. In each power supply case, the alternative energy source is a standby dc battery. The UPS keeps the battery charged when the ac input is supplying the output power.

15.5.1 Single-phase UPS A basic single-phase UPS is shown in figure 15.46. A key safety objective is to retain the supply neutral at both the supply input and the ac output, without resorting to any from of isolating transformer. Consequently, the input ac mains is half-wave rectified by diodes DR+ and DR− . Boost converters on the positive and negative groups ensure supply sinusoidal input current and unity power factor. The output


558

H-bridge (T1-T4) uses pwm and feedback control to produce a fixed frequency and magnitude output (and ac mains phase synchronisation if required), which is filtered by an L-C filter. In the event of a loss of the ac supply, the backup batteries, V+ and V -, provide energy to the boost converters, hence to the output inverter. The battery backup voltage magnitude is much less than the ac supply magnitude and diodes, DB+ and DB− , isolate the batteries from the rectified ac supply voltage. The shown UPS has two basic limitations that manufactures strive to overt. • •

If the battery is to be connected to neutral, then two batteries are necessary. Proprietary attempts using only one battery involve circuit complications and limitations. At best, with one battery, it is one forward biased diode voltage drop from neutral. Because the batteries supplies are not isolated during normal operation, during part of the mains cycle near zero voltage, the batteries alternately provide energy. This decreases their lifetime and necessitates more complicated trickle charge circuits. The input current is also distorted at the 0V crossover. Replacement of the blocking diodes DB by switches involves complexity and battery backup operation requires detection and is not fail safe. ½ wave rectifier

+

DR ac

+

boost converter

+

L

H-bridge inverter

+

T3

D

DB V

+

L-C filter

+

T

+

C

+

-

T1

D1

D3

Lo Co

N

N V

-

T

-

C

+

DB DR

T4

D4

D2

L

D

-

Figure 15.46. Single-phase uninterruptible power supply.

DB

Figure 15.47. Three-phase uninterruptible power supply.

T2

o/p

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15.5.2 Three-phase UPS Figure 15.47 shows a basic three-phase UPS, used up to a few tens of kilowatts. The ac supply is rectified and filtered. A forward converter controls the dc link voltage to just above the battery voltage level. This dc voltage is boosted to a dc level such that after inversion it provides the required output voltage magnitude. If the input ac fails or droops, the dc link power is provided by the battery via diode DB. The output inverter is usually operational in a pwm mode, which allows precise frequency control, voltage control, ac mains phase synchronisation, and minimisation of low frequency output harmonics. With pwm control minimal filtering is required, which minimises the filter weight, cost, size, and losses. A three-phase UPS can utilise third harmonic injection (15.1.4(iv)). A three-phase boost input converter can be used to maintain sinusoidal ac supply input currents at unity power factor. 15.6

Power filters

Power L-C filters are used to reduce harmonics or ripple from • the rectifier output (dc filter) • the inverter output (ac filter). L-C low-pass, second-order filters are shown in figures 15.44, 15.46, and 15.47. In figure 15.47, the L-C smoothing filter at the rectifier output, filters the ac mains frequency components leaving dc. The same type of filter is used in the inverter output to filter pwm harmonics, leaving the relative low frequency modulation frequency. The L-C filter fundamental cut-off frequency is dependent on L, C, and the load impedance ZL vo 1 1 = = (15.94) vi 1 + jω L ( Z1L + jωC ) 1 − ω 2 LC + j ωZ LL

The simplest design approach is to assume a non-load condition, ZL → ∞, whence the filter cut-off frequency is f o = 1/ 2π LC . Frequency components below fo, including dc, are passed. Those components above fo are attenuated by a second order fall-off in gain. Any frequency components inadvertently around the resonant frequency, fo, will be amplified. For this reason, the filter may be damped with parallel connected R-C snubbers.

(

)

Reading list

See chapter 11 reading list. Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1994. Mohan, N., Power Electronics, 3rd Edition, Wiley International, 2003.


560

Problems

15.1.

The inverter in figure 15.7 is supplied from a 340 V dc source. The load has a resistance of 10 Ω and an inductance of 10 mH. The basic operating frequency is 50 Hz, with three notches per half cycle giving half the maximum output, similar to that shown in figure 15.13. Determine the load current waveform over the first two cycles and determine the power delivered to the load based on the current waveform of the final half cycle.

15.2.

The inverter and load in problem 15.1 are controlled so as to eliminate the third and fifth harmonics in the output voltage. Determine the load current waveform over the first two cycles and the power delivered to the load based on the current waveform of the last half cycle.

15.3.

Output voltage harmonic reduction can be achieved by employing multiphase, selected notching modulation control on a three-phase bridge as discussed in 15.1.4. An output as in figure 15.14b with α1 = 16.3° and β1 = 22.1° eliminates the 5th and 7th harmonics. Determine the fundamental voltage output component and compare it with that of a square wave. Determine the output rms voltage.

15.4.

With the aid of figure 15.11 determine the line-to-neutral and line-to-line output voltage of a dc to three-phase inverter employing 120° device conduction. Calculate the interphase: i. mean half-cycle voltage ii. rms voltage iii. rms voltage of the fundamental.

15.5.

The three-phase inverter bridge in figure 15.4 has a 600 V dc rail and a 10 Ω per phase load. For 180° and 120° conduction calculate: i. the rms phase current ii. the power delivered to the load iii. the switch rms current. [24.5 A, 18 kW, 17.3 A; 28.3 A, 24 kW, 14.15 A]

15.6

A single-phase square-wave inverter is supplied from a 340V dc source and the load is a 17 Ω resistor. Determine switch average and rms current ratings. What power is delivered to the load?

15.7

A single-phase square-wave inverter is supplied from a 340V dc source and the series R-L load is a 20 Ω resistor and L=20mH. Determine: i. an expression for the load current, hence the maximum switch current ii. rms load current iii. average and rms switch current iv. maximum switch voltage v. average source current, hence power delivered to the load vi. load current total harmonic distortion.

16 DC to AC Inverters – Resonant Mode Inversion (in this chapter) is the conversion of dc power to ac power at a desired output voltage or current and frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation. The terms voltage-source and current-source are used in connection with the output from inverter circuits. A voltage-source inverter (VSI) is one in which the dc input voltage is essentially constant and independent of the load current drawn. The inverter specifies the load voltage while the drawn current shape, near sinusoidal, is dictated by the series resonant load, in this case. A current-source inverter (CSI) is one in which the source, hence the load current is predetermined and the load impedance, a parallel resonant circuit in this case, determines the, near sinusoidal output voltage. The supply current cannot change quickly. This current is controlled by series dc supply inductance which prevents sudden changes in current. Being a current source, the inverter can survive an output short circuit thereby offering fault ride-through properties. Inverter switching losses (either turn-on or turn-off) can be significantly reduced if zero current or voltage switching can be utilised. This switching loss reduction allows higher operating frequencies hence smaller L and C components (in size, weight, and value). Also radiated switching noise is significantly reduced. Two main techniques can be used to achieve near zero switching losses a resonant load that provides natural voltage or current zero instances for switching a resonant circuit across the switch which feeds energy to the load as well as introducing zero current or voltage instances for switching. The inverter and its output are single-phase and the output is controlled around the load resonant frequency. Zero current, ZCS, and zero voltage, ZVS, switching occurs when the inverter switches are operated either side of resonance. 16.1

Resonant dc-ac inverters

The voltage source inverters considered in 15.1 involve inductive loads and the use of switches that are hard switched. That is, the switches experience simultaneous maximum voltage and current during turn-on and turn-off with an inductive load. The current source inverters considered in 15.2 required capacitive circuits to commutate the bridge switches. When self-commutatable devices are used in current source inverters, hard switching occurs. In resonant inverters, the load enables commutation of the bridge switches with near zero voltage or current switch conditions, resulting in low switching losses. A characteristic of L-C-R resonant circuits is that at regular, definable instants for a step load voltage, the series L-C-R load current sinusoidally reverses or for a step load current, the parallel L-C-R load voltage sinusoidally reverses. If the load can be resonated, as considered in chapter 6.2.3, then switching stresses can be significantly reduced for a given power through put, provided switching is synchronised to the V or I zero crossing. Three types of resonant converters utilise zero voltage or zero current switching. load-resonant converters resonant-switch dc-to-dc converters resonant dc link and forced commutated converters

BWW


562

The single-phase load-resonant converter, which is extensively used in induction heating applications, is presented and analysed in this chapter. Such resonant load converters use an L-C load which oscillates, thereby providing load zero current or voltage intervals at which the converter switches can be commutated with minimal electrical stress. Resonant switch dc-to-dc converters are presented in chapter 18. Two basic resonant-load single-phase inverters are used, depending on the L-C load arrangement: current source inverter with a parallel L-C resonant (tank) load circuit: switch turn-off at zero load voltage instants and turn-on with zero voltage switch overlap is essential (a continuous source current path is required) voltage source inverter with a series connected L-C resonant load: switch turn-off at zero load current instants and turn-on with zero current switch under lap is essential (to avoid dc voltage source short circuiting) Each load circuit type can be fed from a single leg (or arm) circuit or H-bridge circuit depending on the load Q factor. This classification is divided according to symmetrical full bridge for low Q load circuits (class D) single bridge leg circuit for a high Q load circuit (class E) High Q circuits can also use a full bridge inverter configuration, if desired, for higher through-put power. In induction heating applications, the resistive part of the resonant load, called the work-piece, is the active load to be heated - melted, where the heating load is usually transformer coupled. Energy transfer control complication is usually associated with the fact that the resistance of the load work-piece changes as it heats up and melts, since resistivity is temperature dependant. However, control is essentially independent of the voltage and current levels and is related to the resonant frequency which is L and C dependant. Inverter bridge operation is near the load resonant frequency so that the output waveform is essentially sinusoidal. By ensuring operation is below the resonant frequency, such that the load is capacitive, the resultant leading current can be used to self commutate thyristor converters which may be used in high power series resonant circuits. This same capacitive load commutation effect is obtained for parallel resonant circuits with thyristor current source inverters operating just above resonance. The output power is controlled by controlling the converter output frequency, with maximum power being transferred at the resonant frequency.

16.2

L-C resonant circuits

L-C-R resonant circuits, whether parallel or series connected are characterised by the load impedance being capacitive at low frequency and inductive at high frequency for the series circuit, and vice versa for the parallel case. The transition frequency between being capacitive and inductive is the resonant frequency, ωo, at which frequency the L-C-R load circuit appears purely resistive and maximum power is transferred to the load, R. L-C-R circuits are classified according to circuit quality factor Q, resonant frequency, ωo, and bandwidth, BW, for both parallel and series circuits. The characteristics for the parallel and series resonant circuits are related since every practical series L-C-R circuit has a parallel equivalent, and vice versa. The parallel circuit can be series R-L in parallel with the capacitor C. As shown in figure 16.1 each resonant half cycle is characterised by the series resonant circuit current is zero at maximum capacitor stored energy the parallel resonant circuit voltage is zero at maximum inductor stored energy The capacitor in a series resonant circuit must have an external path through which to release its stored energy. The parallel resonant circuit can release its stored inductive energy within its parallel circuit, without an external circuit. The stored energy can internally resonate, transferring energy back and forth between the L and C, gradually dissipating energy in the circuit R, as heat. 16.2.1 - Series resonant L-C-R circuit The series L-C-R circuit current for a step input voltage Vs, with initial capacitor voltage vo and series inductor current io is given by V −v ω (16.1) i (ωt ) = s o × e −α t × sin ωt + io × e −α t × o × cos (ωt + φ ) ω ωL where 1 R 1 R tan φ = α ω 2 = ωo2 (1 − ξ 2 ) = ωo2 − α 2 ωo = α= =ξ = and ω 2L 2Qs 2ωo L LC ξ is the damping factor. The capacitor voltage is important because it specifies the energy retained in the L-C-R circuit at the end of each half cycle. ω i vc (ωt ) = Vs − (Vs − vo ) o e −αt cos (ωt − φ ) + o e −α t sin ω t (16.2) ω ωC

Power Electronics

563

−j

ωC

jωL

i Vs

Is

jωL

Is

R

high Q

high Q low Q

low Q

Vs

Is vcapacitor

iseries

iinductor

vparallel

ωt

ideal commutation

instants

instants

|Z(ω)| R

Qs

decreasing

0

→

BWs

√2

∞

+90°

θZ(ω)

ωt

ideal commutation

∞

|Z(ω)| R

1

v

R

−j ωC

Z capacitive

θZ(ω) 0

ωo

ωu

Qp

1 √2 +90°

decreasing

→

BWp

0

Z inductive

ωℓ

1

ω=2πf

Z inductive

ωℓ

ωu ωo

ω=2πf Z capacitive

-90°

-90° (a)

(b)

Figure 16.1. Resonant circuits, step response, and frequency characteristics: (a) series L-C-R circuit and (b) parallel L-C-R circuit.

At the series circuit resonance frequency ωo, the lowest possible circuit impedance results, Z = R as shown in figure 16.1a, hence it can be termed, low-impedance resonance. The series circuit quality factor or figure of merit, Qs, is defined by reactive power 2π × maximum stored energy Qs = = average power energy dissipated per cycle (16.3) 2 ωo L 1 Z o 2π ½ Li = = = = R R ½ Ri 2 / f o 2ξ where the characteristic impedance is L (Ω) Zo = C The series circuit half-power bandwidth BWs is given by ω 2π f o BWs = o = Qs Qs and upper and lower half-power frequencies are related by ωo = ωA ωu .

(16.4)


564

ωAu = ωo ± α (16.5) R 4π L Figure 16.1a shows the time-domain step-response of the series L-C-R circuit for a high Q load and a lower Q case. In the lower Q case, to maintain and transfer sufficient energy to the load R, the circuit requires re-enforcement every half sine cycle, while with a high circuit Q, re-enforcement is only necessary once per sinusoidal cycle. Thus for a high circuit Q, full bridge excitation is not essential, yielding a simpler power circuit as shown in figure 16.2a and b. f Au = f o ±

The energy transferred to the load resistance R, per half cycle 1/2fr, is W½ =

π

∫ i (ω t ) R d ω t 2

(16.6)

0

The active power transferred to the load depends on the repetition rate of the excitation, fr. P = W½ × f r (W)

(16.7)

Table 16.4 Characteristics and parameters of parallel and series resonant circuits characteristic

series

Resonant period/time constant

s

Resonant angular frequency

rad/s

Damping factor

pu

Damping constant

/s

Characteristic impedance

Ω

τ = LC ωo = 2π f o = ξs = ½

Quality factor 1 Qs =

Bandwidth

τ

=

pu

=

1

=

LC

(½RI ) τ 2

p

ωo Qs

1 2CR

L 1 = ωo L = C ωo C

L ωL C = o R R 2 2π (½LI p )

BW s =

ωo L 1 =½ R ωo C R

αp =

ω = ωo 1 − ξ p2 Qp =

Z 1 = o = 2ξs R

ωo CR

1

ξp = ½

ω = ωo 1 − ξs2

Qs =

rad/s

1

R 2L Zo =

rad/s

Qp

R = ½ ωo C R ωo L

αs =

Damped resonant angular frequency

ω = ωo 1 − ξ 2 = ωo2 − α 2

parallel

R 1 R = = = ωo CR L 2ξ p Z o C

=

2π (½CV p2 ) R = ωo L  V p2   ½  τ  R 

BW p =

ωo Qp

16.2.2 - Parallel resonant L-C-R circuit The load for the parallel case is a parallel L-C circuit, where the active load is represented by series resistance in the inductive path. For analysis, the series L-R circuit is converted into its parallel R-L equivalent circuit, thus forming the equivalent parallel L-C-R circuit shown in figure 16.1b. A parallel resonant circuit is used in conjunction with a current source inverter, thus the parallel circuit is excited with a step input current. The voltage across a parallel L-C-R circuit for a step input current Is, with initial capacitor voltage vo and initial inductor current io is given by I −i ω (16.8) v (ωt ) = vc (ωt ) = s o × e −α t × sin ωt + vco × e −αt × ωo × cos (ωt + φ ) ωC The inductor current is important since it specifies the tank circuit stored energy at the end of each half cycle.

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565

iL (ωt ) = I s − ( I s − io ) ×

ωo − α t v × e × cos (ωt − φ ) + o × e −α t × sin ωt ω ωL

(16.9)

where 1 2CR The parallel circuit Q for a parallel resonant circuit is R R 1 Qp = ωo RC = = = (16.10) ωo L Z o Qs where Zo and ωo are defined as in equations (16.1) and (16.3), except L, C, and R refer to the parallel circuit values. The half-power bandwidth BWp is given by ω 2π f o (16.11) BWp = o = Qp Qp

α=

and upper and lower half power frequencies are related by ωo = ωAωu . At the parallel circuit resonance frequency ωo, the highest possible circuit impedance results, Z = R as shown in figure 16.1b, hence it can be termed, high-impedance resonance. The energy transferred to the load resistance R, per half cycle 1/2fr, is π

W½ = ∫ v (ωt ) / R d ωt 2

(16.12)

0

The active power to the load depends on the repetition rate of the excitation, fr. P = W½ × f r (W)

(16.13)

T3 D3 T1 D1

Vs

T1 D1

C

L

C R

R

T4 D4

T2 D2

T4D4

VSI

(a)

(b)

CSI

I constant

I constant L large

L large C

Vs

L

L

R

T1 D1

C

Vs

T3 D3

L

T3 D3

T1 D1

(c)

T4 D4

R

T2 D2

(d)

Figure 16.2. Resonant converter circuits: (a) series L-C-R with a high Q; (b) low Q series L-C-R; (c) parallel L-C-R and high Q; and (d) low Q parallel L-C-R circuit.

16.3

Series-resonant voltage-source inverters

Series resonant circuits use a voltage source inverter (class D series) as considered in 16.1.1 and shown in figure 16.2a and b. If the load Q is high, then the resonance of energy from the energy source,


566

Vs, need only be re-enforced every second half-cycle, thereby simplifying converter and control requirements. A high Q circuit is characterised by successive half-cycle capacitor voltage peak magnitudes being of similar magnitude, that is the decay rate is π vc = e 2 Q ≈ 1 for Q 1 (16.14) vc n

n +1

Thus there is sufficient energy stored in C to be transferred to the load R, without need to involve the supply Vs. The circuit in figure 16.2a is simpler and control is easier. Also, for any Q, each converter can be used with or without the shown freewheel diodes. Without freewheel diodes, the switches have to block high reverse voltages due to the energy stored by the capacitor. MOSFET and IGBTs require series diodes to achieve the reverse voltage blocking requirements. In high power resonant applications, the reverse blocking abilities of the GTO and GCT make them ideal converter switches. Better load resonant control is obtained if freewheel diodes are not used. asymmetrical bridge conducting devices T1

D4

T4

D1

T1

D4

symmetrical H-bridge conducting devices T1 T2

D3 D4

T3 T4

D1 D2

T1 T2

D3 D4

φ lagging IT1

H-bridge output voltage

IT1 t

0 IT4

Zero for half bridge

φ lagging IT1

switch T1/T2 hard turn-off

IT1 t

0

Vref

Vref

Vref IT4

switch T4/T3 hard turn-off t

0

Figure 16.3. Series L-C-R high Q resonance using the converter circuit in figure 16.2a and b, with a lagging power factor φ.

16.3.1 – Series-resonant voltage-source inverter – single inverter leg Operation of the series load single leg circuit in figure 16.2a depends on the timing of the switches. 1 - Lagging operation (advancing the switch turn-off angle, f > fo) If the converter is operated at a frequency above resonance (effected by commutating the switches before the end of an oscillation cycle), the inductor reactance dominates and the load appears inductive. The load current lags the voltage as shown in figure 16.3. This figure shows the conducting devices and

Power Electronics

567

that a switch is turned on when its parallel connected diode is conducting. Turn-on therefore occurs at a low voltage (hence low switch turn-on loss and no need for fast recovery diodes), while turn-off (premature) is as with a hard switched inductive load (associated with switch high turn-off loss and turnoff Miller capacitance effects). Operation and switch timing are as follows: Switch T1 is turned on while its anti-parallel diode D1 is conducting and the current in the diode reaches zero and the current transfers to, and begins to oscillate through the switch T1. The capacitor charges to a maximum voltage and before the current reverses, the switch T1 is hard turned off. The current is diverted through diode D4. T4 is turned on which allows the oscillation to reverse. Before the current in T4 reaches zero, it is turned off and current is diverted to diode D1, which returns energy to the supply. The resonant cycle is repeated when T1 is turned on before the current in diode D1 reaches zero and the process continues. 2 - Leading operation (delaying the switch turn-on angle, f < fo) By operating the converter at a frequency below resonance (effectively by delaying switch turn-on until after the end of an oscillation cycle), the capacitor reactance dominates and the load appears capacitive. The load current leads the voltage as shown in figure 16.4. This figure shows the conducting devices and that a switch is turned off when its parallel diode is conducting. Turn-off therefore occurs at a low current, while turn-on is as with a hard switched inductive load. Fast recovery diodes are therefore essential. Switch output capacitance charging and discharge (½CV2) and the Miller effect at turn-on (requiring increased gate power) are factors to be accounted for. Operation and switch timing are as follows: Diode D4 is conducting when switch T1 is turned on, which provides a step input voltage Vs to the series L-C-R load circuit, and the current continues to oscillate. The capacitor charges to a maximum voltage and the current reverses through D1, feeding energy back into the supply. T1 is then turned off with zero current. The switch T4 is turned on, commutating D1, and the current oscillates through the zero volt loop created through T4 and the load. The oscillation current reverses through diode D4, when T4 is turned off with zero current. T1 is turned on and the process continues. Without the freewheel diodes the half oscillation cycles are controlled completely by the switches. On the other hand, with freewheel diodes, the timing of switch turn-on and turn-off is determined by the load current zeros, if maximum energy transfer to the load is to be gained. Analysis – single inverter leg – figure 16.2a For a square wave input voltage, 0 to Vs, of frequency ω ≈ ωo , the input voltage fundament of magnitude 2 Vs / π produces the dominant load current component, since higher frequency components are attenuated by second order L-C filtering action. That is, the resonant circuit excitation voltage is V i = 2Vs π . The series circuit steady-state current at resonance for the single-leg half-bridge can be approximated by assuming ωo≈ω, such that in equation (16.1) io = 0: V 1 i (ωt ) = 0 ≤ ωt ≤ π × s × e −αt × sin ωt (16.15) −απ ωL 1− e ω which is valid for the + Vs loop (through T1) and zero voltage loop (through T4) modes of cycle operation at resonance, provided the time reference is moved to the beginning of each half-cycle. In steady-state the successive capacitor voltage absolute maxima are ∧ ∨ 1 e −απ / ω and = − Vc = Vs V V c s 1 − e −απ / ω 1 − e −απ / ω

(16.16)

The peak-to-peak capacitor voltage is therefore 1 + e−απ / ω 2ω Vc = × Vs = Vs × coth (απ / 2ω ) ≈ × Vs −απ / ω 1− e απ p− p

(16.17)

The energy transferred to the load R, per half sine cycle (per current pulse) is 2

W=

∫

π /ω 0

i Rdt = 2

(

∫

π /ω 0

= ½CVs2 coth απ

 1  V  × s × e −αt × sin ωt  R dt −απ ωL    1− e ω 

2ω

)

(16.18)


568

asymmetrical bridge conducting devices T1

D1

T4

D4

T1

D1

T1 T2

D1 D2

symmetrical H-bridge conducting devices T1 T2

D1 D2

T3 T4

D3 D4

φ leading IT1

H-bridge output voltage

IT1 t

0 Zero for half bridge

IT4

φ leading IT1

switch T1/T2 hard turn-on

IT1 t

0

Vref

switch T4/T3 hard turn-on

Vref

Vref

IT4 t

0

Figure 16.4. Series L-C-R high Q resonance using the converter circuit in figure 16.2a and b, with a leading power factor φ.

The input impedance of the series circuit is   ω ωo   1   Z s = Ze j ϕ = R + j  ωL − = R  1 + jQ s  −    ωC  ω     ωo 

(16.19)   ω ωo   − where ϕ = tan Q s   ω     ωo The frequency ratio terms in the equation for the input phase angle φ show that the resonant circuit is inductive (φ > 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL. If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by varying inversely the frequency with output voltage. Alternatively, output voltage feedback can be used. 17.1.4i - fixed on-time tT, variable switching frequency fvar The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 (17.27) ½ ∆iL Ei tT = o R f var Isolating the variable switching frequency fvar gives vo2 1 f var = ½ ∆iL Ei tT R 1 f var = fs Rcrit × R (17.28) 1 f var α R

Switched Mode DC to DC Converters

582

That is, once discontinuous inductor current occurs, if the switching frequency is varied inversely with load resistance and the switch on-state period is maintained constant, output voltage regulation can be maintained. Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R substitution for R in equation (17.28) gives R f var = f s crit × Io vo (17.29)

α Io That is, for I o < ½∆iL or Io < vo / Rcrit , if tT remains constant and fvar is varied proportionally with load current, then the required output voltage vo will be maintained. f var

17.1.4ii - fixed switching frequency fs, variable on-time tTvar

The operating frequency fs remains fixed while the switch-on time tTvar is reduced, resulting in the ripple current being reduced. Operation is specified by equating the input energy and the output energy as in equation (17.27), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 (17.30) ½ ∆iL Ei tT var = o R fs Isolating the variable on-time tTvar yields vo2 1 tT var = ½ ∆iL Ei f s R Substituting ∆iL from equation (17.2) gives 1 tT var = tT Rcrit × R (17.31) 1 tT var α R That is, once discontinuous inductor current commences, if the switch on-time is varied inversely to the square root of the load resistance, maintaining the switching frequency constant, regulation of the output voltage can be maintained. Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.31) gives .

.

tT var = tT

Rcrit × vo

α

tT var

.

.

Io

(17.32)

Io

That is, if fs is fixed and tT is reduced proportionally to required output voltage magnitude vo will be maintained.

.

Io , when I o < ½∆iL or Io < vo / Rcrit , then the

17.1.5 Output ripple voltage

Three components contribute to the output voltage ripple • Ripple charging/discharging of the ideal output capacitor, C • Capacitor equivalent series resistance, ESR • Capacitor equivalent series inductance, ESL The capacitor inductance and resistance parasitic series component values decrease as the quality of the capacitor increases. The output ripple voltage is the vectorial summation of the three components that are shown in figure 17.3 for the forward converter. Ideal Capacitor: The ripple voltage for a capacitor is defined as ∆vC =

1 C

∫ i dt

Figures 17.2 and 17.3 show that for continuous inductor current, the inductor current which is the output current, swings by ∆i around the average output current, I o , thus ∆vC =

1 C

∫ i dt = ½ C1

∆i τ 2 2

Substituting for ∆iL from equation (17.2) ∆vC =

1 C

∫ i dt = ½ C1

∆i τ 2 2

=

1

8

(17.33) 1 vo C L

× (τ − tΤ )τ

(17.34)

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583

If ESR and ESL are ignored, after rearranging, equation (17.34) gives the percentage voltage ripple (peak to peak) in the output voltage ½ ∆vC ∆vo 1 1 f (17.35) = = 8 LC × (1 − δ )τ 2 = ½π 2 (1 − δ )  c  vo vo  fs  In complying with output voltage ripple requirements, from this equation, the switching frequency fs=1/τ must be much higher that the cut-off frequency given by the forward converter low-pass, second-order LC output filter, fc = 1/2π√LC. The voltage switching harmonics before filtering are the dc part δEi and 2 Ei 1 − cos 2π nδ (17.36) Vn = nπ ESR: The equivalent series resistor voltage follows the ripple current, that is, it swings linearly about VESR = ±½ ∆i × RESR (17.37) ESL: The equivalent series inductor voltage is derived from v = Ldi / dt , that is, when the switch is on V + = L∆i / ton = L∆i / δτ (17.38) ESL

When the switch is off

− VESL = − L∆i / toff = − L∆i / (1 − δ )τ

(17.39)

The total instantaneous ripple voltage is ∆vo = ∆vC + VESR + VESL (17.40) Forming a time domain solution for each component, then differentiating, gives a maximum ripple when t = 2CRESR (1 − δ ) (17.41) This expression is independent of the equivalent series inductance, which is expected since it is constant during each operational state. If dominant, the inductor will affect the output voltage ripple at the switch turn-on and turn-off instants.

∆i

o

iC

τ∆i/8C

o

VC

∆i R

o

VESR

o

VESL

v c = vo

L∆i/ton

-

L∆i/tD

Figure 17.3. Forward converter, three output ripple components, showing: left - voltage components; centre – waveforms; and right - capacitor model.

Example 17.1: Buck (step-down forward) converter

The step-down converter in figure 17.2a operates at a switching frequency of 10 kHz. The output voltage is to be fixed at 48 V dc across a 1 Ω resistive load. If the input voltage Ei =192 V and the choke L = 200µH: i. calculate the switch T on-time duty cycle δ and switch on-time tT. ii. calculate the average load current I o , hence average input current I i . iii. draw accurate waveforms for • the voltage across, and the current through L; vL and iL • the capacitor current, ic • the switch and diode voltage and current; vT, vD, iT, iD.


584

Hence calculate the switch utilisation ratio as defined by equation (17.11). iv. v. vi. vii.

viii. ix.

calculate the mean and rms current ratings of diode D, switch T and L. calculate the capacitor average and rms current, iCrms and output ripple voltage if the capacitor has an internal equivalent series resistance of 20mΩ, assuming C = ∞. calculate the maximum load resistance Rcrit before discontinuous inductor current. Calculate the output voltage and inductor non-conduction period, tx, when the load resistance is triple the critical resistance Rcrit. if the maximum load resistance is 1Ω, calculate • the value the inductance L can be reduced, to be on the verge of discontinuous inductor current and for that L • the peak-to-peak ripple and rms, inductor and capacitor currents. specify two control strategies for controlling the forward converter in a discontinuous inductor current mode. output ripple voltage hence percentage output ripple voltage, for C = 1,000µF and an equivalent series inductance of ESL = 0.5µH, assuming ESR = 0Ω.

Solution i. From equation (17.4), assuming continuous inductor current, the duty cycle δ is v 48V δ= o = = ¼ = 25% Ei 192V Also, from equation (17.4), for a 10kHz switching frequency, the switching period τ is 100µs and the transistor on-time tT is given by vo tT 48V t = = = T Ei τ 192V 100µs whence the transistor on-time is 25µs and the diode conducts for 75µs. vo 48V = 48A = I L = 1Ω R From power-in equals power-out, the average input current is I i = vo I o / Ei = 48V×48A/192V = 12A

ii. The average load current is I o =

iii. From equation (17.1) (or equation (17.2)) the inductor peak-to-peak ripple current is E −v 192V-48V ∆iL = i o × tΤ = ×25µs = 18A L 200µH

From part ii, the average inductor current is the average output current, 48A. The inductor current is ∨ continuous since i L = 39A. Circuit voltage and current waveforms are shown in the figure to follow. The circuit waveforms show that the maximum switch voltage and current are 192V and 57A respectively. The switch utilising ratio is given by equation (17.11), that is v2 48V 2 Pout 1Ω ≡ 21% R SUR = = = Ei × i o Ei × i o 192V × 57A o

If the ripple current were assume small, the resulting SUR value of δ = 33% gives a misleading underestimate indication. iv. Current iD through diode D is shown on the inductor current waveform. The average diode current is τ − tT ID = × I L = (1 − δ ) × I L = (1 − ¼)×48A = 36A

τ

The rms diode current is given by 75µs ∆iL 2 1 τ −t ∧ 1 18A 2 iDrms = t ) dt = t ) dt = 41.8A (i L − (57A∫ ∫ − t τ 0 0 100µs 75µs τ T Current iT through the switch T is shown on the inductor current waveform. The average switch current is t I T = T I L = δ I L = ¼×48A = 12A T

.

.

τ

Alternatively, from power-in equals power-out I T = I i = vo I o / Ei = 48V×48A/192V = 12A

Power Electronics

585

Ei -vo

3.6mV.s

(V) 192V

Icap 0

VTran

VDiode

VDiode

VTran 18A

25 125

Figure: Example 17.1

The transistor rms current is given by 25µs 1 t ∨ ∆iL 2 1 18A 2 (i + (39A+ iT rms = t ) dt = t ) dt ∫ ∫ τ 0 tT 100µs 0 25µs T

L

.

.

= 24.1A

The mean inductor current is the mean output current, Io = I L = 48A . The inductor rms current is given by equation (17.6), that is 2

2

½ ∆iL  = 48A 2 +  ½ × 18A  = 48.3A I L rms = I L2 +     3 3   

v. The average capacitor current I C is zero and the rms ripple current is given by iC rms = =

1

∆i

tT

∆i

τ −tT



L (− 1 2 ∆iL + L t ) 2 dt + ∫ ( 1 2 ∆iL − t ) 2 dt  τ  ∫ 0 0 tT τ − tT 

.

.

1   100µs 

∫

25µs 0

(-9A+

18A 2 t ) dt + 25µs

∫

75µs 0

(9A-

18A 2  t ) dt  75µs 

= 5.2A (= ∆iL / 2 3) The capacitor voltage ripple (hence the output voltage ripple), assuming infinite output capacitance, is determined by the capacitor ripple current which is equal to the inductor ripple current, 18A p-p, that is vo ripple = ∆iL × RCesr

= 18A×20mΩ = 360mV p - p and the rms output voltage ripple is vo rms = iCrms × RCesr = 5.2A rms×20mΩ = 104mV rms

vi. Critical load resistance is given by equation (17.26), namely v 2L Rcrit ≤ o = Io τ (1 − δ )


=

586

2×200µH = 16/3Ω 100µs × (1-¼)

= 5 1 3 Ω when I o = 9A Alternatively, the critical load current is 9A (½ ∆iL), thus from the equation immediately above, the load resistance must not be greater than vo / I o = 48V/9A = 5⅓Ω, if the inductor current is to be continuous.

When the load resistance is tripled to 16Ω the output voltage is given by equation (17.20), which is shown normalised in table 17.2. That is  8  Rτ 16Ω × 100µs = = 8 thus vo = Ei × ¼kδ 2  −1 + 1 + 2  where k = δ k L 200µH   8  i L = 14.625A  vo = 192V × ¼ × 8 × ¼ 2 ×  −1 + 1 + 2  = 75V   ¼ ×8   The inductor current is zero for an interval of the 100µs switching period, and the time is given by the appropriate normalised expression involving tx for the forward converter in table 17.2 or by equation (17.16), which when re-arranged to isolate tx becomes     δ  ¼  = 100µs ×  1 − = 36µs [tT = 25µs tD = 39µs ] tx = τ 1 −   75V   vo  50V   Ei  

vii. The critical resistance formula given in equation (17.26) is valid for finding critical inductance when inductance is made the subject of the equation, that is, rearranging equation (17.26) gives Lcrit = ½ × R × (1 − δ ) × τ (H) = ½×1Ω×(1-¼)×100µs = 37½µH This means the inductance can be reduced from 200µH with a 48A mean and 18A p-p ripple current, to 37½µH with the same 48A mean plus a superimposed 96A p-p 2I L ripple current. The rms capacitor current is given by iCrms = ∆iL / 2 3

( )

.

= 96A/2 3 = 27.2A rms .

The inductor rms current requires the following integration τ −t ∧  ∆i 1  t ∨ ∆iL 2 2 ( ) iLrms = i t dt + +  ∫ 0 (i L − τ − LtT t ) dt  τ ∫ 0 tT T

=

.

T

L

.

75µs  25µs 1 96A 2 96A 2  ×  ∫ (0 + t ) dt + ∫ (96A t ) dt  0 0 100µs  25µs 75µs 

= 96/ 3 = 55.4 A rms or from equation (17.6) iLrms = I L2 + iL2ripple = 482 + (96 / 2 3) 2 = 55.4 A rms

viii. For R >16/3Ω, or I o < 9A , equations (17.29) or (17.32) can be used to develop a suitable control strategy. (a) From equation (17.29), using a variable switching frequency of less than 10kHz, R 5 13 Ω f var = f s crit Io = 10kHz Io vo 48V 10 × Io kHz 9 (b) From equation (17.32), maintaining a fixed switching frequency of 10kHz, the on-time duty cycle is reduced (from 25µs) for I o < 9A according to f var

=

tT var = tT tT var

=

Rcrit vo

.

25 × Io 3 .

I o = 25µs µs

5 13 Ω 48V

.

Io

Power Electronics

587

From equation (17.33) the output ripple voltage with an ideal 1,000µF capacitor is given by ∆i τ ∆vC = 8C 18A × 100µs = 225mV p - p = 8 × 1000µF The voltage produced because of the equivalent series 0.5 µH inductance is V + = L∆i / δτ ix.

ESL

=0.5µH×18A/0.25×100µs = 360mV V

− ESL

= − L∆i / (1 − δ )τ

= - 0.5µH×18A/(1 - 0.25)×100µs = -120mV Time domain summation of the capacitor and ESL inductor voltages show that the peak to peak output voltage swing is determined by the ESL inductor, giving + − ∆vo = VESL − VESL = 360mV + 120mV = 480mV The percentage ripple in the output voltage is 480mV/48V = 1%. ♣

17.1.6 Underlying operational mechanisms of the forward converter

The inductor current is pivotal to the analysis and understanding of any smps. For analysis, the smps internal and external electrical conditions are in steady-state on a cycle-by-cycle basis and the input power is equal to the output power. The first concept to appreciate is that the net capacitor charge change is zero over each switching cycle. That is, the average capacitor current is zero: 1 t +τ Ic = ic ( t ) dt = 0

τ

∫

t

In so being, the output capacitor provides any load current deficit and stores any load current (inductor) surplus associated with the inductor current within each complete cycle. Thus, the capacitor is a temporary storage component where the capacitor voltage is fixed on a cycle-by-cycle basis, and because of its large capacitance does not vary significantly within a cycle. The second concept involved is that the average inductor voltage is zero. Based on v = L di / dt , the equal area criteria in chapter 11.1.3i, 1 t +τ it +τ − it = ∫ vL ( t ) dt = 0 since it +τ = it in steady - state L t Thus the average inductor voltage is zero: 1 t +τ VL = vL ( t ) dt = 0

τ

∫

t

The most enlightening way to appreciate the converter operating mechanisms is to consider how the inductor current varies with load resistance R and inductance L. The figure 17.4 shows the inductor current associated with the various parts of example 17.1. For continuous inductor current operation, the two necessary and sufficient equations are Io = vo /R and equation (17.2). Since the duty cycle and on-time are fixed for a given output voltage requirement, equation (17.2) can be simplified to show that the ripple current is inversely proportional to inductance, as follows v ∆iL = o × (τ − tΤ ) L (17.42) 1 ∆i L α L Since the average inductor current is equal to the load current, then, at a given output voltage, the average inductor current is inversely proportional to the load resistance, that is I L = I o = vo / R (17.43) 1 IL α R


IL

IL

Rload

588

L

IL

decre asing L

vo/R

Ω

decreasing R LOAD

72A

48A

24A

ILp-p

96A

36A 18A

200µH

1Ω

vo/R

100µH 37½µH

2Ω

verge of discontinuous 16/3Ω inductor current

9A δ

0

1-δ

25µs

δ

100µs

(a)

t

0

1-δ

25µs

100µs

t

(b)

Figure 17.4. Forward converter (buck converter) operational mechanisms showing that: (a) the average inductor current is inversely proportional to load resistance R (fixed L) and (b) the inductor ripple current magnitude is inversely proportional to inductance L (fixed load R).

Equation (17.43) predicts that the average inductor current is inversely proportional to the load resistance, as shown in figure 17.4a. As the load is increased (load resistor decreased), the triangular inductor current moves vertically up, but importantly, from equation (17.42), the peak-to-peak ripple current is constant, that is the ripple current is independent of the load. As the load current is progressively decreased, by increasing R, the peak-to-peak current is unchanged; the inductor minimum current eventually reduces to zero, and discontinuous inductor current operation occurs. Equation (17.42) indicates that the inductor ripple current is inversely proportional to inductance, as shown in figure 17.4b. As the inductance is varied the ripple current varies inversely, but importantly, from equation (17.43), the average current is constant, and specifically the average current value is not related to inductance L and is solely determined by the load current, vo /R. As the inductance decreases the magnitude of the ripple current increases, the average is unchanged, and the minimum inductor current eventually reaches zero and discontinuous inductor current operation results. 17.2

Flyback converters

Flyback converters store energy in an inductor, (‘choke’), before transferring any energy to the load and output capacitor such that controllable output voltage magnitudes in excess of the input voltage are attainable. The key characteristic is that whilst energy is being transferred to the inductor, all the load energy is provided by the output capacitor. Such converters are also known as ringing choke converters. Two basic (minimum component count and transformerless) versions of the flyback converter are possible, both are integral to the same underlying fundamental circuit configuration (see section 17.5). • The step-up voltage flyback converter, called the boost converter, where the input and output voltage have the same polarity - non-inversion, and vo ≥ Ei. • The step-up/step-down voltage flyback converter, called the buck-boost converter, where output voltage polarity inversion occurs, that is vo ≥ 0.

Power Electronics

589

17.3

The boost converter

The boost converter transforms a dc voltage input to a dc voltage output that is greater in magnitude but has the same relative polarity as the input. The basic circuit configuration is shown in figure 17.5a. It will be seen that when the transistor is off, the output capacitor is charged to the input voltage Ei. Inherently, the output voltage vo can never be less than the input voltage level. When the transistor T is turned on, the supply voltage Ei is applied across the inductor L and the diode D is reverse-biased by the output voltage vo. Energy is transferred from the supply to L and when the transistor is turned off this energy is transferred to the load and output capacitor through D. While the inductor is transferring its stored energy into C and the load, energy is also being provided from the input source. The output current is always discontinuous, but the input current can be either continuous or discontinuous. For analysis, assume vo > Ei and a constant input and output voltage. Inductor currents are then linear and vary according to v = L di/dt. 17.3.1 Continuous inductor current

The circuit voltage and current waveforms for continuous inductor conduction are shown in figure 17.5b. The inductor current excursion, from v = L di/dt, which is the input current excursion, during the switch on-time tT and switch off-time τ- tT , is given by (v - E ) E ∆iL = o i (τ − tT ) = i tT (17.44) L L After rearranging, the voltage and current transfer function is given by vo I i 1 = = (17.45) Ei I o 1 − δ where δ = tT /τ, tT is the transistor on-time, and Pin = Pout, that is, Ei Ii = vo Io is assumed. ii = iL

tD

tD

Figure 17.5. Non-isolated, step-up, flyback converter (boost converter) where v0 ≥E1: (a) circuit diagram; (b) waveforms for continuous input current; and (c) waveforms for discontinuous input current.


590

∧

The maximum inductor current, which is the maximum input current, i L , using equation (17.44) and vo = IoR, is given by ∧ Et i = I L + ½ ∆iL = I i + ½ i T L (17.46)  1- δ ) δτ  ( Io vo 1 = + ½ (1- δ ) δτ = vo  +  L 1− δ 2 L   (1 − δ ) R L

∨

while the minimum inductor current, i is given by ∨ Et i = I L − ½ ∆iL = I i − ½ i T L L

L

=

 (1- δ ) δτ  Io v 1 − ½ o (1- δ ) δτ = vo  −  L 1− δ 2 L   (1 − δ ) R

(17.47)

∨

For continuous conduction i ≥ 0 , that is, from equation (17.47) Et v (1 − δ ) tT IL ≥ ½ i T = ½ o L L The inductor rms ripple current (and input ripple current in this case) is given by ∆i 1 vo iLr = L = (1- δ ) δτ 2 3 2 3 L L

.

(17.48)

(17.49)

.

The harmonic components in the input current are 2 Eiτ sin nδπ 2 voτ sin nδπ = I in = 2π 2 n 2 (1 − δ ) L 2π 2 n 2 L

(17.50)

while the inductor total rms current is 2

2 ∨  1  ∧2 ∧ ∨  = i L + i L× i L + iL    3 3  The switch and diode average and rms currents are given by IT = Ii − Io = δ Ii = δ I L ITrms = δ iL rms

 ½ ∆iL iLrms = I L2 + iL2r = I L2 +  

I D = (1 − δ ) I i = I o

(17.51)

.

I Drms = 1 − δ iL rms

(17.52)

Switch utilisation ratio

The switch utilisation ratio, SUR, is a measure of how fully a switching device’s power handling capabilities are utilised in any switching application. The ratio is defined as P (17.53) SUR = out p VT I T where p is the number of power switches in the circuit; p=1 for the boost converter. The switch maximum instantaneous voltage and current are VT and I T respectively. As shown in figure 17.5b, the maximum switch ∧voltage supported in the off-state is vo, while the maximum current is the maximum inductor current i L which is given by equation (17.46). If the inductance L is large such that the ripple current is small, the peak inductor current is approximated by the average inductor current such that I T ≈ I L = I o /1 − δ , that is vo I o (17.54) = 1− δ SUR = vo × I o 1− δ which assumes continuous inductor current. This result shows that the lower the duty cycle, that is the closer the step-up voltage vo is to the input voltage Ei, the better the switch I-V ratings are utilised. 17.3.2 Discontinuous capacitor charging current in the switch off-state

It is possible that the input current (inductor current) falls below the output (resistor) current during a part of the cycle when the switch is off and the inductor is transferring energy to the output circuit. Under such conditions, towards the end of the off period, part of the load current requirement is provided by the capacitor even though this is the period during which its charge is replenished by inductor energy. The circuit independent transfer function in equation (17.45) remains valid. This C discontinuous charging ∨ condition commences when the minimum inductor current i L and the output current Io are equal. That is

Power Electronics

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∨

IL− Io ≤ 0 I L − ½ ∆iL − I o ≤ 0

(17.55)

E δτ Io −½ i − Io ≤ 0 L 1− δ

which yields

δ ≤ 1−

2L τR

(17.56)

17.3.3 Discontinuous inductor current

If the inequality in equation (17.48) is not satisfied, the input current, which is also the inductor current, reaches zero and discontinuous inductor conduction occurs during the switch off period. Various circuit voltage and current waveforms for discontinuous inductor conduction are shown in figure 17.5c. ∨ The onset of discontinuous inductor current operation occurs when the minimum inductor current i L , ∨ reaches zero. That is, with i L = 0 in equation (17.47), the last equality (1- δ ) δτ 1 − =0 (17.57) 2L (1 − δ ) R relates circuit component values (R and L) and operating conditions (f and δ) at the verge of discontinuous inductor current. ∨

With i L = 0 , the output voltage is determined as follows ∧ Et ( v − Ei ) i = iT = o (τ − tT − t x ) L L yielding t 1 − τx vo = Ei 1 − t x − δ τ L

(17.58)

(17.59)

Alternatively, using ∧

i = L

Ei tT L

and ∧

I L − I o = ½δ i

L

yields 2

Ei tT L δ Assuming power-in equals power-out and I L = I i 2 v Et I o ( o − 1) = i T Ei L δ that is vo E τδ 2 v τδ 2 = 1+ i = 1+ o Ei 2 LI o 2 LI i or vo 1 = Eiτδ 2 Ei 1− 2 LI i ( I L − Io ) =

(17.60)

(17.61)

On the verge of discontinuous conduction (when equation (17.45) is valid), these equations can be rearranged to give E (17.62) I o = i τδ (1 − δ ) 2L At a low output current or low input voltage, there is a likelihood of discontinuous inductor current conduction. (See appendix 17.11.) To avoid discontinuous conduction, larger inductance values are needed, which worsen the transient response. Alternatively, with extremely high on-state duty cycles, (because of a low input voltage Ei) a voltage-matching step-up transformer can be used to decrease δ. Figures 17.5b and c show that the output current is always discontinuous.


592

17.3.4 Load conditions for discontinuous inductor current

As the load current decreases, the inductor average current also decreases, but the inductor ripple current magnitude is unchanged. If the load resistance is increased sufficiently, the bottom of the ∨ triangular inductor current, i L , eventually reduces to zero. Any further increase in load resistance causes discontinuous inductor current and the voltage transfer function given by equation (17.45) is no longer valid and equations (17.59) and (17.60) are applicable. (Certain circuit parameter values - L, R, and τ - can avoid discontinuous conduction for all δ. See appendix 17.11.) The critical load resistance for continuous inductor current is specified by v (17.63) Rcrit ≤ o Io Eliminating the output current by using the fact that power-in equals power-out and I i = I L , yields Rcrit ≤

vo v2 = o I o Ei I L

(17.64)

Using I L = ½ ∆iL then substituting with the right hand equality of equation (17.44), halved, gives vo v2 v2 2L 2L = o = o2 = (17.65) I o Ei I L Ei tT τδ (1 − δ ) 2 The critical resistance can be expressed in a number of forms. By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ) the following forms result. Rcrit ≤

vo v 2 fs L XL 2L 2L (Ω ) = = o× = = (17.66) 2 2 πδ (1 − δ ) 2 Ei τδ (1 − δ ) δ (1 − δ ) I o τδ (1 − δ ) Equation (17.66) is equation (17.57), re-arranged. If the load resistance increases beyond Rcrit, generally the output voltage can no longer be maintained with purely duty cycle control according to the voltage transfer function in equation (17.45). Rcrit ≤

17.3.5 Control methods for discontinuous inductor current

Once the load current has reduced to the critical level as specified by equation (17.66), the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge, thereby increasing vo. Hardware approaches can be used to solve this problem – by ensuring continuous inductor current • increase L thereby decreasing the inductor current ripple p-p magnitude • step-down transformer impedance matching to effectively reduce the apparent load impedance Two control approaches to maintain output voltage regulation when R > Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL. If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by inversely varying the frequency with output voltage. Alternatively, output voltage feedback can be used. 17.3.5i - fixed on-time tT, variable switching frequency fvar

The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 (17.67) ½ ∆iL Eiτ = o R f var Isolating the variable switching frequency fvar gives vo2 1 1 = fs Rcrit × f var = R ½ ∆iL Eiτ R 1 f var α (17.68) R Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R , substitution for R in equation (17.68) gives

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f var = f s

Rcrit × Io vo

(17.69)

α Io That is, for discontinuous inductor current, namely I i < ½∆iL or Io < vo / Rcrit , if the switch on-state period tT remains constant and fvar is either varied proportionally with load current or varied inversely with load resistance, then the required output voltage vo will be maintained. f var

17.3.5ii - fixed switching frequency fs, variable on-time tTvar

The operating frequency fs remains fixed while the switch-on time tTvar is reduced such that the ripple current can be reduced. Operation is specified by equating the input energy and the output energy as in equation (17.67), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 (17.70) ½ ∆iL Ei tT var = o R fs Isolating the variable on-time tTvar gives vo2 1 tT var = ½ ∆iL Ei f s R Substituting ∆iL from equation (17.44) gives 1 tT var = tT Rcrit × R (17.71) 1 tT var α R Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.71) gives Rcrit tT var = tT × Io vo (17.72) .

.

.

tT var α Io That is, if the switching frequency fs is fixed and switch on-time tT is reduced proportionally to Io or inversely to R , when discontinuous inductor current commences, namely I i < ½∆iL or Io < vo / Rcrit , then the required output voltage magnitude vo will be maintained. .

.

.

17.3.6 Output ripple voltage

The output ripple voltage is the capacitor ripple voltage. The ripple voltage for a capacitor is defined as ∆vo =

1 C

∫ i dt

Figure 17.5 shows that for continuous inductor current, the constant output current I o is provided solely from the capacitor during the period tT when the switch is on, thus ∆vo =

1 C

∫ i dt = C1 t

T

Io

Substituting for I o = vo / R gives ∆vo =

1 C

∫ i dt = C1 t

Io =

1 C

tT

vo

R Rearranging gives the percentage voltage ripple (peak to peak) in the output voltage ∆vo δτ = (17.73) vo RC The capacitor equivalent series resistance and inductance can be account for, as with the forward converter, 17.1.4. When the switch conducts, the output current is constant and is provided from the capacitor. Thus no ESL voltage effects result during this constant capacitor current portion of the cycle. T

Example 17.2: Boost (step-up flyback) converter

The boost converter in figure 17.5 is to operate with a 50µs transistor fixed on-time in order to convert the 50 V input up to 75 V at the output. The inductor is 250µH and the resistive load is 2.5Ω. i. Calculate the switching frequency, hence transistor off-time, assuming continuous inductor current. ii. Calculate the mean input and output current. iii. Draw the inductor current, showing the minimum and maximum values.


594

iv. Calculate the capacitor rms ripple current. v. Derive general expressions relating the operating frequency to varying load resistance. vi. At what load resistance does the instantaneous input current fall below the output current. Solution i. From equation (17.45), which assumes continuous inductor current vo t 1 = where δ = T τ Ei 1 − δ that is 75V 1 50µs 1 = where δ = = 3 τ 50V 1 − δ That is, τ = 150 µs or fs = 1/τ = 6.66 kHz, with a 100µs switch off-time. ii. The mean output current I o is given by I o = vo / R = 75V/2.5Ω = 30A From power transfer considerations I i = I L = vo I o / Ei = 75V×30A/50V = 45A

iii. From v = L di/dt, the ripple current ∆iL = Ei tT /L = 50V x 50µs /250 µH = 10 A

that is ∧

i = I L + ½ ∆iL = 45A + ½×10A = 50A L

∨

i = I L − ½ ∆iL = 45A - ½×10A = 40A L

Figure: Example 17.2a

iv. The capacitor current is derived by using Kirchhoff’s current law such that at any instant in time, the diode current, plus the capacitor current, plus the 30A constant load current into R, all sum to zero. τ −t ∧  ∆i 1 t 2 iCrms = I o dt + ∫ ( L t − i + I o ) 2 dt   ∫ τ 0 0 τ − tT   T

T

L

.

=

.

1   150µs 

∫

50 µs 0

30A 2 dt +

∫

100 µs 0

(

 10A t − 20A) 2 dt  = 21.3A 100µs 

ic equal areas (charges) 1.5mC

Figure: Example 17.2b

v. The critical load resistance, Rcrit, produces an input current with ∆iL = 10 A ripple. Since the energy input equals the energy output ½ ∆i × Ei × τ = vo × vo / Rcrit × τ

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that is 2vo2 2×75V 2 = = 22½Ω Ei ∆i 50V×10A Alternatively, equation (17.66) or equation (17.48) can be rearranged to give Rcrit. For a load resistance of less than 22½ Ω, continuous inductor current flows and the operating frequency is fixed at 6.66 kHz with δ = , that is Rcrit =

fs = 6.66 kHz for all R ≤ 22½ Ω

For load resistance greater than 22½ Ω, (< vo /Rcrit = 3⅓A), the energy input occurs in 150 µs burst whence from equation (17.67) v2 1 ½ ∆iL Ei × 150µs = o R f var that is R 1 22½Ω 1 = f var = crit τ R 150µs R 150 f var = kHz for R ≥ 22½ Ω R The ±5A inductor ripple current is independent of the load, provided the critical resistance is not vi. exceeded. When the average inductor current (input current) is less than 5A more than the output current, the capacitor must provide load current not only when the switch is on but also when the switch is off. The transition is given by equation (17.56), that is

δ ≤ 1−

2L

τR

1 2×250µH ≤1 3 150µs × R

This yields R ≥ 7½Ω and a load current of 10A. The average inductor current is 15A, with a minimum value of 10A, the same as the load current. That is, for R < 7½Ω all the load requirement is provided from the input inductor when the switch is off, with excess energy charging (replenishing) the output capacitor. For R > 7½Ω insufficient energy is available from the inductor to provide the load energy throughout the whole of the period when the switch is off. The capacitor supplements the load requirement towards the end of the off period. When R > 22½Ω (the critical resistance), discontinuous inductor current occurs, and the duty cycle dependent transfer function is no longer valid. ♣ Example 17.3: Alternative boost (step-up flyback) converter

The alternative boost converters (producing a dc supply either above Ei (left) or below 0V (right) – see figure 17.8b) shown in the following figure are to operate under the same conditions as the boost converter in example 17.2, namely, with a 50µs transistor fixed on-time in order to convert the 50 V input up to 75 V at the output. The energy transfer inductor is 250µH and the resistive load is 2.5Ω.

vC

io = vo /R

io = vo /R

R L

Figure: Example 17.3 - circuits

i.

vC

Derive the voltage transfer ratio and critical resistance expression for the alternative boost converter, hence showing the control performance is identical to the boost converter shown in figure 17.5.


596

By considering circuit voltage and current waveforms, identify how the two boost converters differ from the conventional boost circuit in figure 17.5. Use example 17.2 for a comparison basis.

ii.

Solution i. Assuming non-zero, continuous inductor current, the inductor current excursion, from v = Ldi/dt, which for this boost converter is not the input current excursion, during the switch on-time tT and switch off-time τ - tT, is given by L∆iL = Ei tT = vC (τ − tT ) but vC = vo − Ei , thus substitution for vC gives Ei tT = ( vo − Ei )(τ − tT ) and after rearranging vo I i 1 δ   : that is vo ≥ Ei alternately Ei + δ vo = vo  = = = 1+ 1− δ Ei I o 1 − δ   where δ = tT /τ and tT is the transistor on-time. This is the same voltage transfer function as for the conventional boost converter, equation (17.45). This result would be expected since both converters have the same ac equivalent circuit. Similarly, the critical resistance would be expected to be the same for each boost converter variation. Examination of the switch on and off states shows that during the switch on-state, energy is transfer to the load from the input supply, independent of switching action. This mechanism is analogous to ac autotransformer action where the output current is due to both transformer action and the input current being directed to the load. The critical load resistance for continuous inductor current is specified by Rcrit ≤ vo / I o . By equating the capacitor net charge flow, the inductor current is related to the output current by I L = I o /(1 − δ ) . At minimum inductor current, I L = ½ ∆iL and substituting with ∆iL = Ei tT / L , gives v vo vo vo 2L Rcrit ≤ o = = = = I o (1 − δ ) I L (1 − δ )½ ∆iL (1 − δ )½ Ei tT / L τδ (1 − δ )2 Thus for a given energy throughput, some energy is provided from the supply to the load when providing the inductor energy, hence the discontinuous inductor current threshold occurs at the same load level for each boost converter, including the basic converter in figure 17.5. ii. Since the boost circuits have the same ac equivalent circuit, the inductor and capacitor, currents and voltages would be expected to be basically the same for each circuit, as shown by the waveforms in example 17.2. Consequently, the switch and diode voltages and currents are also the same for each boost converter. The two principal differences are the supply current and the capacitor voltage rating. The capacitor voltage rating for the alternative boost converter is lower, vo - Ei, as opposed to vo for the conventional converter. The supply current for the alternative converter is discontinuous (although always non-zero), as shown in the following waveforms. This will negate the desirable continuous current feature exploited in boost converters that are controlled so as to produce sinusoidal input current. iC

vC

io = vo /R Ls

Lp I su p p ly (A )

80 70 30

I lo a d

t (µ s )

Figure: Example 17.3 – waveforms and transformer coupled version

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An isolated version, with the input supply isolated from the load, is not possible. But the couple inductor version shown in the example figure can be useful in avoiding very short (or long) switch duty cycles and help control (both avoiding or ensuring) continuous inductor current conduction conditions. ♣ 17.4

The buck-boost converter

The basic buck-boost flyback converter circuit is shown in figure 17.6a. When transistor T is on, energy is transferred to the inductor and the load current is provided solely from the output capacitor. When the transistor turns off, inductor current is forced through the diode. Energy stored in L is transferred to C and the load R. This transfer action results in an output voltage of opposite polarity to that of the input. Neither the input nor the output current is continuous, although the inductor current may be continuous or discontinuous.

tD

tD

Figure 17.6. Non-isolated, step up/down flyback converter (buck-boost converter) where vo ≤ 0:

(a) circuit diagram; (b) waveforms for continuous inductor current; and (c) discontinuous inductor current.

17.4.1 Continuous choke (inductor) current

Various circuit voltage and current waveforms for the buck-boost flyback converter operating in a continuous inductor conduction mode are shown in figure 17.6b. Assuming a constant input and output voltage, from v = Ldi/dt, the change in inductor current is given by E −v ∆iL = i tT = o (τ − tT ) (17.74) L L


Thus assuming Pin = Pout, that is v o I o = E i I i vo I i δ = =− 1− δ Ei I o

598

(17.75)

where δ = tT /τ. For δ < ½ the output magnitude is less than the input voltage magnitude, while for δ > ½ the output voltage is greater in magnitude (but as for δ < ½, opposite in polarity) than the input voltage. The maximum and minimum inductor current is given by  ∧ (1- δ )τ  I v 1 + (17.76) i = o + ½ o (1- δ )τ = vo   L 2 L  1− δ  (1 − δ ) R and ∨  (1- δ )τ  I v 1 − i = o − ½ o (1- δ )τ = vo  (17.77)  L 2 L  1− δ  (1 − δ ) R The inductor rms ripple current is given by ∆i 1 vo iL r = L = (17.78) (1- δ ) δτ 2 3 2 3 L while the inductor total rms current is L

L

.

.

2

2 ∨  1  ∧2 ∧ ∨  ½ ∆iL  iL rms = I L2 + iL2r = I L2 +  i L + i L × i L + iL   =  3 3  

(17.79)

.

The switch and diode average and rms currents are given by IT = Ii = δ I L I Trms = δ iL rms I D = (1 − δ ) I L = I o

I Drms = 1 − δ iL rms

(17.80)

Switch utilisation ratio The switch utilisation ratio, SUR, is a measure of how fully a switching device’s power handling capabilities are utilised in any switching application. The ratio is defined as P SUR = out (17.81) p VT I T

where p is the number of power switches in the circuit; p=1 for the buck-boost converter. The switch maximum instantaneous voltage and current are VT and I T respectively. As shown in figure 17.6b, the maximum switch ∧voltage supported in the off-state is Ei + vo, while the maximum current is the maximum inductor current i which is given by equation (17.76). If the inductance L is large such that the ripple current is small, the peak inductor current is approximated by the average inductor current which yields I T ≈ I L = I o /1 − δ , that is vo I o SUR = = δ (1 − δ ) (17.82) ( Ei + vo ) × I o /1 − δ L

which assumes continuous inductor current. This result shows that the closer the output voltage vo is in magnitude to the input voltage Ei, that is δ = ½, the better the switch I-V ratings are utilised. 17.4.2 Discontinuous capacitor charging current in the switch off-state

It is possible that the inductor current falls below the output (resistor) current during a part of the cycle when the switch is off and the inductor is transferring (replenishing) energy to the output circuit. Under such conditions, towards the end of the off period, some of the load current requirement is provided by the capacitor even though this is the period during which its charge is replenished by inductor energy. The circuit independent transfer function in equation (17.75) remains valid. This discontinuous capacitor charging condition occurs when the minimum inductor current and the output current are equal. That is ∨

IL− Io ≤ 0 I L − ½ ∆iL − I o ≤ 0

(17.83)

Io I R − ½ o (1- δ )τ − I o ≤ 0 L 1− δ

which yields 2

δ ≤ 1+

L L   − 1 +  −1 τR  τR

(17.84)

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17.4.3 Discontinuous choke current ∨

The onset of discontinuous inductor operation occurs when the minimum inductor current i L , reaches ∨ zero. That is, with i = 0 in equation (17.77), the last equality (1- δ )τ 1 − =0 (17.85) 2L 1 δ R − ( ) L

relates circuit component values (R and L) and operating conditions (f and δ) at the verge of discontinuous inductor current. The change from continuous to discontinuous inductor current conduction occurs when ∧

I L = ½ i = ½ ∆iL

(17.86)

L

∧

i = vo (τ − tT ) / L

where from equation (17.74)

L

The circuit waveforms for discontinuous conduction are shown in figure 17.6c. The output voltage for discontinuous conduction is evaluated from ∧ E v i = i t = − o (τ − tT − t x ) (17.87) L L which yields vo δ =− (17.88) t Ei 1− δ − x L

τ

Alternatively, using equation (17.87) and ∧

I i = ½δ i

(17.89)

L

yields

Eiτδ 2 (17.90) 2L The inductor current is neither the input current nor the output current, but is comprised of separate components (in time) of each of these currents. Examination of figure 17.6b, reveals that these currents are a proportion of the inductor current dependant on the duty cycle, and that on the verge of discontinuous conduction: Ii =

∧

I i = ½δ i

L

and

I o = ½δ off i = ½ (1- δ ) i ∧

∧

L

∧

L

where i = ∆iL L

Thus using power in equals power out, that is Ei I i = vo I o , equation (17.90) becomes vo Eiτδ 2 voτδ 2 τR = = =δ Ei 2L 2 LI o 2 LI i On the verge of discontinuous conduction, these equations can be rearranged to give E v I o = i τδ (1 − δ ) = o τ (1 − δ ) 2 2L 2L

(17.91)

(17.92)

At a low output current or low input voltage there is a likelihood of discontinuous conduction. To avoid this condition, a larger inductance value is needed, which worsen the transient response. Alternatively, with extremely low on-state duty cycles, a voltage-matching transformer can be used to increase δ. Once a transformer is employed, any smps technique can be used to achieve the desired output voltage. Figures 17.6b and c show that both the input and output current are always discontinuous. 17.4.4 Load conditions for discontinuous inductor current

As the load current decreases, the inductor average current also decreases, but the inductor ripple current magnitude is unchanged. If the load resistance is increased sufficiently, the bottom of the ∨ triangular inductor current, i L , eventually reduces to zero. Any further increase in load resistance causes discontinuous inductor current and the voltage transfer function given by equation (17.75) is no longer valid and equations (17.87) and (17.91) are applicable. The critical load resistance for continuous inductor current is specified by v (17.93) Rcrit ≤ o Io ∧

Substituting for, the average input current in terms of i yields

L

and vo in terms of ∆iL from equation (17.74),


600

vo 2L (17.94) = I o τ (1 − δ ) 2 By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ) the following critical resistance forms result. v v 2 fs L XL 2L 2L Rcrit ≤ o = (Ω ) = o× = = (17.95) I o τ (1 − δ ) 2 Ei τδ (1 − δ ) (1 − δ ) 2 π (1 − δ ) 2 Equation (17.95) is equation (17.85), re-arranged. Rcrit ≤

If the load resistance increases beyond Rcrit, the output voltage can no longer be maintained with duty cycle control according to the voltage transfer function in equation (17.75). 17.4.5 Control methods for discontinuous inductor current

Once the load current has reduced to the critical level as specified by equation (17.95), the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge. Hardware approaches can solve this problem – by ensuring continuous inductor current • increase L thereby decreasing the inductor current ripple p-p magnitude • step-down transformer impedance matching to effectively reduce the apparent load impedance Two control approaches to maintain output voltage regulation when R > Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL. If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by inversely varying the frequency with output voltage. Alternatively, output voltage feedback can be used. 17.4.5i - fixed on-time tT, variable switching frequency fvar

The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 ½ ∆iL Ei tT = o (17.96) R f var Isolating the variable switching frequency fvar gives vo2 1 1 = fs Rcrit × f var = ½ ∆iL Ei tT R R 1 (17.97) R Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R , substitution for R in equation (17.97) gives R f var = f s crit × Io vo (17.98)

α

f var

f var

α

Io

That is, for discontinuous inductor current, namely I L < ½ ∆iL or Io < vo / Rcrit , if the switch on-state period tT remains constant and fvar is either varied proportionally with load current or varied inversely with load resistance, then the required output voltage vo will be maintained. 17.4.5ii - fixed switching frequency fs, variable on-time tTvar

The operating frequency fs remains fixed while the switch-on time tTvar is reduced such that the ripple current can be reduced. Operation is specified by equating the input energy and the output energy as in equation (17.96), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 ½ ∆iL Ei tT var = o (17.99) R fs

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Isolating the variable on-time tTvar gives vo2 1 ½ ∆iL Ei f s R Substituting ∆iL from equation (17.74) gives 1 tT var = tT Rcrit × R (17.100) 1 tT var α R Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.71) gives tT var =

.

.

tT var = tT

Rcrit × vo

α

tT var

.

Io

(17.101)

Io

.

That is, if the switching frequency fs is fixed and switch on-time tT is reduced proportionally to Io or inversely to R , when discontinuous inductor current commences, namely I L < ½∆iL or Io < vo / Rcrit , then the required output voltage magnitude vo will be maintained. .

.

Alternatively the output voltage is related to the duty cycle by vo = −δ Ei Rτ / 2 L . See table 17.2. 17.4.6 Output ripple voltage

The output ripple voltage is the capacitor ripple voltage. Ripple voltage for a capacitor is defined as ∆vo =

∫ i dt

1 C

Figure 17.6 shows that the constant output current I o is provided solely from the capacitor during the on period tT when the switch conducting, thus ∆vo =

1 C

∫ i dt = C1 t

T

Io

Substituting for I o = vo / R gives ∆vo =

1 C

∫ i dt = C1 t

Io =

1 C

tT

vo

R Rearranging gives the percentage peak-to-peak voltage ripple in the output voltage ∆vo (17.102) = 1 tT = δ τ RC RC vo The capacitor equivalent series resistance and inductance can be account for, as with the forward converter, 17.1.5. When the switch conducts, the output current is constant and is provided solely from the capacitor. Thus no ESL voltage effects result during this constant capacitor current portion of the switching cycle. T

17.4.7 Buck-boost, flyback converter design procedure

The output voltage of the buck-boost converter can be regulated by operating at a fixed frequency and varying the transistor on-time tT. However, the output voltage diminishes while the transistor is on and increases when the transistor is off. This characteristic makes the converter difficult to control on a fixed frequency basis. A simple approach to control the flyback regulator in the discontinuous mode is to fix the peak inductor current, which specifies a fixed diode conduction time, tD. Frequency then varies directly with output current and transistor on-time varies inversely with input voltage. With discontinuous inductor conduction, the worst-case condition exists when the input voltage is low while the output current is at a maximum. Then the frequency is a maximum and the dead time tx is zero because the transistor turns on as soon as the diode stops conducting. Given Worst case Ei (min)

Io (max)

Vo

f (max)

Ei = Ei (min) ∆eo

tx = 0

Io = Io(max)

∧

Assuming a fixed peak inductor current i and output voltage vo, the following equations are valid i

∧

Ei (min)tT = votD = i × L

(17.103)

τ (min) = 1/ f (max)

(17.104)

i


602

Equation (17.103) yields tD =

1 v f (max) ( o + 1) Ei (min)

(17.105) ∧

Where the diode conduction time tD is constant since in equation (17.103), v0, i , and L are all constants. The average output capacitor current is given by i

∧

Io = ½ i (1 − δ ) and substituting equation (17.105) yields i

∧

Io (max) = ½ i × f (max) × i

1 v f (max) ( o + 1) Ei (min)

therefore ∧

i = 2 × Io (max) × ( i

vo + 1) Ei (min)

and upon substitution into equation (17.103) tD vo L= v 2 Io (max) ( o + 1) Ei (min)

(17.106)

The minimum capacitance is specified by the maximum allowable ripple voltage, that is ∧

∆Q i t D C= = ∆eo 2∆eo ∨

i

that is ∨

C=

Io (max) t D v ∆eo ( o + 1) Ei (min)

(17.107)

For large output capacitance, the ripple voltage is dropped across the capacitor equivalent series resistance, which is given by ∆e ESR(max) = ∧ o (17.108) i The frequency varies as a function of load current. Equation (17.104) gives ∧ Io (max) Io = ½ i tT = f f (max) therefore I f = f (max) × o (17.109) Io (max) and I f (min) = f (max) × o (min) (17.110) Io (max) i

i

Example 17.4: Buck-boost flyback converter

The 10kHz flyback converter in figure 17.6 is to operate from a 50V input and produces an inverted nonisolated 75V output. The inductor is 300µH and the resistive load is 2.5Ω. Calculate the duty cycle, hence transistor off-time, assuming continuous inductor current. Calculate the mean input and output current. Draw the inductor current, showing the minimum and maximum values. Calculate the capacitor rms ripple current and output p-p ripple voltage if C = 10,000µF. Determine • the critical load resistance. • the minimum inductance for continuous inductor conduction with 2.5 Ω load vi. At what load resistance does the instantaneous inductor current fall below the output current? vii. What is the output voltage if the load resistance is increased to four times the critical resistance? i. ii. iii. iv. v.

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Solution i. From equation (17.88), which assumes continuous inductor current vo δ =− where δ = tT / τ Ei 1−δ that is 75V δ = thus δ = 3 5 50V 1 − δ That is, τ = 1/ fs = 100 µs with a 60µs switch on-time. ii. The mean output current I o is given by I o = vo / R = 75V/2.5Ω = 30A From power transfer considerations I i = I L = vo I o / Ei = 75V×30A/50V = 45A iL (A) 80 10A

75

IL=75A

70 IT

ID

IT

ID

60µs

0

50

100

150

t (µs)

iC (A) Io=30A

30 1.8mC

0 0

50

100

150

t (µs)

1.8mC

40 50

Figure: Example 17.4

iii. The average inductor current can be derived from I i = δ I L or I o =(1- δ ) I L That is I L = I i /δ = I o /(1- δ ) = 45A/ 3 5 = 30A/ 2 5 = 75A From v = L di/dt, the ripple current ∆iL = Ei tT /L = 50V x 60µs /300 µH = 10 A, that is ∧

i L = I L + ½ ∆iL = 75A + ½×10A = 80A ∨

i L = I L − ½ ∆iL = 75A - ½×10A = 70A

∨

Since i L = 70A ≥ 0A, rhe inductor current is continuous, thus the analysis in parts i, ii, and iii, is valid. iv. The capacitor current is derived by using Kirchhoff’s current law such that at any instant in time, the diode current, plus the capacitor current, plus the 30A constant load current into R, all sum to zero. τ −t ∧  ∆iL 1 t 2 2 iCrms = τ  ∫ 0 I o dt + ∫ 0 (τ − tT t − i + I o ) dt    60 µs 40 µs  1  10A = t − 50A) 2 dt  = 36.8A 30A 2 dt + ∫ (  0 100µs  ∫ 0 40µs  T

T

L

.

.


604

The output ripple voltage is given by equation (17.102), that is 3 ∆vo δτ 5 × 100µs = = ≡ 0.24% vo CR 10, 000µF × 2½ Ω The output ripple voltage is therefore ∆vo = 0.24 × 10−2 × 75V = 180mV v. The critical load resistance, Rcrit, produces an inductor current with ∆iL = 10 A ripple. From equation (17.95) 2L 2×300µH = Rcrit = = 37½Ω 2 τ (1 − δ ) 100µs × (1- 35 ) 2

The minimum inductance for continuous inductor current operation, with a 2½Ω load, can be found by rearranging the critical resistance formula, as follows: Lcrit = ½ Rτ (1 − δ ) 2 = ½×2.5Ω×100µs×(1- 3 5 ) 2 = 20µH vi. The ± 5A inductor ripple current is independent of the load, provided the critical resistance of 37½Ω is not exceeded. When the average inductor current is less than 5A more than the output current, the capacitor must provide load current not only when the switch is on but also for a portion of the time when the switch is off. The transition is given by equation (17.84), that is 2

δ ≤ 1+

L L   − 1 +  −1 τR τ R 

Alternately, when I i − I o = 5A Io − I o = 5A 1− δ

For δ = ⅗, I o = 3⅓A. whence v 75V R= o = = 22½Ω 10 Io 3A The average inductor current is 8⅓A, with a minimum value of 3⅓A, the same as the load current. That is, for R < 22½Ω all the load requirement is provided from the inductor when the switch is off, with excess energy charging the output capacitor. For R > 22½Ω insufficient energy is available from the inductor to provide the load energy throughout the whole of the period when the switch is off. The capacitor supplements the load requirement towards the end of the off period. When R > 37½Ω (the critical resistance), discontinuous inductor current occurs, and the purely duty cycle dependent transfer function (circuit parameter independent) is no longer valid. When the load resistance is increased to 150Ω, four times the critical resistance, the output vii. voltage is given by equation (17.91): τR 100µs × 150Ω vo = Ei δ = 50V × 3 5 × = 150V 2L 2 × 300µH ♣ 17.5

Flyback converters – a conceptual assessment

In section 17.2 the boost and buck-boost converters were both introduced as flyback or ringing choke converters. This is not the traditional approach adopted to the classification of these two converters. This text has classified both as flyback converters since they are in fact the same converter. A converter is considered a two port network – an input Ei and an output vo – that are related by a transfer function which is expressed in terms of the switch on-state duty cycle δ.

vo = f (δ ) Ei A second output v1 exists between the input Ei and the output vo, as shown in figure 17.7. By Kirchhoff’s voltage law, this auxiliary output is v 1 = E i −v o

v v1 = 1 − o = 1 − f (δ ) Ei Ei

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buck-boost output

v v1

v1 = Ei ×

Ei

1

½

-1

I1 1

Ii

δ

-

+ I1

1 − f (δ ) v1

+

vo

Ismps

f(δ)

Ei

Ei

vo

-δ 1-δ

Io +

vo = Ei ×

1 1-δ

(a)

boost output

Ei

1

I1

vo = δEi Ii v1= (1-δ)Ei

v 1 = E i × (1 − δ )

+

1 − f (δ ) v1

+ Ei

Ei

I1 vo

f(δ)

Ismps

Io +

vo = Ei ×δ

(b)

buck output

δ

0

½

1

Figure 17.7. Basic converters shown as a three-port block diagrams for (a) the flyback converter and (b) the forward converter.

The flyback converter – figure 17.7a If f(δ) represents a boost converter, with 1/ 1- δ, then 1 - f(δ) = - δ /1- δ, which is the buck-boost converter transfer function. The converse is also true. Thus if a boost converter output exists, a buck-boost output is inherently available, independent of the connection position of the output capacitor Co. In terms of dc circuit theory, the output capacitor can be connected across vo, v1 or apportioned between both outputs. The circuit permutations in figure 17.8 show how the boost converter, using ac and dc circuit theory, can be systematically translated to the buck-boost converter, and vice versa. The schematic of an autotransformer (variac) is interposed since it too can provide the equivalent two ac output possibilities. Whether a dc converter or an ac variac, power can be drawn from each output separately or from both outputs simultaneously. The output ports of both converters, when an extra switch and diode are added, are bidirectional reversible as considered in section 17.7.2. The forward converter – figure 17.7b Just as the boost and buck-boost outputs are complementary, the buck converter has a complementary output possibility. If the output vo is defined by the buck converter transfer function δ then the supplementary output v1 is defined by 1-δ. The output 1-δ cannot exist independently of the output δ. In order to maintain output voltage transfer function integrity according to the duty cycle dependant transfer functions, the current sourced from port vo (the buck output) must exceed the current sunk by port v1. That is, if the outputs are resistively loaded I smps > 0

Io ≥ I1 vo v1 ≥ Ro R1 or

R1 ≥ Ro

1−δ

δ

Notice in figure 17.7a, in the flyback converter case, Ismps is always positive. Therefore no load resistance restrictions exist for the two outputs, save the inductor current is continuous. Thus only two fundamental single-switch, single-inductor converters (flyback and forward) exist, each offering two output voltage transfer function possibilities. One of the four output possibilities, 1- δ, cannot uniquely exist.


Figure 17.8. Basic (a) boost to (e) buck-boost converter systematic translations.

606

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17.6

The output reversible converter

The basic reversible converter, sometimes called an asymmetrical half bridge converter (see chapter 14.5), shown in figure 17.9a allows two-quadrant output voltage operation. Operation is characterised by both switches operating simultaneously, being either both on or both off. The input voltage Ei is chopped by switches T1 and T2, and because the input voltage is greater than the load voltage vo, energy is transferred from the dc supply Ei to L, C, and the load R. When the switches are turned off, energy stored in L is transferred via the diodes D1 and D2 to C and the load R but in a path involving energy being returned to the supply, Ei. This connection feature allows energy to be transferred from the load back into Ei when used with an appropriate load and the correct duty cycle. Parts b and c respectively of figure 17.9 illustrate reversible converter circuit current and voltage waveforms for continuous and discontinuous conduction of L, in a forward converter mode, when δ > ½.

T1

+

D1 D2 T2 (a) ON

switch period iL Io ∨ iL

T

D

T

D

tT

tD

tT

tD

io

τ

t

iL

tx

τ

t

ii

∨

iL t

∨

-iL

t iD

iL ∨

iL t

Ei

t

vD

t

t (b)

(c)

Figure 17.9. Basic reversible converter with δ>½: (a) circuit diagram; (b) waveforms for continuous inductor current; and (c) discontinuous inductor current.

For analysis it is assumed that components are lossless and the output voltage vo is maintained constant because of the large capacitance magnitude of the capacitor C across the output. The input voltage Ei is also assumed constant, such that Ei ≥ vo > 0, as shown in figure 17.9a. 17.6.1 Continuous inductor current

When the switches are turned on for period tT, the difference between the supply voltage Ei and the output voltage v0 is impressed across L. From V = Ldi/dt, the rising current change through the inductor will be ∧ ∨ E −v ∆iL = i L − i L = i o × tΤ (17.111) L


608

When the two switches are turned off for the remainder of the switching period, τ - tT, the two freewheel diodes conduct in series and Ei + vo is impressed across L. Thus, assuming continuous inductor conduction the inductor current fall is given by E +v ∆iL = i o × (τ − tΤ ) (17.112) L Equating equations (17.111) and (17.112) yields vo I i 2t − τ (17.113) 0 ≤ δ ≤1 = = T = 2δ − 1 τ Ei I o The voltage transfer function is independent of circuit inductance L and capacitance C. Equation (17.113) shows that for a given input voltage, the output voltage is determined by the transistor conduction duty cycle δ and the output voltage |vo| is always less than the input voltage. This confirms and validates the original analysis assumption that Ei ≥ |vo|. The linear transfer function varies between -1 and 1 for 0 ≤ δ ≤ 1, that is, the output can be varied between vo = - Ei, and vo = Ei. The significance of the change in transfer function polarity at δ = ½ is that • for δ > ½ the converter acts as a forward converter, but • for δ < ½, if the output is a negative source, the converter acts as a boost converter with energy transferred to the supply Ei, from the negative output source. Thus the transfer function can be expressed as follows vo I i = = 2δ − 1 = 2 (δ − ½) ½ ≤ δ ≤1 Ei I o and Ei I o 1 1 = = = 0≤δ ≤ ½ vo I i 2δ − 1 2 (δ − ½) where equation (17.115) is in the boost converter transfer function form.

(17.114)

(17.115)


In the forward converter mode,∨ δ ≥ ½, the onset of discontinuous inductor current operation occurs when the minimum inductor current i L , reaches zero. That is, I L = ½ ∆i L = I o (17.116) If the transistor on-time tT is reduced or the load resistance increases, the discontinuous condition dead ∨ time tx appears as indicated in figure 17.9c. From equations (17.111) and (17.112), with i = 0 , the following output voltage transfer function can be derived ∧ E −v E +v (17.117) ∆iL = i L − 0 = i o × tΤ = i o × (τ − tΤ − t x ) L L which after rearranging yields L

tx vo 2δ − 1 − τ = t Ei 1 − τx

0 ≤δ ½ and provides part of the voltage function of the buck-boost converter when δ < ½ but with energy transferring in the opposite direction. Comparison of example 17.1 and 17.4 shows that although the same output voltage range can be achieved, the inductor ripple current is much larger for a given inductance L. A similar result occurs when compared with the buck-boost converter. Thus in each case, the reversible converter has a narrower output resistance range before discontinuous inductor conduction occurs. It is therefore concluded that the reversible converter should only be used if two quadrant operation is needed. ∼ The ripple current I f given by equation (17.2) for the forward converter and equation (17.111) for the reversible converter when vo > 0, yield the following current ripple relationship. I f = (2 − 1/ δ r ) × I r (17.127) where 2δ r − 1 = δ f for 0 ≤ δ f ≤ 1 and ½ ≤ δ r ≤ 1 ∼

This equation shows that the ripple current of the forward converter I f is never greater than the ripple ∼ current I r for the reversible converter, for the same output voltage. In the voltage inverting mode, from equations (17.74) and (17.111), the relationship between the two corresponding ripple currents is given by 2(δ r − 1) I fly = × Ir 2δ r − 1 (17.128) 2(δ r − 1) where = δ fly for 0 ≤ δ fly ≤ ½ and 0 ≤ δ r ≤ ½ 2δ r − 1


612

Again the reversible converter always has the higher inductor ripple current. Essentially the higher ripple current results in each mode because the inductor energy release phase involving the diodes, occurs back into the supply, which is effectively in cumulative series with the output capacitor voltage. The reversible converter offers some functional flexibility, since it can operate as a conventional forward converter, when only one of the two switches is turned off. (In fact, in this mode, switch turn-off is alternated between T1 and T2 so as to balance switch and diode losses.)

17.7

The Ćuk converter

The Ćuk converter in figure 17.10 performs an inverting boost converter function with inductance in the input and the output. As a result, both the input and output currents can be continuous. A capacitor is used in the process of transferring energy from the input to the output and ac couples the input boost converter stage (L1, T) to the output forward converter (D, L2). Specifically, the capacitor C1 ac couples the switch T in the boost converter stage into the output forward converter stage. 17.7.1 Continuous inductor current

When the switch T is on and the diode D is reversed biased iC 1( on ) = − I L 2 = I o

(17.129)

When the switch is turned off, inductor currents iL1 and iL2 are divert through the diode and iC 1(off) = I i

(17.130)

C1

L1

L2

vo

C2 +

Figure 17.10. Basic Ćuk converter.

Over one steady-state cycle the average capacitor charge is zero, that is iC 1(on)δτ + iC 1(off) (1 − δ )τ = 0

(17.131)

which gives iC 1(on) δ I = = i iC 1(off) (1 − δ ) I o

(17.132)

From power-in equals power-out vo I I = i = L1 Ei I o I L 2

Thus equation (17.132) becomes vo I I δ = i = L1 = − (1 − δ ) Ei I o I L 2

(17.133)

(17.134)


The current rise in L1 occurs when the switch is on, that is δτ Ei ∆i L 1 = L1 For continuous current in the input inductor L1,

(17.135)

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I i = I L 1 ≥ ½ ∆i L 1 (17.136) which yields a maximum allowable load resistance, for continuous inductor current, of v 2 f Lδ 2δ L1 δ X L1 = s 12 = (17.137) Rcrit ≤ o = 2 (1 − δ ) π (1 − δ ) 2 I o τ (1 − δ ) This is the same expression as that obtained for the boost converter, equation (17.66), which can be rearranged to give the minimum inductance for continuous input inductor current, namely 2 ∨ (1 − δ ) Rτ (17.138) L1 = 2δ The current rise in L2 occurs when the switch is on and the inductor voltage is Ei, that is δτ Ei (17.139) ∆i L 2 = L2 For continuous current in the output inductor L2, I o = I L 2 ≥ ½ ∆i L 2 (17.140) which yields X 2f L v 2 L2 = s 2 = (17.141) Rcrit ≤ o = I o τ (1 − δ ) (1 − δ ) π (1 − δ ) This is the same expression as that obtained for the forward converter, equation (17.26) which can be re-arranged to give the minimum inductance for continuous output inductor current, namely L2

∨

L 2 = ½ (1 − δ ) Rτ

(17.142)

17.7.3 Optimal inductance relationship

Optimal inductor conditions are that both inductors should both simultaneous reach the verge of discontinuous conduction. The relationship between inductance and ripple current is given by equations (17.135) and (17.139). δτ Ei δτ Ei ∆iL1 = and ∆iL 2 = L1 L2 After diving these two equations L2 ∆iL1 = (17.143) L1 ∆iL 2 Critical inductance is given by equations (17.138) and (17.142), that is 2 ∨ ∨ (1 − δ ) Rτ L 2 = ½ (1 − δ ) Rτ and L1 = 2δ After dividing ∨

L2 ∨

=

δ 1−δ

(17.144)

L1 At the verge of simultaneous discontinuous inductor conduction ∨

L2

=

δ

=

v ∆iL1 = o Ei ∆iL 2

(17.145) L1 1 − δ That is, the voltage transfer ratio uniquely specifies the ratio of the minimum inductances and their ripple current. ∨

17.7.4 Output voltage ripple

The output stage (L2, C2, and R) is the forward converter output stage; hence the per unit output voltage ripple on C2 is given by equation (17.35), that is ∆vC 2 ∆vo 1 (1 − δ )τ 2 (17.146) = = 8× vo vo L2 C2 If the ripple current in L1 is assumed constant, the per unit voltage ripple on the ac coupling capacitor C1 is approximated by ∆vC1 δτ = (17.147) vo R C1


614

Example 17.6: Ćuk converter

The Ćuk converter in figure 17.10 is to operate at 10kHz from a 50V battery input and produces an inverted non-isolated 75V output. The load power is 1.8kW. Calculate the duty cycle hence switch on and off times, assuming continuous current in both inductors. ii. Calculate the mean input and output, hence inductor, currents. iii. At the 1.8kW load level, calculate the inductances L1 and L2 such that the ripple current is 1A p-p in each. iv. Specify the capacitance for C1 and C2 if the ripple voltage is to be a maximum of 1% of the output voltage. v. Determine the critical load resistance for which the purely duty cycle dependant voltage transfer function becomes invalid. vi. At the critical load resistance value, determine the inductance value to which the noncritically operating inductor can be reduced. vii. Determine the necessary conditions to ensure that both inductors operate simultaneously on the verge of discontinuous conduction, and the relative ripple currents for that condition. i.

Solution

The voltage transfer function is given by equation (17.134), that is vo δ 75V =− =− = −1½ Ei (1 − δ ) 50V from which δ = 3 5 . For a 10kHz switching frequency the period is 100µs, thus the switch on-time is 60µs and the off-time is 40µs. i.

ii. The mean output current is determined by the load and the mean input current is related to the output current by assuming 100% efficiency, that is I o = I L 2 = Po / vo = 1800W / 75V = 24A I i = I L1 = Po / Ei = 1800W / 50V = 36A

The load resistance is therefore R = vo /Io = 75V/24A = 3⅛Ω. iii.

The inductor ripple current for each inductor is given by the same expression, that is equations (17.135) and (17.139). Thus for the same ripple current of 1A pp δτ Ei δτ Ei ∆iL1 = = ∆iL 2 = L1 L2 which gives δτ Ei 35 × 100µs × 50V L1 = L2 = = = 3mH ∆i 1A

iv.

The capacitor ripple voltages are given by equations (17.147) and (17.146), which after rearranging gives v δ τ 100 35 ×100µs C1 = o × = × = 1.92mF 25 ∆vC1 R 1 8Ω C2 =

vo (1 − δ )τ 2 100 1 (1 − 35 ) × 100µs 2 × 18 × = × 8× = 16.6µF ∆vC 2 L2 1 3mH

The critical load resistance for each inductor is given by equations (17.137) and (17.141). When both inductors are 3mH: 2δ L1 2 × 35 × 3mH = = 225Ω Rcrit ≤ 2 τ (1 − δ ) 100µs × (1 − 35 ) 2 2 L2 2 × 3mH = = 150Ω Rcrit ≤ τ (1 − δ ) 100µs × (1 − 35 ) The limiting critical load resistance is 150Ω or for Io = vo /R = 75V/150Ω = ½A, when a lower output current results in the current in L2 becoming discontinuous although the current in L1 is still continuous. v.

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vi.

From equation (17.137), rearranged τ R(1 − δ ) 2 100µs × 100Ω × (1 − 35 ) 2 = = 2mH L1 crit ≥ 2δ 2 × 35 That is, if L1 is reduced from 3mH to 2mH, then both L1 and L2 enter discontinuous conduction at the same load condition, 75V, ½A, and 150Ω.

vii. For both converter inductors to be simultaneously on the verge of discontinuous conduction, equation (17.145) gives ∨

L2

=

δ

=

v ∆iL1 = o Ei ∆iL 2

L1 1 − δ 3 3mH 1A 75V 3 5 = = = = 3 2 2mH 1 − 5 50V 2 3A ♣ ∨

17.8

Comparison of basic converters

The converters considered employ an inductor to transfer energy from one dc voltage level to another dc voltage level. The basic converters comprise a switch, diode, inductor, and a capacitor. The reversible converter is a two-quadrant converter with two switches and two diodes, while the Ćuk converter uses two inductors and two capacitors. Table 17.1 summarises the main electrical features and characteristics of each basic converter. Figure 17.11 shows a plot of the voltage transformation ratios and the switch utilisation ratios of the converters considered. With reference to figure 17.11, it should be noted that the flyback step-up/stepdown converter and the Ćuk converter both invert the input polarity. Every converter can operate in any one of three inductor current modes: • • •

discontinuous continuous both continuous and discontinuous

The main converter operational features of continuous conduction compared with discontinuous inductor conduction are • The voltage transformation ratio (transfer function) is independent of the load. • Larger inductance but lower core hysteresis losses and saturation less likely. • Higher converter costs with increased volume and weight. • Worse transient response (L /R). • Power delivered is inversely proportional to load resistance, P = Vo 2 / R . In the discontinuous conduction mode, power delivery is inversely dependent on inductance. 17.8.1 Critical load current

Examination of Table 17.1 shows no obvious commonality between the various converters and their performance factors and parameters. One common feature is the relationship between critical average output current Io and the input voltage Ei at the boundary of continuous and discontinuous conduction. Equations (17.14), (17.62), and (17.92) are identical, (for all smps), that is Eτ Io = i δ (1 − δ ) (A) (17.148) 2L This quadratic expression in δ shows that the critical mean output current reduces to zero as the onstate duty cycle δ tends to zero or unity. The maximum critical load current condition, for a given input voltage Ei, is when δ = ½ and critical

I oc = Eiτ / 8L

(17.149)

Since power in equals power out, then from equation (17.148) the input average current and output voltage at the boundary of continuous conduction for all smps are related by vτ Ii = o δ (1 − δ ) (A) (17.150) 2L The maximum output current at the boundary (at δ = ½), for a given output voltage, vo, is critical

I ic = voτ / 8 L

(17.151)


The smps commonality factor reduces to Rcrit =

616

vo 2L × . E i τ δ (1 − δ )

The reversible converter, using the critical resistance equation (17.122) derived in section 17.6.3, yields twice the critical average output current given by equation (17.148). This is because its duty cycle range is restricted to half that of the other converters considered. Converter normalised equations for discontinuous conduction are shown in table 17.2. A detailed analysis summary of discontinuous inductor current operation is given in appendix 17.11.

1

step-down 3

step-up 1

¾

½

buck-boost /Cuk 2 reversible 4

¼

full bridge

Po / PT & Cuk

0

¼

½

¾

1

δ = tT/τ Figure 17.11. Transformation voltage ratios and switch utilisation ratios for five converters when operated in the continuous inductor conduction mode.

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Table 17.1 Converter characteristics comparison with continuous inductor current

converter Forward Step-down Output voltage continuous I

vo /Ei

Output voltage discontinuous I

vo /Ei

δ 1−

Output polarity with respect to input Current sampled from the supply Load current Maximum transistor voltage Maximum diode voltage

2 LI i Eiδ 2τ

Flyback Step-up

Flyback Step-up/down

1 1− δ E δ 2t 1+ i T 2L I o

−

Reversible

δ

2δ − 1

1−δ Eiδ 2τ 2 LI o

Non-inverted

Non-inverted

inverted

any

discontinuous

continuous

discontinuous

bi-directional

continuous

discontinuous

discontinuous

continuous

V

V

Ei

vo

Ei + vo

Ei

V

V

Ei

vo

Ei + vo

Ei

Ripple current

∆i

A

Eiδτ (1 − δ ) / L

Eiδτ / L

Eiδτ / L

2 Eiδτ (1 − δ ) / L

Maximum transistor current

iˆT

A

Io +

switch utilisation ratio Transistor rms current

voτ (1 − δ ) 2L

SUR

Ii +

Eiτδ 2L

IL +

Eiτδ 2L

Io +

( Ei − vo )τδ 2L

δ

1-δ

δ (1-δ)

low

high

high

low

½δ

Critical load resistance

Rcrit

Ω

2L τ (1 − δ )

2L τδ (1 − δ ) 2

2L τ (1 − δ ) 2

2(δ − ½ ) L τδ (1 − δ )

Critical inductance

Lcrit

H

½ R (1 − δ )τ

½ Rτδ (1 − δ ) 2

½ Rτ (1 − δ ) 2

½ R (1 − δ )δτ (δ − ½ )

o/p ripple voltage

∆vo

V

p-p

τ 2 (1 − δ ) 8LC

vo

τδ RC

τδ

vo

RC

τδ

vo

RC

vo

Table 17.2 Comparison of characteristics when the inductor current is discontinuous, δ < δ critical

k=

t Rτ ; δ= T τ L

δ critical ( k ) = vo IoR ( k,δ ) = Ei Ei

δD =

tD

δx =

tx

τ τ

( k,δ ) ( k,δ )

Forward step-down

δ ≤ 1−

 8  ¼ kδ 2  −1 + 1 + 2  kδ    v  v δ × 1 − o  / o Ei  Ei 

v 1− δ/ o Ei

= 1− δ − δD ∧

I L×

R ( k,δ ) Ei

2 k



k δ × 1 − 

vo   Ei 

converter Flyback step-up

k>

27 2 2 then δ (1 − δ ) ≤ k 2

½ 1 + 1 + 2kδ 2   

v o

δ /

Ei

1−δ ×

 − 1 

vo v Ei / o −1 Ei

kδ

Flyback step-up/down

δ ≤ 1−

2 k

−δ ½ k

δ/

vo Ei

 vo 1 − δ  1 + Ei 

kδ

  / v o  Ei


Ii Io Ei

+

Ii +

δ 1-δ

Ii

Io Ton

Toff

Ii +

1-δ δ

R

vo

C

Ii

Ei

vo

C

+

Io

R

Toff

L

Io Ei

Io

L Ton

618

Io Ton

+

Ii

Toff

C

δ L

R

vo

1-δ +

Figure 17.12. The three basic bidirectional current converter configurations: (a) the forward converter; (b) step-up flyback converter; and (c) step up/down flyback converter.

17.8.2 Bidirectional converters

Discontinuous inductor current can be avoided if the smps diode is parallel connected with a shunt switch as shown in figure 17.12. If the switch has bipolar conduction properties, as with the MOSFET, then it can perform three functions • Synchronised rectification: If the shunting switch conducts when the diode conducts, during period δD, then the diode is bypassed and losses are reduced to those of the MOSFET, which can be less than those of a Schottky diode. • Guaranteed continuous inductor current conduction: If the shunting switch conducts for the period 1- δD, (complement to the main smps switch) then if the inductor current falls to zero, that current can reverse with energy taken from the output capacitor. Seamless, continuous inductor current results and importantly, the voltage transfer function is then that for continuous inductor current, independent of the load resistance. • Bidirectional energy transfer: If the output diode has a shunting switch and an inverse parallel diode is added across the converter main switch (or both switches have bidirectional conduction properties, as with the MOSFET) then power can be efficiently and seamlessly transferred in either direction, between Ei and vo. The voltage polarities are unchanged – it is the current direction that reverses. The buck and boost converters interchange transfer functions when operating in the reverse direction, while the buck/boost converter has the same transfer function in both current directions of operation. 17.8.3 Isolation

In each converter, the output is not electrically isolated from the input and a transformer can be used to provide isolation. Figure 17.13 shows isolated versions of the three basic converters. The transformer turns ratio provides electrical isolation as well as matching to obtain the required output voltage range.

619

•

•

Power Electronics

Figure 17.13a illustrates an isolated version of the forward converter shown in figure 17.2. When the transistor is turned on, diode D1 conducts and L in the transformer secondary stores energy. When the transistor turns off, the diode D3 provides a current path for the release of the energy stored in L. However when the transistor turns off and D1 ceases to conduct, the stored transformer magnetising energy must be released. The winding incorporating D2 provides a path to reset the core flux. A maximum possible duty cycle exists, depending on the turns ratio of the primary winding and freewheel winding. If a 1:1 ratio (as shown) is employed, a 50 per cent duty cycle limit will ensure the required volts-second for core reset. The step-up flyback isolated converter in part b of figure 17.13 is little used. The two transistors must be driven by complementary signals. Core leakage and reset functions (and no-load operation) are facilitated by a third winding and blocking diode D2. ∆vC (1 − δ )τ 2 = vo 8 LC

∆vC δτ = vo RC

∆vC δτ = vo RC

Figure 17.13. Isolated output versions of the three basic converter configurations: (a) the forward converter; (b) step-up flyback converter; and (c) step up/down flyback converter.

•

The magnetic core in the buck-boost converter of part c of figure 17.13 performs a bifilar inductor function. When the transistor is turned on, energy is stored in the core. When the transistor is turned off, the core energy is released via the secondary winding into the capacitor. A core air gap is necessary to prevent magnetic saturation and an optional clamping winding can be employed, which operates at zero load.

The converters in parts a and c of figure 17.13 provide an opportunity to compare the main features and attributes of forward and flyback isolated converters. In the comparison it is assumed that the transformer turns ratio is 1:1:1. 17.8.3i - The isolated output, forward converter – figure 17.13a: • vo = nT δ Ei or I i = nT δ I o • The magnetic element acts as a transformer, that is, because of the relative voltage polarities of the windings, energy is transferred from the input to the output, and not stored in the core, when the switch is on. A small amount of magnetising energy, due to the magnetising current to flux the core, is built up in the core. • The magnetising flux is reset by the current through the catch (feedback) winding and D3, when the switch is off. The magnetising energy is recovered and returned to the supply Ei. • The necessary transformer Vµs balance requirement (core energy-in equals core energy-out) means the maximum duty cycle is limited to 0 ≤ δ ≤ 1/ ( 1 + nf / b ) < 1 for 1:nf/b:nsec turns ratio. For example, the duty cycle is limited to 50%, 0 ≤ δ ≤ ½, with a 1:1:1 turns ratio.


• • •

620

Because of the demagnetising winding, the off-state switch supporting voltage is Ei + vo. The blocking voltage requirement of diode D3 is Ei, vo for D1, and 2Ei for D2. The critical load resistance for continuous inductor current is independent of the transformer: 4L Rcrit ≤ (17.152) τ (1 − 2δ )

17.8.3ii - The isolated output, flyback converter – figure 17.13c: • vo = nT Eiδ /(1 − δ ) or I i = nT I oδ /(1 − δ ) • The magnetic element acts as a magnetic energy storage inductor. Because of the relative voltage polarities of the windings (dot convention), when the switch is on, energy is stored in the core and no current flows in the secondary. • The stored energy, which is due to the core magnetising flux is released (reset) as current into the load and capacitor C when the switch is off. (Unlike the forward converter, where magnetising energy is returned to Ei, not the output, vo.) Therefore there is no flyback converter duty cycle restriction, 0 ≤ δ ≤ 1. • The third winding turns ratio is configured such that energy is only returned to the supply Ei under no load conditions. • The switch supporting off-state voltage is Ei + vo. • The diode blocking voltage requirements are Ei + vo for D1 and 2Ei for D2. • The critical load resistance for continuous inductor current is independent of the transformer turns ratio when the magnetising inductance is referenced to the secondary: 4 ηT2 Lm prim 4 Lm sec (17.153) = Rcrit ≤ 2 2 τ (1 − 2δ ) τ (1 − 2δ )

The operational characteristics of each converter change considerably when the flexibility offered by tailoring the turns ratio is exploited. A multi-winding magnetic element design procedure is outlined in section 9.1.1, where the transformer turns ratio (np :ns) is not necessarily 1:1. The basic approach to any transformer (coupled circuit) problem is to transfer, or refer, all components and variables to either the transformer primary or secondary circuit, whilst maintaining power and time invariance. Thus, maintaining power-in equals power-out, and assuming a secondary to primary turns ratio of nT is to one (nT:1), gives ip

vs ns = = nT v p np

n = s = nT is n p

Z s  ns = Z p  n p

2

 2  = nT 

(17.154)

Time, that is switching frequency, power, and per unit values (δ, ∆vo /vo), are invariant. The circuit is then analysed without a transformer. Subsequently, the appropriate parameters are referred back to their original side of the magnetically coupled circuit. If the coupled circuit is used as a transformer, magnetising current (flux) builds, which must be reset to zero each cycle. Consider the transformer coupled forward converter in figure 17.13a. From Faraday’s ∧ equation, v = Ndφ / dt , and for maximum on-time duty cycle δ the conduction V-µs of the primary must equal the conduction V-µs of the feedback winding which is returning the magnetising energy to the supply Ei. E Ei ton = i toff and ton + toff = τ (17.155) nf /b That is ∧

Ei δ = ∧

δ=

( )

∧ Ei 1− δ nf /b

1 1+ nf /b

0≤δ ≤

(17.156)

1 1+ nf / b

From Faraday’s Law, the magnetizing current starts from zero and increases linearly to ∧

I M = Ei ton / LM (17.157) where LM is the magnetizing inductance referred to the primary. During the switch off period, this current falls linearly, as energy is returned to Ei. The current must reach zero before the switch is turned on again, whence the energy taken from Ei and stored as magnetic fluxing energy in the core, has been returned to the supply.

Power Electronics

621

Two examples illustrate the features of magnetically coupled circuit converters. Example 17.7 illustrates how the coupled circuit in the flyback converter acts as an inductor, storing energy from the primary source, and subsequently releasing that energy in the secondary circuit. In example 17.8, the forward converter coupled circuit acts as a transformer where energy is transferred through the core under transformer action, but in so doing, self-inductance (magnetising) energy is built up in the core, which must be periodically released if saturation is to be avoided. Relative orientation of the windings, according to the flux dot convention shown in figure 17.13, is thus important, not only the primary relative to the secondary, but also relative to the feedback winding. Io = Io = 10A 10A I i = 45A

Cs

Ei =50V

vo = 225V

300µH

Rs = 22½Ω 1:3 '

I i = 45A

Io =

30A

30A

9Cs

Ei = 50V

'

Io =

300µH

vo' = 75V Rp = 2½Ω

Figure 17.14. Isolated output step up/down flyback converter and its equivalent circuit when the secondary output is referred to the primary.

Example 17.7: Transformer coupled flyback converter

The 10kHz flyback converter in figure 17.13c operates from a 50V input and produces a 225V dc output from a 1:1:3 (1:nf/b:nsec) step-up transformer loaded with a 22½Ω resistor. The transformer magnetising inductance is 300µH, referred to the primary (or 300uH×32 = 2.7mH referred to the secondary): i. Calculate the switch duty cycle, hence transistor off-time, assuming continuous inductor current. ii. Calculate the mean input and output current. iii. Draw the transformer currents, showing the minimum and maximum values. iv. Calculate the capacitor rms ripple current and p-p voltage ripple if C = 1100µF. v. Determine • the critical load resistance • the minimum inductance for continuous inductor conduction for a 22½ Ω load. Solution

The feedback winding does not conduct during normal continuous inductor current operation. This winding can therefore be ignored for analysis during normal operation. Figure 17.14 shows secondary parameters referred to the primary, specifically vo = 225V vo' = vo / nT = 225V/3 = 75V Rs = 225Ω

Rp = Rs / nT2 = 225Ω / 32 = 22½Ω

Note that the output capacitance is transferred by a factor of nine, nT2 , since capacitive reactance is inversely proportion to capacitance (X = 1/ωC). It will be noticed that the equivalent circuit parameter values to be analysed, when referred to the primary, are the same as in example 17.4. The circuit is analysed as in example 17.4 and the essential results from example 17.4 are summarised in Table 17.3 and transferred to the secondary where appropriate. The waveform answers to part iii are shown in figure 17.15.


622

Table 17.3 Transformer coupled flyback converter analysis

Ei

V

value for primary analysis 50

vo

V

75

3

225

2½

2

22½

-2

1100

-2

parameter

RL

Ω

Co

transfer factor nT = 3 → 3

value for secondary analysis 150

3

10,000

µF

3

300

3

2700

A

30

⅓

10

Po

W

2250

invariant

2250

Ii(ave)

A

45

⅓

15

δ

p.u.

⅗

invariant

⅗

τ

µs

100

invariant

100

ton

µs

60

invariant

60

tD

µs

40

invariant

40

fs

kHz

10

invariant

10

∆iL

A

10

⅓

10/3

IL

A

75

⅓

25

A

80

⅓

80/3

IL

A

70

⅓

70/3

iCrms

A rms

36.8

⅓

13.3

37½

2

337½

20

2

3

180

LM

µH

Io(ave)

∧

IL ∨

Rcrit

Ω

3

Lcrit

µH

VDr

V

125

3

375

∆vo

mV

180

3

540

∆vo /vo

p.u.

0.24%

invariant

0.24%

Note the invariance of power, Po; normalised parameters δ, and ∆vo/vo; and time ton, tD, τ, and 1/f.

I transformer

80A

70A

70A I primary

I primary

80/3A 70/3A Io = 10A

I secondary

I secondary

70/3A Io

0µs

60 µs

100 µs

t

Figure 17.15. Currents for the transformer windings in example 17.7.

♣

Power Electronics

623

Example 17.8: Transformer coupled forward converter

The 10kHz forward converter in figure 17.13a operates from a 192V dc input and a 1:3:2 (1:nf/b:nsec) step-up transformer loaded with a 4Ω resistor. The transformer magnetising inductance is 1.2mH, referred to the primary. The secondary smps inductance is 800µH. Calculate the maximum switch duty cycle, hence transistor off-time, assuming continuous inductor current. At the maximum duty cycle: ii. Calculate the mean input and output current. iii. Draw the transformer currents, showing the minimum and maximum values. iv. Determine • the critical load resistance • the minimum inductance for continuous inductor conduction for a 4 Ω load i.

Solution i. The maximum duty cycle is determined solely by the transformer turns ratio between the primary and the feedback winding which resets the core flux. From equation (17.156) ∧ 1 δ= 1+ nf /b 1 =¼ 1+ 3 The maximum conduction time is 25% of the 100µs period, namely 25µs. The secondary output voltage is therefore vsec = δ nT Ei =

= ¼×2×192 = 96V The load current is therefore 96V/4Ω = 24A, as shown in figure 17.16a.

Figure 17.16b shows secondary parameters referred to the primary, specifically Rs = 4Ω Rp = Rs / nT2 = 4Ω / 22 = 1Ω vo = 96V vo' = vo / nT = 96V/2 = 48V Lo =800µH L'o = Lo / nT2 = 800µH/22 = 200µH Note that the output capacitance is transferred by a factor of four, nT2 , since capacitive reactance is inversely proportion to capacitance, X = 1/ωC.

Inspection of example 17.1 will show that the equivalent circuit in figure 17.16b is the same as the circuit in example 17.1, except that a magnetising branch has been added. The various operating conditions and values in example 17.1 are valid for example 17.8. ii. The mean output current is the same for both circuits (example 17.1), 48A, or 24 A when referred to the secondary circuit. The mean input current from Ei remains 12A, but the switch mean current is not 12A. Magnetising current is provided from the supply Ei through the switch, but returned to the supply Ei through diode D2, which bypasses the switch. The net magnetising energy flow is zero. The magnetising current maximum value is given by equation (17.157) ∧

I M = Ei ton / LM = 192V×25µs/1.2mH = 4A

This current increases the switch mean current from 12A to I T = 12A + ½ × δ × 4A = 12½A Figure 17.16c show the equivalent circuit when the switch is off. The output circuit functions independently of the input circuit, which is returning stored core energy to the supply Ei via the feedback winding and diode D2. Parameters have been referred to the feedback winding which has three times the turns of the primary, nf/b =3. The 192V input voltage remains the circuit reference. Equation (17.157) - Faraday’s law, referred to the feedback winding, must be satisfied during the switch off period, that is ∧

IM nf /b

=

Ei toff n 2f / b LM

4 192V×75µs = 2 3 3 × 1.2mH


624

The diode D2 voltage rating is (nf/b+1)×Ei, 768V and its mean current is I 4A = ½A I D 2 = ½ (1 − δ ) M = ½ × (1 - 0.25 ) × 3 nf / b

800µH

24A

RL = 4Ω Ei=192V

vo = 96V

1:3:2 (a) IM/3

48A

24A 800µH

200µH RL=1Ω

Ei=192V

LM

Ei=192V

vo=48V

1.2mH

RL=4Ω

10.8mH

4C

vo=96V

9LM

IM

(b)

(c)

Figure 17.16. Isolated output forward converter and its equivalent circuits when the output is referred to the primary.

iii. The three winding currents for the transformer are shown in figure 17.17. iv. The critical resistance and inductance, referred to the primary, from example 17.1 are 5⅓Ω and 37½µH. Transforming into secondary quantities, by multiplying by 22, give critical values of RL = 21⅓Ω and L = 150µH. I transformer

61A

IM =4A

57A 39A I primary

I primary

57/2A I secondary I sec

39/2A

IM

4A 4/3A

0µs

25 µs

100 µs

t

Figure 17.17. Currents for the three transformer windings in example 17.8.

♣

625

17.9

Power Electronics

Multiple-switch, balanced, isolated converters

The basic single-switch converters considered have the limitation of using their magnetic components (whether as an inductor or transformer) only in a unipolar flux mode. Since only one quadrant of the B-H characteristic is employed, these converters are generally restricted to lower powers because of the limited flux swing, which is reduced by the core remanence flux. The high-power forward converter circuits shown in figure 17.18 operate the magnetic transformer component in the bipolar or push-pull flux mode and require two or four switches. Because the transformers are fully utilised magnetically, they tend to be almost half the size of the equivalent single transistor isolated converter at power levels above 100 W. Also core saturation due to the magnetising current (flux) not being fully reset to zero each cycle, is not a major issue, since with balanced bidirectional fluxing, the average magnetising current (flux) is zero.

C

∆vC (1 − 2δ )τ 2 = vo 32 LC

C

∆vC (1 − 2δ )τ 2 = vo 16 LC

C

∆vC (1 − 2δ )τ 2 = vo 32 LC

Figure 17.18. Multiple-switch, isolated output, pulse-width modulated converters: (a) push-pull; (b) half-bridge; and (c) full-bridge.


626

17.9.1 The push-pull converter

Figure 17.18a illustrates a push-pull forward converter circuit which employs two switches and a centretapped transformer. Each switch must have the same duty cycle in order to prevent unidirectional core saturation. Because of transformer coupling action, the off switch supports twice the input voltage, 2Ei, plus any voltage associated with leakage inductance stored energy. Advantageously, no floating gate drives are required and importantly, no switch shoot through (simultaneous conduction) can occur. The voltage transfer function, for continuous inductor current conduction, is based on the equivalent secondary output circuit show in figure 17.19. Because of transformer action, the input voltage is N×Ei where N is the transformer turns ratio. When a primary switch is on, current flows in the outer loop shown in figure 17.19. That is ∧ ∨ N × Ei − vo ∆i L = i L − i L = × tΤ (17.158) L When the primary switches are off, the secondary voltage falls to zero and current continues to flow through the secondary winding due to the energy stored in L. Efficiency is increased if the diode Df is used to bypass the transformer winding, as shown in figure 17.19. The secondary winding i2R losses are decreased and minimal voltage is coupled from the secondary back into the primary circuit. The current in the inner off loop shown in figure 17.19 is given by v ∆iL = o × (τ − tΤ ) (17.159) L Equating equations (17.158) and (17.159) gives the following voltage and current transfer function t vo I i (17.160) = = 2 N T = 2Nδ 0≤δ ≤ ½ τ Ei I o The output voltage ripple is similar to that of the forward converter ∆vC ∆vo (1 − 2δ )τ 2 = = vo vo 32 LC

(17.161)

L 1 +

N +

Df

off on

Ei

Vo

N×Ei

Figure 17.19. Equivalent circuit for transformer bridge converters based on a forward converter in the secondary.

17.9.2 Bridge converters

Figures 17.18b and c show half and full-bridge isolated forward converters respectively. i. Half-bridge

In the half-bridge the transistors are switched alternately and must have the same conduction period. This ensures the core volts-second balance requirement to prevent saturation due to bias in one flux direction. Using similar analysis as for the push-pull converter in 17.9.1, the voltage transfer function of the half bridge with a forward converter output stage, for continuous inductor conduction, is given by t vo I i (17.162) = = N T = Nδ 0≤δ ≤ ½ τ I Ei o A floating base drive is required. Although the maximum winding voltage is ½Ei, the switches must support Ei in the off-state, when the complementary switch conducts.

Power Electronics

627

The output ripple voltage is given by ∆vC ∆vo (1 − 2δ )τ 2 = = vo vo 16 LC

(17.163)

ii. Full-bridge

The full bridge in figure 17.18c replaces the capacitor supplies of the half-bridge converter with switching devices. In the off-state each switch must support the rail voltage Ei and two floating gate drive circuits are required. This bridge converter is usually reserved for high-power applications. Using similar analysis as for the push-pull converter in 17.9.1, the voltage transfer function of the full bridge with a forward converter output stage, with continuous inductor conduction is given by t vo I i (17.164) = = 2 N T = 2 Nδ 0≤δ ≤ ½ τ Ei I o Any volts-second imbalance (magnetising flux build-up) can be minimised by using dc blocking capacitance Cc, as shown in figures 17.18b and c. The output ripple voltage is given by ∆vC ∆vo (1 − 2δ )τ 2 = = (17.165) 32 LC vo vo

Output stage variations

In each forward converter in figure 17.18, a single secondary transformer winding and full-wave rectifier can be used. Better copper utilisation results. If the output diode shown dashed in figure 17.18c is used, the off state loop voltage is decreased from two diode voltage drops to one. The three converters in figure 17.18 all employ the same forward converter output stage, so the critical load resistance for continuous inductor current is the same for each case, viz., 4L (17.166) Rcrit = τ (1 − 2δ ) Re-arrangement of this equation gives an expression for minimum inductance in terms of the load resistance. If the output inductor is not used, conventional unregulated transformer square-wave voltage ratio action occurs for each transformer based smps, where, independent of δ: vo I i n = = s =N (17.167) n Ei I o o

17.10

Basic generic smps transfer function mapping

The three basic smps, viz., the buck, boost and buck-boost converters, utilise a switch, diode and inductor, as shown in figure 17.20a, to perform their fundamental dc to dc conversion function. Figure 17.20b shows a general form of the circuit in figure 17.20a, where the function of the two switching elements have not be prejudged to be a diode and a unidirectional voltage and current switch. If the switch T1 in the configuration of the circuit in figure 17.20a is controlled with an on-state duty cycle of δ, then the transfer functions associated with the buck, boost and buck boost converters are realised. Although each transfer function is fixed, the output function can be modified by mapping the input parameter. For example, if the complement of the duty cycle δ is used to control T1, namely 1-δ, then in the case of the buck converter, the output voltage tracks 1-δ. The mapped transfer functions of the three basic converters, when controlled by the duty cycle complement 1-δ, are shown in table 17.4 and are plotted in figure 17.21. Practically, the same result is obtained if switch T2 in the generalised case in figure 17.20 part b and part c is controlled by δ and switch T1 is controlled by the complement, 1- δ. Generally, if the duty cycle is encoded by f(δ), any effective transfer function can be generated within the voltage range of the basic converter. For example, in the case of the buck converter, any monotonically increasing output voltage profile can be produced in the range between zero volts and the input voltage magnitude. A lookup table mapping approach provides total flexibility.


+

+

X

628

+

X

Df

X

T2

T2

Y

Y

Y

L

L

L

T1

T1

T1

Z

Z

Z

0V

0V

0V

(a)

(b)

(c)

Figure 17.20. Circuit elements of basic smps: (a) circuit diagram; (b) generalised functional circuit; and (c) specific circuit components.

Table 17.4. Mapped transfer functions duty cycle mapping

0 13½, discontinuous inductor current occurs for δ around ⅓ as given by the two (of the three) real roots of equation (17.168) associated with the local minimum turning point of the cubic equation (17.168).

Power Electronics

631

1

Io Io

= 4δ (1 − δ )

vo /Ei

step-down 4

0.8

vo

0.6

Io

δ =½

δ 0.4

Ei

×

Io

3

1−

1,½

vo

2

5

discontinuous

5

continuous 1

5

Io /Io

0 0.2

0.4

1

Io Io

0.8

0.6

0.8

= 4δ (1 − δ )

1.0

step-up

vo

5

δ = 0.6 0.4

−1

Ei

vo Ei

2½

v  δ =½ ×  o − 1  I o  Ei Io

δ

Ei

5

Ei

0.2

0

vo

δ =

1,½

123 discontinuous

0.2

continuous 1¼

Io /Io

0 0

0.2

0.4

0.6

1

Io Io

0.8

0.8

1.0

step-up/down

= 4δ (1 − δ )

vo

-4

δ = 0.6

δ

Io

δ =½

0.4

Io

×

vo Ei

-1½

1,½

discontinuous

Ei

−1

continuous -¼

0 0.2

vo

- 23

0.2

0

Ei

0.4

0.6

0.8

1.0

Figure 17.22. Characteristics for three dc-dc converters with respect to I o , when the input voltage Ei is held constant. See table 17.5.

Io /Io


632

Table 17.5. Transfer functions with constant input voltage, Ei, with respect to I o

converter

Ei constant

step-down

step-up

step-up/down

(17.4)

(17.45)

(17.75)

vo =δ Ei

vo 1 = Ei 1 − δ

vo −δ = Ei 1 − δ

vo Ei

vo −1 E δ= i vo Ei

reference equation

continuous inductor current conduction (and change of variable)

δ=

reference equation

(17.21)

vo = Ei

discontinuous inductor current conduction

δ=

(17.60)

1

vo −1 Ei

(17.91)

vo δ 2 Ei τ = 1+ Ei 2 LI o

2 LI 1+ 2 o δ τ Ei

vo Ei

vo δ 2 Eiτ =− Ei 2 LI o

normalised

vo = Ei where ∧

Io =

vo = Ei

Eiτ 8L

∧

δ = ½;

I o = I o = 1pu @ change of variable

Io ∧

=

Io change of variable δ= all with a boundary

δ = ½ + ½ 1 − I∧ o Io

conduction boundary

1 1 I 1+ 2 × ∧o 4δ Io

vo =½ Ei

 vo  1 −  Ei  Io 2 = 4δ ×  ∧ vo Io Ei vo E δ = ½ I∧ o × iv Io 1− o Ei Io ∧

Io

= 4×

vo Ei

 vo  1 −   Ei 

δ = ½ + ½ 1 − I∧ o Io

vo I = 1 + 4δ 2 / ∧ o Ei Io

= 4δ (1 − δ )

δ = ½;

Io ∧

Io

vo I = − 4δ 2 / ∧ o Ei Io

vo =2 Ei

= 4δ 2 ×

δ = ½;

1 vo −1 Ei

Io ∧

 vo   − 1 Ei Io  = 4×  2 ∧   vo Io   E  i = 4δ (1 − δ )

= −4δ 2 ×

Io

v  δ = ½ I∧ o ×  o − 1 E  Io  i

vo = −1 Ei 1 vo Ei

v δ = ½ I∧ o × o Ei Io

Io ∧

Io

= −4 ×

vo Ei

 vo  1 −   Ei  = 4δ (1 − δ )

2

Power Electronics

633

1

Ii Ii

0.8

=

4

27

× (1 − δ ) δ

2

4

δ

discontinuous

δ =

4 27

1−

0.4

1, 2 3

Ii vo

×

5

vo

δ =

Ii 0.6

vo /Ei

step-down

3

Ei

5

continuous 2 5

Ei

0.2 1

5

Ii /Ii

0 0

0.2

0.4

1

δ =

0.8

Ii Ii

0.6

+ 1−

×

0.6

vo Ei

Ii Ii

=δ

1.0 step-up

vo 5

vo

δ =

0.4

Ei

123

0.2

1¼

0 0

0.2

0.4

1

0.6

δ =

0.8

Ii

step-up/down

0.8

Ii

Ii /Ii

1.0

vo

= δ2 -4 δ =

Ii

Ei vo Ei

Ii

0.6 discontinuous

δ

vo

2½

continuous

−1

Ei

Ei

discontinuous

δ

0.8

−1

-1½

continuous

0.4

- 23

0.2 -¼ 0 0

0.2

0.4

0.6

0.8

1.0

Figure 17.23. Characteristics for three dc-dc converters with respect to I i , when the input voltage Ei is held constant. See table 17.6.

Ii /Ii


634

Table 17.6. Transfer functions with constant input voltage, Ei, with respect to I i

converter

Ei constant

step-down

step-up

step-up/down

(17.4)

(17.45)

(17.75)

vo =δ Ei

vo 1 = Ei 1 − δ

vo −δ = Ei 1 − δ

v δ= o Ei

vo −1 Ei δ= vo Ei

reference equation

(17.20)

(17.61)


vo 2 LI = 1− 2 i Ei δ τ Ei

normalised

vo 4 I =1− × ∧i Ei 27δ 2 I i

reference equation


vo = Ei

∧

Ii =

∧

Ii ∧

vo 2 = 3 Ei

δ=

δ=

4

 v  v  = 27 4 ×  1 − o   o  ∧  Ei   Ei  Ii

Ii

∧

Ii

   

= 27 4 δ 2 (1 − δ )

δ=

2

 vo   − 1  Ei 

vo −1 I i Ei ∧ × vo Ii Ei

 vo   − 1 I i  Ei  = ∧ vo Ii Ei =δ

δ = ∧I i Ii

∧

Ii where

Ii =

vo Ei

Ii

1=δ2 /

∧

Eiτ 2L

vo →∞ Ei

=δ2×

Ii

1 27 × ∧ × v I i 1− o Ei

= 27 4 δ 2 (1 − δ ) conduction boundary

Ii

∧

Ii

Ii

conduction boundary

I 1− δ 2 /  ∧i   Ii

δ = 1;

 v  = 27 4 δ 2 1 − o  ∧  Ei  Ii

Ii

vo voτδ 2 = Ei 2 LI i

1

∧

vo −1 Ei

(17.91)

1 E τδ2 1− i 2 LI i

Ii =

Ii

=

change of variable

4 Eiτ × 27 2 L

δ = ⅔;

change of variable

vo = Ei

δ=

where

where

I i = I i = 1pu @

vo = Ei

vo Ei

δ = 1;

Eiτ 2L

vo → −∞ Ei

Ii

∧

=δ 2

Ii

δ=

Ii

∧

Ii

 vo    I i  Ei  = ∧ v I i  o − 1   Ei  =δ2

δ=

Ii

∧

Ii

2

Power Electronics

635

Io

1

Io

=1−δ

vo /Ei

step-down 4

0.8

5

vo

δ = 3

0.6

Ei

5

Io

δ 0.4

δ =

2

vo

Io vo

Ei

1−

0.2

discontinuous

Ei

5

continuous 1

5

Io /Io

0 0

0.2

0.4

0.6

0.8

1.0

1

Io Io

0.8

=

4

27

× δ (1 − δ )

step-up

2

δ =

0.6

δ

δ =

0.4

vo

5

4

27

×

1, 1 3

discontinuous

0.2

Ei

1 23 continuous 1¼

Io /Io

0 0

0.2

vo

2½

vo vo Io  1 −  Ei  Ei Io 

0.4

0.6

0.8

−1

Ei

1.0

1

Io

0.8

Io

= (1 − δ )

step-up/down

2

vo

-4

δ =

0.6 -1½

δ 0.4

δ =

0.2

vo

Io

Ei

Io

discontinuous

Ei

−1

continuous

0 0.2

vo

- 23 -¼

0

Ei

0.4

0.6

0.8

1.0

Figure 17.24. Characteristics for three dc-dc converters with respect to I o , when the output voltage vo is held constant. See table 17.7.

Io /Io


636

Table 17.7. Transfer functions with constant output voltage, vo, with respect to I o

converter

vo constant

step-down

step-up

step-up/down

(17.4)

(17.45)

(17.75)

vo =δ Ei

vo 1 = Ei 1 − δ

vo −δ = Ei 1 − δ

v δ= o Ei

vo −1 Ei δ= vo Ei

reference equation

(17.20)

(17.61)


vo 2 LI = 1− 2 i Ei δ τ Ei

reference equation


normalised

vo = Ei

vo 1 I v  = 1 − 2 × ∧o ×  o  4δ Ei E Io  i  where

voτ 2L

∧

Io = ∧

I o = I o = 1pu @ change of variable

Io ∧

=

Io change of variable δ=

 vo  1 −  Ei  Io 2 =δ × 2 ∧  vo  Io    Ei  vo Ei

Io ∧

conduction boundary

Io

2

vo = Ei

Io ∧

×

Io

= 1−

1 vo 1− Ei

vo Ei

δ = 1 − I∧ o Io

vo voτδ 2 = Ei 2 LI i

 I  v 2  1 − 27 4 δ /  ∧ o ×  o    E   Io  i   2

I vo v  = δ 2 /  ∧o × o   Ei Ei   Io  where

Io =

vo = 1½ Ei

δ = ⅓;

∧

= 27 4 δ 2 ×

Io

δ=

4

δ = 0;

1

Io

 vo  vo  − 1  Ei  Ei v

27

v

× I∧ o ×  o − 1 o E  Ei I  i

 vo   − 1 E I o 27  i  = 4× 3 ∧  vo  Io    Ei  Io ∧

Io

2

= 27 4 δ (1 − δ )

2

vo =0 Ei

=δ2×

∧

Io

δ=

o

= 27 4 δ (1 − δ )

voτ 2L

∧

4 voτ × Io = 27 2 L

= 1− δ conduction boundary

1 E τ δ2 1− i 2 LI i

∧

Io

vo −1 Ei

(17.91)

1

where

vo =0 Ei

δ = 0;

δ=

vo = Ei

δ=

vo Ei

Io ∧

Io

=

vo Ei

1  vo     Ei  Io ∧

Io 1

 vo  1 −   Ei 

= (1 − δ )

δ = 1−

2

Io ∧

Io

2

2

Power Electronics

637

1

Ii Ii

= 4δ (1 − δ )

vo /Ei

step-down 4

0.8

5

vo

δ = vo

0.6

Ii

δ =½

δ 0.4

Ei vo

×

Ii

3

1−

1,½

2

5

Ei discontinuous

0.2

continuous 1

5

Ii /Ii

0 0

0.2

1

0.4

Ii Ii

0.8 0.6

0.6

0.8

= 4δ (1 − δ )

1.0

5

δ =

v  ×  o − 1 δ =½  I i  Ei

0.4

vo

step-up

Ii

δ

Ei

5

−1

Ei

vo Ei

2½ 1,½

123 discontinuous

0.2

continuous 1¼

Ii /Ii

0 0

0.2

0.4

0.6

0.8

1.0

1

Ii Ii

0.8

= 4δ (1 − δ )

0.6

δ

δ =½

0.4

Ii Ii

×

vo

step-up/down

-4

δ =

vo Ei

−1

-1½

1,½

- 23 discontinuous

continuous -¼

0 0.2

vo Ei

0.2

0

Ei

0.4

0.6

0.8

1.0

Figure 17.25. Characteristics for three dc-dc converters with respect to I i , when the output voltage vo is held constant. See table 17.8.

Ii /Ii


638

Table 17.8. Transfer functions with constant input voltage, vo, with respect to I i

converter

vo constant

step-down

step-up

step-up/down

(17.4)

(17.45)

(17.75)

vo =δ Ei

vo 1 = Ei 1 − δ

vo −δ = Ei 1 − δ

vo Ei

vo −1 E δ= i vo Ei

reference equation


δ=

reference equation

(17.21)

vo = Ei


δ=

(17.60)

1

vo −1 Ei

(17.91)

vo δ 2 voτ = 1+ Ei 2 LI i

2 LI 1+ 2 i δ τ vo

vo Ei

vo δ 2 voτ =− Ei 2 LI i

normalised

vo = Ei

vo = Ei

where ∧

Ii =

voτ 8L

∧

δ = ½;

I i = I i = 1pu @ change of variable

Ii ∧

=

Ii change of variable δ= all with a boundary

δ = ½ + ½ 1 − I∧ o Io

conduction boundary

1 1 I 1+ 2 × ∧i 4δ Ii

vo =½ Ei

 vo  1 −  Ei  Ii 2 = 4δ ×  ∧ vo Ii Ei vo E δ = ½ I∧ i × iv o I i 1− Ei Ii ∧

Ii

=4

vo Ei

 vo  1 −   Ei 

δ = ½ + ½ 1 − I∧ o Io

= 4δ (1 − δ )

vo I = 1 + 4δ 2 / ∧ i Ei Ii

δ = ½;

Ii ∧

vo =2 Ei

= 4δ 2 ×

Ii

vo I = − 4δ 2 / ∧ i Ei Ii

δ = ½;

1

Ii

vo −1 Ei

∧

Ii

 vo   − 1 Ei Ii  = 4×  2 ∧  vo  Ii    Ei  = 4δ (1 − δ )

= −4δ 2 ×

Ii

v  δ = ½ I∧ i ×  o − 1  Ei

vo = −1 Ei 1 vo Ei

v δ = ½ I∧ i × o



Ii

Ii ∧

Ii

= −4 ×

Ei

vo Ei

 vo  1 −   Ei  = 4δ (1 − δ )

2

Power Electronics

639

1

vo

Ei

vo

vo Ei

2

δ

0

4 0

−1

Ei δ

v

2

o

4δ

E

i

δ=½

v

o

vo

=

Ei

−1

E

1

δ=0 δ=1

vo

i

vo

 vo  vo  4 1 − E  E  i  i  

vo

2

Ei

2

δ=½

Ei

−1

vo

discontinuous

δ=¼

1

δ=0 δ=1

vo δ=¼

1− δ

2

27 δ2 4

=δ

Ei

( ) 1−

v

o

½

E i

discontinuous

∧

δ=½

δ=¼

0

1

δ=¼

i

=δ

Ei

  v v 4 o E 1− o E  i i

I i / Ii

=

vo

 v  4δ 21− o  Ei   vo Ei

δ=0

E

1

δ=¾

δ=½

o

=

Ei

δ=¾

v

−1

Ei

1− δ

δ=¼

27

2

( ) ( )

δ=0 ∧

1

Io / Io

δ=¼

-½

−δ

v

o

1−δ

E

=

i

-1 δ=½

− 4δ vo Ei

−δ 1−δ

2

δ=½

continuous

 v E  − v  E −1  o

i

o

i

    

discontinuous

2

−4

(

1−

-2

1

vo

Ei

Ei

)

2

∧

Ii / Ii

Ei constant

vo

=δ

2

Ei constant 0

0

Figure 17.26. Characteristics for three dc-dc converters, when the input voltage Ei is held constant.


(

27 vo 4

vo

Ei

)

vo Ei

0

−1

0

4

Ei

vo 2

(

27 4

Ei

Ei

−1

δ=½

v

o

E

δ

=

Ei

)

−1

i

o

E

i

vo

δ=¾

1− vo

vo

Ei

½

Ei = δ

 v

∧

δ=0 δ=1

=δ

Ei

δ=¾

 v  4 δ 2  1− o E i   vo Ei

δ=½



δ=¼

δ 21− o E  

i 2  vo   E i 

δ=0

−δ

1

v

o

E

4

0

2

( )

o

vo

   v  E i  1− o E  i 

δ=0 ∧

1

I i / Ii

2

i

δ=¼

δ=¼

-½

v

E

i

=

−δ

v

o

1− δ -1

δ=½

−4δ 2 vo Ei

−4

(

1−

vo constant

vo

Ei

(

discontinuous

)

E

= i

−δ 1−δ

δ=½

continuous

−1

1−δ

δ=¼

v

1

δ=½

1

2

δ=0 δ=1

o

2

2

vo

1− δ

δ=¼

−1

Ei

discontinuous

1

δ=¼

Io / I

vo

Ei

δ=½

=

( ) ( ) vo

0

3

4δ

vo

640

1−

2

vo vo

Ei

Ei

)

2

-2

0

-

vo Ei

0

0

vo constant

Figure 17.27. Characteristics for three dc-dc converters, when the output voltage vo is held constant.

641

Table 17.9. Converter parameters for discontinuous and continuous inductor conduction regions and boundaries.

t Rτ ; 0 ≤ δ = T ≤1 k= τ L

discontinuous

δ critical ( k ) = k≥

δ ≤1−

v 2 × o δ (1 − δ ) Ei

vo I R ( k , δ ) = i = Io × Ei Ei Io

δD =

δx =

∧

2

k > 27

k

δ

½ 1 + 1 + 2kδ 2   

1−

δ×

vo ± ½k δ (1 − δ ) Ei

1−

½k δ 2 ×

tτ

t twice the output current

Resonant Mode DC to DC Converters

662

Reconnecting the capacitor CR terminal not associated with Vs, to the other end of inductor LR in the half-wave circuit in figures 18.10b-e, will create four full-wave resonant switch circuits, with the commutation type, namely ZVS or ZCS, interchanged. Full and half wave operation is dependent on whether the circuit configuration allows the resonant capacitor to complete a full or half resonant sinusoidal cycle. CR parallel output

T1

CR parallel switch

CR

LR Lo CR

Vs

Lo

+ vo

D1 Co

T1

Vs

(b)

LR

D1 Co

CR

ZCS

LR

DR full - wave

CR

T1

-

½-wave (c)

LR

DR

+ vo

T1 T1 Lo Vs

T1

+ vo

D1Co

-

(a)

LR

CR

LR

full - wave CR T1

ZVS (d)

DR

T1

(e)

CR

LR

LR

DR Lo

Vs

½- wave

CR

D1 Co

+ vo

-

Lo Vs

T1

D1 Co

+ vo

-

Figure 18.10. Dc to dc resonant switch step-down converters: (a) conventional switch mode forward step-down converter; (b) and (c) half-wave zero current switching ZCS resonant switch converters; and (d) and (e) half-wave zero voltage switching ZVS resonant switch converters. Topological translations between half-wave and full-wave versions also shown.

Power Electronics

663

18.4.1 Zero-current, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with load version

The zero current switching of T1 in figure 18.11 (18.10b) can be analysed in five distinctive stages, as shown in the capacitor voltage and inductor current waveforms in figure 18.11b. The switch is turned on at to and turned off after t4 but before t5. Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with both the capacitor voltage and inductor current being zero, and the load current is freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off. Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1 conducts the output current, thereby clamping the associated inductor terminal to zero volts. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time tI = I o LR / VS (18.23)

according to iLR ( t ) =

Vs t LR

(18.24)

During this interval the resonant capacitor voltage is clamped to zero since CR is in parallel with D1 which is conducting a current decreasing from Io to zero: vc ( t ) = 0 (18.25) Time interval IIA When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally increases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to twice the supply Vs when the inductor current falls back to the load current level Io, at time t3. Time interval IIB Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle cannot reverse through the switch once the inductor current reaches zero at time t4, because of the series blocking diode (the switch must have uni-directional conduction characteristics). The capacitor voltage and current for period IIA and approximately for period IIB, are given by equations 14.60 and 14.61 with the appropriate initial conditions of io = 0 and vo = 0:  ω  vc (ωt ) = Vs  1 − o e −α t cos (ωt − φ )  ω (18.26)   ≈ Vs (1 − e −α t cos ωt )

ic (ωt ) =

Vs × e−α t × sin ωt ωL

(18.27)

If the circuit Q is high these equations can be approximated by

vC ( t ) = Vs (1 − cos ωo t ) where R

v C = 2Vs R

(18.28)

Vs sin ωo t (18.29) Zo The inductor current is the constant load current plus the capacitor current: V V (18.30) iLR ( t ) = I o + iCR ( t ) = I o + s sin ωo t where iT 1 = i LR = I o + s Zo Zo s where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.30) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with a non-zero current flow. Setting iL = 0 in equation (18.30) gives the time for period II as  IZ  (18.31) tII =  π + sin −1  o o   / ωo Vs     after which time the capacitor voltage and inductor current reach iCR ( t ) =

.


664

2   I o Z o    VC t 4 = Vs 1 + 1 −    Vs      IL t4 = 0

(18.32)

R

R

Time interval III At time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to zero volts at time t5 according to 2   I o Z o   I o Io  vC ( t ) = VC t 4 − × t = Vs 1 + 1 −  ×t (18.33)  −  CR Vs   CR    where VC t 4 is given by equation (18.32). R

R

R

The inductor current is

iLR ( t ) = 0 T1

(18.34)

LR Lo D1

CR

Vs

Io + Vs/Zo

-

(a)

ZCS

T1 on

0

+ vo

Co

T1 on

T1 off

IT1

τ Io

-Vs /LR t0

ID1

ICR

t1

t2

t3

t4

2Vs

t5

t

t0

VCR

I

IIA

IIB

III

IV

Vs

INTERVALS

Vs

-Io /CR

t

t2

t1

t5

t1

(b)

VLR (c)

IT1

IT1 Io

Vs

Io

Io Vs

Vs

Io

Io

Io

Vs

Figure 18.11. Zero current switching, ZCS, half-wave resonant switch dc to dc converter with the resonant capacitor across the output: (a) circuit; (b) waveforms; and (c) equivalents circuits.

Power Electronics

665

The time for interval III is load current dependant and is given by setting equation (18.33) to zero: 2  VC t 4 CR  I o Z o   CR  tIII = = × Vs 1 + 1 −  (18.35)   Io Io  Vs    R

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is zero, and the input inductor current is zero. At time t1 the cycle recommences. The switch off-time, interval IV, t5 to the subsequent t0, is used to control the rate at which energy is transferred to the load. Output voltage

The output voltage can be specified by either evaluating the energy from the supply, through the input resonant inductor LR, or by evaluating the average voltage across the resonant capacitor CR (or the freewheel diode D1) which is filtered by the output filter Lo - Co. By considering the input inductor energy (volt-second integral) for each period shown in the waveforms in figure 18.11b, the output energy, whence voltage, is given by V vo = s (½tI + t II + t III )

τ

2 (18.36)     Io Zo    I o Z o   CR  Vs  1  I o LR −1  × + sin + ½ + 1 + 1 − × π V       s  τ  ωo  VS  Vs    Vs   I o     where the time intervals I, II, and III are given by equations (18.23), (18.31), and (18.35) respectively, the switching frequency f s = 1/ τ , and τ > t I + tII + tIII . The output voltage based on the average capacitor voltage (after resetting time zero references) is t5 −t4  1  t4 −t1 t   vo =  Vs (1 − cos ωt ) dt + VCR t 4  1 −  dt  0 0 τ   t5 − t4   (18.37) 2 2    Io Zo  Io Zo   I o Z o    I o Z o   CR  1  Vs  −1 2 = × + ½ × Vs × 1 −   π + sin  +  × 1+ 1−   ×  τ  ωo   Vs  Vs   Vs    Vs   I o    The output voltage in equation (18.37) reduces to equation (18.36).

=

∫

∫

The minimum switch commutation period is tI + tII + tIII which limits the upper operating frequency, hence maximum output voltage. The circuit has a number of features: i. ii. iii. iv.

Turn-on and turn-off occur at zero current, hence switching losses are minimal. Increasing the switch off period (interval VI) decreases the average output voltage. At light load currents the switching frequency may become extreme low. The capacitor discharge time is tIII ≤ VCR t 4 × CR / I o , thus the output voltage is load current dependant. v. LR and CR are dimensioned such that the capacitor voltage is greater than Vs at time t4, at maximum load current Io. vi. Supply inductance is inconsequential, and decreases the inductance LR requirement. vii. Being based on the forward converter, the output voltage is less than the input voltage. The output increases with increased switching frequency. viii. If a diode in antiparallel to the switch is added as shown below figure 18.10b, reverse inductor current can flow and the output voltage is vo ≈ Vs × f s / f o . A full-wave resonant zero current switch circuit is formed.

18.4.1i - Zero-current, full-wave resonant switch converter

By adding a diode in anti-parallel to the switch, as shown in figure 18.12 (and the circuit below figure 18.10b), resonant action can continue beyond ωt ≥ π . Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with both the capacitor voltage and inductor current being zero, and the load current is freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off.


666

Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1 conducts the output current, thereby clamping the associated inductor terminal to Vs. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time 1 Zo Io (18.38) tI = I o LR / VS = ωo Vs

according to iL ( t ) = R

and also iD1

R

Vs t LR

(18.39)

V ( t ) = I o − iL ( t ) = I o − s t LR R

During this interval the resonant capacitor voltage is clamped to -Vs (with respect to input voltage positive terminal) since CR is in parallel with LR which is conducting Io: (18.40) vc ( t ) = − Vs LR

DR

CR

T1

T1 on

0

(a)

D1

T1 on

T1 off

Io + Vs/Zo

τ ILR

Io ID1

ICR t0

t1

t2

IDR

t3

t4

t5

t

t0

2Vs

I

II

III

IV

Vs

INTERVALS

Vs VCR (b) t1

t2

t5

t

t1

VLR

DR IT1

IT1 Io

Vs

IDR Io

Vs

Io

Io Vs

Vs

Io

Io

Io

(c)

Vs

Figure 18.12. Zero current switching, ZCS, full-wave resonant switch dc to dc converter with the resonant capacitor across the output: (a) circuit; (b) waveforms; and (c) equivalents circuits.

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Time interval II When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally decreases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to the opposite polarity +Vs when the inductor current falls back to the load current level Io, at time t3. Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle reverses through the switch parallel diode DR once the inductor current reaches zero at time t4.

Assuming a high circuit Q, the capacitor voltage and inductor current for period II, are given by vC ( t ) = Vs (1 − cos ωo t ) (18.41) R

V sin ωo t (18.42) Zo where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.42) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with non-zero current flow. The peak inductor current hence maximum switch current, from equation (18.42), is iLR ( t ) = I o + iC ( t ) = I o + R

.

iT 1 = i LR = I o +

Vs Zo

(18.43)

By adding a diode in anti-parallel to the switch, resonant action can continue beyond ωt ≥ π . The capacitor can resonant to a lower voltage level, hence the capacitor linear discharge period starts from a lower voltage, equation (18.44). 2  I Z   (18.44) VC t 4 = Vs  1 + 1 −  o o    Vs      The lower limit of load current for proper circuit action is therefore decreased with full wave resonant circuits. Equations (18.26) to (18.37) remain valid except the time for interval II is extended to the fourth quadrant where iL = 0 and the capacitor voltage at t4 is decreased. That is  IZ  (18.45) tII =  2π − sin −1  o o   / ωo Vs     R

Time interval III Before time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to zero volts at time t5 according to 2  I Z   I I (18.46) vC ( t ) = VC t 4 − o × t = Vs 1 + 1 −  o o   − o × t  CR Vs   CR    where VCR t 4 is given by equation (18.44). R

R


iLR ( t ) = 0

(18.47)

The time for interval III is load current dependant and is given by setting equation (18.46) to 0: 2  VC t 4 CR  I o Z o   CR  = × Vs 1 + 1 −  tIII = (18.48)   Io Io  Vs    R

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is zero, and the input inductor current is zero. At time to the cycle recommences. The switch off-time, interval IV, t5 to the subsequent to, is used to control the rate at which energy is transferred to the load. Output voltage Since switch turn-off is dependent on the resonant cycle, the output voltage does not depend on the duty cycle, but is resonant period depend according to 2π LR C R 2π v o =Vs =Vs (18.49)

τ

ωo τ


668

18.4.2 Zero-current, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with switch version

Operation of the ZCS circuit in figure 18.13 (figure 18.10c), where the capacitor CR is connected in parallel with the switch, is essentially the same as the circuit in figure 18.11. The capacitor connection produces the result that the capacitor voltage has a dc offset of Vs, meaning its voltage swings between ± Vs rather than zero and twice Vs, as in the circuit in figure 18.11. The zero current switching of T1 in figure 18.13 is analysed in five distinctive stages, as shown in the capacitor voltage and inductor current waveforms in figure 18.13b. The switch is turned on at to and turned off after t4 but before t5. Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with the inductor current being zero, the capacitor charged to Vs with the polarity shown, and the load current freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off. +

CR

T1

LR Lo + vo

D1 Co

Vs

-

ZCS T1 on

0 Io + Vs/Zo

T1 on

T1 off

IT1

τ Io ID1

ICR t0 t1

t2

t3

t4

t5

t

t0

Vs

I

II

III

IV

INTERVALS

0

t

VCR VLR

-Vs

-Vs t1

t2

t5

IT1

IT1 Io

Vs

Io

Io Vs

Vs

t1

Io

Io

Io

Vs

Figure 18.13. Zero current switching, ZCS, half-wave resonant switch dc to dc converter with resonant capacitor across the switch: (a) circuit; (b) waveforms; and (c) equivalents circuits.

Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1 conducts the output current, thereby clamping the associated inductor terminal to Vs. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time 1 Zo Io tI = I o LR / VS = (18.50) ωo Vs

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according to Vs t (18.51) LR During this interval the resonant capacitor voltage is clamped to -Vs (with respect to input voltage positive terminal) since CR is in parallel with LR which is conducting Io: vc ( t ) = − Vs (18.52) iL ( t ) = R

Time interval II When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally decreases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to the opposite polarity +Vs when the inductor current falls back to the load current level Io, at time t3.

Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle cannot reverse through the switch once the inductor current reaches zero at time t4, because of the series blocking diode (the switch must have uni-directional conduction characteristics). Assuming a high circuit Q, the capacitor voltage and inductor current for period II, are given by (18.53) vC ( t ) = −Vs cos ωo t R

V sin ωo t (18.54) Zo where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.54) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with non-zero current flow. iL ( t ) = I o + iC ( t ) = I o + R

.

Setting iL = 0 in equation (18.54) gives the time for period II as  IZ  tII =  π + sin −1  o o   / ωo Vs     at which time the capacitor voltage and inductor current are I Z  = Vs 1 −  o o  t4  Vs  IL t4 = 0

VC

(18.55)

2

(18.56)

R

R

Time interval III At time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to - Vs volts at time t5 according to I Z  × t = Vs 1 −  o o  vC ( t ) = VC t 4 − CR  Vs  where VC t 4 is given by equation (18.56). Io

R

R

2

−

Io

CR

×t

(18.57)

R


iLR ( t ) = 0

(18.58)

The time for interval III is load current dependant and is given by setting equation (18.57) to - Vs: tIII =

VC

R

t4

Io

CR

2   I o Z o   CR  = × Vs 1 + 1 −    Io Vs     

(18.59)

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is - Vs, and the input inductor current is zero. At time t1 the cycle recommences. The switch off-time, interval IV, t5 to the subsequent t0, is used to control the rate at which energy is transferred to the load.


670

Output voltage By considering the input inductor energy (volt-second integral) for each period shown in the waveforms in figure 18.13b, the output energy, whence voltage, is given by V vo = s (½tI + t II + t III )

τ

2 (18.60)     Io Zo    I o Z o   CR  Vs  1  I o LR −1  × + sin + ½ + 1 + 1 − × V π       s  VS τ  ωo   Vs    Vs   I o     where the time intervals I, II, and III are given by equations (18.50), (18.55), and (18.59) respectively, the switching frequency f s = 1/ τ , and τ > t I + tII + tIII . The output voltage based on the average diode voltage (after resetting time zero references) is t −t  1  t −t t   vo =  ∫ Vs (1 − cos ωt ) dt + ∫ VC t 4  1 −  dt  0 0 τ   t5 − t4   (18.61) 2 2    Io Zo  Io Zo   I o Z o    I o Z o   CR  1  Vs  −1 2 = ×  π + sin   + ½ × Vs × 1 −  +  × 1+ 1−   × τ  ωo   Vs  Vs   Vs    Vs   I o    The output voltage in equation (18.61) reduces to equation (18.60).

=

4

1

5

4

R

18.4.3 Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with switch version

The zero voltage switching of T1 in figure 18.14 (18.10e) can be analysed in four distinctive stages, as shown in the resonant capacitor voltage and inductor current waveforms. The switch is turned off at to and turned on after t4 but before t5. The circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with the capacitor CR voltage being zero and the load current Io being conducted by the switch and the resonant inductor, LR. The output inductor Lo is large enough such that its current, Io can be assumed constant. The switch T1 is on. Time interval I At time to the switch is turned off and the parallel capacitor CR acts as a turn-off snubber for the switch. In the interval to to t1, the supply current is provided from Vs through CR and LR. Because the load current is constant, Io, due to large Lo, the capacitor charges linearly from 0V until its voltage reaches Vs in time V C V 1 tI = s R = s Io I o ωo Z o (18.62) LR where Z o = and ωo = LR CR CR

according to vc ( t ) =

The inductor current is zero, that is

Io t × t = Vs × CR tI

iLR ( t ) = 0

(18.63) (18.64)

The freewheel diode voltage, which is related to the output voltage, is given by  I t  VD1 = Vs − vc = Vs − o × t = Vs ×  1 −  CR  tI 

(18.65)

Time interval II When the voltage across CR reaches Vs at time t1, (equation (18.62)), the load freewheel diode conducts, clamping the load voltage to zero volts. The capacitor CR and LR are free to resonant, where the initial inductor current is Io and the initial capacitor voltage is Vs. The energy in the inductor transfers to the capacitor, which increases its voltage from Vs to a maximum, at time t2, of v = V +I Z (18.66) C

s

o

o

The capacitor energy transfers back to the inductor which has resonated from + Io to – Io between times t1 to time t3. For the capacitor voltage to resonantly return to zero, Io > Vs / Zo. Between t3 and t4 the voltage Vs on CR is resonated through LR, which conducts – Io at t3, as part of the resonance process. Assuming a high circuit Q, the resonant capacitor voltage and inductor current during period II are given by

Power Electronics

671

vC ( t ) = Vs + I o Z o sin ωo t

(18.67)

R

iL

R

(t ) = I

o

cos ωo t

and the duration of interval II is  V  tII =  π + sin −1 s  / ωo I Z o o  

(18.68)

At the end of interval II the capacitor voltage is zero and the inductor and capacitor currents are iC

R

(t ) = i (t ) = I 4

4

LR

o

 V  cos ωo tII = − I o 1 −  s   Io Zo 

(18.69)

CR LR

DR

Lo

T1

+ vo

D1 Co

VD1

Vs

(a)

-

ZVS T1 off

0 Vs + Io Zo

T1 off

T1 on

VCR

τ

Vs VD1

Vo t0 t1

t2

t3

t4

t5

t6 V

Io

s

t

t0 Io

L

R

I

II

III

IV

INTERVALS

IT1

0

(b) t

ICR ILR -Io t1

t2

t5

t6

t1 (c)

0V

ILR

ILR

ILR Io

Io

Vs

Vs

ID1

ILR Io

Vs

ID1

Io

Vs

Figure 18.14. Zero voltage switching, ZVS, half-wave, resonant switch dc to dc converter: (a) circuit; (b) waveforms; and (c) equivalents circuits.


and

vCR ( tII ) = 0

672

(18.70)

The freewheel diode current at the end of interval II is  V  iD1 ( t4 ) = I o + I o 1 −  s   Io Zo 

(18.71)

Time interval III At time t4 the voltage on CR attempts to reverse, but is clamped to zero by diode DR. The inductor energy is returned to the supply Vs via diode DR and the freewheel diode D1. The inductor current decreases linearly to zero during the period t4 to t5. During this period the switch T1 is turned on. No turn-on losses occur because the diode DR in parallel with T1 is conducting during the period the switch is turned on, that is, the switch voltage is zero and the switch T1 can be turned on with zero voltage, ZVS. With the switch on at time t5 the current in the inductor LR reverses and builds up, linearly to Io at time t6. The current slope is supply Vs dependant, according to Vs = LR di/dt, that is V iL ( t ) = iD ( t ) = s t + I o cos ωo t II (18.72) LR and the time of interval III is load current dependant: I L t III = o R × (1 − cos ωo t II ) (18.73) Vs The freewheel diode current is given by i D 1 (t ) = I o + i DR (t ) (18.74) R

R

Time interval IV At t6, the supply Vs provides all the load current through the switch resonant inductor, and the diode D1 recovers with a controlled di/dt given by Vs /LR. The freewheel diode Df supports the supply voltage Vs. The switch conduction interval IV, t6 to the subsequent to when the switch is turned off, is used to control the rate at which energy is transferred to the load. Output voltage

The output voltage can be derived from the diode voltage (shown hatched in figure 18.14b) since this voltage is averaged by the output L-C filter. 1 vo = ( Volt × second area of interval I + Volt × second area of interval IV )

τ

=

Vs

τ

= 2π

(½t

1

+ τ − t6 ) = Vs (1 − f s ( t6 − ½t1 ) )

Vs   Io Zo  1 −  ½ + 2π Vs ωoτ  

(18.75)

   

The circuit has a number of features: i. ii. iii. iv.

Switch turn-on and turn-off both occur at zero voltage, hence switching losses are minimal. At light load currents the switching frequency may become extreme high. The inductor defluxing time is tIII ≤ I L tII × LR / Vs , hence the output voltage is load current dependant. LR and CR are dimensioned such that the inductor current is less than zero (being returned to the supply Vs) at time t5, at maximum load current Io. Also Io>Vs/Zo. v. Being based on the forward converter, the output voltage is less than the input voltage. Increasing the switching frequency decreases the output voltage since τ - t5 is decreased in equation (18.75). R

18.4.3i - Zero-voltage, full-wave resonant switch converter

By removing the supply return diode in the half-wave ZVS converter in figure 18.10e (figure 18.14) a full wave ZVS resonant converter is formed, where the capacitor sinusoidal oscillation can continue past π, t4, as shown in figure 18.15. Consequently, the inductor current attains a level closer to the load level, Io, before the capacitor voltage oscillation is complete, thereby shortening the cycle time.

Power Electronics

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18.4.4 Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with load version

Operation of the ZVS circuit in figure 18.10d, where the capacitor CR is connected in parallel with the load circuit (the freewheel diode D1), is essentially the same as the circuit in figure 18.14. The capacitor connection produces the result that the capacitor voltage has a dc offset of Vs, meaning its voltage swings between + Vs and -Io Zo, rather than zero and Vs - Io Zo, as in the ZVS circuit considered in 18.4.3. Specifically the inductor waveforms and expressions are unchanged, as is the output voltage expression (18.75). The expression for the time of each interval is the same and the capacitor voltage waveform equations are negated, with Vs then added. Any dc supply inductance must be decoupled when using the ZVS circuit in figure 18.10d. It will be noticed that, at a given load current Io, a ZCS converter has a predetermined on-time, while a ZVS converter has a predetermined off-time. CR LR

T1

D1

T1 off

(a)

T1 off

T1 on

Vs + Io Zo

VCR Vs VD1

VLR

t0

t1

t2

t3

VT1

t4

t5

t

t0

2Io

I

II

III

IV

Io

INTERVALS

(b)

ILR ILR

ICR

ICR

0

t1

t2

ICR

t5

t1

-Io

Figure 18.15. Zero voltage switching, ZVS, full-wave resonant switch dc to dc converter with the resonant capacitor across the switch: (a) circuit and (b) waveforms.

Example 18.2: Zero-current, resonant-switch, step-down dc-to-dc converter - ½ wave

The ZCS resonant dc step-down voltage converter in figure 18.11a produces an output voltage for the armature of a high voltage dc motor and operates from the voltage produced from the 50Hz ac mains rectified, 340V dc, with an L-C dc link filter. The resonant circuit parameters are LR = 100µH, CR = 0.47µF, and the high frequency ac resistance of the resonant circuit is Rc = 1Ω. Calculate i. the circuit Zo, Q, and ωo ii. the maximum output current to ensure ZCS occurs iii. the maximum operating frequency, represented by the time between switch turn on and the freewheel diode recommencing conduction, at maximum load current


674

iv. the average diode voltage (capacitor voltage), hence load voltage at the maximum frequency v. switching frequency for vo = 170V dc and RL = 17Ω, peak input current, and diode maximum reverse voltage. Solution i. The characteristic impedance is given by LR 100µH Zo = = = 14.6Ω CR 0.47µF

The resonant circuit Q is Zo 100µH = /1Ω = 14.6 Rc 0.47µF For this high Q, the circuit resonant frequency and damped frequency will be almost the same, that is Q=

ω ≈ ωo = 1/ LR CR = 1/ 100µH × 0.47µF = 146 krad/s = 2π f f = 146 krad/s /2π = 23.25 kHz or T = 43µ s

ii. For zero current switching, the load current must not be greater than the peak resonant current, that is I o < Vs / Z o = 340V/14.6Ω = 23.3A iii. The commutation period comprises the four intervals, I to IV, shown in figure 18.11b. Interval I The switch turns on and the inductor current rises from 0A to 23.3A in a time given by tI = LR ∆I / Vs =100µH×23.3A/340V = 6.85µs Interval II These two sub-intervals take over half a resonant cycle to complete. Assuming action is purely sinusoidal resonance then from equation (18.31)  IZ  tII =  π + sin −1  o o   / ωo V s    −1 23.3A × 14.6Ω /146krad/s = 32.27µs = π + sin 340V The capacitor voltage at the end of this period is given by VC t 4 = Vs (1 − cos ωo t II )

(

))

(

R

= 340V × (1 − cos 3 2 π ) = 340V

Interval III The capacitor voltage must discharge from 340V dc to zero volts, providing the 23.3A load current. That is tIV = VC t 4 × CR / I o R

= 340V×0.47µF/23.3A = 6.86µs The minimum commutation cycle time is therefore 6.85+32.27+6.86 = 46µs. operating frequency is 21.75kHz.

Thus the maximum

iv. The output voltage vo is the average reverse voltage of freewheel diode D1, which is in parallel with the resonant capacitor CR. Integration of the capacitor voltage shown in figure 18.11b gives equation (18.37) t −t  1  t −t t   vo =  ∫ Vs (1 − cos ωt ) dt + ∫ VC t 4  1 −  dt  0 0 t5   t5 − t4   6.86µs  32.27µs  1 t   340V × (1 − cos ωt ) d ωt + ∫ 340V ×  1 − = × ∫  dt  0 46µs  o  6.86µs   1    3π  43µs +1 × + ½ × 340V × 6.86µs  = × 340V ×  46µs  2 2 π    4

1

5

4

R

=

1 × [13292Vµs + 1166Vµs ] = 314.3Vdc 46µs

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The maximum output voltage is 314V dc. Alternatively, using the input inductor energy based equation (18.36): V vo = s (½tI + t II + III + t IV )

τ

340V = × (½ × 6.85µs + 32.25µs + 6.86µs ) = 314.4V 46µs

v. When the output current is vo /RL=170V/17Ω=10A, the operating frequency is obtained from equation (18.36)     −1  I o Z o     π + sin  2     I Z  V  I L C   Vs   + Vs 1 + 1 −  o o   × R  vo = s ×  ½ o R +    VS τ ωo  Vs   I o          −1  10A × 14.6Ω   2    π + sin  340V  340V  10A × 100µH     10A × 14.6Ω  170V = × ½× + + 340V × 1 + 1 −     τ 340V 146krad/s 340V      That is, τ = 108.2µs, or fs = 9.25kHz. The peak input current is the peak inductor current is V 340V I i /p = I L = I o + s = 10A + = 33.3A Zo 14.6Ω The diode peak reverse voltage is 2×Vs = 640V ♣

  0.47µF   ×  10 A    

R

Example 18.3: Zero-current, resonant-switch, step-down dc-to-dc converter – full-wave

In example 18.2, a diode is connected in anti-parallel with the switch (figure 18.12), forming a quasi resonant full-wave switch, dc converter. Using the data in example 18.2: i. Determine the maximum operating frequency with a 10A load current. ii. Repeat the calculations when an infinite Q is not assumed. Solution

Using the data in example 18.2:

ωo = 1/ LR CR = 1/ 100µH × 0.47µF = 146 krad/s Zo =

LR 100µH = = 14.6Ω CR 0.47µF

α=

Q=

Zo 100µH = /1Ω = 14.6 Rc 0.47µF

R 1Ω = = 5, 000 2 L 2 × 100µH

ω = ωo2 − α 2 =

(146krad/s )

2

− 0.0052 = 146.1 krad/s

i. Three intervals are involved. Interval I is given by equation (18.24) tI = LR ∆I / Vs =100µH×10A/340V = 2.94µs The time for interval II is given by equation (18.45)  I Z  tII =  2π − sin −1  o o   / ωo V s   

(

(

= 2π − sin −1 10A × 14.6Ω

340V

)) /146krad/s = 40.0µs

The capacitor voltage at the end of interval II is VC t 4 = Vs (1 − cos ωo t II ) R

= 340V × (1 − cos (146krad/s × 40.0µs )) = 32.8V


676

Interval III The capacitor voltage must discharge from 32.8V dc to zero volts, providing the 10A load current. That is tIV = VC t 4 × CR / I o R

= 32.8V×0.47µF/10A = 1.5µs The minimum commutation cycle time is therefore 2.94 + 40 + 1.5 = 44.44µs. Thus the maximum operating frequency is 22.5kHz. ii. Circuit Q does not affect the first interval, which from part i. requires 2.94µs. When a finite Q of 14.6 is used, equations (18.26) and (18.27) are employed for the second interval, the resonant part of the cycle. From equation (18.27) V ic (ωt ) = s × e −α t × sin ωt ωL − 1Ω t 340V −10 A = × e 2×100µH × sin (146krad/s × t ) 146krad/s × 100µH which yields t = 39.27µs. The capacitor voltage at this time is given by equation (18.26), that is vc (ω × t ) = Vs (1 − e −α t cos ωt ) vc (146krad/s × 39.27µs) = 340V × (1 − e −5,000×39.27µs × cos (146krad/s × 39.27µs ) ) = 101.8V The time for interval III is given by equation (18.35), that is VC t 4 CR 101.8V × 0.47µF tIII = R = = 4.78µs 10A Io The minimum commutation cycle time is therefore 2.94 + 39.27 + 4.78 = 47.0µs. Thus the maximum operating frequency is 21.3kHz, which is required for maximum voltage output at 10A. The main effect of a finite Q is to result in a higher voltage being retained on the capacitor to be discharged into the load at a constant rate, during interval III. Never-the-less this voltage is much less than that retained in the half-wave resonant switch case. ♣

Example 18.4: Zero-voltage, resonant-switch, step-down dc-to-dc converter - ½ wave

The zero voltage resonant switch converter in figure 18.14 operates under the following conditions: Io = 25A Vs = 192V LR = 10µH CR = 0.1µF Determine i. ii. iii. iv.

the minimum output current the switching frequency fs for vo = 48V switch average current and the peak switch/diode/capacitor voltage.

Solution

ωo =

1 LR CR

=

1 10µH × 0.1µF Zo =

= 1× 106 rad/s that is f o = 159.2kHz

LR 10µH = = 10Ω CR 0.1µF

i. For proper resonant action the maximum average output current must satisfy, I o > Vs / Z o , that is Vs 192V = = 19.2A Zo 10Ω Since the load current, 25A is larger than the minimum current requirement, 19.2A, the switch voltage will be reduced zero giving ZVS turn-off. ∨

Io =

ii. The period of interval I is given by equation (18.62), that is V C 192V × 0.1µF tI = s R = = 0.768µs Io 25A

Power Electronics

677

The period of interval II is given by equation (18.68), that is  V  192V   6 tII = t3 − t1 =  π + sin −1 s  / ωo =  π + sin −1  /10 rad/s = 4.017µs Io Zo  25A × 10Ω    The period for the constant current period III is given by equation (18.73) I L 25A × 10µH t III = o R × (1 − cos ωo t I 1 ) = × 1 − cos (106 × 4.017µs ) = 2.136µs Vs 192V After re-arranging equation (18.75), the switching frequency is given by  vo  48V   1 −  1 −  V 192V s    fs =  = = 114.7kHz t5 − ½t1 ( 0.768µs + 4.017µs + 2.136µs − ½ × 0.768µs )

(

)

iii. The switch current is shown by hatched dots in figure 18.14. The average value is dominated by interval IV, with a small contribution in interval II between t5 and t6.  I  ½ × t III + (τ − t6 )  IT = o ×   τ  1 + cos ωo t II   ½ × 2.136µs 1    = 25A × 114.7kHz  + − + + 0.768µs 4.017µs 2.136µs ( )   1 + cos (106 × 4.017µs )  114.7kHz   = 7.0A iv. The peak switch/diode/capacitor voltage is given by equation (18.66), namely v = V +I Z C

s

o

o

= 192V + 25A × 10Ω = 442V ♣

18.5

Resonant-switch, dc-to-dc step-up voltage converters

18.5.1 ZCS resonant-switch, dc-to-dc step-up voltage converters

The zero current resonant ZCS (and ZVS) principle can be applied to the step-up converter (and buckboost converter), as shown in figure 18.16b. The resonant L-C circuit around the switch does not affect the primary boosting function, but only facilitates resonant switching of switch T. But now the output voltage is determined by the switch off-time. When the switch T is off, the input inductor L provides near constant current to the output circuit through diode D. The inductor current Ii comprises the load current Io and the output capacitor current Ic. The resonant capacitor CR is charged to the output voltage vo, as is the output capacitor C. Period 1: tP1 When the switch is turned on at to, the input current Ii is progressively diverted to the resonant inductor LR as its current builds up linearly according to

i LR (t ) =

vo t LR

(18.76)

The current to the output circuit, ID, through diode D, decreases linearly according to

i D (t ) = I i − i LR (t ) = I i −

vo t LR

(18.77)

At time t1 the resonant inductor consumes all the input current, when

tP1 =

LR I i vo

(18.78)

Period 2: tP2 The resonant capacitor can now resonate through LR and the switch T. The inductor resonant current is superimposed on the constant input current, the constant current not producing any voltage across the inductor since di/dt is zero for a constant current. The inductor, hence switch, current is

i LR (t ) = I i +

vo sin ωt Z

(18.79)


Z =

where

LR 1 and ω = CR LR C R

while the resonant capacitor current is

i CR (t ) = − Ii

vo sin ωt Z Io

D L

D T

+

(18.80) Ii

Io

L Ei

678

+

R

vo

Vs

IC

LR

+

CR

+

R

vo

T C

C DR

switch mode

ZCS full-wave

(a)

(b)

T on

T on

T off

Ii + vo / Z ILR Ii ID

ICR

t0

t1

t2

t3

t4

IDR

t5

t6

t

t0

-Ii

I

II

III

IV

vo

INTERVALS

VCR VLR

LR

VLR

VLR

0

t1

t2

t6

VCR

t1

(c)

-vo

Figure 18.16. Zero current switching, ZCS, full-wave resonant switch dc to dc step-up voltage converter: (a) conventional smps circuit; (b) ZCS resonant circuit; and (c) waveforms.

The resonant capacitor and inductor are in parallel hence

v LR (t ) = v CR (t ) = LR

di LR = v o sin ωt t

(18.81)

The maximum switch capacitor and inductor currents occur at t2, namely ωt = ½π , when

iCR = −

vo Z

iT = i LR = I i +

vo Z

(18.82)

The resonant capacitor current is zero when the inductor current falls back to the input current level Ii, that is, at time t3 when ωt = π .

Power Electronics

679

The oscillation continues according to equation (18.79) and the resonant inductor current falls to zero at t3, namely time ZI 1 (18.83) t LR =0 = π + sin−1 i

ω

vo

when the resonant circuit voltage from equation (18.81) is

v LR (t LR =0 ) = v CR (t LR = 0 ) = −v o and the resonant capacitor current is

 ZI  1− i   vo 

2

(18.84)

i CR (t LR =0 ) = I i

(18.85)

The input current now charges the resonant capacitor with a constant current Io. During period 2, all the load current Io is provided by the output capacitor C, and the output diode D is reverse biased. Due to the resonant capacitor retaining a negative voltage at time t4, the resonant oscillation current reverses for a negative half resonant cycle through the switch antiparallel diode DR. During this period when the antiparallel diode DR conducts, the switch can be turned off under a zero current condition, ZCS. The inductor current returns to zero at time t5 ZI  1 (18.86) t P 2 = 2π − sin−1 i  ω vo  The capacitor voltage is given by equation (18.81) at the time tP2, namely

v LR (t P 3 ) = v CR (t P 3 ) = v o sin ωt P 3 = v o

 ZI  1− i   vo 

2

(18.87)

Period 3: tP3 The constant input current Ii charges the resonant capacitor CR linearly to the output voltage level vo. At this voltage the output capacitor C ceases to provide load current Io since diode D conducts and the input current provides the load current Io and replenishes to output capacitor C with the remainder of the input current, Ii - Io. The charging time of the resonant capacitor CR is load current magnitude Io dependent.

v CR (t ) = v CR (t P 3 ) +

Ii t CR

(18.88)

18.5.2 ZVS resonant-switch, dc-to-dc step-up voltage converters

The alternative boost resonant ZVS converter in figure 18.17a uses a constant current input as in figure 14.35 in chapter 14.3.4, but the output is half wave rectified by the diode Drect. Initially, before to, the switch is on and the load requirement Io is being provided by the output capacitor C. The large input inductance ensures a constant input current Ii, which is conducted by the switch T. The resonant circuit capacitor voltage is zero, as is the initial resonant inductor current. The switch T is turned off at to and the resonant circuit waveforms as in figure 18.17 parts b and c occur. Period 1: tP1 The resonant capacitor charges with the constant input current which is diverted by the turn-off of switch T. The capacitor and parallel connected switch voltages increases according to

VT (t ) = VCR (t ) =

Ii t CR

(18.89)

The capacitor and switch voltage rise linearly until equal to the output voltage vo, when the output rectifying diode becomes forward biased at time t1. The time for this first period is

tP1 =

vo C Ii R

(18.90)

Period 2: tP2 The output rectifying diode Drect is able to conducts and allows L-C resonance between LR and CR where the inductor is clamped to the output voltage vo and both LR and CR are fed from the constant current


680

source Ii. These two dc conditions do not prevent an ac resonant oscillation from occurring. The voltage across the capacitor increasing from vo at time t1 according to v CR (t ) = v o + I i Z sin ωt (18.91) where Z =

LR 1 and ω = CR LR C R

The inductor voltage hence current are v LR (t ) = v o − v CR (t ) = −I i Z sin ωt

(18.92)

i LR (t ) = I i (1 − cos ωt )

This inductor current replenishes to output capacitor C whilst providing a portion of the load current Io. The capacitor current resonantly decreases from Ii according to i CR (t ) = I i − i LR = I i cos ωt (18.93) This period continues until the capacitor voltage given by equation (18.91) reaches zero at time t4. This zero voltage condition is necessary if the switch is to turn-on with zero voltage and from equation (18.91) a zero voltage condition occurs provided Ii Z > vo. The capacitor voltage reaches zero and attempts to reverse at time t4. The duration of the resonant period is v  π + sin−1  o   Ii Z  (18.94) tP 2 =

ω

The inductor current (whence capacitor current) at the instant t4 is 2  V   i LR (t 2 ) = I i 1 + 1 −  o     I i Z     Vo    Ii Z 

i CR (t 2 ) = i LR (t 2 ) − I i = I i 1 − 

(18.95)

2

Period 3: tP3 At time t4 the diode DR conducts, preventing the resonant capacitor from charging negatively. The resonant inductor releases its energy into the load circuit at a constant voltage vo, according to 2   Vo   v o  (18.96) i LR (t ) = I i 1 + 1 −   − t  I i Z   LR   

The diode DR current decreases linearly to zero at time t5 according to 2

 Vo  v o  + t LR  Ii Z 

i DR (t ) = I i − i LR (t ) = −I i 1 − 

(18.97)

And reaches zero at time t5 after a period 2

2

V  V  I t P 3a = (18.98) 1 −  o  = LR i 1 −  o  ω vo vo  Ii Z   Ii Z  At time t5, the resonant inductor current is the input current Ii and the switch is turned on between t4 and t5 in order to achieved zero voltage turn-on ZVS. The inductor current continues to fall at the same rate to zero as the switch current linearly increases to Ii 1 Ii Z

iT (t ) = I i − I LR (t ) =

vo t LR

(18.99)

The inductor current reaches zero time t6 that is input current Ii (hence load current Io) dependent. The time for the inductor current to fall from the input current level Ii at time t5 to zero at time t6 is:

t P 3b = LR

Ii vo

(18.100)

The time for the third period (t3 to t6) is  V   Ii  1+ 1− o   vo   Ii Z   2

t P 3 = T P 3a + t P 3b = LR

(18.101)

  At time t6 the switch conducts the input current Ii. and can be turned off so as to control the output voltage vo.

Power Electronics

681

Ii

+

Drect

LR

L

T

IC

CR

DR

Io

R

+

Vs

vo

C

(a)

ZVS

T off

T off

T on

τ

0

vo + Ii Z

VCR

vo Vs

t0 t1

t2

t3

t4

t5

t6

t

t0

(b)

ILR ILR

V

o

L

R

Ii

Ii

I

II

III

IT

IV

INTERVALS

0 t

ICR

(c) -Ii

t1

t2

t5

t6

t1

Figure 18.17. Zero current switching, ZVS, full-wave resonant switch dc to dc step-up voltage converter: (a) ZCS resonant circuit; (b) resonant capacitor voltage; and (c) current waveforms.

18.6

Appendix: Matrices of resonant switch buck, boost, and buck/boost converters

A series switch diode may not be necessary when an inverse parallel diode is used, as with full-wave ZCS and half-wave ZVS circuits. In the following circuits, the series diode (preferably in the drain circuit) is used to block the MOSFET internal parasitic diode which may have poor recovery characteristics.

Resonant Mode DC to DC Converters Ii

Ei

Io

L

T

+

682

+

R

vo vo ≤ Ei

C

ZCS full-wave

ZCS half-wave Ii

Ii

Io

L

LR

LR Ei

+

D1

T

+

CR

R

vo

Ei

+

T

D1

+

CR

CR

CR

Ii

Io

L

+

D1

T

+

R

vo

Ei

+

D1

T

+

Ii

LR D1

+

CR

R

vo

Ei

+

T

D1

+

CR

CR

CR

Ii

Io

L

+

T

vo

Io

L

LR

LR Ei

R

C

C

Ii

Io

L

LR T

vo

ZVS half-wave

Ii

Io

L

R

C

add switch antiparallel diode subtract

ZVS full-wave

+

Io

L

C

Ei

vo

LR

LR Ei

R

C

C

Ii

Io

L

D1

+

R

vo

Ei

+

T

D1

C

Figure 18.17. Forward (buck) voltage converter resonant switch circuits.

+ C

R

vo

Power Electronics

683

Ii

Io

L Ei

D T

+

+

vo

R

vo ≥ Ei

C

ZCS full-wave

ZCS half-wave Ii

Ii

Io

D

L

L Ei

LR

+

+

CR

CR

Ii

R

vo

Ei

LR

+

T

R

vo

L Ei

LR

+

vo

R

vo

C

ZVS half-wave

Ii

Io

D

+ T


Ii

R

Io

D

C

ZVS full-wave

Io

D L

L LR

+ CR

+ T

Ii

R

vo

Ei

CR

Ii

Io

R

vo

C

Io

D L

LR CR

+ T

C

D

+

LR

+

L Ei

+ T

CR

Ii

L

Ei

CR

C

Io

D

+

LR

+

C

T

Ei

Io

D

+ T

C

R

vo

Ei

LR

+ CR

+ T

Figure 18.18. Setup (boost) voltage converter resonant switch circuits.

C

R

vo


Ii

Ei

Io

D

T

+

684

C R

L

vo vo ≤ 0

+

ZCS full-wave

ZCS half-wave Ii

Ii

Io

D

LR

LR Ei

+

L

T

C

CR

R

vo

Ei

+

T

L

C

CR

CR

CR

Ii

Io

D

+

L

T

C

R

vo

Ei

+

L

T

C

Ii

LR L

C

CR

R

vo

Ei

+

T

L

C

CR

CR

CR

Ii

Io

D

+

T

vo

Io

D

LR

LR Ei

R

+

+

Ii

Io

D

LR T

vo

ZVS half-wave

Ii

Io

D

R

+


ZVS full-wave

+

Io

D

+

Ei

vo

LR

LR Ei

R

+

+

Ii

Io

D

L

C

R

vo

Ei

+

T

L

+

Figure 18.19. Setup/down (buck/boost) voltage converter resonant switch circuits.

C +

R

vo

Power Electronics

685

Table 18.2 Characteristics of resonant tank circuits

characteristic

series

parallel

series/parallel

constant

Load dependent

Load dependent

Open circuit output

OK

Large current near resonance ωo

Short circuit output

High current near resonance ωo

Protected by L at all ω

Large current near resonance ωo High current near resonance ωo

High at no load and light loads

Good light load regulation but low efficiency

Resonant frequency ωo

Output voltage frequency sensitivity

OK but extra resonant component

Reading list

Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1997. Mohan, N., et al., Power Electronics, 3rd Edition, Wiley International, 2003. Thorborg, K., Power Electronics – in theory and practice, Chartwell-Bratt, 1993.

Problems

Series resonant dc to dc converter 18.1. The series resonant dc converter in figure 18.1a operates from a 340V dc supply at 100kHz with a 17Ω load. If the series L-C resonant components are 100µH and 47nF, determine the output voltage assuming high resonant circuit Q. 18.2 If the operating frequency in problem 18.1 is decreased to 50kHz, determine suitable L-C values if the output voltage to be halved. Parallel resonant dc to dc converter 18.3. The series resonant dc converter in figure 18.5a operates from a 340V dc supply at 100kHz with a 17Ω load. If the parallel L-C resonant components are 10µH and 470nF, determine the output voltage assuming high resonant circuit Q. 18.4 If the operating frequency in problem 18.3 is decreased to 50kHz, determine suitable L-C values if the output voltage to be halved. Zero-current resonant switch converter 18.5 The zero current resonant switch converter in figure 18.11a operates with a 20V dc input supply and resonant L-C values of 5µH and 10nF, and a 5A output load requirement. Determine i. the output voltage if the switching frequency is 100kHz ii. the switching frequency if the output voltage is 10V In each case determine the maximum capacitor voltage and maximum inductor current. Zero-voltage resonant switch converter 18.5 The zero current resonant switch converter in figure 18.14a operates with a 20V dc input supply and resonant L-C values of 10µH and 100nF, and a 5A output load requirement. Determine i. the output voltage if the switching frequency is 100kHz ii. the switching frequency if the output voltage is 10V In each case determine the maximum capacitor voltage and maximum inductor current.


Blank

686

CHAPTER

19

HV Direct-Current Transmission

Originally electrical power generation, transmission, and distribution systems were direct current. The advent of the three-phase induction motor and the ability of transformers to converter one ac voltage to another ac voltage level (at the same frequency), saw the unassailable rise to dominance of ac electrical power systems. But for long distance electrical power transmission, of just a few hundred kilometres of typically about 200 to 350km, a dc transmission system is a viable possibility. For underwater or underground electrical power transmission, ac may not be viable at just 50km due to high capacitive charging currents because of the close proximity of the cables (particularly subsea cables). The highest functional dc voltage for dc transmission, HVDC, is ±600kV over 785km and 805km transmission lines in Brazil. Each of the two bipolar dc transmission systems carry 3.15GW. Also involved are three, threephase 765kV ac lines which are 1GVAr variable capacitor series compensated (FACTS) at two intermediate substations.

19.1

HVDC Electrical Power Transmission

Electrical power is generated in ac form and is also usually distributed and consumed in an ac form. Its long distance transmission between these two stages may be an ac or a dc transmission system. In a high-voltage dc (HVDC) system the generated 50/60Hz ac is controlled-rectified to dc, transmitted, then at the receiving end, converted from dc back to 50/60Hz ac. A HVDC system is two ac systems connected by a dc transmission system, where the ac systems can be totally independent. The dc-link of a HVDC transmission system is either • A controlled voltage dc-link or • A controlled current dc-link. A HVDC controlled current link has the following characteristics. The link in highly inductive, achieved with series inductance at each end. The converter/inverter technology is operated in a controlled current mode, thus the converter/inverter devices require reverse voltage blocking ability. Symmetrical blocking thyristor devices are applicable, but such devices are restricted to line commutation and phased control. A HVDC controlled voltage link has the following characteristics. The link in highly capacitive, achieved with parallel connected capacitance at each end. The converter/inverter technology is operated in a controlled voltage mode, thus the converter/inverter devices can be uni-directional voltage blocking IGBT technology. Since devices are gate commutatable, a switching frequency of kHz’s is possible, thus PWM techniques can be employed for harmonic minimisation.

BWW

688

Y Y

q =3 r =1 s = 2 p=qxrxs p = 12 Y Y

Power Electronics

Y Y

Id

Y Y

Id

Y Y

(a)

Id

Y ∆

Y Y

∆ Y

(b)

q =3 r =1 s = 4 p=qxrxs p = 12

Y ∆

∆ Y

Y Y

Y Y

Y ∆

Id

∆ Y

(c)

Figure 19.1. HVDC transmission systems: (a) 6 pulse monopole, (b) 12 pulse monopole, and (c) 12 pulse bipolar, converter bridge configurations.

19.2

HVDC Configurations

There are a number of different configurations for transmitting dc power, depending on the number of cables employed. Each uses a three-phase fully-controlled thyristor converter (rectifier) coupled through a dc link to another identical three-phase fully-controlled thyristor converter (inverter). Both converters have the same modular structure except the converter connections to the dc link are interchanged for one converter, hence power flow is fully reversible. Since the valves can only conduct current in one direction, power reversal is achieved by changing the polarity of the dc link terminal voltages through control of the converter thyristor firing delay angles. The rectification mode (positive dc link voltage) is achieved with thyristor firing angles of 0 < α < ½π while inversion (negative dc link voltage) is achieved with firing angles of ½π < α < π. Because one converter terminal connection is reversed, a rectifying voltage (0 < α < ½π) is opposed by an inverting voltage (½π < α < π) – subtractive not additive voltages. 19.2i - Monopole and earth return The monopole configurations shown in figure 19.1 parts a and b (6 pulse and 12 pulse respectively) use just one transmission cable and earth is used as the negative return. Occasionally, a metal earth return may be used, but importantly any return is at ground potential thus does not need the full transmission voltage insulation. The converter output terminals are reversed relative to one another, as indicated by the direction of the thyristors in the symbol blocks. Issues involved in using a ground return are • Electrochemical corrosion of buried metals objects, like pipelines • Electrode chemical reaction under the sea • Magnetic field disturbances when the go and return paths become unbalanced The monopole system is limited in power handling capability, typically 1.5GW above the ground, and 600MW below the ground or under the sea. 19.2ii - Bipolar In the bipolar arrangement two high voltage conductors, at opposite potentials with respect to ground, are used as shown in figure 19.1c. Any pole imbalance uses an earth return, if a low-voltage metal ground return is not used. The bipolar configuration has a number of advantages over the monopole arrangement. • Normally no earth-current flows which minimises earth losses and any earth related environmental effects, including minimal corrosion of underground system metal components • If a fault develops on one pole, the other pole can continue to operate in a monopole arrangement, using the earth as the return path • For a given power rating, each conductor has half the cross-sectional area of the monopole line, thus reducing the extra cost of using a second conductor • The same dc transmission line towers can carry two lines with a small additional capital cost A homopolar hvdc link is formed if the two high voltage conductors have the same polarity, with, undesirably, a high ground or metal return current. The bipolar system is capable of higher transmission powers than the monopole configuration. Bipolar systems can carry over 3GW at voltages of over ±500kV, over distances well in excess of 500km.

HVDC

689

19.2iii - Tripole Two of the three conductors of an ac system are used in a bipolar configuration, with the third conductor used as a parallel monopole with bidirectional power flow capability. The bidirectional capability of the third conductor allows each of the two bipolar conductors to carry higher than rated current when each in turn is relieved periodically by the monopole system, such that all three conductors do not exceed rated I2R losses. In this way each of the three conductors experience the same thermal losses. This is achieved if the bipolar currents are cycled every few minutes between 0.366pu ½ 3 − 1 and 1.366 pu ½ 3 + 1 , with ±1 pu being appropriately alternated in the monopole. As a result, 80% more power can be transmitted compared with the ac equivalent, using the same conductors, towers, etc. Unlike the ac equivalent, the dc system can be fully loaded without system instability or need for reactive power compensation.

(

(

)

)

19.2iv - Back-to-back Two different ac systems in close proximity, possibly operating at different frequencies, can be interconnected by either a monopole or bipolar system. Since no dc transmission cables are necessary, because of the close proximity of the two systems, the system type and voltage level are not restrictive. 19.2v - Multi-terminal More than two converters are connected to the same dc link, where simultaneously, at least one converter operates in the rectification mode and at least one other converter operates in an inversion mode. Mechanical switching of the converter terminals is necessary.

19.3

Typical HVDC transmission system

A fully modular hardware structure is used. Each 8.8kV symmetrically blocking thyristor is configured in a module with its gate electronics and RC snubber as shown in figure 19.2. Many thyristors are connected in series to form a valve, with internal static voltage sharing resistors and a saturable reactor turn-on snubber as shown in figure 19.2a. Six valves are needed to form the 6 pulse valve group converter bridge in figure 19.3a, while 12 valves are used to form the twelve pulse value group converter in figure 19.3b. Each group of four valves in a single vertical stack form quadrivalves as shown in figure 19.3b. Each quadrivalve may contain hundreds of series connected thyristors to give the necessary hundreds of kV pole voltage rating. Typical six and twelve pulse valve group configurations are shown in figure 19.3, which form the unipolar converters in figure 19.1 parts a and b respectively. A more detailed circuit diagram of the 12-pulse converter and its MOV voltage protection and dc and ac harmonic filtering circuitry, in a substation installation, is shown in figure 19.4. The dc inductors Ldc in each pole assist in filtering harmonic currents and smooth the dc side current thereby reducing the current level for the onset of discontinuous current flow. Because the inductors control the dc link side di/dt, converter commutation is more robust. No dc filters may be necessary with the back-to-back HVDC converter configuration. Saturable reactor

C1

RC snubber damping circuits

Valve electronics

C2 C1>>C2 Static voltage sharing resistors

(a) Vf/b

(b)

Valve electronics

Figure 19.2. Thyristor valve: (a) modules components assembled into a valve and (b) valve symbol.

Power Electronics

690 19.4

Twelve-pulse ac line frequency converters

The six-pulse line-frequency fully-controlled thyristor converter was discussed in chapter 12.6. Harmonic filters are required on both the ac and dc side of the converter as shown in figure 19.4. The ac side harmonics occur at 6n±1 the fundamental, while the dc side harmonics are generated at 6n. In order to reduce the filtering requirements, and increase the effectiveness of the filtering, on both the ac and dc sides, most high power HVDC systems use 12-pulse, phase-shited transformer/converter arrangements. The ac side harmonics now occur at 12n±1 and the dc components are generated at 12n. Twelve-pulse converter operation is achieved by using the series bridge connection in conjunction with ∆-Y and Y-Y compound connected transformers as shown in figure 19.3b. (A delta connection is usually employed on the lower voltage side of the transformer.) Figure 19.5a shows the arrangement in more detail, with the necessary transformer turns ratio to ensure each converter bridge produces the same output voltage at the same thyristor firing delay angle. Voltage matching between the ac line and required dc link voltage is achieved with the transformer turns ratio N, shown in figure 19.5a. The series thyristors in each bridge provide paths which allow both converter currents to be equal.

DC side

AC side a

Y Y 6 pulse valve group

b

c

valves shaded

q =3 r =1 s =2 p=qxrxs p=6

Y Y (a)

Y ∆

AC side

Y∆

(b)

DC side

a Y∆

b

Y Y

c

a 3 Quadrivalves shaded b

c

q =3 r =1 s =4 p=qxrxs p = 12 Y Y

(c)

(d)

Figure 19.3. Monopole converter bridges: Six-pulse valve group (a) converter bridge schematic and (b) six-pulse valve group converter symbol; Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers: (c) converter schematic and (d) twelve-pulse valve group converter symbol.

HVDC

691

As a result of the transformer configuration, the corresponding upper and lower transformer voltages are displaced by 30°, where VaYs-nY leads Va∆s-n∆ by π radians. The dc-link current Id is assumed constant because of the large smoothing inductor Ldc (linear and typically ½H). If source impedance is neglected, then the various circuit current waveforms are constituted from rectangular current blocks as shown in figure 19.5b. Each converter operates with the same firing delay angle α, with respect to the voltage references shown in figure 19.5b. Because the transformer primaries are in parallel, the input current is the sum of the appropriate two transformer phase currents, namely ia = iYa + i∆a for phase a. The Fourier series for each transformer primary phase current is obtained from analysis of the appropriate six-pulse converter current, for each converter 2 3 Id  1 1 1 1  (19.1) iYa =  cos θ − cos 5θ + cos 7θ − cos11θ + cos13θ .....  Nπ  5 7 11 13  and 2 3 Id  1 1 1 1  (19.2) i∆a =  cos θ + cos 5θ − cos 7θ − cos11θ + cos13θ .....  Nπ  5 7 11 13  Because of the symmetry of a three-phase system, no triplens exist in each input current. The total line current drawn is 4 3 Id  1 1  (19.3) ia = iYa + i∆a =  cos θ − cos11θ + cos13θ .....  Nπ  11 13  The 12-pulse transformer/converter arrangement cancels harmonic components 6×(2n-1) ±1. The line current ia rms value is (1 +

1

3

)I

d

/ N and the rms fundamental is 2 6 I d / N π .

The ac line current harmonics occur at 12n±1. The valve side ac line current, shown as N×IYsa (or N×I∆sa) in figure 19.5b has an rms value of I d 2 / 3 , and once rectified, the valve unipolar current has an rms value of Id /√3. The converter outputs are series connected, hence the output voltage is additive for each pole, namely Vdr = Vdr1 + Vdr2. The converter output voltage, with the constraint that both converters have a trigger delay of α, is V 6 2 Vdr = Vdr1 + Vdr 2 = VLL cos α = 2.70 LL cos α (19.4) N πN converter transformer

bridge converter

Converter unit 6 pulse

dc filters

dc bus surge capacitor

Ldc

hv dc

½H linear

Metallic return transfer breaker

ac filters Midpoint dc bus arrestor

hv ac

dc bus arrestor

Y Y

Neutral bus Neutral bus arrestor surge capacitor

earth line and electrode earth return transfer breaker

Y ∆ ½H linear

Converter unit 12 pulse

hv dc

Ldc

dc reactor and arrestor

dc bus arrestor

Figure 19.4. Thyristor HVDC substation.

dc line arrestor

692

Power Electronics

The peak output voltage occurs midway between the peak voltage from each converter, and for α = 0 V V (19.5) Vldr = 2 2 LL cos 15° = 1.932 2 LL πN πN Each converter delivers six current blocks of magnitude Id, comprised of two ⅔π current blocks π radians apart in each converter arm. Since each converter output is shifted by π radians, the resultant 12 current block per cycle results in the dc side voltage harmonics in Vdr being of the order 12n. 19.4.1 Rectifier mode Figure 19.5b shows that the angle between the input ac voltage and its fundamental current Ia1 is determine by and equals, the phase delay angle αr. The phasor diagram for rectification is shown in figure 19.6a. For a constant link current Id, the fundamental ac input power factor is cos αr while the input reactive power is given by Qr = 3 VLL I a1 sin α r = Pr tan α r (19.6) I 2 6 = 3 VLL × I d × sin α r = 2.7 × VLL × d × sin α r Nπ N The rms of the fundamental line current Ia1 is 2 6 I d / N π . The real power transfer, which is the rectifier output power, is given by Pr = Vdr I d = 3 VLL I a1 cos α r = Qr / tan α r (19.7) I 2 6 = 3 VLL × I d × cos α r = 2.7 × VLL × d × cos α r Nπ N To maximize the power flow and minimize the reactive power, the delay angle αr should be small. From equation (19.7), to minimise the link I2R loss, both Id and the delay angle αr should be small. That is, from equation (19.4), the rectifier output voltage should be maximised. A low converter firing angle minimise the reactive power, reduce snubber losses, and reduces the harmonic content. 19.4.2 Inverter mode The same basic rectifier mode equations hold in the inversion mode except that αi > ½π. Operational waveforms and the phasor diagram for this mode are shown in figure 19.6b. The reactive power is I 2 6 Qi = 3 VLL I a1 sin αi = 3 VLL × I d × sin αi = 2.7 × VLL × d × sin α i (19.8) Nπ N = Pi tan αi and the real power transfer, which is inverted into the ac system is given by I 2 6 Pi = Vdi I d = 3 VLL I a1 cos αi = 3 VLL × I d × cos αi = 2.7 × VLL × d × cos α i (19.9) Nπ N = Qi / tan αi To maximize the inverted power flow and minimize the reactive power, the delay angle αi should be large (→ π). From equation (19.9), to minimise the link I2R loss, Id should be minimised (maximise dc link voltage) and the delay angle αi should be large (→ π). Thus the inversion voltage should be as large as possible, avoiding commutation failure. Then the maximum αi decreases as current increases since thyristor commutation time increases with current (and temperature).

HVDC +

AC side a

693 Ldc DC side

ia

iYa

id(t) = Id = constant

+

+

iYsa

aYs

q =3 r =1 s =4 p=qxrxs p = 12

N:1 Vdr1

-

ia

cYs

b

nY bYs Id Y Y

c

a

+

Y Y

i∆a

a∆s

∆ Y

Vdr

ia = iYa + i∆a

√3N : 1

∆Y n∆

Vdr2

c∆s

b

Vdr

ia ib ic

i∆sa

b∆s (a) c

-

-

Vdr = Vdr1 + Vdr2

Vdr2 Vdr1 VcYs-nY

-30°

o°

o°

VaYs-nY

αr

αr

N×iYa

Id

+

Ia 0

30°

180°

90°

330° -

Ia

150°

0° 30°

-Id N×i∆a − −

2Id

Id

3

3

N×ia −

(−

1

3

− 1) I d

1

3

(b)

Id

( − 2 3 − 1) I

d

Ia1 fundamental of Ia

Figure 19.5. Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers: (a) converter schematic and (b) twelve-pulse valve group waveforms.

Power Electronics

694 P

P

Q

q =3 r =1 s =4 p=qxrxs p = 12

Id Y Y

Q Id Y Y

+ ia = iYa + i∆a

- Vdr + = Vdr1+Vdr2

ia ib ic

Vdr2 ∆Y

Vdr

Vdr1

Vdr1

ia = iYa + i∆a

+ -

ia ib ic

-

= Vdr1+Vdr2

Vdr2

+

∆Y

Vdr2 ½Vdr Vdr1 VcYs-nY VcYs-nY -30° o°

αi VaYs-nY

VaYs-nY o° αr

o°

αi Vdr1 ½Vdr

-30° o° αr

Vdr2

N×iYa

N×iYa

Id

+

Ia 0 30°

180°

90°

+

Ia

300°

-

Ia

150°

-

360°

-Id

-Id

N×i∆a

Ia

0 30°

90°

Id 180° 150°

N×i∆a −

Id

3

−

2Id

−

Id

3

−

3

2I d

3

Ia1

N×ia

Ia1

N×ia −

( − 2 3 − 1) I

o

(−

1

1

I

3 d

−

1

I

3 d

( − 1 3 − 1) I

3 − 1) I d

d

ℜ ( I a1 )

ℜ ( I a1 )

VaYs-nY

αr

d

( − 2 3 − 1) I

d

VaYs-nY

o

αi

ℑ ( I a1 )

ℑ ( I a1 ) Ia1 (a)

Ia1 (b)

Figure 19.6. Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers operating in: (a) a rectifying mode and (b) an inverting mode.

HVDC

695

Id

+

Rdc

Vdr

P

-

Vdi (a)

+

Rectification αr < 90°

inversion αi > 90°

Vd

Vdi Operating point

maximum αi decreases with increased Id

I dref α Vdr

(b)

Id

Figure 19.7. Basic HVDC transmission system: (a) circuit diagram and (b) load line characteristics.

19.5

Twelve-pulse ac line frequency converter operation control

Rectification and inversion modes of converter operation and the line (or natural) commutation process of the three-phase fully-controlled thyristor converter have been considered in chapter 12.4 for rectification, with overlap in 12.5, and 12.6 for inversion with overlap. One converter operates as a rectifier (power flow from ac to dc) and the other dc link converter operates as an inverter (power flow from dc to ac). Either terminal converter can operate as an inverter or rectifier, since the delay angle determines the mode (voltage) of operation. The power flow between the two ac systems connected to the HVDC link is controlled by controlling the delay angle of each converter. Current only flows in one direction in the dc link, from the rectifier to the inverter. A simple system model is shown figure 19.7 where the link dc resistance is represented by Rdc and source reactance, hence overlap effects have been neglected. Let the transformer turns ratio factor N equal 1. The dc current Id is V + Vdi I d = dr (19.10) Rdc where 3 Vdr = 2 V LL cos αr for 0 ≤ αr ≤ ½π π (19.11) 3 2 VLL cos αi for ½π ≤ αi ≤ π Vdi =

π

The rectifier output power is Pr = Vdr I d

(19.12)

Pi = Vdi I d

(19.13)

Pr = Vdr I d = Vdi I d + I d2Rdc = Pi + I d2Rdc

(19.14)

while the power supplied to the inverter is where If transformer per phase leakage inductance Ls, referred to the converter side, is accounted for, then the resultant overlap at commutation reduces the output voltage for each six-pulse converter. 3ω Ls  6 3 Vdr = 2 ×  I d  = × 2 VLL cos α r − ω Ls I d (19.15) 2 VLL cos α r − π π  π

(

)

Both the rectifier and inverter dc output voltages can be compensated for leakage reactance commutation overlap. Remember the overlap voltage component is not a loss element in the resistor sense. It represents a ‘lossless’ loss of voltage which increases with current.

696

Power Electronics

If the link voltage is controlled by the inverter and the dc current controlled by the rectifier, then the load line characteristic in figure 19.7b results. The inverter voltage is kept slightly below the rectifier voltage. As the load current increases, the inverter terminal voltage is reduced. This is because the time to safely commutate the inverter thyristors increases with current, hence αi must decrease, as shown by the droop in the output characteristics in figure 19.7b. The more detailed practical approach to HVDC power transport control is considered in section 19.5.1. 19.5.1 Control and protection HVDC transmission systems must operate under tightly controlled conditions. Dc-link current and the two terminal voltages are precisely controlled to affect the desired power transfer. Accurate system quantities measurement are required, which include at each converter bridge, the dc-link current, the dcside voltages, and the delay angle α for each converter/inverter. Two terminal dc transmission systems have a preferred control mode during normal operation. Inverter Under steady-state conditions, the inverter controls the dc voltage by one of two methods. • The inverter maintains a constant delay angle αi > 90°, or extinction angle γ, where γ = π - αi, This constant angle maintenance causes the dc voltage Vd to droop with increasing dc ∨ current Id, as shown in the minimum constant extinction angle γ characteristic in figure 19.8b and labelled A-B-C-D in figure 19.8c. The weaker the ac system at the inverter, the steeper the droop characteristic. • Alternatively, the inverter may operate in a dc voltage controlling mode which is the constant Vd characteristic shown dashed in figure 19.8b and labelled B-H-E in figure 19.8c. To achieve this, the extinction angle γ must increase beyond its minimum value characterised in figure ∨ 19.8b as γ . Rectifier If the inverter is operated in either a minimum constant γ or constant Vd mode, then the rectifier is used to control the dc link current Id. This is achievable provided the delay angle αr is not at its minimum limit. The steady-state constant current characteristic of the rectifier is shown in figure 19.8a as the vertical section of the characteristic S-T and is labelled S-C-H-T in figure 19.8c. The rectifier delay angle is increased toward αr = 90° if the link current attempts to increase beyond the reference level I dref . During an attempted short circuit fault, the rectifier delay angle reaches 90° which sets the rectifier output voltage to zero, as shown by equation (19.11), and controls the fault current to I dref as shown by trajectory S-T in figure 19.8a. The operating point of the HVDC system is where the rectifier characteristic intersects the inverter characteristics, either at point C or point H on figure 19.8c, depending on which of the two inverter control methods is being employed. The operating point is tuned over a period of tens of seconds by adjusting the line-side tap changers of the converter transformers. The inverter controls the dc-link voltage as follows. • The inverter establishes the desired dc voltage Vd by tap changer adjustment, if it is operated in a constant minimum γ mode. • If the inverter is operated in a constant Vd mode, the tap changer ∨is adjusted to produce constant Vd with an extinction angle slightly larger than the minimum γ . The ac-side tap changers on the rectifier end transformers are adjusted so that the delay angle α is small but with a 5° working range, whilst maintain the constant current I dref. If the inverter is constant dc voltage operated at the operating point H, and if the dc current I dref is increased so that the operating point H moves towards A, the inverter control mode reverts to constant extinction angle γ control when operating in the droop region A-B. The voltage Vd droops to less than the desired value, so the inverter end transformer tap changer progressively boosts the dc-side voltage until dc voltage control recommences, in region B-C-D. Not all HVDC transmission systems use constant dc voltage control, which is the horizontal characteristic B-H-E in figure 19.8c. Instead, the tap changer in conjunction with the constant extinction angle γ control characteristic A-B-C-D in figure 19.8c, provides dc voltage control. Current margin The rectifier and inverter controllers both receive the dc current demand I dref but the inverter current demand is decreased by an amount termed the current margin Imargin, as shown in Figure 19.8c. This

HVDC

697

current margin is usually a constant magnitude of about 10% of rated current. The inverter current controller endeavours to control the dc link current to II = I dref – Imargin but the rectifier current controller dominates and maintains the dc current at I dref. In steady-state the rectifier controller overrides the inverter controller which is not able maintain a dc current I dref - Imargin. The inverter current controller only becomes active when the rectifier current controller has reduced its delay angle αr to the minimum limit. This rectifier minimum delay angle limit is characterised by R-S in figure 19.8c. droop due to link resistance

Vdr

RECTIFIER

Vdi

R

I dref

S minimum rectifier delay angle characteristic

∨

γ

constant current operation °

D

Vdr

B

constant Id current operation°

Id

minimum rectifier delay angle characteristic S D C E

H

Vdi

Vdr

RECTIFIER

Y VDCDL

Imargin X

F

I dref

Operating point B

(a)

(b)

(c)

(d)

Id

I I < I dref

Vd D

Vdr

A R

minimum extinction angle characteristic droop

E

S

Operating point

Vdi

INVERTER

∨

γ T

II

αi =γ= 90° Vdi = 0

F

I dref

γ greater than minimum extinction angle

Vdi

T

R

A

E

αr = 90° Vdr = 0

Vd

INVERTER

minimum extinction angle characteristic droop

INVERTER

RECTIFIER

Imargin F

Id

II

I dref

Id

Figure 19.8. Steady-state Vd - Id characteristics for a two terminal HVDC system.

Control characteristic performance Variations in the ac voltages change the control operating point of the system as follows. i. When the rectifier side ac voltage decreases and/or the inverter side ac voltage increases, then the transformer tap adjustment mechanisms on both the rectifier and inverter transformers should attempt to remedy this ac voltage regulation problem. If the disturbance is large enough, the new stable operating point is shown in figure 19.8d. The R-S characteristic falls below points D or E, the operating point will shift from point H to somewhere on the vertical characteristic D-E-F where it is intersected by the lowered minimum αr R-S characteristic as shown in figure 19.8d. The inverter converts to current control, controlling the dc current Id to the value II = I dref - Imargin, approximately 10% of rated current and the rectifier effectively controls the dc voltage provided it is operating at its minimum delay angle characteristic R-S. The dc power flow is relatively unaffected and safely returns to the normal operating condition shown in figure 19.8c, once the ac disturbances have subsided. ii. If the rectifier ac voltage increases, the reference current, which is set by the rectifier, is unaffected. Since the link voltage is set by the inverter, any increase in rectifier ac voltage does not affect the power flow. This can be seen in figure 19.8c where increasing the rectifier characteristic R-S does not affect the intersection of the operating point C, whence power flow is unaffected by an increase in the rectifier ac-side voltage. iii. If the inverter side ac voltage is decreased, the link voltage decreases proportionally, but the current is unaffected because it is set by the rectifier. The power flow is therefore decreased in line with the inverter ac voltage decrease. This can be seen in figure 19.8c where the inverter side ac voltage decrease will lower the inverter characteristic A-B-C-D. The operating point C, the operating voltage, decreases but the current is unaffected. Thus the power transferred is decreased in-line with the inverter ac-side voltage. vi. Worse case conditions are a dc-link short circuit. As seen in figure 19.8a, the rectifier maximum current is I dref, while figure 19.8b shows that the maximum inverter current is II. The maximum fault current is therefore limited to the operational current margin Imargin. As seen in figures 19.8a and 19.8b,

Power Electronics

698

the control angle of both converters moves to 90°, which produces 0V converter output voltages, as shown by equation (19.11). Hence the power associated with any short circuit fault is low, unlike short circuit faults in ac transmission systems. Voltage dependant current demand limit (VDCDL) If the ac voltages sag significantly because of weak ac systems, it may not be possible to maintain full load current. In such a case the dc-link voltage is decreased, and the controller characteristics are dictated by the trajectories X and Y in figure 19.8c. A controller which reduces the maximum current demand in such conditions, is termed a voltage dependant current demand limiter, or VDCDL. The current is not reduced to zero so that recovery response is faster once the dc-link voltage has sufficiently recovered. Power flow reversal The controllers can be designed such that the transition from the rectifier controlling current to the inverter controlling current is automatic and smooth. That is, seamless automatic power flow reversal is achieved by interchanging the inverter and rectifier functions, as seen in figure 19.9. This is realised by appropriate control of the delay angles, hence terminal polarities, but the dc link current direction does not reverse. Such a bi-directional power flow requirement may be necessary when two ac systems are required to bi-directionally interchange power. The rectifier delay angle is progressively increased while the inverter delay angle is decreased, such that the rectifier and inverter voltage difference is control to be virtually constant. This is achieved if αr + αi ≈ 180° is maintained. Id

+

Id

+

-

Vdr

Vdi

Vdr

Vdi

-

-

+

+

P

Vdr > Vdi Rectification α < 90°

P

-

Vdr < Vdi inversion α > 90°

inversion α > 90°

Rectification α < 90°

Figure 19.9. Power reversal in HVDC systems by voltage polarity reversal, not current reversal.

19.5.2 HVDC Control objectives The fundamental objectives of a CSI-based HVDC control system are as follows: • to control basic system quantities such as dc line current, dc voltage, and transmitted power accurately and with sufficient speed of response; • to maintain adequate commutation margin in inverter operation so that the valves can recover their forward blocking capability after conduction before their voltage polarity reverses; • to control higher-level quantities such as frequency in isolated mode or provide power oscillation damping to help stabilize the ac network; • to compensate for loss of a pole, a generator, or an ac transmission circuit by rapid readjustment of power; • to ensure stable operation with reliable commutation in the presence of system disturbances; • to minimize system losses and converter reactive power consumption; and • to ensure proper operation with fast and stable recovery from ac system faults and disturbances. 19.6

Filtering and power factor correction

As shown in figure 19.4, both ac and dc side filtering is used to reduce radiated EMC on the dc link and conducted EMC on the ac side which causes power losses and interference. On the dc-side, the large link inductance at each converter (typically between 0.2H and 0.5H) is supplemented with LC filters, tuned to eliminate selected 12n current harmonics in a 12-pulse system. A filter is notch tuned to eliminate (shunt) one specific harmonic, usually the most dominate 12th. At 50/60Hz, these filters are capacitive thus provide reactive power absorbed by the converters.

HVDC

699

Harmonics occur at 12n±1 on the ac-side. Again, tuned LC filters eliminate (shunt) specific low order harmonics and a general high pass shunt filter is used for components above the 11th and 13th. Generally, higher pulse order (>12) transformer/converter arrangements are not attractive in HVDC because of the difficulties in producing high-voltage transformers (auto-transformers tend to be used). Additional to the VAr compensation provided by the ac harmonic filters, pure capacitance may also be used. In order to avoid overcompensation voltage regulation problems which can occur at low power transmission levels, the extra capacitance tends to be switched in-circuit as needed. The main transformers may be provided with ac-side voltage taps to adjust the secondary voltage, as considered in section 19.5.1. The taps are switched automatically by motorised tap-changing drives, which only operate when large voltage changes occur for prolonged periods of time. If the transformers have only Y-Y winding configurations, they may also have a low-voltage delta tertiary winding for VAr compensation, provide ancillary supplies, and suppression of transformer core triplen harmonic fluxes. Example 19.1: Basic six-pulse converter based hvdc transmission The basic six-pulse converter dc transmission system represented by figure 19.10 connects a 230kV ac rms, 50Hz system to a 220kV, 60Hz system. The 6-pulse converters at each transmission line end are interface by a ∆ac-Ydc transformers of turns ratio √3:2, as shown, such that the transformer dc-side line voltage is double the ac side line voltage. The power transmission is 500MW to the inverter which is maintained at a dc voltage level of 500kV. The total dc-line resistance is 8Ω. Determine i. The inverter delay angle, αi. ii. The dc-link current, hence rectifier output voltage, thence rectifier delay angle, αr. iii. The rectifier input power and VAr, and inverter VAr, thence system efficiency. Solution Because of the transformer turns ratio, the transformer dc-side ac voltages are double the ac-side voltages. i.

The inverter delay angle is derived from equation (19.11) 3 Vdi = 2 VLL cos αi

π

500kV =

3

π

2 2 × 220kV × cos αi

that is αi = 147.3°

ii.

From Pi = Vdi × Id, the link current is

Id =

500 × 10 6 W 500 × 10 3 V

= 1000 A

The rectifier output voltage is given by equation (19.10), rearranged Vdr = −Vdi + I d Rdc = − -500kV + 1000A×1Ω = 508kV The rectifier delay angle is derived from equation (19.11) 3 2 VLL cos αi Vdr =

π

508kV =

3

π

2 × 2 × 230kV × cos αr

yields αr = 35°

iii. The input power is the output plus dc-link resistive losses, that is Pr = I d2 × Rdc + Pi

= 10002×8Ω + 500MW = 508MW The input VAr from the ac side is Qr = Pr tan αr = 508MW × tan35° = 355.7MVAr

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Similarly, the inverter VAr into the ac side (indicated by the negative sign) is Q i = Pi tan αir = 500MW × tan148° = -312.4MVAr

The efficiency is

η=

Pi Po

=

500MW ×100 = 98.43% 508MW

Figure 19.10. HVDC Example 19.1.

Id = 1kA

+

460kV 230kV 50Hz

VRdc = 8kV

440kV 220kV 60Hz

Vdr = 508kV Vdi = 500kV ∆:Y √3:2

-

Y:∆ 2:√3

-

508MW

8MW

Rectification

356MVAr

+

αr = 35°

inversion

αi = 148°

500MW -312MVAr

♣ The following example is based on example 19.1. Example 19.2: 12-pulse hvdc transmission The dc transmission line represented by figure 19.7 connects a 230kV ac rms, 50Hz system to a 220kV, 60Hz system. The 12-pulse bipolar converters at each transmission line end are interface by a Y-Y transformer of turns ratio 1:1 and a ∆-Y transformer of turns ratio 1:√3, each with a converter side inductance of 1mH. The rectifier delay angle is α = 30° for 500MW power transmission and the inverter advance angle is α = 160° (in order to avoid any reactive power increase), which maintains the dc voltage level at 500kV at the inverter end. The total line resistance is 8Ω and the dc link smoothing inductance is large enough to initially consider the dc current to be ripple free. Determine i. The transformer tap ratios at each end, the dc link efficiency, I2R losses, and both terminal VAr ii. If the rectifier tap ratio of 0.866 results in the transmission current limit giving a power of 600MW, find the delay angle and line efficiency for 500kV at the inverter. iii. The value of the dc link inductance Ldc such that the link peak to peak current is 0.1pu the average load current at full load (1200A), assuming the normalised magnitude of the dc side harmonic V12 is 0.15pu maximum (with respect to the 50Hz supply). Solution i.

From Pi = Vdi × Id, the link current is

Id =

500 × 10 6 W

= 1000 A 500 × 10 3 V The inverter voltage, accounting for the transformer tapping is given by an equation similar to equation (19.15), that is 3ω Ls  3 Vdi = 2 ×  2 ai VLL cos α r − I π π d   3 × 2 × π × 60Hz × 1× 10−3 H 3  500 × 103 V = 2 ×  2 ai 220 × 103 V cos (180° − 160° ) − 1000A  π π  which gives a transformer tap ratio at the inverter end of ai = 0.896. From equation (19.10), the rectifier voltage is

Vdr = Vdi + Rdc I d = 500kV + 8Ω × 1000A = 508kV

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701

and the necessary transformer tap ratio is derive from 3ω Ls  3 Vdr = 2 ×  2 ar VLL cos α r − I π d  π 3 × 2 × π × 50Hz × 1 × 10−3 H 3  508 × 103 V = 2 ×  2 ar 230 × 103 V cos 30° − 1000A  π π   which gives a transformer tap ratio at the rectifier end of ar = 0. 945.

The link efficiency is

VI Pi × 100 = i d × 100 Pr Vr I d

η=

500kV

=

508kV

× 100 = 98.4%

The I2R losses are 1000A2×8Ω = 8MW or (508-500)2/8 Ω, dissipated, distributed along the line. The rectifier reactive power is given by equation (19.6), that is Q r = Pr tan αr = (500MW + 1000A 2×8Ω)×tan30° = 293.3MVAr This is 293.3MVAr from to rectifier ac side.

The inverter reactive power is given by equation (19.8), that is Qi = Pi tan αi

= 500MW × tan160° = - 182MVAr This is 182MVAr to the ac side of the inverter. ii.

At 500kV and 600MW:

Id =

Pi 600MW = = 1200A 500kV Vdi

Accounting for the link resistive voltage drop

Vdr = Vdi + Rdc I d

The efficiency is

= 500kV + 8Ω × 1200A = 509.6kV

η= =

VI Pi × 100 = i d × 100 Pr Vr I d 500kV

× 100 = 98.1% 509.6kV The necessary rectifier angle, accounting for transformer reactive inductance, is 3ωLs 3  Vdr = 2 ×  2 ai VLL cos αr − Id  π π     3 3 × 2 × π × 50Hz × 1 × 10−3 H 509.6 × 103 V = 2 ×  2 × 0.866 × 230 × 103 V cos αr − × 1200A  π π  which gives a rectifier delay angle of αr = 18.5°.

iii. The maximum link voltage from the 50Hz rectifier, accounting for leakage at maximum current is 3ωLs 3  Vdr = 2 ×  Id  2 VLL cos αr − π π  3  3 × 2π 50Hz × 1 × 10−3 H 2 230kV × cos 0° − 1200A  = 2× π π   = 620.5 kV The magnitude of the 600Hz component (12×50Hz) is 15% of 620.5kV, namely 93.1kV, which produces a ripple current of 10% of rated current, 1200A, namely 120A. Thus from v = Ldi/dt

Power Electronics

702

Ldc = v 12

∆t 12 ∆i 12

= 93.1kV × Figure 19.11. HVDC Example 19.2.

1 12 × 50Hz × 120A

= 1.3H

Id = 1000A

Y:Y 1:1

+

230kV 50Hz

VRdc = 8kV

Vdr = 508kV

∆:Y √3:1

Y:Y 1:1

+

220kV 60Hz

Vdi = 500kV

-

Y:∆ 1:√3

-

508MW Rectification

293MVAr

19.7

αr = 30°

500MW

8MW

inversion

-182MVAr

αi = 160°

♣

VSC-Based HVDC

Voltage source converter-based (VSC) dc-transmission consists of a bipolar two-wire HVDC system with self commutatable converters connected pole-to-pole, as shown in figure 19.12. DC capacitors are used at each VSC dc-side to provide a stiff dc voltage source. The dc capacitors are grounded at their electrical centre point to establish the earth reference potential for filtering and the transmission system. The VSC is effectively mid-point grounded and DC filters and a zero-sequence blocking inductor are used to mitigate interference on any metallic communication circuits adjacent to the DC cables. There is no earth return operation. The converters are coupled to the ac system through ac phase inductors and power transformers, with harmonic filters located between the phase inductor and the transformer. The AC filters are tuned to multiples of the switching frequency, as shown in figure 19.16. This arrangement minimizes harmonic currents and avoids dc voltage stresses in the transformer, which allows use of a standard AC power transformer for matching the 50/60Hz AC network voltage to the converter AC voltage necessary to produce the desired DC transmission voltage. Converter valves AC transformer

DC capacitors

DC-link cables

DC capacitors

Converter valves

AC phase inductors

AC transformer

AC phase inductors

Vac 1

Vac 2 Iac 2

Iac 1 Vdc-1

AC harmonic filters

Vdc-2

AC harmonic filters

Vac-ref2

Vac-ref1

Vdc-ref2

Vdc-ref1 ac voltage control

PWM current control

dc voltage control Pref 1 Qref 1

dc voltage control Pref 2 Qref 2

PWM current control

Figure 19.12. VSC HVDC transmission.

ac voltage control

HVDC

703

The IGBT valves used in VSC converters are comprised of series-connected IGBT cells. Present technology uses 2.5kV igbt die parallel connected on a common electrically-conducting substrate in 2500A sub-modules, with 30 series connected sub-modules in a string cell. Strings are then series connected to produce the required link valve voltage requirement. The IGBT switching frequency is limited to about 2 kHz. The valves are cooled with circulating water and water to air heat exchangers. The structure is constructed to shield electromagnetic interference (EMI) radiation. 19.7.1 VSC-Based HVDC control Power flow between the VSC and ac network can be controlled by changing the phase angle of the converter ac voltage VS with respect to the filter bus ac voltage VT, whereas the reactive power can be controlled by changing the magnitude of the fundamental component of the converter ac voltage VT with respect to the filter bus ac voltage VS. By controlling these two aspects of the converter voltage, operation in all four quadrants is possible. This means that the converter can be operated in the middle of its reactive power range near unity power factor to maintain dynamic reactive power reserve for contingency voltage support similar to a static VAr compensator. This also means that the real power transfer can be changed rapidly without altering the reactive power exchange with the ac network or waiting for switching of shunt compensation. Reactive power control can be used for dynamic voltage regulation to support the ac interconnection, by synthesising a balanced set of three phase voltages. Independent control of the VSC ac voltage magnitude and phase relative to the system voltage decouples the active and reactive power control loops for HVDC system regulation. The active power control loop can be set to control either the active power (dc-link current) or the dc-side voltage. In a dc link, one station is selected to control the active power while the other controls the dc-side voltage. The reactive power control loop controls either the reactive power or the ac-side voltage. Either of these two modes can be selected independently at either end of the dc link. Figure 19.12 shows the characteristic ac voltage phasors including the controlled variables Vdc, Id, Q, and VL. 19.7.2 Power control concept dc-link power The dc-link power flow concepts are not complicated by ac phasor considerations. No reactive power is involved with dc, only the real power flows. Consider the HVDC configuration depicted in figure 19.13 involving converter #1 and converter #2. Idc

Rdc

VL1

XC1 I C1

IC2 XC2

Vdc2

Vdc1

IL1

VL2 IL2

VC1

VC2

(a)

2

1

{

ℜ −VC 1 I L 1 + VC 2 I L 2

VL1-n

*

*

}=I

2

dc

Rdc

jXR1

jXR2

IC1

IC2

VC1-n

VC2-n

VL2-n (b)

Figure 19.13. VSC HVDC transmission dc-side.

If one converter #1 produces an ac voltage represented by VC 1 = VC 1 ( cos δ1 + j cos δ1 ) = VC 1 ∠δ1

(19.16)

Power Electronics

704

while the other converter #2 is represented by the voltage source VC 2 = VC 2 ( cos δ 2 + j cos δ 2 )

(19.17)

= VC 2 ∠δ 2

Then if the power transmitted equals the power received, then ℜ {−VC 1I L*1 +VC 2I L*2 } = 0

(19.18)

If the dc link resistive losses are incorporated equations (19.18) becomes ℜ {−VC 1I L*1 +VC 2I L*2 } = I dc2 Rdc

(19.19)

ac-side powers Transformer

jXR

IT

Idc

VXR VS-n

VT-n

Power transformer

Vdc

VL-n

IR

XR

IT

IL 1:N

{Im}

ITq

VS

IT

VS-n

VL Harmonic filter

VXR

δ

VT-n

ITp

VT

{Re}

(a) (c) (b)

Figure 19.14. VSC HVDC transmission ac-side.

The fundamental base apparent power ST at the filter bus between the converter reactor and the AC filter is defined as follows (see figure 19.14):

S T = PT + jQT = 3 ×VT × I R (19.20) The active and reactive power components on the grid-side are defined as (see section 20.3 of ac power transmission): V ×V S × sin δ V ×V S × sin δ P = T = T ωL

XR

(19.21)

V × cos δ −VT QT = VT S XR

where: δ = phase angle between the filtered voltage VT and the converter output voltage VS L = inductance of the converter ac line inductance Changing the phase angle δ controls the active power flow P between the converter and the filter bus and consequently between the converter and the AC network. Rectifier

Inverter

VX

Reactive Power Consumed generated

VX

VX VX

VT

VS

VS

VT VS

δ

δ

VT

VS

IR IR Active power flow P

IR

(a)

(b)

IR

Reactive power flow Q

Figure 19.15. Active and reactive power phasor diagrams.

VT

HVDC

705

As shown in figure 19.15a, for active power flows • If the VS phase-lags VT, active power P flows from the AC to the DC side (rectifier). • If the VS phase-leads VT, the active power P flows from the DC to the AC side (inverter). Changing the amplitude difference between the filter voltage VT, and the converter voltage VS controls the reactive power flow between the converter and the AC network. As shown in figure 19.15b, for reactive power flows • If VT > VS, there is reactive power consumed from the ac network. • If VS > VT, there is reactive power generated into the ac network. With the PWM (Pulse-Width-Modulation, see Section 15.2.3) controlled VSC it is possible to create any phase angle and voltage amplitude (within limits set by the dc-link voltage magnitude) by changing the PWM modulation depth and the relative phase displacement respectively, by using phase-locked-loop grid synchronised displacement. This allows independent control of the active and reactive power. The typical P-Q diagram, which is valid within the whole steady-state AC network voltage, is shown in the figure 19.16. This figure illustrates the grid real power, P, and reactive power, Q, capability of the HVDC VSC converter terminal, measured at the interconnection point, as a function of ac system voltage. P(φ) pu

Rectifier

1pu

1pu

+½

Vdc limit

Vac

Active power

0.9 pu +½

Q(φ)

-½

pu

Q(φ)

Vac

pu

1.0 pu -½

Vac

1.1 pu

Idc limit

Q consumption inductive

1pu

reactive power

Inverter

Q generation capacitive

Figure 19.16. P-Q active and reactive power control locus.

The 1st and 2nd quadrants represent rectification and the 3rd and 4th inversion. A positive Q indicates delivery of reactive power to the AC network. Because the dc-link decouples the two converters, reactive power can be controlled independently at each station. There are dc-link voltage and current limitations that have been taken into account in this typical P-Q diagram. The capacitive reactive power capability increases with decreasing voltage when it is needed most. Similarly, the inductive reactive power capability increases with increasing network voltage when it is needed most. For a given ac system voltage the converter can be operated at any point within its respective ‘circle’.

19.8

HVDC Components

i. Power transformer Because of the use of the converter ac inductors and the use of VSC PWM, the current in the transformer windings contains minimal harmonics and is not exposed to any DC voltage. The transformer is a 50/60Hz single or three phase power transformer, with taps and a tap-changer. The secondary voltage, the filter bus voltage, is controlled by the tap changer to achieve the maximum active and reactive power from the VSC, both consumed and generated. The tap changer is located on the secondary side, which has the largest voltage swing, and also to ensure that the ratio between the line winding and a possible tertiary winding is fixed. This tertiary winding feeds the station auxiliary power system and if delta connected suppresses any core triplen fluxes. In order to maximize the active power transfer, the converter generates a low frequency zero-sequence voltage ( 0), increases the transmittable power and the reactive power. Maximum power is transmitted with a load angle of δ = ½π, when k → 1, that is when ωLL = 1/ωCsc (line resonance at frequency ω). ½XL

½Xsc

I

½Xsc

½XL

P Q =

Q

VS

VT

VM

2V

k

2

XL

(1 − k )

2

(1 − cos δ )

4P

3P p =

½jXLI

½jXLI

2P

V

2

1

XL 1 − k

sin δ

k=0.4

-½jXcsI

-½jXcsI

VM VS

VT

k=0.2

P k=0

k =

I ½δ

Q=0 k=0

½δ

0

½π

π

X cs XL

δ

transmission angle

Figure 20.9. Midpoint static series compensation: (a) two source power system model; (b) phasor diagram for |VS|= |VT|= V; and (c) power versus load angle.

Series static VAr compensators 20.6.1 - Thyristor switched series capacitor TSSC A thyristor switched series capacitor compensator TSSC consist of a least one series capacitor, each shunted by a back-to-back pair of anti-parallel connected phase control thyristors, as shown in figure 20.10a. The thyristors when continuously triggered, provide a path for the line current to by-pass the series compensating capacitors. The thyristor are taken out of circuit when the gate triggering is removed and natural turn-off commutation occurs at the subsequently line current reversal, that is, the thyristors are line or naturally commutated. With this commutation process, the series capacitor charges with a dc bias as shown in figure 20.10b. Subsequent thyristor turn-on should only occur at the line zero current points in order to avoid high initial anode di/dt currents.

FACTS

Vℓ +

VC1

-

+

C1

VCi

-

+

THi

TH1

I

(a) THn

TH on VCi =0

I

TH on

-

Cn

Ci

TH off I=0

VCn

726

Vm

TH on

I

ωt

(b)

VCi

VCi

Figure 20.10. Thyristor switched series capacitor compensation TSSC: (a) series connected capacitors and (b) zero current activation and zero voltage deactivation.

20.6.2 - Thyristor controlled series capacitor TCSC Better capacitor series voltage control is obtained if the thyristors in figure 20.10a are selfcommutatable, such as with symmetrical voltage blocking IGCThyristors. This series TCSC compensator is the dual to the shunt TSR in figure 20.6b.

• Instead of thyristors in series with inductance, thyristors are in parallel with capacitance. • Instead of uni-directional voltage blocking, naturally commutating switches, the capacitive series compensator uses bidirectional voltage blocking, self-commutatable switches. • In the series compensator, compensation occurs when the series thyristors are on, while compensation is active in the series compensator case when the parallel IGC Thyristors are off. • The shunt compensator supports a sinusoidal voltage and produces current harmonics, while the series compensator conducts the sinusoidal line current and produces voltage harmonics. Typical series TCSC waveforms are shown in figure 20.11c, while the harmonics produced are shown in figure 20.6d. It will be noted that the same equations as in section 20.2.4i for the TCR hold, except that voltages and currents are interchanged, and capacitive reactance is used instead of inductive reactance. Specifically, if the line current is

i = I M sin ωt = 2I sin ωt Then the capacitor voltage is given by

v c (t ) = I M X C ( cos α + cos ωt ) =

IM ( cos α + cos ωt ) ωC

(20.31) (20.32)

The power factor of the fundamental voltage component lags I by 90º, always producing reactive power. The odd order rms (total) harmonics shown in figure 20.6d vary with delay angle according to  sin ( n + 1) α sin ( n − 1) α sin n α  4 (20.33) cos α  for n = 3, 5, 7... Vn = I X C  + − π 2 ( n − 1) n  2 ( n + 1)  and the 90º lagging fundamental rms voltage is given by 2 I 2 V1 = where X C = 1 / ωC (20.34) ½ sin 2α + π − α  = I X C ½ sin 2α + π − α 

π ωC π for ½π ≤ α ≤ π with respect to zero current cross over. If the delay angles of both thyristors are not equal, even voltage harmonics are produced, including a dc voltage component. The total harmonic distortion is increased. As the delay angle increases the voltage period angle σ decreases and the voltage decreases, as if the capacitance were increasing, so that the series TCSC effective acts like controllable capacitive susceptance. I C eff = ωV1 (20.35) I2 2 Q 1 = V1 I = = I X eff ω C eff

Power Electronics

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Also, as the delay angle α increases and the voltage decreases, thyristor conduction increases, hence thyristor losses increase. As with the shunt TCR, operation below 90º is possible if two capacitors are used as shown in figure 20.11b. Extra semiconductors (diodes) are needed, but the IGC Thyristors only need forward voltage blocking properties. Consequently, capacitors with uni-directional voltage properties can be used. The voltage harmonics are lower but at the expense of extra devices and losses. Vℓ I

+

VC

-

-

C

C

D

D

TGTO

Vℓ

VC

+

I

Vm

VC

+

C

(b)

TGTO

TGTO

(a) (c)

Vc ( ½π ) =

I

VC

I ωC

I

I VC(¼π)

VC

VC(½π)

VC GTO on

VC VC

GTO on

GTO on

ωt VC(α)

VC(½π)

VC I α=45º

α=90º

α=120º

α=157½º

Figure 20.11. Thyristor controlled series capacitor compensation TCSC: (a) series connected capacitors with shunt self-commutable GTOs for α≥90º and (b) for α≥0º and (c) line current and current waveforms for delay angles α=45º, 90º, 120º and 157½º.

20.6.3 - Series Static VAr compensator SVC (TCR//C) The TCR//C consists of a line series compensating capacitor in parallel with a thyristor controlled reactor (TCR), as shown in figure 20.12. By varying the delay angle of the TCR thyristors, the capacitive reactance can be decreased, since the fundamental reactance of the parallel combination is given by

X eff (α ) =

X C X L 1 (α ) X C − X L 1 (α )

(20.36)

where, from equation (20.19), the reactance at the fundamental frequency is ½π where X L = ω L X L 1 (α ) = XL ½ sin 2α + π − α

(20.37)

Vm

Vℓ I

VC1

+

XC

-

XC

C XL

TH

VCn

+

L

-

C XL

TH

L

Figure 20.12. Thyristor controlled reactance and series connected capacitance, SVC compensation.

FACTS

728

The voltage harmonics produced by the reactor tend to be trapped in the parallel connected capacitor due to its the low capacitive reactance XC which is inversely proportion to harmonic frequency (relative to line reactance Xs which increases proportional to harmonic frequency). Accounting for the line reactance Xs and compensator fundamental reactance Xeff, the active and sending reactive powers are given by equations (20.6) and (20.8), that is

PT =

V S VT sin (δ S − δT X L + X eff

)

V −VT cos (δ S − δT QS = VS × S X L + X eff

(20.38)

)

The signs in these equations are appropriately changed for capacitive operation. The capacitor and inductor voltages and currents can be define during the period when the thyristors block and when a thyristor conducts. If the rms line current is IM then • when the thyristors block: Vc (t , α ) = 2I M X C  sin α 1 − sin (ωt − α ) − cos α cos (ωt + α )  + VC t =α +σ

I C (t , α ) = 2I M sin ωt I Th = I L = 0 • when a thyristor conducts: V L (t , α ) = Vc (t , α ) = 2I M X L

and

(= line current ) V L (t , α ) = 0

  cos (ωt − α ) − k sin (ωo t − k (α − ½π ) )   ωk 2    cos α  1−k2 −  sin (ωt − α ) − cos (ωo t − k (α − ½π ) )   (20.40) 



+VC t =α cos (ωo t − k (α − ½π ) )

I L (t , α ) = 2I M

(20.39)

 sin α sin (ωo t − (α − ½π ) / k ) − k cos (ωt − α )       1−k2  − cos α  cos (ωo t − (α − ½π ) / k ) + sin (ωt − α )    



k

(20.41)

I C (t , α ) = I L (t , α ) + 2I M sin ωt where ωo =

1

LC

= k ω = 2π f , that is, k =

ωo ω

Example 20.3: Series thyristor controlled reactor specification – integral control A 50Hz 230kV three-phase ac transmission line has line reactance of XL = 52 Ω per phase and a maximum thermally limited line current of 2000A. The line voltage can vary by ±5% at each end and the load angle between the ends varies between 5° and 10°, where the load is lagging. Series TCSC SVC connected at the midpoint, comprised of four compensating three-phase modules has a capacitive reactance of 10Ω with 1.66Ω of switchable parallel inductance. Calculate i. the nominal power ii. the line current and powers under worse case conditions, before series compensation iii. the effective module reactance when the impedances are parallel connected iv. the effective line impedance at worse case, if 50% of rated power is the transmission objective, and the resultant transmission powers Solution i. The nominal maximum power is given by P = 3V L I L = 3 × 230V × 2000A = 796MW

ii. Worse case power delivery conditions are when the sending end is 5% below the nominal ac voltage, while the receiving end is 5% above the nominal, at the highest load angle, δ=10°. The current can be evaluated by equating equation (20.1) with equations (20.6) and (20.7)

Power Electronics

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I = I cos φ + jI sin φ = I × e j φ I sin φ =

V S cos δ −VT QT = XL VT

I cos φ =

218.5kV × cos10° − 241.5kV 52Ω = −0.5051kA

V S sin δ P = XL VT

218.5kV × sin10° 52Ω = 0.730kA

=

=

I = −505.1+ j730.0 = 887.7− j 55.3° pu wrt VT The real power flow is:

P =

VT ×VR sin δ XL

218.5kV × 241.5kV sin10° 52Ω = 176.2MW =

The sending end reactive power is V −V cos δ Qs = VS × S T

XL

= 218.5kV ×

218.5kV − 241.5kV × cos10° = −81.2MVAr 52Ω

The terminal end reactive power is V cos δ −VT QT = VT S

XL

218.5kV × cos10° − 241.5kV = −122.2MVAr 52Ω The line reactive power is given by Qs - QT = -81.2MVAr + 122.2 MVAr = 41.0MVAr. Alternatively, the line reactive power can be calculated from I2XL = 887.72×52 = 41.0MVAr = 241.5kV ×

iii. The inductor j1.66Ω in parallel with the capacitor –j10Ω give a parallel combination impedance of − jX cap × jX ind X cell = − jX cap + jX ind =

− j 10Ω × j 1.66Ω = j 2Ω − j 10Ω + j 1.66Ω

iv. Worse case power delivery conditions are when the sending end is 5% below the nominal ac voltage, while the receiving end is 5% above the nominal, at the highest load angle, δ. That is, the necessary line reactance, for half rated power, is given by V ×VR P = T sin δ

XL

= 50% of 796MW =

95%VNom × 105%VNom

XL

sin δ

95%230kV × 105%230kV

XL

sin10°

⇒ X L = 23Ω Figure 20.13 shows that with only one module activated, the line reactance can be compensated to 24Ω. The real power flow and reactive powers are: V ×VR sin δ P = T

XL

218.5kV × 241.5kV = sin10° 24Ω = 381.8MW

The sending end reactive power is V −V cos δ Qs = VS × S T

XL

= 218.5kV ×

218.5kV − 241.5kV × cos10° = −176MVAr 24Ω

FACTS

730

The terminal end reactive power is V cos δ −VT QT = VT S

XL

218.5kV × cos10° − 241.5kV = −264.8MVAr 24Ω The line reactive power is given by Qs - QT = -176MVAr + 264.8 MVAr = 88.8MVAr. = 241.5kV ×

The current is

I = I cos φ + jI sin φ = I × e j φ I sin φ =

V S cos δ −VT QT = XL VT

I cos φ =

218.5kV × cos10° − 241.5kV 24Ω = −1.10kA

V S sin δ P = XL VT

=

I = −1100 + j1581 = 1926

− j 55.2°

218.5kV × sin10° 24Ω

= = 1.58kA

pu wrt VT

The line reactive power can be calculated and confirmed from I2XL = 19262×24Ω = 89.0MVAr The sending power factor is

P = 3V s I L cos φ = 3 × 218.5kV × 1.926kA × cos 52.5° = 443.7MW ½XL = j26Ω

-j10Ω

-j10Ω

-j10Ω

½XL = j26Ω

-j10Ω

1926A

218.5kV ∟0°

-96.4MVAr

j1⅔Ω

j1⅔Ω

j1⅔Ω

j1⅔Ω

j2Ω

j2Ω

j2Ω

j2Ω

37.1MVAr

37.1MVAr

-7.4MVAr

-96.4MVAr -265MVAr

-176MVAr

382MW

37.1MVAr

241.5kV∟15°

89MVAr

241.5kV∟15°

218.5kV ∟0° XLeq = j24Ω

382MW

1926A

1926A x°

218.5kV/√3

15° 241.5kV/√3

46.2kV/√3

Figure 20.13. Example 20.3.

♣ Example 20.4: Series thyristor controlled reactor specification – Vernier control A 50Hz 400V ac transmission line has line reactance of XL = 2.2 Ω and is delivering 100kW at a load angle of 80º. The TCSC comprising C=30µF and L=3.53mH is operated at a load angle of 80º. Calculate i. the degree of compensation k ii. the compensating capacitive reactance iii. the line current I iv. the reactive power Q v. the TCSC delay angle if the effective capacitive reactance is 200Ω

Power Electronics

731

Solution i.

From equation (20.29)

k =1−

V2 4002 sin δ = 1 − × sin 80° = 0.284 X L Psc 2.2Ω × 100kW

ii.

From equation (20.28), the compensation reactance is X sc = kX L = 0.284 × 2.2Ω = 0.624Ω

iii.

From equation (20.29) 2V 2 × 400V sin ½δ = sin ½80° = 326.5A I= X L (1 − k ) 2.2Ω × (1 − 0.284 )

iv.

From equation (20.29) 2V 2 k 2 × 4002 0.284 Q sc = × 1 − cos δ = × × (1 − cos 80° ) = 66,586 VAr ( ) 2 2 X L (1 − k ) 2.2Ω (1 − 0.284 )

v.

The compensator capacitive reactance is 1 1 1 Xc = = = = 106.1Ω ω C 2π f C 2π 50Hz × 30µF The compensator inductive reactance is X L = ω L = 2π f L = 2π 50Hz × 3.53mH = 1.11Ω From equations (20.36) and (20.37)

X eff (α ) = 200Ω =

X C X L 1 (α ) − X C + X L 1 (α )

106.1Ω × X L1 (α )

−106.1Ω + X L1 (α )

⇒

X L1 (α ) = 32.0Ω

Then ½π XL ½ sin 2α + π − α ½π × 1.11Ω 32.0Ω = ½ sin 2α + π − α ♣

X L 1 (α ) =

⇒

α = 167°

20.6.4 Static series phase angle reactive power compensation/shift SPS Phase compensation is a specific case of series compensation, as shown in figure 20.14, where the phase angle change is used to control the power flow. Where as series reactive control is usually located at the line reactance midpoint, phase angle compensation is performed at the sending end of the transmission line. The compensator is an ac voltage source Vε of controllable magnitude and phase angle. The effecting sending end voltage VS eff becomes V S eff = V S + V ε (20.42) The compensator can function in one of two ways.

•

The load angle is varied maintaining a voltage magnitude VS eff the same as the sending voltage Vs (20.43) V s eff = V S = V S eff = V S = V

•

The compensator phase angle is maintained at quadrature to the sending voltage

V S eff = V S eff = V S2 + V ε2

(20.44)

In both cases, power flow control is achieved at the expense of consuming reactive power from the network. The system transfer admittance has Vs replaced by Vs eff, that is I S eff  1 cos φ + j sin φ  V S eff  1  (20.45)  =    1   VT   I T  X L  − ( cos φ − j sin φ )

FACTS Series connected transformer

VS I

732

VT

XL

excitation transformer

(a) Thyristor network

TH

Phase angle controller see right and figure 20.17

VS

VT

Φ I

(b) XL j½XsIδ

Vε+ Vε

I

TH

VT

Vs δ+

Vs eff(+ε)

Φ

VS

j½XsIε+

XL

VS eff

+ε

VT

δ Iδ

(c)

Figure 20.14. Transformer series phase angle compensation: (a) series transformer with ac tap changing thyristor network; (b) variable phase angle representation; and (c) two port series phase angle compensator system.

Phase shifting (Φ VT

VT ISC

generates (leading) VAr capacitive

PCC

VSC VSI

ISC XSC

VT

ISC

VSC

IL

XSC

VT ∠δT

VSC ∠δ sc

ISC

VT

PCC

VSC

VSC

ISC = 0 VSC = VT ISC = 0 VAr = 0

VA VB

ISC

VC

VT

IDC VSC Rdump

VSC < VT

XSC I a

C

+

VDC

Ic

Ib

VSI

absorbs (lagging) VAr inductive

PCC VSC

ISC XSC

(b)

(d)

(c)

Figure 20.22. Active shunt regulator - STATCOM: (a) a voltage source inverter VSI, inductively shunt connected (transformer coupled) to the ac network; (b) shunt connected STATCOM shown as a variable magnitude and phase angle voltage source; (c) main VSI circuit; and (d) phasor diagrams for leading (upper phasor diagram) and lagging (lower phasor diagram) modes of operation.

In steady-state, the inverter output voltage fundamental VSC (which is controlled by the PWM modulation index) is in phase with the ac line voltage VT (δSC = δT), while the STATCOM current ISC always leads or lags the line voltage by 90º because of the inductive reactive coupling XSC therefore cos(δT - δSC) = cos0 = 1, Thus P ≈ 0 is maintained as given by equation (20.54) when sin(δT - δSC) = sin0 = 0.

Power Electronics

741

From equations (20.54) and (20.55), since δSC = δT, only reactive power flows and • when the STATCOM voltage VSC is less than the line voltage VT (│VSC││VT│, the STATCOM generates (capacitive) reactive power (which tends to increase the point of connection voltage). • When VSC =VT, the voltage VSC across the connecting inductance XSC is zero, so no STATCOM current flows Isc = 0. Thus a STATCOM behaves like a shunt inductor (I lags V) without a physical inductor or magnetic field, and like a shunt capacitor (I leads V) without a physical capacitor or electric field. When used in a voltage regulation mode (as opposed to a VAr control mode with constant reactive power output) the STATCOM terminal I-V characteristics are as shown in figure 20.8c for the SVC. The dc link capacitor is initially charged through the VSI freewheel diodes which form an uncontrolled three-phase line rectifier. Subsequently the STATCOM is controlled to self regulate its dc-link voltage, VDC, as follows. When the fundamental voltage of the STATCOM slightly leads the ac supply voltage, VSC leads VT, the capacitor voltage decreases resulting in VSC < VT, real power is transferred from the dc link to the ac line and reactive power is absorbed by the STATCOM – lagging power mode. When the STATCOM fundamental voltage slightly lags the ac supply voltage, the capacitor voltage increases, VSC > VT, real power is transferred from the ac line to the dc link and reactive power is generated by the STATCOM – leading power mode. Thus the STATCOM fundamental magnitude VSC controls the reactive power, while the phase angle between the STATCOM and the ac line, δT – δSC, controls real power flow. In practice, when VSC slightly lags VT (δSC lags δT), the capacitor voltage VDC is maintained whilst catering for system inverter and transformer power losses. In this way no separate dc power supply is needed to maintain the dc-link capacitor voltage. Notice that the dc-link voltage will always be greater than the rectified ac grid voltage due to the rectification action through the six inverter bridge freewheel diodes. Although practical limits exist on the magnitude of VSC, the STATCOM power load angle δSC is continuously adjustable between 0 and 2π, but operates near the line phase angle δT in order to minimize real power transfer. The SATCOM can generate more reactive power during a fault than the SVC since • from equation (20.27), SVC capacitive reactance power decreases proportionally to voltage VM while • from equation (20.55), STATCOM capacitive reactive power decreases linearly with voltage VSC. jXR

IS

IT Ish

VXR

Vsh-n

jXsh

VT-n

VS-n

VXsh = - jXshIsh

N

Vsh-n

φ

Ish N

O

VT-n IT

IS

W

VS-n VT-n + jITXR N

φ IT

VT-n

(a)

(b)

(c)

(d)

jIshXR

Y

O

I sh X R jITXR

-jIshXR Z

VS-n

Ish N

jIshXR

VS-n φ

VT-n

jITXR

I sh X R Vsh-n

jIshXsh

IT

Figure 20.23. Active shunt compensation: (a) shunt compensated network; (b) general shunt voltage compensation phasor diagram; (c) shunt voltage compensation; and (d) quadrature reactive-power shunt current compensation.

FACTS

742

Shunt voltage regulation The terminal voltage VT in figure 20.23a draws a lagging current IT and the shunt compensator Vsh is to maintain the load voltage VT constant, but at any angle with respect to VS. From Kirchhoff’s voltage law for the right hand loop in figure 20.23a, VT = jI sh X sh +V sh −n (20.57) The shunt compensator can deliver any current from zero up to a converter maximum I sh , giving, for a fixed compensation reactance Xsh, the circle outer locus with centre O as shown in figure 20.23b. Thus a small change in the magnitude and phase of Vsh will cause the shunt reactance voltage to rotate through 360°. From Kirchhoff’s current law, the shunt regulator point of common contact, PCC, yields I S = I sh + I T (20.58) These currents are shown in figure 20.23b. The outer voltage loop in figure 20.23a gives V S −n = jI S X R +VT −n (20.59) Substituting equation (20.58) gives V S −n = j ( I T + I sh ) X R +VT −n (20.60) = {VT −n + jI T X R } + jI sh X R Since the load network VT in conjunction with the load network current IT specify the load power factor, the phasor N-O, {VT-n + jITXR} in figure 20.23c is fixed. Because Ish can be varied between zero and I sh , phasor VS-n can lie anywhere within the circle shown in figure 20.23c and not affect the load network VT. In figure 20.23c, the shunt regulator is delivering real power into the load network since the shunt compensating network PCC voltage VT-n and shunt current (angle given by phasor O-W in figure 20.23c) are not in quadrature. Figure 20.23d shows the loci for the case when no real power is transferred by the shunt compensator, since the compensator current Ish is in quadrature to the shunt voltage Vsh-n, which is in phase with the load network VT. The allowable range of variation on the source voltage VS-n is a minimum for phasor NY (voltage-swell) and a maximum for phasor N-Z (voltage-sag), as shown in figure 20.23d. This range of possible voltage compensation is determine by the line reactance XR, which specifies the inverter current rating Ish needed to produce the necessary compensation range, namely the diameter of the circle in figure 20.23c. That is, the lower the line reactance XR the higher the necessary compensating inverter current rating for a given voltage compensation range. The shunt compensator operates in a type of current push-pull or sourcing-sinking mode. • When the source voltage VS is too high, voltage swell, the shunt draws or sinks current additional to the load current in order to increase the voltage across the line reactance XR, thereby tending to decrease the load voltage VT. • When the source voltage VS sags, the shunt compensator sources current to the load network VT, thereby reducing the source current which decreases the voltage across the line reactance XR, making a higher component of the source voltage available across the load network VT. During each mode of operation, the phasor angular relationships must be observed within this simplistic explanation. The basic shunt converter arrangement can also be using for line current distortion compensation. jXR

VXR VS-n

IS

PCC

jXsh

IT

Ish

Rsh

VT-n Vsh-n

φ N

(a)

VT-n

N

VXsh = jXshIsh

Vsh-n

VXsh = RshIsh

Ish

(b)

Figure 20.24. Active shunt compensator used for power factor correction: (a) shunt compensated network and (b) phasor diagram.

Power factor correction The shunt compensator can be used for power factor correction at the PCC. The compensator current Ish is set to be 90° behind the PCC voltage VT-n, with the magnitude of the current Ish determining the magnitude of the compensation. This is achieved by ensuring that the load voltage and shunt regulator voltage are in phase, but the relative magnitudes are varied (Vsh-n > VT-n). Since only VAr are involved

Power Electronics

743

from the shunt regulator, no shunt regulator dc voltage supply is needed to maintain the dc-link capacitor, except inverter losses must be accounted for. By ensuring the shunt voltage Vsh-n slightly lags the line voltage VT-n, the necessary inverter losses can be provided from the grid. If the inverter losses are incorporated, as represented by the resistor in figure 20.24a, then the resultant phasor diagram in figure 20.24b complies with the following output loop voltage equation. V sh −n = I sh Rsh + jX sh I sh +VT −n (20.61) The reactive power provided to the ac system from the shunt power factor controller is Q = Ish VT-n, while P = Vsh-n Ish cosφ real power is drawn from the line to cater for the inverter power losses. Since no separated dc-link voltage source is required, the shunt regulator is acting as a STATCOM, as considered earlier. Voltage distortion compensation The shunt regulator can be used to cancel line harmonic voltages. If harmonics of the fundamental supply frequency ω are cancelled, the load voltage and current at that frequency are zero as shown in figure 20.25. Then, from figure 20.25, where IS-harm = Ish-harm

V S −n −harm − jI S −harm n ωLR = V sh −n −harm + jI sh −harm n ωLsh

(20.62)

That is

V sh −n −harm = − jnωLR

Lsh × V S −n −harm LR

(20.63)

IT-harm

IS-harm

=0

Ish-harm

VXR jnωLsh

VT-n-harm =0

VS-n-harm Vsh-n-harm N

Figure 20.25. Active shunt compensator used for voltage distortion compensation.

The necessary cancelling voltage magnitude from the shunt regulator is dependant on the relative magnitudes of the two line reactance’s, independent of harmonic frequency. If Lsh > LR the shunt compensator must produce an anti-phase voltage greater in magnitude than the harmonic line voltage. Series compensation techniques are more effective for line voltage distortion compensation, while shunt compensation methods are more effective for line current harmonic compensation. The four-quadrant P-Q and boundary phasor diagrams for the shunt regulator are shown in figure 20.26. Table 20.1 Comparison of STATCOM and SVC property

STATCOM

SVC

Current source Good under-voltage performance Symmetrical Otherwise hybrid solution Redundancy Compensated aging degradation Common inverter to other applications 1 to 2 cycles No natural commutation delays Self protecting on critical system faults

Impedance source Good overvoltage performance Adjustable with cascaded TCR/TSC Redundancy Aging degradation TCR/TSC branches common additions to SVC 2 to 3 cycles Limited by supply frequency Active before, during and after transient conditions

Volume requirements

40% to 50% of SVC

100%

On-line availability

96% to 98% of time

>99% of the time

120% to 150% that of SVC

100%

I-V characteristic Control range

Modularity

Response time Transient behaviour

Capital costs

FACTS

744 VT-n

N

Vsh-n

Ish

Vsh-n

Vsh-n

Ish

VT-n

VAr to the grid capacitive

Vsh-n

+Q power from the grid

Q=0 P0 P=0

VT-n

N

Vsh-n > VT-n

VT-n = Vsh-n

-P

VT-n = Vsh-n

+P

Vsh-n

power to the grid

Vsh-n

-Q

N VT-n

VAr from the grid inductive

Ish

Ish

φ

VT-n N

Q=0 P>0

N

φ Vsh-n

Q12) converters. In the case of ac transmission, transformerless series power filtering is possible since lower voltages are usually involved, but usually a separate isolated single-phase inverter is needed in each phase. The inverter default mode is to operate with all (upper or lower) switches on so that the series compensator is seen as a short circuit. I IL t

t dc blocking capacitor

VS

XS

I

P of C

IL

+

XL

Idc

½Ldc

Cdc Ishunt

-

INL Rectifier

Lsh

Inductive load

Csh

High pass L-C filter

C VSI

Controlled 12 pulse converter

½Ldc Ihar

C

VDC

IDC

(a) ac APF

Controlled 12 pulse converter

VSI Single-phase

VDC

IDC

(b) dc APF

Figure 20.30. Combined transformerless active and passive power filters: (a) 50/60Hz ac decoupled shunt APF method and (b) dc decoupled shunt APF approach.

20.9

Summary of Compensator Comparison and Features

FACTS devices enhance high-voltage ac-grids by:

• • • • • • •

increase of power transfer without adding new transmission lines transmission cost minimization steady-state and dynamic voltage control reactive power control of dynamic loads active damping of power oscillations increase of reliability under system contingencies improvement of system stability and voltage quality high flexibility for embedding of various energy sources

A shunt compensator acts like a controllable current source and can draw or inject reactive leading or lagging current at the point of connection. Objectives of dynamic shunt compensation are • steady state and transient voltage control • Reactive power control of transient loads • Damping of active power oscillations • Increase of system stability

FACTS

750

A series compensator is a driving voltage at the line reactance midpoint, hence is more effective than a shunt compensator for controlling current and power flow, and for damping oscillations. It can only supply or absorb reactive power. When used as a phase angle controller, at the sending or receiving ends, a real power source is required. Objectives of dynamic series compensation are • Reduction of load dependent voltage drops • Reduction of system transfer impedance • Reduction of transmission angle • Increase of system stability • Load flow control to specific power branches • Damping of active power oscillations Two points to bear in mind when transformer coupling compensation FACTS type devices. • The transformer core must be able to transmit at the highest harmonic frequency. • Series coupling into a dc link imposes a dc bias current, hence flux in the coupling core. 20.10

Summary of the Advantages of AC Transmission over DC Transmission

The general advantages of ac transmission, over dc transmission, are • No costs associated with ac-dc-ac conversion equipment • Transformer (and autotransformer) voltage matching • Reactive power and harmonics readily compensated • Not restricted to only point-to-point connection, as is HVDC (there is one exception) • Established system control methods • No ac transformer dc voltage stressing due to asymmetrical phase control alignment, and no I2R and core losses due to high harmonic currents • ac switch gear and breakers, (and particularly vacuum circuit breakers up to 33kV) are very effective - compared with the difficulties in breaking dc current • Lower current harmonics

Reading list Mohan, N., Power Electronics, 3rd Edition, Wiley International, 2003. Acha, E., et al., Power Electronic Control in Electrical Systems, Newes, 2002.

CHAPTER

21

Energy Sources and Storage: Primary Sources

The progressive proliferation of embedded and distributed generation with renewable energy sources has spurred research into alternative energy sources and storage methods. Although this chapter is mainly concerned with primary sources, namely fuel cells and photovoltaic cells, their energy and power density capabilities can only be put into context by considering conventional energy sources, specifically, the hydrocarbons. In electrical terms, primary and secondary energy sources are defined as follows. Primary source is not a reversible energy source. During energy discharging, the original states are permanently changed as electrical energy is released until the original energy reactants, or any one of them, are depleted. A primary cell can be used only once. Secondary source is reversible and the original states can be reconstituted by the application of an electrical potential which injects energy into the source. A secondary cell can source and sink energy many times. 21.1

Hydrocarbon attributes

Table 21.1 shows that the energy density associated with the hydrocarbons dwarfs all other common sources such as batteries and supercapacitors. The table highlights why petrol is so firmly entrenched, while the limitations of hydrogen are made apparent. Although hydrogen offers 3 times more energy than petrol for a giving reactant weight, its volume per kg is grossly in excess of that of petrol. One mole of hydrogen H2 occupies 22.4 litres and weight just 2 grams. Thus the energy per unit volume for petrol is 2500 times more than that for hydrogen. Pressurising hydrogen mitigates the volume limitation some what, but liquefaction is at an impractical temperature of 20K (only helium has a lower boiling point). Pressure helps minimally since the boiling point rises to only 43K at 13 bar, with minimal temperature increase for higher pressures. On the other hand, propane has a boiling point of -42°C, but can be liquefied at 21°C and 13bar, with a gain in energy density. The expansion ratio for hydrogen is 1:850, that is, at atmospheric temperature and pressure, hydrogen gas occupies 850 times the volume as in its liquid state. The ratio is 1:240 at 250 bar and atmospheric temperature, but cannot approach the liquid ratio at much higher pressures, as shown in Table 21.2. Basically, hydrogen has a poor molecular packing density. A cubic metre of water contains 111kg of hydrogen, whereas a cubic metre of liquid hydrogen contains only 71kg of hydrogen. In fact, water (111kg) contains more kg/m3 of hydrogen that methanol (100kg) and a similar weight of hydrogen as in heptane (113kg). Thus, in summary, the specific energy of pure hydrogen (the energy per kilogram) is higher than any other fuel at better than 120 MJ/kg. However, its energy density (energy per m3) is very low, that is, it is

752

Primary Energy Sources

difficult to get a large mass of hydrogen into a small volume, as shown in table 22.2. Cryo-adsorption of hydrogen into graphite at low temperature and pressures up to 5MPa, or the use of metal hydrides, provide higher hydrogen storage densities, as shown in table 21.2. Table 21.1, in conjunction with figure 21.1, show that both batteries and super capacitors fall significantly short of the energy that can be released from hydrocarbons, on an equivalent volume and weight basis.

Table 21.1 Energy properties of hydrocarbons and alternative energy sources Fuel Type

Fuel

solid

charcoal

CO2

kWh/kg

MJ/Litre

MJ/m3

kg/m3

Litres/kg

30

10

-

6250

208

-

25

8

-

37500

1500

-

wood

16

5.4

-

8000

400-700

-

dung cake

7

2.3

-

5000

700

-

48

15

35

44000

820

0.73

petrol

50

16

48

37000

751

1.36

diesel

45

15

39

38200

850

1.19

ethanol

30

10

30

23700

789

1.00

bio gas

38

12

46

1.2

50

16

29

30000

600

butane gas

50

16

29

125

2.5

methane

55

18

0.9kJ/mol

39

0.668

hydrogen

150

49

13

0.0838

coal

kerosene

gas

butane(LPG)

battery

Density

MJ/kg

kg/kWh

liquid

Calorific Value

0.32

0.27

0.23

Lithium-ion

0

0.2

Lead acid

0

0.04

capacitor

double layer

0

0.02

fuel cell

hydrogen

0

26

PV cell

1.72

0

Flywheel

FES

0

0.13

fusion

U235

0

2.5×107

Table 21.2 Hydrogen; high gravimetric energy density but low volumetric energy density Energy carrier

Hydrogen

Form of hydrogen Storage 120 MJ/kg

Energy density by volume kWh/l

gas

20 MPa

33.3

0.53

gas

24,8 MPa

33.3

0.64

gas

30 MPa

33.3

0.75

liquid

-253°C

33.3

2.36

metal hydride fusion

Energy density by weight kWh/kg

U235

0.58 2.5×10

3.18 7

4.7×109

Comparisons The Ragone plot in figure 21.1 shows the energy storage and power handling capacity of some alternative storage techniques. Energy and power densities, in steady-state, are related by Energy = Power × time.

753

Power Electronics

W h/kg

103

1h

10 h

100 h

fuel cells

102

36s

3.6s

IC gas turbine

batteries Energy density

6 min

360ms

36ms

flywheel

1

10

3.6ms

double layer capacitors

100

super conductor magnetic energy storage

-1

10

capacitors

10-2 100

101

102

103

Power density

104

105

106

107

W/kg

Figure 21.1. Gravimetric energy and power densities of common energy sources.

21.2

The fuel cell

The fuel cell is similar to a battery, in function and appearance. It produces electricity directly, using chemicals. A fuel cell is a solid-state electrochemical device that consists of two electrodes, an anode and cathode, sandwiched around an electrolyte, with a catalyst membrane between each electrode and the electrolyte, which enhances ionization of the fuel molecules. The oxidant oxygen, usually from air, passes over the cathode electrode and typically hydrogen fuel over the anode, generating electricity, and water and heat by-products. An ion-conducting membrane separates the anode and cathode, allowing the reaction to take place without affecting the electrodes. The fuel cell relies on a basic oxidation/reduction reaction, as with a battery, but the reaction takes place on the fuel rather than on the electrodes. As long as fuel is supplied and oxidized old fuel is disposed of, the cell will continue to generate energy, both electrical power and heat. Since conversion of the fuel to energy takes place via an electrochemical process, not combustion, the process is clean - no CO2, quiet and highly efficient - two to three times more efficient than fuel combustion. How the Fuel Cell Operates The fuel cell process can be divided into three stages; two of these stages involve the chemical reactions at each electrode and the third is ion conduction through the electrolyte. (i) At the hydrogen electrode - anode The reaction at the anode involves the release of electrons from the hydrogen fuel that will then be conducted by the electrode to the electrical load. The hydrogen arrives at the anode as a diatomic gas 2H2 where each adsorbed hydrogen molecule ionizes into four hydrogen protons, H+ and four electrons, e-. The rate of this process is increased with the aid of a catalyst. Because the chemical reaction at this electrode produces positive ions, it is the anode. The negatively charged electrons are then forced to flow from the conductive electrode (anode) to an external electrical load before reentering the fuel cell at the cathode (that is, electrons diffuse naturally from a high concentration to a low concentration of electrons). However, the hydrogen ions may or may not conduct through the electrolyte since this depends on the pH and type of electrolyte used, meaning the hydrogen ions may have to temporarily remain at the anode in a receptive state. (ii) At the oxygen electrode - cathode Meanwhile, oxygen molecules O2 are diffusing through to the catalytic surface of the cathode electrode which facilitates the separation of the adsorbed oxygen molecule (oxygen bonds are broken) into oxygen atoms which are held momentarily in a receptive state on the active catalyst. The entering electrons diverted externally from the anode bypassing the electrolyte, the oxidant, and cathode electrode together causes another reaction to occur where negative ions and products are produced. If H+ ions are the free moving ions (because of the acid electrolyte used), they are attracted to the negative ions generated at the cathode and conduct through the acid electrolyte and product 2H2O, along with heat. If however, H+ ions are not able to travel through the electrolyte, then

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the cathode produced free moving negative ions move through the alkali electrolyte to combine with the H+ ions to complete the process at the anode. (iii) Through the electrolyte medium The electronically-insulated (does not conduct free electrons) electrolyte serves as the physical barrier preventing the fuel and oxidant gas streams from directly mixing allowing, only the appropriate ions to move freely through the layer. This requires that one of the reactants must be able to form the ionized specie needed to complete the process and form the primary by-product, water. Fuel cells that use hydrogen can be thought of as an electrochemical devices that perform the reverse of electrolysis, where passing an electric current through water splits it up into hydrogen and oxygen. In the fuel cell, hydrogen and oxygen are joined together to produce water and electricity. Although the majority of fuel cells use hydrogen as the fuel, some fuel cells work off methane, and a few use liquid fuels such as methanol. H2

anode (-)

anode (-)

catalyst

catalyst

acid electrolyte

cations

catalyst

H2O

cathode (+)

O2

(a)

electrons

electrons

H2

base electrolyte

H2O anions

catalyst cathode (+)

(b)

O2

Figure 21.2. Pictorial representation of a fuel cell with electrolyte conduction of: (a) cations and (b) anions.

Two basic ion operating mechanism are possible. The first involves cations passing through an acid electrolytic membrane from anode to cathode, while the second mechanism involves anions passing through an alkali membrane in the opposite direction, namely from the cathode to the anode. The ion conducting membrane is non-conducting to electrons. •

•

Cation conduction: Pressurised hydrogen H2 gas fuel is fed into the anode of the fuel cell. The pressure forces the H2 through the catalyst. When an H2 molecule comes in contact with the platinum catalyst, it splits into two H+ ions (protons) and two electrons e-, which take different paths to the cathode. The catalyst increases the rate of this splitting process. The electrolyte membrane does not pass electrons. The electrons conduct externally from the anode, creating a current that can be utilized in an external circuit, then return to the cathode-side of the fuel cell where they are reunited with the hydrogen plus oxygen ions forming a molecule of water, as illustrated in figure 21.2a. Meanwhile, on the cathode-side of the fuel cell, oxygen gas O2 (or air) is being forced through the catalyst, where it is encouraged to form two oxygen atoms. Each of these atoms has a strong negative charge. This negative charge attracts two H+ ions, protons, at the anode side through the membrane, where they combine with an oxygen atom and two of the electrons from the external circuit to form a water molecule H2O, plus heat energy.

Anion conduction: The operating principle of an anion conducting cell is illustrated in Figure 21.2b. Oxygen supplied at the cathode (air electrode) reacts with incoming electrons from the external circuit to form oxide ions, which migrate to the anode (fuel electrode) through the anion conducting electrolyte. At the anode, anions combine with hydrogen ions (and/or carbon monoxide) in the fuel to form water (and/or carbon dioxide), liberating electrons. Electrons (electricity) flow from the anode through the external circuit to the cathode. In principle, fuel cells can operate on many combination of reactants but most fuel cells actually operate on a narrow range of fuels in combination with oxygen from the air. As considered in section 21.9, fuels range from pure hydrogen gas, liquid alcohols and other liquid or gaseous hydrocarbons to metals and solid carbon. For the fuel cell types restricted to operating only on pure hydrogen, it is necessary to involve systems that generate hydrogen. Electrolysis and fuel reforming technologies generate hydrogen, but storage at useful energy densities is problematic. Several types of fuel cell can be operated directly on readily available fuels such as methanol, ethanol and natural gas, thereby dispensing with the infrastructure issues of hydrogen. Traditionally these fuels come predominantly from

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fossil sources, but they are also increasingly available from renewable bio-sources. Since the fuel cell relies on electro-chemistry and not combustion, emissions are smaller than emissions from the cleanest fuel combustion processes. Fuel cells can be made in a huge range of sizes, from a few watts to MW. The potential power generated by a fuel cell stack depends on the number and size of the individual fuel cells that comprise the stack and the surface area of the membrane. Since the single fuel cell produces only about 0.7V, many separate fuel cells must be series connected to form a high-voltage fuel-cell stack. Bipolar plates are used to judiciously connect one fuel cell to another and are subjected to both oxidizing and reducing conditions and potentials. An issue with bipolar plates is stability. Metallic bipolar plates corrode, and the by-products of corrosion (iron and chromium ions) decrease the effectiveness of fuel cell membranes and electrodes. Low-temperature fuel cells use lightweight metals, graphite, and carbon plus high temperature thermoset composites, as bipolar plate material. The fuel cell offers a unique combination of benefits. In addition to low or zero emissions, benefits include high efficiency and reliability, multi-fuel capability, siting flexibility, durability, scalability and ease of maintenance. Fuel cells operate silently, so they reduce noise pollution as well as air pollution and the waste heat from a fuel cell can be used to provide domestic hot water or space heating. There are several different types of fuel cells, each using a different chemistry. Fuel cells are usually classified by their operating temperature and the type of electrolyte used. The materials for the cell components are selected based on suitable electrical conducting properties required of these components to perform their intended cell functions: • adequate chemical and structural stability at high temperatures encountered during cell operation as well as during cell fabrication; • minimal reactivity and interdiffusion among different components; and • matching thermal expansion among different components. 21.3

Materials and cell design

Like the battery, the fuel cell has few component parts although the materials may be sophisticated, involving rare earth transitional metals, high temperature composite ceramics, cermets, etc. The basic fuel cell component parts are: • Electrodes; • Catalysts; • Electrolyte; • Interconnects; and their • Stack construction. 21.3.1 Electrodes Fuel cell electrodes serve three functions: • To ensure a stable interface between the reactant gas and the electrolyte; • To catalyze the electrode reactions; and • To conduct electrons from or to the reaction sites An electrode forms part of the three-phase boundary, where the electrolyte, electrode, and gas all come together. i.

•

Cathode The cathode is the positive electrode of the fuel cell because it is the electrode where negative ions are produced. It has etched channels that distribute the oxygen to the surface of the catalyst. It also conducts the electrons received from the external circuit to the catalyst, where they can recombine with the hydrogen ions and oxygen to form water. An integral part of the cathode is the metallic interconnect, a bipolar plate, which forms an integral part of the anode of the adjacent cell, when cells are series connected to give higher voltage output.

The oxidant gas is air or oxygen at the cathode, and the electrochemical reduction of oxygen requires a series of elementary reactions and involves the receipt of multiple electrons. The cathode must meet the requirements of: • high catalytic activity and high surface area for oxygen molecule dissociation and oxygen reduction; • high electronic conductivity; • chemical and dimensional stability in environments encountered during cell fabrication and cell operation; • thermal expansion match with other cell components;


• • ii.

•

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compatibility and minimum reactivity with the electrolyte and the interconnection; and must have a stable, porous microstructure so that gaseous oxygen can readily diffuse through the cathode to the cathode/electrolyte interface.

Anode The anode is the negative electrode of the fuel cell because it is the electrode where positive ions are produced. It conducts away the electrons that are released from the hydrogen molecules so that they can be used in an external electrical circuit. An integral part of the anode is the metallic interconnect, a bipolar plate, which form parts of the cathode of an adjacent series cell. It has channels etched into it that disperse the hydrogen gas uniformly over the surface of the catalyst.

The properties of the anode must include: • an excellent catalyst (in the case of high temperature fuel cells) with a large surface area for the oxidation of fuel (hydrogen, carbon monoxide); • stable in the reducing environment of the fuel; • electronically conducting; • have sufficient porosity to allow the transport of the fuel to and the transport of the products of fuel oxidation away from the electrolyte/anode interface where the fuel oxidation reaction takes place; • matching thermal expansion coefficient with that of the electrolyte and interconnect; • integrity of porosity for gas permeation; • chemical stability with the electrolyte and interconnect; • applicability to use with versatile fuels and impurities; and • cost effective is a commercialization factor. 21.3.2 Catalyst • The catalyst facilitates and speeds up the rate of the ionization reaction of oxygen at the cathode and hydrogen at the anode. It is usually made of platinum for low temperature cells and nickel at higher temperatures. The catalyst is rough and porous so that the maximum surface area can be exposed to the hydrogen or oxygen. The catalyst faces the electrolyte and must be able to conduct electrons to/from the electrode. The effectiveness of the catalyst is paramount to fuel cell operation. Platinum is sufficiently reactive in bonding H and O intermediates as is required to facilitate the electrode process, then effectively releases the intermediate to form the final product. For example, the anode process requires Pt sites to bond H atoms when the H2 molecule reacts, and these Pt sites release the H atom as H+ + e-, as shown in the two equations: H 2 + 2 Pt → 2 Pt −H

2 Pt −H → 2 Pt + 2 H + + 2 e − Platinum can be oxidized which is a problem because it compete with hydrogen oxidation, reducing the half-cell potential: Pt + H 2O ↔ PtOH + H + + e −

Pt + H 2O ↔ PtO + 2H + + 2e − O 2 + 2H + + 2e − → H 2O Catalytic reduction action also occurs on the cathode: O 2 + 2 Pt → 2 Pt −O 2 Pt −O → 2 Pt + 2 O 2− − 4 e − The reaction effectiveness is dependant on temperature and platinum surface area. At lower temperature reactions, platinum particles are used, 2 nanometres in diameter, resulting in a large Pt area that is accessible to the gas molecules. At elevated temperatures, over 400C, transition metals, Ni and oxides NiO, become effective, low cost catalysts, that can also act as the electrode. NiO + CO 2 → Ni 2+ + CO 32− At higher again temperatures no catalyst is necessary. Reduction of oxygen at the cathode is less efficient than the catalytic action on hydrogen at the anode. In lower temperature fuel cell, various nanoparticle platinum alloys (AuPt and Pt3Ni-III) are used to increase the O2 reduction reaction activity. The tolerance to poisoning and the affects of an acidic environment are factors to be overcome with semi-formed alloy catalysts.

21.3.3 Electrolyte In terms of chemistries, there are two main types of fuel cells, depending on the pH of the electrolyte. Common to all electrolytes is that they must not conduct free electrons.

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• •

Acid electrolyte which allows H+ hydrogen ion (proton) migration and free movement through the electrolyte from the anode to the cathode, producing water at the cathode, while conversely Alkaline electrolyte which allows anion migration, for example, OH- hydroxyl ion migration through the electrolyte from the cathode to the anode, producing excess water at the anode.

The electrolyte is the either a solid (< 200°C) or a liquid (> 200°C), depending on the operating temperature. The electrolyte can be acidic or alkali and must pass ions but importantly, the electrolyte does not conduct free electrons and does not react with reactant ions. There are several criteria that the electrolyte has to meet. The electrolyte must be: • Dense and leak tight; • Stable in reducing and oxidising environments; • A good ionic conductor at operating temperatures; • Non-electron conductor; • Thin to reduce ionic resistance; • Extended in area for maximum current capacity; • Thermal shock resistant; and • Economically processable. 21.3.4 Interconnect Since a single cell only produces a voltage of less than 1V and power around 1W/cm2, many cells are electrically connected together in a cell stack to obtain higher voltage and power. To connect multiple cells together, an interconnection is used in stacks. The requirements of the interconnection are the most severe of all cell components and include: • High, nearly 100 percent electronic conductivity, not only through the bulk material but also in in-situ-formed oxide scales; • strong adhesion between the as-formed oxide scale and the underlying alloy substrate; • resistance to corrosion and surface stability in both oxidizing and reducing atmospheres at the cell operating temperature since it is exposed to duel atmospheres, with air (or oxygen) on the cathode side and fuel on the anode side; • low permeability for oxygen and hydrogen to minimize direct combination of oxidant and fuel during cell operation; • chemical compatibility with other materials in contact with the interconnect, such as seals and cell materials; • mechanical reliability and durability at the cell operating temperature; • a thermal expansion coefficient close to that of other stack components, mainly the cathode and the electrolyte (particularly for stacks using a rigid seal design); and • non-reactivity chemical compatibility with other cell materials. Suitable metallic alloy interconnects offer advantages such as improved manufacturability, significantly lower raw material and fabrication costs, and higher electrical and thermal conductivity. 21.3.5 Stack design In the case of planar cell stacks, an effective seal must be provided to isolate air from the fuel. The seal must have a thermal expansion match to the fuel cell components, must be electrically insulating and must be chemically stable under the operational conditions of the stack. Also, the seal should: • exhibit no deleterious interfacial reactions with other cell components; • be stable under both the high temperature oxidizing and reducing operational conditions; • be created at a low enough temperature to avoid damaging cell components (under 850oC for some materials); and • should not migrate or flow from the designated sealing region during sealing or cell operation. In addition, the sealing system should be able to withstand thermal cycling between the cell operation temperature and room temperature. Sealing is more of a problem with cell which operate at higher temperatures, where different sealing approaches include rigid, bonded seals (for example, glassceramics and brazes), compliant seals (for example viscous glasses) and compressive seals (for example, mica-based composites); multiple sealants may also be used in any given stack design between different cell components.

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Primary Energy Sources bipolar flow-field plate, graphite gas diffusion backing layer anode catalyst 3nm electrolyte membrane 25µm cathode catalyst gas diffusion layer

membrane catalyst

Heat water H2O

anode

cathode

-

e

-

e

+

H

hydrogen fuel

air

hydrogen H2

porous gas diffusion layers

air O2

Figure 21.3. The parts of a fuel cell/Membrane/electrode assembly with backing layers. Enlarged cross-section of a membrane/electrode assembly showing structural details.

21.4

Fuel Cell Chemistries

The two chemical ion mechanisms involving anions and cations, will be discussed in terms of: • an acid electrolyte and transfers cations, protons, H+, through the electrolyte, producing water at the cathode and • an alkaline electrolyte and transfers anions (OH-, CO32-, O2-) through the electrolyte, producing water at the anode. 21.4.1 Proton H+ Cation Conducting Electrolyte: e.g. PEMFC, DMFC, PAFC The Acidic electrolytic Fuel Cell utilises one of the simplest reactions of any fuel cell. In low temperature PEMFC and DMFC Fuel Cells, the electrolyte is a flexible acidic membrane that when saturated offers a number of desirable features: • Highly chemical resistant; • Mechanically strong, when only 50µm thick; • Acidic; • Highly water absorptive; • Good proton conductor, H+ cation, when saturated, but not flooded; • Electrically insulating, high resistance to electrons; and • Non-diffusive the gas molecules, no H2 and O2 crossover. Chemistry In both acid electrolyte and solid polymer fuel cells the electrolyte conducts mobile H+ ions, protons, generated at the anode. It is these H+ ions that are key to the reactions within the cell. At the anode, hydrogen gas is readily ionised, producing free electrons and H+ ions: 2 H 2( g ) → 4 H + + 4 e -

E ½o cell = 0.0V

(21.1)

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The electrons from the anode conduct through the external circuit connected to the fuel cell, to the cathode. The H+ ions migrate or permeate through the electrolyte, and also reach the cathode. At the cathode the H+ ions and electrons react with the oxygen atoms, producing water. At the cathode the oxygen undergoes a two-step indirect reduction reaction. The stable H2O2 intermediate is undesirable as it lowers the cell voltage and H2O2 attacks and corrodes the carbonaceous electrodes commonly used in lower temperature cells. O 2 + 2H + + 2e − = H 2O 2 (21.2) H 2O 2 + 2H + + 2e − = 2H 2O Overall cathode half reaction:

O 2 ( g ) + 4 H + + 4 e - → 2 H 2O

E ½o cell = 1.23V

(21.3)

This movement of ions through the electrolyte, and movement of electrons through the external circuit is illustrated in the diagram in figure 21.4a. The net fuel cell reaction, which is exothermic, is the algebraic summation of the half-cell reactions: 2H 2( g ) + O 2( g ) → 2H 2O + energy

o E cell = 1.23V

(21.4)

o = 1.23 - 0 = 1.23V. Standard tables give the enthalpy as The chemistry of the fuel cell gives E cell 285.15kJ/mol and the number of electrons per H2, as n = 2. The dissociation kinetics of O2 and H2 improve with increased temperature but the cell potential decreases with temperature.

electron flow

anode

∆G = 237kJ/mol

-

-

-

4e

4e

2e -

∆H = 286kJ/mol

H2 → 2H+ + 2e-

∆G = ∆H - T∆S

+

2H2 2e

acidic electrolyte

-

cathode

O 2 ( g ) + 4 H + + 4 e - → 2 H 2O

+

-

fuel H2 hydrogen

2 H 2( g ) → 4 H + + 4 e -

-

+ +

-

-

or oxidant - oxidiser

O2

O + 2H+ + 2e- → H2O

O-

H

+ +

O2 oxygen from air

2e

-

heat 85°C T∆S = 49kJ/mol

2H2O

unused fuel recirculates exhaust

air and water vapour H2O exhaust flow field plate

flow field plate anode gas diffusion electrode

cathode gas diffusion electrode

Pt catalyst

Pt catalyst cation exchange membrane

Figure 21.4. The chemistry mechanisms of an acidic electrolyte fuel cell.

Positive ions are produced at the anode and negative ions are produced at the cathode. The water molecules are always produced at the cathode, the production of which exceeds that which may be required (if any) at the anode. The H+ cations, as found in the Polymer Exchange Membrane Fuel Cell - PEMFC, Direct Methanol Fuel Cell – DMFC, and the Phosphoric Acid Fuel Cell - PAFC all behave the same within the fuel cell. That is, equations (21.1) to (21.4) are applicable to the three cation fuel cells presented.

4e

760


21.4.2 Anion (OH-, CO32-, O2-) Conducting Electrolyte: e.g. AFC, MCFC, SOFC The important feature of an alkali is that there is an excess of anions, X- ions, generated at the cathode, and these are key to the reactions within the alkali electrolyte fuel cell. An electric current is produced as a result the half-cell reaction at each electrode. At the anode, hydrogen gas reacts with the X- ions, anions which have migrated through the electrolyte, producing water, and releasing electrons. The reaction is: 2H 2( g ) + 4 X (−aq ) → 4H 2 0(l ) + 4e -

(21.5)

The electrons leave the fuel cell at the anode, passing through the external electrical circuit connected to the fuel cell, and reach the cathode. At the cathode the entering electrons react with the incoming oxygen, and water, producing more X- ions to replenish those used at the anode.

O 2( g ) + 2H 2O + 4e - → 4 X (-aq )

(21.6)

The X- ions move through the electrolyte, and the electrons move round the external circuit. The complementary movement of ions and electrons is illustrated in the diagram in figure 21.5a. The net reaction, which is exothermic, is the algebraic half-cell reaction summation: 2H 2( g ) + O 2( g ) → 2H 2O + energy

(21.7)

Positive ions are produced at the anode and negative ions are produced at the cathode. Water molecules are always produced at the anode, and at a faster rate than those (if any) being consumed at the cathode. Anions, such as OH-, CO32- and O2- as found in the Alkaline Fuel Cell - AFC, Molten Carbonate Fuel Cell - MCFC, and Solid Oxide Fuel Cell - SOFC, behave similarly within the fuel cell, as given by equations (21.5) to (21.7). electron flow

-

anode

-

-

4e

4e

-

-

2 H 2( g ) + 4 X − → 4 H 2O + 4 e alkali electrolyte

cathode O 2

4e

+ 2 H 2O + 4 e → 4 X -

(g )

−

+ 2-

O OH 2CO3

4e -

fuel, H2 hydrogen

-

2H2

O2 oxygen from air

4e -

-

heat 200°C

O2

-

X-

-

2H2O CO2

2H2O

water vapour H2O

air

CO2/H2O electrode - anode

electrode - cathode

catalyst

anion exchange electrolyte

catalyst

Figure 21.5. The chemistry mechanisms of an alkaline electrolyte fuel cell.

21.5

Six different Fuel Cells

Some of the main types of fuel cells, with increasing operating temperature, include:

•

Low-temperature Fuel Cell Types (200°C) o Phosphoric-acid fuel cell (PAFC) - H+ o Molten-carbonate fuel cell (MCFC) - CO32o Solid oxide fuel cell (SOFC) - O2-

Low-temperature Fuel Cell Types

21.6.1 Polymer exchange membrane fuel cell (PEMFC) (Proton Exchange Membrane FC) The PEMFC has a high power density and a relatively low operating temperature (ranging from 60 to 80°C). The low operating temperature means that the fuel cell can warm-up and begin to generate electricity quickly, resulting in less wear on system components, leading to better durability. Cells do not use corrosive fluids like some fuel cells. However, it requires a noble-metal catalyst (typically platinum) to separate the hydrogen's electrons and protons, adding to system cost. The platinum catalyst is also hyper-sensitive to CO poisoning, making it necessary to employ an external reactor to reduce CO in the fuel gas if the hydrogen is derived from an alcohol or hydrocarbon fuel. Platinum/ruthenium catalysts are more resistant to CO. The slow kinetics of oxygen at the cathode also necessitates the use of a catalyst. Higher-density liquid fuels such as methanol, ethanol, natural gas, liquefied petroleum gas, and gasoline can be used for fuel, but the system must have an external fuel processor to reform the methanol to hydrogen. Reforming releases minimal carbon dioxide. The PEMFC has a high power density, high efficiency, and can adapt to varying demands. It promises a high conversion efficiency of over 60% and an energy density of 120 W/Kg, with 2kW/l and 2W/cm2. The PEM fuel cell is currently favoured for electric motor vehicles. Other applications include air conditioning and domestic sized electronic equipment. Key features are: • Fast start-up, rapid transient power response, high power density, compact • H+ via polymer (ionomer) membrane electrolyte, Pt, 50°C to 150°C, H2 at < 5 atm. • Sensitive to impurities, CO, sulphur species, and NH3 • Anode and cathode gas sealing is simpler with a solid electrolyte therefore cheaper, no orientation restrictions, and low corrosion leads to a longer cell and stack life. • Portable applications, 50 to 500kW – automotive, small stationary auxiliary power units • Overall reaction ∆H = -286.0kJ/mol, with n = 2. PEMFC Pt

E ½o cell = 0.0V

Anode Reactions:

2 H 2( g ) → 4 H + + 4 e -

Cathode Reactions:

o Pt O 2( g ) + 4 H + + 4 e - → 2 H 2O E ½cell = 1.229V

Overall Cell Reactions: 2 H 2( g ) + O 2( g ) → 2 H 2O

o E cell = 1.229V

As shown in figure 21.3 for the PEMFC case, which is typical of the basic physical structure, there are four basic elements of the fuel cell: • The anode is the negative electrode and conducts the electrons that are released from the hydrogen molecules so that they can be used in an external electrical circuit. The carbon or metal interconnect, which makes electrical contact to the anode carbon sheet, has channels etched into it that disperse the hydrogen gas uniformly over the back surface of the catalyst layer. • The cathode is the positive electrode and also has etched channels that distribute the oxygen to the back surface of the catalyst layer. It also conducts the electrons received from the external circuit to the catalyst, where they can recombine with the hydrogen ions and oxygen to form water. The carbon or metal interconnect, like the anode interconnect, makes electrical contact to the cathode carbon sheet. • The electrolyte is the proton exchange membrane. This specially treated organic material is a thin, 50µm, flexible plastic (poly-perfluorosulphonic acid) film, which only conducts positively charged ions when it is saturated with water. The membrane must be hydrated (by absorbing water) in order to function and remain stable. Importantly, the membrane blocks electrons. Being a solid, membrane helps minimise gas crossover. • The catalyst is usually made of platinum nanoparticles thinly coated onto carbon paper or cloth, which is the effective anode or cathode. The catalyst is rough and porous so that the maximum platinum surface area can be exposed to the hydrogen or oxygen. The platinum-coated side of the carbon sheet, the catalyst, faces the polymer membrane.

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The Backing Layers The fuel cell anode and cathode assemblies are designed to maximize the current that can be obtained from an electrode and catalyst assembly. The backing layers on which the catalyst is deposited, are usually made of a porous carbon paper or carbon cloth, typically 100 to 300 µm thick, that can conduct the electrons and effectively diffuse reactant gas ions created and reacted in the platinum catalyst. The platinum catalyst particles are deposited 50µm thick on one side of each backing layer; the side that faces the electrolytic. Diffusion refers to the flow of gas molecules from a region of high concentration, the outer side of the backing layer where the gas is flowing by in the flow fields, to a region of low concentration, the inner side of the backing layer next to the catalyst layer where the gas is consumed by the reaction. The porous structure of the backing layers allows the gas to spread out as it diffuses so that when it penetrates the backing, the gas will be in contact with the entire surface area of the catalyzed membrane. The backing layers also assist in water management during the operation of the fuel cell. An effective backing material allows the correct amount of water vapour to reach the membrane/electrode assembly to keep the membrane humidified. The backing material also allows the liquid water produced at the cathode to leave the cell to avoid flooding. The backing layers are often wet-proofed with Teflon to ensure that most of the pores in the carbon cloth (or carbon paper) do not become saturated with water, which would prevent the rapid gas diffusion necessary for a good rate of reaction, from occuring at the electrodes. The solid organic polymer electrolyte membrane The polymer electrolyte membrane is essentially PTFE containing a fraction of pendant sulphonic acid groups. (Nomenclature: ‘sulphonic acid group’ usually refers to the un-dissociated SO3H group, where as ‘sulphonate’ refers to the ionised SO3– group after the proton has dissociated). The ion containing component is normally given in terms of equivalent weight (that is, number of grams of dry polymer per mole of acidic groups). The useful equivalent weight for Nafion ranges from 800-1500 g/mol. The length of and the precise nature of the side chains vary between different brands of polymer. Common to all is the PTFE based fluorocarbon ‘backbone’ of the polymer that has several desirable properties: • PTFE is hydrophobic - this means the hydrophilic sulphonate groups are effectively repelled by the chains and cluster together; • PTFE is extremely resilient to chemical attack – the environment within the membrane is hostile and acidic. Hydrocarbon-based polymers would tend to degrade rapidly; and • PTFE is a thermoplastic with high mechanical strength – meaning very thin membranes can be produced, reducing the thickness of each cell and increasing the power density of the stack. As shown in figure 21.6, the thin permeable electrolyte sheet of poly-perflourosulphonic acid consists of three distinct regions. • A Teflon-like fluorocarbon backbone of hundreds of repeating chains −CF 2 − CF − CF 2 − • Side chains connecting the molecular backbone to the third region O − CF 2 − CF − O − CF 2 − CF 2 − • Ion clusters of sulphonic acid ions -

SO 3−H + When the membrane becomes hydrated, the hydrogen ions become mobile and bond to water molecules as they move from one SO3- site to another in the acid molecule. main backbone

side chain ion cluster Figure 21.6. A PTFE fluorocarbon used for the PEM fuel cell electrolyte.

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21.6.2 Alkaline fuel cell (AFC) This is one of the oldest designs for fuel cells, with modest cell efficiencies of nearly 70%. The AFC is susceptible to contamination, so requires pure hydrogen and oxygen. It is also expensive, which is hampering commercialization. Key features are: • Fast start-up, but bulky, 10kW to 100kW • OH via liquid or polymer electrolyte, KOH, non-Pt, 80°C to 160°C, gas or liquid fuels • Susceptible to carbon contamination by K2CO3 formation, needs pure H2 and O2 • Portable, small stationary/transport, space vehicles, submarines • Overall reaction ∆H = -286.0kJ/mol, with n = 2. The anode half-cell reaction involves two stages. Ni

2H 2 → 4H + + 4e − Ni

4H + + 4OH − → 4H 2O

The overall cell reactions are: Anode Reaction:

o Ni 2 H 2( g ) + 4 OH - → 4 H 2O + 4 e - E ½cell = -0.83V

Cathode Reaction:

O 2( g ) + 2 H 2O + 4 e - → 4 OH -

Ni

Overall Net Reaction: 2 H 2( g ) + O 2( g ) → 2 H 2O

E ½o cell = 0.401V o E cell = 1.231V

o The chemistry of this fuel cell gives E cell = 0.401 - -0.83 = 1.231V. Standard tables give the enthalpy as 286kJ/mol and the number of electrons per H2, as n = 2.

These fuel cells use an alkali solution of potassium hydroxide KOH in water as the electrolyte and can use a variety of non-precious metals as a catalyst at the anode and cathode. High-temperature AFCs operate at temperatures between 100°C and 250°C, with newer AFC designs operating at temperatures below 100°C. Concentration of electrolyte, KOH, which is contained in an asbestos matrix, decreases to 50% at lower temperatures. Electro-catalyst can by Ni, Ag, metal oxides, spinels, and noble metals. Aqueous alkaline solutions do not reject CO2. Thus a disadvantage of this fuel cell type is that it is readily poisoned by carbon dioxide CO2, which reacts to produce K2CO3 that irreversibly blocks the pores in the cathode. The levels of CO2 in the air affect cell operation, making it necessary to purify both the hydrogen and oxygen used in the cell. This purification process is costly. This susceptibility to catalyst poisoning affects the cell's lifetime and precludes the use of platinum as a catalyst. 21.6.3 Direct-methanol fuel cell (DMFC) The methanol fuel cells is an optimised PEMFC but is not as efficient. The efficiency is low due to the permeation of neutral methanol and water through the sulphonated organic hydrocarbon polymer membrane, termed crossover. The low-temperature oxidation of methanol to hydrogen ions and carbon dioxide requires more active platinum catalyst, which makes these fuel cells expensive. Other catalysts are Ni, Ag, metal oxides, spinels and noble metals. DMFC do not use hydrogen fuel, but more convenient liquid methanol. The anode catalyst draws H2 from liquid methanol, thus eliminating the need for a fuel reformer. They are less efficient but offer compact and convenient designs suitable for future consumer electronics applications and in automotive areas because the fuel is convenient. One litre of methanol can theoretically provide 5kWh, but 1.7kWh outputs are typical. Key features are: • Use with liquid alcohol - methanol canisters, compact, no reforming • Methanol is liquid from -97°C to 65°C, with ×10 the energy/litre of highly compressed H2 • H+ via polymer electrolyte, Pt or alternatives (Ru), 90°C to 100°C Direct Methanol • Cell efficiency of 40% and increases with temperature • Small portable, battery replacement in mobile phones and laptops, small transport • Overall reaction ∆H = -726.6kJ/mol, with n = 6.

CO2

764


Anode Reaction: Cathode Reaction: Overall Cell Reaction:

o Pt/Ru 2 CH 3OH + 2 H 2O → 2 CO 2( g ) + 12 H + + 12 e - E ½cell = 0.2V

Pt

3 O 2( g ) + 12 H + + 12 e - → 6 H 2O 2 CH 3OH + 3 O 2( g ) → 2 CO 2( g ) + 4 H 2O

E ½o cell = 1.23V o E cell = 1.214V

Note that H2O is required at the anode, with an excess over the anode requirement being produced at the cathode. 21.7

High-temperature Fuel Cell Types (well in excess of 100°C)

21.7.1 Phosphoric-acid fuel cell (PAFC) The liquid phosphoric-acid fuel cell has potential for use in small stationary power-generation systems up to 10MW with 50% cell efficiency and better than 80% efficiency if steam produces cogeneration, CHP. It operates at a higher temperature than polymer exchange membrane fuel cells, so it has a longer warm-up time, restricting its application areas, and it must be continuously operated since H3PO4 electrolyte effloresces irreversibly and solidifies at 40°C. A silicon carbide matrix is used to retain the H3PO4 electrolyte. CO2 does not affect the electrolyte or cell performance, which can therefore be operated with reformed fossil fuel. Simple construction, low electrolyte volatility, and long-term stability are additional advantages. Key features are: • First commercially available, best suited to large size • H+ via liquid or polymer electrolyte, Pt, 150-250°C, with near 100% concentration H3PO4 • Carbon paper electrodes Pt coated, Pt unaffected by CO (60%; internal combustion engine is typically about 30%. High energy density. Silent operation and safe, with no moving parts, vibration free Portable. Modular construction. Low maintenance.

Shortcomings • The environmentally friendly credentials of fuel cells overlook the processes needed to generate and distribute the necessary hydrogen fuel. Fuel cells merely shift the pollution from the fuel cell to the reforming location. • 98% of hydrogen is produced from fossil fuel sources. • No infrastructure exists to provide and distribute the necessary hydrogen fuel. • Electrolyte freeze-up at low temperatures. • Electrodes and catalysts are prone to contamination and are expensive. • Because of the exotic materials and complex design, the system is expensive. • Not yet proven commercially viable in common usage, compared to the alternatives. • Best as primary source. • Limited availability. • Low durability. • Low power density per unit volume, not volume efficient due to associated ancillaries. • Alternatively hydrogen can be generated in situ, as required, from hydrocarbon fuels such as ethanol, methanol, petrol or compressed natural gas from the reforming process. Reforming generates carbon dioxide as a waste product. It is also expensive


• • • • • • • 21.16

780

with a chemical plant in situ, but this does simplify the fuel supply infrastructure problem, however the fuel could just as readily be used in an internal combustion engine. Despite safety precautions, there is a perception that hydrogen fuel is unsafe. The low cell voltage, 0.6V to 0.7V, means that many series connected cells are needed. Pulse demands shorten lifetime. The process is not reversible within the fuel cell and as with the primary cell, it cannot accept or store regenerative energy. The reactants must flow continuously. Fuel cells have a low dynamic range and slow transient response which causes an unacceptable lag in responding to instant power demands. At low powers levels, a power boost from a battery or supercapacitor would improve transient performance. Most designs operate at high temperatures so as to achieve reasonable operating efficiencies. To generate the same efficiencies at lower temperatures requires large quantities of expensive platinum catalysts. Complex to operate.

Fuel Cell Challenges

The shortcomings of the fuel cell represent the possible challenges of this energy source. 21.16.1 Chemical Technology Challenges Fuel cell material development is mainly concern with electrolytic membrane materials. Many of the following challenges are orientate towards EV application using the PEM fuel cell.

•

•

•

•

21.16.2

Durability: More durable PEMFC membranes are needed that can operate at temperatures greater than 100 °C and still function at sub-zero ambient temperatures. A 100°C temperature target is required in order for a fuel cell to have a higher tolerance to impurities in fuel. Also, water by-product at over 100ºC has better co-generation possibilities. Because of frequent start and stop, it is important for the membrane to remain stable under cycling conditions. Membranes tend to degrade with cycling, particularly as operating temperatures rise. Hydration: PEMFC membranes must be hydrated in order to transfer hydrogen protons. At around 80°C, hydration is lost without a high-pressure hydration system. Membranes are needed for sub-zero temperature operation, low humidity environments, and high operating temperatures. The SOFC durability: Solid oxide systems have issues with material corrosion. Seal integrity is also a major concern. The cost goal for SOFC’s is less restrictive than for PEMFC systems, but material costs are high. SOFC durability suffers with the cell temperature repeatedly heat cycled with start-up and shut down seqences. Aromatic-based membranes: An alternative to current perfluorosulphonic acid membranes are aromatic-based membranes like benzene, pyridine or indole. These membranes are more stable at higher temperatures, but still require hydration. They swell when they lose hydration, which reduces fuel cell efficiency.

System Technology Challenges

Cost and durability are the major challenges to widespread fuel cell commercialization. However, hurdles vary according to the application in which the technology is employed. Size, weight, and thermal and water management are barriers to the commercialization of fuel cell technology. In transportation applications, fuel cell technologies face more stringent cost and durability hurdles. In stationary power applications, where cogeneration of heat and power is desired, use of PEM fuel cells would benefit from raised operating temperatures to increase efficiency performance. The key challenges include:

• •

•

Cost: The fuel cell power systems is more expensive than conventional technologies. Durability and Reliability: The durability of fuel cell systems has not been established. For transportation applications, fuel cell power systems are required to achieve the same level of durability and reliability of current energy sources in terms of lifespan time, performance, and ambient operating temperature. System Size: The size and weight of fuel cell systems must be reduced to the levels of other technologies. This reduction applies to the fuel cell stack and the ancillary components and major subsystems (for example, fuel processor, compressor/expander, and sensors) making up the balance of power system.

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•

•

21.17

Improved Heat Recovery Systems: The low operating temperature of PEM fuel cells limits the amount and type of CHP applications. Technologies need to be developed that will allow higher operating temperatures and/or more effective heat recovery systems and improved system designs that will enable CHP efficiencies exceeding 80%. Infrastructure: unfamiliar technology to power industry, with no infrastructure in place.

Fuel cell summary Types of fuels

Fuel Cell types

hydrogen methanol liquid fuels

air

evaporation

SOFC

800°C

internal thermal reforming

natural gas sulphur removal

MCFC

xity ple om ure g c rat sin pe es em es roc g t l p ratin p tim ncy u ue g f ope rt - icie sin ng r sta eff rea asi rte ing inc ecre sho reas d c de

reforming

650°C

internal thermal reforming

to H2 and CO

PAFC shift reaction H2 and CO2

CO selective oxidation

CO 30 years

Polycrystalline

10% - 13%

> 25 years

Thin Film / Amorphous

5% - 7%

> 20 years

21.21

Comments

• Highest efficiency = least surface area. • Most expensive due to complicated manufacturing process. • Highest achieved efficiency is 23%. • They generate approximately 35 mA/cm2 at a voltage of 550 mV at full illumination. • Most commonly used type of cell as it offers good efficiency at reasonable cost. • Low efficiency hence requires large surface area. • Made from flexible material. • Works better in diffused light than mono and polycrystalline. • Current density of up to 15 mA/cm2, and the voltage of the cell open-circuit voltage of 0.8 V, is more that a crystalline cell. • Spectral response reaches maximum at the wavelengths of blue light therefore, ideal with fluorescent light sources.

PV Cell Structures

Most PV devices use a single junction to create an electric field. In a single-junction PV cell, only photons with energy equal to or greater than the band gap of the cell material can elevate an electron up into the conduction band. In other words, the photovoltaic response of single junction cells is limited to the portion of the sun's spectrum with energy is above the band gap of the absorbing material. Lowerenergy photons are not used. One way around this limitation is to use two or more different cells, with more than one band gap and more than one junction, to generate a cell voltage. These structures are referred to as multi-function cells. Multi-junction cells can achieve a higher total conversion efficiency because they can convert more of the energy spectrum of light to electricity. The actual structural design of a photovoltaic cell depends on the limitations of the material used in the PV cell. There are four basic device designs commonly used with the semiconducting materials discussed. • Homojunction • Heterojunction • p-i-n/n-i-p • Multi-junction 21.21.1 Homojunction Device A single semiconductor material, crystalline silicon, is altered so that one side is p-type, dominated by positive holes, and the other side is n-type, dominated by negative electrons. The p-n junction is located so that the maximum amount of light is absorbed near it. The free electrons and holes generated by the light in the silicon diffuse to the p-n junction, then separate to produce an external current. In the homojunction design, several cell aspects are varied to increase the conversion efficiency: • Depth of the p-n junction below the cell's surface • Amount and distribution of dopant atoms on either side of the p-n junction • Crystallinity and purity of the silicon Numerous homojunction Si cell examples have been presented in previous sections of this chapter. 21.21.2 Heterojunction Device An example of this type of device structure is a CIS cell, where the junction is formed by contacting two different semiconductors, CdS and CuInSe2. This structure is often used for thin-film cells, which absorb light much better than silicon. The top and bottom layers in a heterojunction device have different functions. The top layer, or ‘window’ layer, is a material with a high bandgap selected for its light transparency. The window allows almost all the incident light to reach the bottom layer, which is a material with a low bandgap that readily absorbs light. This light then generates free electrons and holes near the junction, which separates the electrons and holes before they can recombine.

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A high band-gap window layer reduces the cell's series resistance. The window material can be made highly conductive, and the thickness can be increased without reducing the transmittance of light. Therefore light-generated electrons can readily flow laterally in the window layer to the electrical contact. 21.21.3 p-i-n and n-i-p Devices Typically, amorphous silicon thin-film cells use a p-i-n structure, whereas CdTe cells use an n-i-p structure. A three-layer sandwich is created, with a middle intrinsic (i-type or undoped) layer between ntype and p-type layers. This geometry sets up an electric field between the p and n type regions that breaches the middle intrinsic resistive region. Light generates free electrons and holes in the intrinsic region, which are then separated by the electric field. In the p-i-n amorphous silicon cell, the top layer is p-type amorphous silicon, the middle layer is intrinsic silicon, and the bottom layer is n-type amorphous silicon. Amorphous silicon has many atomic-level electrical defects when it is highly conductive. So little current flows if the cell had to depend on diffusion. However, in a p-i-n cell, current flows because the free electrons and holes are generated within the influence of an electric field, rather than having to move toward the field. Carrier lifetimes are very long in the intrinsic layer. In a CdTe cell, the device structure is similar to the amorphous silicon i cell, except the order of layers is inverted. Specifically, in a typical CdTe cell, the top layer is p-type cadmium sulphide (CdS), the middle layer is intrinsic CdTe, and the bottom layer is n-type zinc telluride (ZnTe). 21.21.4 Multi-junction Devices A multi-junction structure can achieve a higher total conversion efficiency by capturing a larger portion of the solar spectrum. In the typical multijunction cell, individual cells with different bandgaps are stacked in desending bandgap order below one-another. The sunlight falls first on the material having the largest bandgap Eg1. Photons not absorbed in the first cell are transmitted to the second cell Eg2, which then absorbs the higher-energy portion of the remaining solar radiation while remaining transparent to the lower-energy photons. These selective absorption processes continue through to the final cell, which has the smallest bandgap Eg3.

Figure 21.19. A typical multi-junction PV cell showing three progressively decreasing band gap cells.

A multi-junction cell can be made in two different ways. • In the mechanical stack approach, two individual PV cells are made independently, one with a high bandgap and one with a lower bandgap. Then the two cells are mechanically stacked, the one with the highest bandgap on top of the other. • In the monolithic approach, one complete PV cell is made first, and then the layers for the second cell are grown or deposited directly on the first cell.

796


e

light G

-

EG=1.8eV

+ EG=1.43eV

+ Figure 21.20. A monolithic multi-junction PV cell based on GaAs and GaInP.

i. This multi-junction device has a top cell of gallium indium phosphide, then a tunnel junction to allow the flow of electrons between the cells through a thin insulating layer, and a bottom cell of gallium arsenide. ii. Another monolithic cell, a device that uses indium phosphide for the top cell and indium gallium arsenide for the bottom cell (InP/InGaAs), reaches 31.8% efficiency under 50 suns concentration. There are several aspects about this device. • Traditionally, for highest efficiency in a two-junction device, the top cell should have a high band gap of approximately 1.9 eV while the bottom cell should have a band gap of about 1.4 eV. For this device, the band gap of the top cell is 1.35 eV and that of the bottom cell is about 0.75 eV. • The cell is ideally suited for space applications because the resistance of indium phosphide to radiation is 50% better than that of silicon and 15% better than that of gallium arsenide, which are the two materials used for PV power in space. This means that arrays using InP/InGaAs cells are lighter, cheaper, more reliable, longer lifetime, and more powerful. • The band gap of indium gallium arsenide can be altered by varying the ratio of the constituent materials. This offers possibilities for spectrally tuning the cell. High efficiency multi-junction cells focus on gallium arsenide as one, or all, of the component cells which gives efficiencies of more than 35% under concentrated sunlight. Other multi-junction cells include the use of amorphous silicon and copper indium diselenide. i. Amorphous silicon multi-junctions Amorphous silicon cells, include silicon carbon alloyed p-i-n cells, n-i-p cells, and stacked cells. Multijunction devices not only achieve higher efficiencies than single-junction cells, but they also experience less light induced degradation. Because the intrinsic layers are so thin, the electric field sweeps charge carriers from these layers with minimal recombination. Multi-junction devices use two, and sometimes three, individual amorphous silicon cells stacked on top of each other. To capture a broader portion of the sun's spectrum, the cells are made of different materials with different band gaps. Amorphous silicon alloys with carbon, germanium, nitrogen, and tin have all been used to vary the band gap and material properties to improve multifunction devices.

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Power Electronics

+

metal grid

light e

light G

transparent conducting oxide amorphous Si:H

p p

amorphous SiGe:H p amorphous SiGe:H

+ i n

-

i n

+ -

i n

metal substrate

-

Figure 21.21. An amorphous silicon multi-junction p-i-n type PV cell.

Since the depositions needed to make thin-film multifunction devices do not use much energy, such devices are potentially inexpensive to fabricate. Making a multi-layered cell is similar to making one cell, just adding one thin-film after another. ii. Copper Indium Diselenide multi-junction Copper indium diselenide cells have a band gap of 1.0eV and are used as a single junction cell or with a higher band-gap material in a multifunction device. Amorphous silicon, with a band gap of about 1.7eV, on top of CIS is an example of a multi-junction cell. Copper indium diselenide is a versatile material is used as a bottom cell in conjunction with top cells of other materials, such as CdTe and GaAs, which have band gaps of approximately 1.43 or 1.44 eV. light G

-

e

?

+ + Figure 21.22. A CID multi-junction PV cell.

21.22

Equivalent circuit of a PV cell

To understand the electronic behaviour of a PV cell, it is useful to create a circuit model which is electrically equivalent, and is based on discrete electrical components whose behaviour is well known. An ideal PV cell may be modelled by a current source in parallel with a diode; in practice no PV cell is ideal, so shunt resistance and series resistance components are added to the model. 21.22.1 Ideal PV cell model During darkness the PV cell is not active and behaves as a diode, that is, a p-n junction diode, not producing current. The simplest PV cell model consists of diode and current source parallel connected as shown in figure 21.23a. The current source current Iph is directly proportional to the solar radiation G. The diode represents the pn junction of a PV cell. The equations of an ideal PV cell, which represents the ideal PV cell model, are: V qV     I D (V ) = I o e γ kT − 1 = I o e γ Vth − 1 (21.22)     I ph = ηg × G × Ac (21.23)

798


where G is the ambient irradiance, W/m2, ηg is the generation efficiency, and Ac is the cell effective or active area, m2. The net output current I is the difference between the photocurrent Iph and the normal diode current ID V   (21.24) I (V ) = I ph − I D = I ph − I o e γ Vth − 1   where V is the diode voltage (V) Iph is the photo-current from the current source (proportional to the intensity of the incident light), A Io is the diode dark saturation current or reverse saturation current, A (approximately 10-8/m2) k is Boltzman's constant, 1.38 x 10-23J/K q is the charge on an electron, 1.6 x 10-19 J/V, C or As and T is the working temperature of the cell in Kelvin, K.

Vth =

kT q

(21.25)

where Vth - thermal voltage, Vth = 25.7 mV at 25°C, γ - diode non-ideal factor = 1 to 2 (γ = 1 for ideal diode) Both Io and Iph are strongly dependant on temperature. −q E G   1 1 γk −   T T1 η T  e  I o (T ) = I SC (T 1 )    VOC ,T 1   T  1  e γ Vth ,T 1 − 1    I SC , nom ,T1  I SC ,T 2 − I SC ,T1  (T ) = G (T − T 1 )  1 + G nom  T 2 −T1 

3

I ph

(21.26)

(21.27)

Gnom = 1kW/m2 termed 1 sun, EG is the band gap voltage eV, VOC is the open circuit output voltage, which has a temperature coefficient of 2.3mV/°C for silicon, and ISC is the short circuit output current, the largest output current, when V = Iph = ID = 0 in equation (21.24). The cell open circuit voltage VOC (the cell voltage at night, G = 0) is when the output current is zero, I = 0, such that the model diode current Io equals to photo generated current Iph. That is, equating equation (21.24) to zero  V  I (V ) = I ph − I o e γ Vth − 1 = 0 (21.28)   gives I  Voc = γ Vth An  ph + 1  (21.29)  Io  heat

I

ID Iph

Vph

ID Iph

V

Ishunt Vph

Rs Rsh

I V

G (a)

(b)

Figure 21.23. PV cell electrical circuit model: (a) basic model and (b) model incorporating series and shunt resistances.

21.22.2 Practical PV cell model The equivalent circuit of a practical PV cell is a constant current source in parallel with an ideal diode and a shunt resistor Rsh, plus that all in series with a series resistor Rs.

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Power Electronics

The equations which describes the relationship between output current and output voltage characteristics, I-V, of the PV cell are V − IRs   V − IRs (21.30) I (V ) = I ph − I D − I shunt = I L − I o e γ Vth − 1 − Rsh   21.22.3 Maximum-power point A PV cell may operate over a wide range of output voltages V and currents I. The product of I and V is the power output of the cell P, and the solution of the equation that maximizes that product yields the voltage VMPP and current IMPP at the maximum power point Pm, as shown in equation (21.31). By increasing the resistive load on an irradiated cell continuously from zero (a short circuit) to a very high value (an open circuit) one can determine the maximum-power point, the point that maximizes V×I, that is, the load for which the cell can deliver maximum electrical power at that level of irradiation. The output power is zero in both the short circuit and open circuit extremes. Pm = V MPP × I MPP (21.31) A high quality, monocrystalline silicon PV cell, at 25°C cell temperature, may produce an open circuit output voltage of VOC = 0.60V. The cell temperature in full sunlight, even with 25°C air temperature, will probably be close to 45°C, reducing the open circuit voltage to 0.55 Volts per cell, as indicated in figure 21.24d. The voltage drops modestly, with this type of cell, until the short circuit current ISC is approached. Maximum power (with a 45°C cell temperature) is typically produced with 75% to 85% of the open circuit voltage (0.43V in this case) and 80% to 90% of the short circuit current. This output can be up to 70% of the VOC x ISC product. The power output of the cell is almost directly proportional to the intensity of the sunlight. For example, if the intensity of the sunlight is halved the power will also be halved, as shown in figure 21.24c. The short circuit current ISC from a cell is nearly proportional to the illumination, while the open circuit voltage VOC may drop only 10% with a 80% drop in illumination. Lower quality cells have a more rapid drop in voltage with increasing current and can produce only ½VOC at ½ISC. The usable power output could thus drop from 70% of the VOC x Isc product to 50% or even as little as 25%. [Typical temperature coefficients: VOC=-2 x10-3/°C, VMPP=-2.5 x10-3/°C, Isc=0.6 x10-3/°C, Isc=0.5 x10-3/°C]

3

1/R

1 Vmpp

0

0.1

0.2

0.3

0.4

VOC

4

(V)

3

(a)

Current VOC

0 0.3

PV cell voltage

0.4

PV cell voltage

0.5

0.6

(V)

4

2

¼ suns ¼ kW/m2

0.2

0.3

temperature

Pmax

½ suns ½ kW/m2

0.1

0.2

ISC

1 suns 1 kW/m

0

0.1

(b)

2

1

VOC

3

irradiance area

2

½

Vmpp

0

2 suns 2 kW/m2

ISC

1

0.6

0.4

0.5

0.6

1 VOC

0 0

0.1

(V)

0.2

0.3

PV cell voltage

(c)

1½ 1

power

0

(A)

PV cell voltage

0.5

Current

Current

Pmpp

2

0

(A)

2

Impp

3

2

Current

ISC

(W)

Impp

4

0.4

0.5

0.6

(V)

(d)

Figure 21.24. A typical PV cell characteristics: (a) voltage current I-V curve; (b) I-V and power characteristics; (c) effects of increased incident irradiance and cell area; and (d) effects of increased temperature on I-V characteristics.

power

1/Rmpp

ISC

(A)

(A)

maximum power point 4


21.23

800

Photovoltaic cell efficiency factors

Energy conversion efficiency PV cell energy conversion efficiency η, is the percentage of power converted (from absorbed light to electrical energy) and collected, when a PV cell is connected to an electrical circuit. This efficiency is calculated using the ratio of the maximum power point, Pm, divided by the input light irradiance (G, in W/m²) under standard test conditions and the surface area of the PV cell, Ac in m².

η=

Pm G × Ac

(21.32)

STC specifies a temperature of 25°C and an irradiance of 1000 W/m² with an air mass 1.5 (AM = 1/cosθ, where angle θ is relative to the zenith, the vertical,) spectrum. These correspond to the irradiance and spectrum of sunlight incident on a clear day upon a sun-facing 37° - tilted surface with the sun at an angle of 41.81° above the horizon. The losses of a PV cell are divided into: • reflectance losses, • thermodynamic efficiency, • recombination losses, and • resistive electrical loss. The overall efficiency is the product of each of these individual losses, but these losses are not directly measurable. Other measurable parameters are used instead to specify efficiency: • Thermodynamic Efficiency, • Quantum Efficiency, • Voc ratio, and • Fill Factor. Reflectance losses are a portion of the Quantum Efficiency. Recombination losses make up a portion of the Quantum Efficiency, Voc ratio, and Fill Factor. Resistive losses are predominantly categorized under Fill Factor, but also make up minor portions of the Quantum Efficiency and Voc ratio. Thermodynamic efficiency limit PV cell efficiency is limited because it operates as a quantum energy conversion device. Photons with an energy below the band gap of the absorber material can not generate a electron-hole pair, and as such the photon energy is not converted to a useful output. When a photon of greater energy than the band gap is absorbed, the excess energy above the band gap is converted heat as the excess kinetic energy is released as the electron slows to equilibrium velocity. This loss is termed the Thermodynamic Efficiency Limit. Quantum efficiency An elevated electron-hole pair may travel to the surface of the PV cell and contribute to the current produced by the cell; such a carrier is said to be collected. Alternatively, the electron may give up its energy and once again become bound to an atom within the PV cell without reaching the surface; this is called recombination, and carriers that recombine do not contribute to the production of electrical current. Quantum efficiency refers to the percentage of photons that are converted to electric current (that is, collected carriers) when the cell is operated under short circuit conditions. External quantum efficiency is the fraction of incident photons that are converted into electrical current, while internal quantum efficiency is the fraction of absorbed photons that are converted into electrical current. Mathematically, internal quantum efficiency is related to external quantum efficiency by the reflectance of the PV cell; given a perfect anti-reflection coating, they are the same. VOC ratio Due to electron recombination, the open circuit voltage Voc of the cell will be below the band gap voltage of the cell semiconductor. Since the energy of the photons must be at or above the band gap to generate a carrier pair, a cell voltage below the band gap voltage represents a loss. This loss is represented by

VOC ratio =

VOC EG

(21.33)

Fill factor Another term in the overall efficiency behaviour of a PV cell is the fill factor, FF. This is the ratio of the maximum power point divided by the open circuit voltage Voc and the short circuit current Isc:

FF =

η Ac G Pm I V = MPP MPP = VOC I SC VOC I SC VOC I SC

(21.34)

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Power Electronics

The cell fill-factor can be expressed as a function of the open circuit voltage by: V  VOC − An  OC + 0.72  V γVth γ  th  FF ≈ VOC +1

(21.35)

γVth

Concentrators A concentrator is a PV cell designed to operate under illumination greater than 1 sun. The incident sunlight is focused or guided by optical elements such that a high intensity light beam shines on a small PV cell. Concentrators have several potential advantages, including a higher efficiency potential than a one-sun PV cell and the possibility of lower cost. The short-circuit current from a PV cell depends linearly on light intensity, such that a device operating under 10 suns would have 10 times the shortcircuit current as the same device under one sun operation. However, this effect does not provide an efficiency increase, since the incident power also increases linearly with concentration. Instead, the efficiency benefits arise from the logarithmic dependence of the open-circuit voltage on short circuit. Therefore, under concentration, VOC increases logarithmically with light intensity, specifically:   I SC    X × I SC  VOCX = γVTH An  (21.36)  = γVTH  An   + AnX  = VOC + γVTH AnX  Io    Io   where X is the concentration of sunlight. From the equation (21.36), a doubling of the light intensity (X=2) causes an 18 mV rise in VOC. The cost of a concentrating PV system may be lower than a corresponding flat-plate PV system since only a small area of PV cells is needed. The efficiency benefits of concentration may be reduced by increased losses in series resistance as the short-circuit current increases and also by the increased temperature operation of the PV cell. As losses due to short-circuit current depend on the square of the current, power loss due to series resistance increases as the square of the concentration. Module (or array) series and parallel PV cell connection

(A)

(A)

21.24

8 6

IM,sc=k×ISC

6 two cells ISC

I

one cell

2

VM,OC = n×VOC

Vtotal

V1 0 0

0.2

0.4

0.6

PV cell voltage

0.8

1.0

1.2

two cells Itotal V

4

Current

4

Current

8

I1

one cell

2 VOC

0 0

0.2

(V)

0.4

0.6

PV cell voltage

(a)

0.8

1.0

1.2

(V)

(b)

Figure 21.25. I-V characteristics of identical PV cells connected in (a) series and (b) parallel.

Identical PV cells are series and parallel connection to form high-voltage, high-current, modules. For high current applications, modules are connected in parallel. For high voltage applications, modules are connected in series. If all the PV cells in a module have identical electrical characteristics, and all experience the same insolation and temperature, then all the cells will operate at the same current and voltage. In this case, the I-V curve of the PV module has the same shape as that of the individual cells, except that the voltage and current are increased. Series connection of n identical cells: • When series connected, voltage adds Vtotal = V1 + V2 + ... + Vn

802


• The current remains constant Itotal = I1 = I2 With a series connection of voltage sources, the voltage of each source adds incrementally. For n series connected PV cells, each with open circuit voltage VOC, the module open circuit voltage is VM ,OC = n ×VOC (21.37) Parallel connection of k identical cells: • When parallel connected, the currents add Itotal = I1 + I2 +..+ Ik • The voltage remains constant Vtotal = V1 = V2..... With the parallel connection of voltage sources, the currents add. The voltage corresponds to that of a single source. For k parallel connected PV cells, each with short circuit current ISC, the module short-circuit current is I M ,sc = k × I SC (21.38) If each cell has a series resistance Rs, the Thevenin equivalent resistance of the module is

RM , s =

n R k s

(21.39)

The same formula applies to the calculation of the equivalent module shunt resistance. The module maximum power PM deliverable to a resistive load is PM = n × k × Pm (21.40) The module terminal voltage VM and current IM characteristic equation can be expressed in terms of each cell or the characteristics of the module, namely VM −VM ,OC +RM ,s ×I M   n γVth   I M (VM ) = I M ,SC 1 − e (21.41)     or, in terms of the individual cell characteristics: n VM −n ×VOC + Rs ×I M   k   n γVth I M (VM ) = k × I SC  1 − e (21.42)      In terms of the simple model in figure 21.23a  nVγMV  I M (VM ) = k × I ph − k × I o  e th − 1  (21.43)     21.12 Typical and maximum module and cell conversion efficiencies at Standard Test Conditions. Typical module efficiency

Maximum recorded module efficiency

Maximum recorded laboratory efficiency

%

%

%

Single crystalline silicon

12-15

22.7

24.7

Multi-crystalline silicon

11-14

15.3

19.8

Amorphous silicon

5-7

-

12.7

Cadmium telluride

-

10.5

16.0

CIGS

-

12.1

18.2

Type

Example 21.4: PV cell and module characteristics A 100cm2 PV cell has I-V characteristics as shown in figure 21.23 parts a and b, at 25°C, achieved using a concentrator which gives 2kW/m2 on each cell. The PV cell is characterised by VOC = 0.625V VMPP = 0.50V IMPP = 3.5A ISC = 3.7A With diode properties γ = 1.5 and Vth = 25.7mV at 25C. Use this information (and figures 21.24 and 21.25, if necessary) to find i. The maximum cell power and optimal load resistance for delivering this power; ii The fill factor FF; iii The VOC efficiency ratio, if the band gap of the silicon cell is 1.11eV at 25°C; iv. The open-circuit voltage and short-circuit current values if a module uses 36 of such cells series connection, with three cells parallel connected at each voltage level; and

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v.

The module maximum power output and optimal load resistance for the given conditions.

Solution i.

The maximum cell power Pm is given by equation (21.31), that is Pm = VMPP × I MPP = 0.5V×3.5A = 1.75W

ii.

The efficiency fill factor FF is

FF =

Pm VOC I SC

1.75W = 75.7% 0.625V×3.7A Alternatively, using equation (21.35) V  VOC − An  OC + 0.72  γV  γVth  FF ≈ th VOC +1 =

γVth

=

iii.

16.21 − A n (16.21 + 0.72) 16.21 + 1

The VOC ratio is

VOC ratio = =

iv.

= 77%

VOC EG 0.625V = 56.3% 1.11eV

With 36 series connected cells the open circuit output voltage is VM ,OC = n ×VOC = 36 × 0.625V = 22.5V The short circuit output current for three parallel connected cells at each voltage level is I M ,sc = k × I SC = 3 × 3.7A = 11.1A

v.

The module maximum power PM is PM = n × k × Pm = 36 × 3 × 1.75W = 189W where the output voltage is 36×0.50V=18V and the output current is 3×3.5A=10.5A (18V×10.5A=189W) ♣

21.25

Battery storage

PV cells can only produce electricity during the day, and then only on clear days. To be independent of the grid energy storage is needed but batteries add cost and maintenance to the PV system. This problem is avoided with connection to the utility grid, buying power needed and selling when producing more than needed. This way, the utility acts as a practically infinite storage system. You will also need suitable inverter equipment to ensure that the power sold to the utility is synchronous with the grid, specifically the same sinusoidal waveform and frequency. The utility has to be assured that if there is a power outage, the PV system does not try to feed electricity into lines. This is called islanding. Batteries need regular maintenance, and replacement after a few years, although the PV modules last for 20 years or more. Batteries in PV systems can also be dangerous because of voltage level at which the energy is stored and the acidic electrolytes they contain, so the protective environment must be wellventilated and non-metallic. A lead-acid car type battery is a shallow-cycle battery and PV storage requires deep-cycle batteries which can discharge a significant amount of their stored energy while still maintaining long life. PV batteries generally have to discharge a small current for a long period (such as all night), while being


804

charged during the day. The most commonly used deep-cycle batteries is the nickel-cadmium battery which is more expensive than the lead-acid battery, but last longer and can be discharged more completely without harm. Lead-acid batteries cannot be deep-cycled or discharged 100 percent without seriously shortening battery life. Generally, if a PV systems uses lead-acid batteries, the system is designed to discharge the batteries by no more than 40 percent or 50 percent. For long battery life, a charge controller is needed to prevent overcharging and complete discharge. The other problem besides energy storage is that the electricity generated by PV modules, and extracted from the storage batteries if used, is in dc form while household appliances and the utility grid need ac voltage. Most distributed generation inverters automatically control the system. Some PV modules, called AC modules, have a built-in system inverter, eliminating the need for a large, central inverter, and simplifying wiring and safety issues. A PV system requires little maintenance (especially if no batteries are used), and can provide electricity cleanly and quietly for 20 years or more.

Figure 21.26. Schematic of a typical residential PV system with battery storage.

Weather and temperature Weather naturally affects the performance of PV modules but not as may be expected. The amount of sunlight is most important in determining the output a PV electric system will produce at a given location, but temperature is also important. PV modules actually generate more power at lower temperatures with other factors being equal. This is because PV cells generate electricity from light, not heat. Like most electronic devices, PV cells operate more efficiently at cooler temperatures. In temperate climates, PV panels will generate less energy in the winter than in the summer but this is due to the shorter days, lower sun angles and greater cloud cover, not the cooler temperatures. PV module output is proportional to the sun’s intensity, so cloud cover will reduce the system output. Typically, the output of any industrial PV module is reduced to 5% to 20% of its full sun output when operated under cloudy conditions. During a typical sunny day, a PV array one metre square exposed to the sun at noon will receive approximately 1kW of power. Multi-crystalline cells convert roughly 15% of this into electricity, hence 1m² of cells generates 150W in full sunshine. The warmer the cells becomes, the higher the losses. At 60 ºC the capacity decreases by about 18% to 123W, and at 70 ºC output drops by 24% to 114W. As shown in figure 21.24d, this reduced power output is because: • The voltage decreases, at an increasing rate, with increased temperature. • The current increases minimally with increasing temperature. This means that the maximum power output of a PV cell decreases with increased temperature especially under higher irradiation level. 21.26

The organic photovoltaic cell

Following absorption of photons by the polymer, bound electron-hole pairs (excitons) are generated, subsequently undergoing dissociation. Owing to inherent limitations in organic materials (exciton lifetime and low charge mobility), only a small fraction of photon-generated electron-hole pairs effectively contribute to the photocurrent. The organic cell facilitates volume distribution of the photogeneration sites, thereby enhancing exciton dissociation. This is achieved by increasing the junction surface area, with an interpenetrating network of the donor-acceptor type, effecting transport of holes to the indium-tin oxide anode, and of electrons to the aluminium metallic cathode. While quantum separation efficiency, for photo-induced charges in systems associating a semiconducting polymer, polythiophene, with a

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fullerene derivative, is thus close to unity, the objective is to restrict recombination and trapping processes, limiting charge transport and collection at the electrodes, to improve overall device efficiency, this currently still being low, less than 5%. The rise of the pathway is also dependent on the cell aging mechanisms and the thin-film technologies, to protect the device against atmospheric oxygen and water vapour ingress.

Figure 21.27. Organic PV cell.

Organic PV cells Operation of organic PV cells is mechanistically more complex. First, a molecule of an organic compound absorbs a photon and forms an excited state (exciton). Further, the exciton diffuses to a junction border between n- and p-types of semiconductor where it dissociates to form free charge carriers. Organic p- and n-transporters are also known as donors and acceptors correspondingly. If there is no junction border nearby, the exciton may recombine (decay) via photoluminescence, or thermally, back into the ground state of the molecule. This is the main reason, why mono- and bilayered (scheme above) organic PV cells were poorly performing devices until a new concept of bulk heterojunction has been introduced. Bulk heterojunction is a tight blend of a p-type conductor (donor), and n-type conductor (acceptor) in the photoactive layer of a device, where the concentration of each component often gradually increases when approaching to the corresponding electrode. This affords vast expansion of p-n-junction's total surface and strongly facilitates the exciton's dissociation. The implication of this concept in practice allowed increase of power conversion efficiencies of up to 5% for all-organic PV cells. In spite of the impressive results achieved with the realization of the bulk-heterojunction concept, the organic cells and materials still need to be strongly improved in order to find commercial application. Advantages of organic PV cells are: lightweight, environmentally friendly, no requirements for rare metals and minerals, no high temperatures and purity demand on the production stage, potentially inexpensive, virtually unlimited room for further material modification and improvement.

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21.27

Summary of PV cell technology

Table 21.13 Summary of PV cell technology Material

Thickness

Mono-crystalline Si

0.3 mm

Polycrystalline Si

0.3 mm

Polycrystalline transparent Si

0.3 mm

EFG

0.28 mm

Colour

Efficiency

Dark blue, black with AR coating, 15-18% grey without AR coating Blue with AR coating, 13-15% silver-grey without AR coating Blue with AR coating, 10% silver-grey without AR coating 14%

Blue, with AR coating, silver-grey without AR coating Blue, with AR coating, silver-grey without AR coating

Polycrystalline ribbon Si

0.3 mm

Apex (polycrystalline Si)

0.03 to 0.1 mm + ceramic substrate

9.5%

Monocrystalline dendritic web Si

0.13 mm incl contacts

13%

Blue, with AR coating

5-8%

Red-blue, Black

Amorphous silicon Cadmium Telluride (CdTe) Copper-Indium-Diselenide (CIS) Hybrid silicon (HIT)

Advantages

• • • • • • • • • • • • •

0.0001 mm + 1 to 3 mm substrate 0.008 mm + 3 mm glass substrate 0.003 mm + 3 mm glass substrate 0.02 mm

12%

Blue, with AR coating

6-9% (module)

8-10% (module)

18%

Features Lengthy production procedure - wafer sawing necessary. Highly researched PV cell material Highest power/area ratio. Wafer sawing necessary. Currently the most important production procedure. Lower efficiency than monocrystalline PV cells. Limited use of this production procedure Very fast crystal growth, no wafer sawing necessary Limited use of this production procedure, no wafer sawing necessary. Decrease in production costs expected. Single source wafer production procedure, no wafer sawing, production in form of band possible. Significant decrease in production costs. Limited use of this production procedure, no wafer sawing, production in form of band possible. Lower efficiency, shorter life span. No sawing necessary, production in the form of band.

Dark green, Black

Poisonous raw materials High production costs.

Black

Limited indium supply in nature. High production costs.

Dark blue, black

Limited use of this production procedure, higher efficiency, better temperature coefficient and lower thickness.

Infinite source of input energy. The 89 petawatts of sunlight reaching the earth's surface is plentiful - almost 6,000 times more - compared to the 15 terawatts of average power consumed by humans. The silicon cells manufactured from one ton of sand produce as much electricity as burning 500,000 tons of coal. Solar electric generation has the highest power density (global mean of 170 W/m²) among renewable energies. Low maintenance and long service lifetime, durable with minimal degradation over 10 years. No emissions of CO2, SO2, NO2, radiation Peak output matches daily peak demand Can be installed near point of energy need Grid-connected PV electricity can be used locally thus reducing transmission/ distribution losses or used decentralised Grid system integration possible, or independent of the grid thereby avoiding lack any of transmission and distribution infrastructure Quick installation Modular and expandable, for increased power Low operating costs, no fuel, transport and storage costs No moving parts to wear, operate silently with minimal system movement

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• • • • • •

Environmental benign, no waste, no noise, free energy, no fuel transport costs High public acceptance Excellent safety record, with no combustible fuels Suitable for harsh environments Can be portable Suitable for remote locations, including high-temperature, high-altitude environments, with improved performance, where hydrocarbon based systems are derated

Disadvantages • Sun light is a low intensity energy source, hence limited power density, 2-5 kW·h/m2 • Produces dc, which must be converted to ac with at least 4% losses • Hi tech skills to create the technology, but not necessary for installation, operation and maintenance • Some PV materials are toxic, for example the cadmium in cadmium telluride PV cells, therefore requiring careful end of life treatment. • Energy not available at night or during overcast weather • Expensive initial cell costs, plus expensive component replacement costs • High installation costs • Poor ancillary equipment reliability of grid tie inverters and storage methods, e.g., batteries, although PV are highly reliable if maintained (cleaned and protected) • Lack of commercial storage facilities • Accelerated sunlight ageing of associated synthetic materials • Local weather patterns and sun conditions directly affect the potential of photovoltaic systems. Some locations will not be able to use solar power. There are two disadvantages often used by environmentalist concerning high-tech PV: • Production Pollution:- Fossil fuels are extensively utilized to extract, produce and transport PV panels. These processes also entail corresponding sources of pollution. The life cycle analysis of a PV system is a net positive for the environment because it can offset fossil fuel energy production over its approximately 25-year lifetime. • High energy cost:- Require much energy to produce. The three types of photovoltaic (PV) materials, which make up the majority of the active PV market: single crystal, polycrystalline, and amorphous silicon PV cells pay for themselves in terms of energy in a few years (1-5 years). They thus generate enough energy over their lifetimes to reproduce themselves many times (6-31 reproductions) depending on what type of material, balance of system, and the geographic location of the system.

Reading list http://www.mpoweruk.com/ http://science.howstuffworks.com/solar-cell3.htm http://photovoltaics.sandia.gov/ http://americanhistory.si.edu/fuelcells/index.htm http://www1.eere.energy.gov http://www.fctec.com/fctec_basics.asp http://en.wikipedia.org/wiki/Solar_cell http://www.pvresources.com/en/technologies.php http://www.doitpoms.ac.uk/tlplib/index.php http://www.fuelcells.org/info/


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Problems 21.1 Consider the decomposition of H2O2 (hydrogen peroxide) at 298 K and 1 atm pressure according to: 2 H2O2(l) ↔ 2 H2O(l) + O2(g) Substance H2O2(l) H2O(l) O2(g)

∆Gfo kJ/mol -120.2 -237.0 -

∆Hfo kJ/mol -187.6 -285.8 -

So J/ K.mol 109.5 69.4 205

Find the a) standard enthalpy of reaction. b) standard entropy of reaction. [-196.4 kJ; 125 J/K] 21.2. For the reaction in the previous question, find the a) standard (Gibbs) free energy of reaction b) the value of the (thermodynamic) equilibrium constant at 298 K, 1 atm [ -233.6 kJ; 8.85 x 1040] 21.3 Carbon monoxide in the atmosphere slowly converts to carbon dioxide at normal atmospheric temperatures according to: CO(g) + ½ O2(g) ↔ CO2(g) The standard enthalpy of reaction is -284 kJ and the standard entropy of reaction is -87 J/K. Estimate the temperature at which the equilibrium begins to favour the decomposition of CO2. Assume that the enthalpy and the entropy of reaction are not affected by temperature. [3260 K or 3300K] 21.4. Indicate if TRUE or FALSE: The entropy of a gas increases with increasing temperature. The energy of a perfect crystal is zero at O K. Spontaneous processes always increase the entropy of the reacting system. All spontaneous processes release heat to the surroundings An endothermic reaction is more likely to be spontaneous at high temperatures than at low temperatures. The entropy of sugar decreases as it precipitates from an aqueous solution. [T F F F T T]

CHAPTER

22

Energy Sources and Storage: Secondary Sources

The progressive proliferation of embedded and distributed generation with renewable energy sources have spurred research into alternative energy sources and storage methods. This chapter is concerned with secondary energy sources, viz., so called super or double-layer capacitors and electro-chemical batteries. Their energy and power density capabilities (and those of primary electrical sources) have been put into context by considering conventional energy sources in Chapter 21.1, specifically the hydrocarbons and hydrogen gas. In electrical terms, primary and secondary energy sources are defined as follows. Primary source is not a reversible energy source. During energy discharge the original states are permanently changed as electrical energy is released until the original energy reactant sources, or any one of them, are depleted. A primary cell can be used only once. Secondary source is reversible and the original states can be reconstituted by the application of an electrical potential which injects energy into the source. A secondary cell can source and sink energy many times. 22.1

Batteries

A battery cell is an ‘electron pump’ that stores energy in chemical form in its active materials and can convert this to electrical energy on demand, typically by means of an electrochemical oxidationreduction reaction. Cells are classified as either primary cells or secondary cells, depending on whether or not the cell is rechargeable. Primary electrochemical cell: The electrochemical reaction is not reversible. During discharge, the chemical compounds are permanently changed and electrical energy is released until the original compounds, or any one of them, are depleted. A primary cell is assemble in the charged state, discharged during utilisation, used only once until discharged, then discarded, possibly involving recycling of components.

BWW

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Power Electronics

Secondary electrochemical cell: The electrochemical reaction is reversible and the original chemical compounds can be reconstituted by the application of an electrical potential between the electrodes injecting energy into the cell. The cell discharge and charge current directions are opposite. A secondary cell can be discharged and recharged many times. It is usually assembled in a discharged state and has to be charged before under-going discharged. Batteries come in a wide range of sizes and shapes, from wafer-thin to button-size devices to large industrial battery systems. All can be categorised as either primary storage and secondary storage batteries. Primary Batteries A primary battery is designed to be used until it is exhausted, then disposed of or recycled. These cells include carbon-zinc, alkaline, silver-oxide, zinc-air and lithium batteries. Although sometimes consisting of the same active materials as secondary types, they are constructed so that only one continuous or intermittent discharge can be obtained. Primary batteries have the following properties: • • • • •

Designed as a single use battery, discarded or recycled after depletion High impedance which translates to long-life energy storage and for low current loads Available in carbon-zinc, alkaline, silver oxide, zinc air and some lithium metal batteries (like lithium-thionyl-chloride). Lithium-thionyl-chloride batteries come in cylindrical form factors of AAA to D. Larger C and D size lithium-thionyl-chloride batteries are a chemical hazard and are restricted when transported by air Operating temperature range is typically - 40 ºC to + 85 ºC

Secondary Batteries Secondary batteries such as lead-acid, NiCd, NiMH, and lithium-ion (Li-ion), can be recharged, sometimes as often as 1,000 times, by the flow of direct current through them in a direction opposite to the current flow on discharge. By recharging after discharge, a higher state of oxidation is created at the positive electrode plate (cathode) and a lower state at the negative electrode plate (anode), returning the plates to approximately their original charged condition. Secondary batteries have the following properties: • Designed to be recharged • Can be recharged up to 1,000 times depending on the usage and battery type • Very deep discharges result in a shorter cycle life, whereas shorter discharges result in long cycle life for most secondary batteries • Charge time varies from one to twelve hours, depending upon battery condition, depth of discharge, and other factors • Include NiCd, lead-acid, NiMH, some lithium metal and Li-ion batteries • Lead-Acid and NiCd batteries are toxic and are subject to disposal regulations Some of the limitations suffered by secondary batteries are limited life, limited power capability, low energy-efficiency, and disposal concerns. The secondary cell is the subject of this section. The primary cell is not specifically considered further. 22.2

The secondary electro-chemical cell

Each electro-chemical energy cell consists of at least three, sometimes four, components • The cathode or positive electrode (the oxidising electrode) accepts electrons from the external circuit and is chemically reduced during the electrochemical (discharge) reaction. It is usually a metallic oxide or a sulphide. The cathodic process is the reduction of the oxide ion – anion - to leave the metal. (To gain or to accept electrons is termed reduction). The cathode is the half-cell with the highest electrode potential. • The anode or negative electrode (the reducing or fuel electrode) gives up electrons to the external circuit and is oxidised during the electrochemical (discharge) reaction. It is generally a metal or an alloy. The anodic process is the oxidation of the metal to form metal ions - cations. (To lose or to supply electrons is termed oxidation). The anode is the half-cell with the lowest (least positive) electrode potential.

Secondary Energy Sources

•

•

811

The electrolyte (the ionic conductor) provides the medium for transfer of charge in the form of ions inside the cell in either direction between the cathode and anode. The electrolyte is typically a solvent containing dissolved chemicals providing ionic conductivity. It should be a non-conductor of electrons to avoid self-discharge of the cell. The separator electrically isolates the positive and negative electrodes but allows ions to travel back and forth between the electrodes.

The operation of lead-acid and nickel-cadmium batteries are based on oxidation and reduction chemistry, called REDOX. The nickel-metal-hydride and lithium-ion batteries are not based on REDOX reactions, but rather involve an ion transfer mechanism called intercalation, which is the insertion and extraction of ions into and out of the crystalline lattice of an electrode, without chemically altering its crystal structure. 22.2.1 REDOX Galvanic Action Galvanic action is when chemical reactions produce electricity, while electrolysis is the reverse process where electricity is used to produce chemicals. Different metals have different affinities for electrons. When two dissimilar metals (or metal compounds) are put in contact or connected through a conducting medium there is a tendency for electrons to pass from the metal with the smaller affinity for electrons, which becomes positively charged, to the metal with the greater affinity which becomes negatively charged. A potential difference between the metals will therefore build up until it just balances the tendency of the electron transfer between the metals. At this point the ‘equilibrium potential’ is that which balances the difference between the propensity of the two metals to gain or lose electrons. A battery can be considered as an electron pump. The internal chemical reaction within the cell between the electrolyte and the negative metal electrode produces a build-up of free electrons, each with a negative charge, at the cell's negative terminal - the anode. The chemical reaction between the electrolyte and the positive electrode (the cathode) inside the cell produces an excess of positive ions (atoms that are missing electrons, thus with a net positive charge) at the cell cathode. The electrical (pump) pressure or potential difference between the positive and negative electrodes is called voltage or electromotive force, EMF. The Discharge Process When the cell is fully charged there is a surplus of electrons on the anode giving it a negative charge and an electron deficit on the cathode giving it a positive charge, resulting in a potential difference betwwen the cell electrodes. When the external electrical circuit is completed the surplus electrons flow in the external circuit from the negatively charged anode which loses its charge to the positively charged cathode which accepts it, neutralising its positive charge. This action reduces the potential difference across the cell to zero. The external circuit electron flow is balanced by the internal flow of positive ions in the electrolyte from the anode to the cathode. Since the electrons are negatively charged, the electrical current they conventionally represent flows in the opposite direction, from the cathode (positive terminal) to the anode (negative terminal). The Charging Process The charging process strips electrons from the cathode leaving it with a net positive charge and forces them onto the anode giving it a negative charge. The electrical energy pumped into the cell transforms the active chemicals back to their original state. Half-cell reaction Chemical reactions occur on both the anode electrode and the cathode electrode. Half cell reaction refers to the chemical processes occurring at each electrode (half-reactions), namely the negative anode and the positive cathode. The cell is modelled as two half-cells. Gibbs free energy equation (∆G = -nFEo, see Chapter 21.6.6) is used to calculate electrode potentials and characterise the chemical reactions within the cell. The cell voltage or EMF to force the external current from a cell is the difference in the standard electrode potentials of the two half-cell reactions under standard conditions. The actual voltage of a chemical cell is dependant on the temperature, pressure, and concentrations of the reactants and products. The Nernst equation can be used to calculate the EMF for non-standard conditions. The cell EMF decreases as the concentration of the active chemicals diminishes as they are consumed, until one of the reactants is exhausted. The half-cell zero reference potential is defined to be zero for the hydrogen electrode. All the equations are written as reductions. The two half-reaction potentials add to give the overall cell potential. The zinc-mercury half-cell reactions, during discharge, for example, are shown in Table 22.1.

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Table 22.1

Half-cell electro-chemical equations for the zinc-mercury cell Reaction (discharge)

Location

185A-hr/kg

Potential

Anode - oxidation

Negative terminal

Zn(s) + 2OH-(aq) → Zn(OH)2(s) + 2e-

E ½−cell = - 1.25V

Cathode - reduction

Positive terminal

HgO(s) +H2O + 2e- → Hg(s) + 2OH-(aq)

E ½+cell = 0.098V

Zn(s) + HgO(s) + H2O → Zn(OH)2(s) + Hg

o E cell = 1.35V

Net REDOX reaction

The cell potential under standard conditions (25°C, 1 mol, 1 Atmosphere) is o o o E cell = E ½+cell − E ½−cell = E cathode − E anode

(22.1)

The half-cell equations are reversed during cell charging, although the normal Zn-Hg cell is a primary cell, that is, not rechargeable. Table 22.2

Strengths of Oxidizing and Reducing Agents (25°C, 1mol, 1 atmosphere)

Anode Materials

Cathode Materials

(Negative Terminals)

(Positive Terminals)

BEST - Most Negative Standard Cathode (Reduction) Potential Half-cell Reaction E ½o (V)

BEST Most Positive

Li+(aq) + e− Æ Li(s) K+(aq)

−

+ e Æ K(s)

Ca2+(aq)

−

Cathode (Reduction) Half-cell Reaction

Standard Potential E ½o (V)

-3.045

F2(g) + 2e− Æ 2F−(aq)

+2.87

-2.925

MnO42−

+

−

+ 4H + 2e Æ MnO2(s) + 2H2O +

−

2+

+ 2e Æ Ca(s)

-2.766

Co3O4(s) + 8H + 2e Æ Co

Mg2+(aq) + 2e− Æ Mg(s)

-2.353

PbO2(s) + SO42−(aq) + 4H+(aq) + 2e− Æ PbSO4(s)+ 2H2O(l)

+1.685

-1.66

FeO42−

+1.56

Al3+(aq)

−

+ 3e Æ Al(s)

Zn2+(aq)

−

+ 2e Æ Zn(s)

Fe2+(aq) Ni2+(aq)

−

+ 2e Æ Fe(s) −

+ 2e Æ Ni(s)

Pb2+(aq) +

−

+ 2e Æ Pb(s) −

2H + 2e Æ H2(g) Cu2+(aq)

−

+ 2e Æ Cu(s)

Ag+(aq) + e− Æ Ag(s)

-0.763

+

−

+ 6H + 3e Æ +

Fe(OH)2+

−

MnO2 + 4H + 2e Æ Mn +

+ 4H2O

+2.257

2+

+ 2H2O

+ 2H2O

+2.11

+1.23

−

-0.440

O2(g) + 4H + 4e Æ 2H2O

+1.229

-0.250

+

+1.173

-0.126 0.00

−

Ag2O(s) + 2H + 2e Æ 2Ag(s) + H2O +

−

HgO(s) + 2H + 2e Æ Hg(l) + H2O +

−

+0.93

+

CuO(s) + 2H + e Æ Cu + H2O −

+0.62 −

+0.337

NiOOH + H2O + e Æ Ni(OH)2 + OH

+0.799

NiO2(s) + 2H2O + 2e− Æ Ni(OH)2(s) + 2OH−

+0.49 +0.49

Choice of Active Cell Chemicals The voltage and current generated by a galvanic cell is directly related to the types of chemical materials used for the electrodes and electrolyte. The propensity of an individual metal or metal compound to gain or lose electrons in relation to another material is known as its electrode potential. Thus the strengths of oxidizing and reducing agents are indicated by their standard electrode potentials. Compounds with a positive electrode potential are used for anodes and those with a negative electrode potential for cathodes. The larger the difference between the electrode potentials of the anode and cathode, the greater the EMF of the cell and the greater the amount of energy that can be produced by the cell. The Electrochemical Series is a table of metallic elements or ions arranged according to their electrode potentials, as shown in Table 22.2. The order shows the tendency of one metal to reduce the ions of any other metal below it in the series, at 25°C, standard pressure and 1mol of reactant. Table 22.2 shows some common chemicals used for battery electrodes arranged in order of their relative electrode potentials. Lithium has the most negative standard potential, -3.045V, indicating that it is the strongest reducing agent. The strongest practical oxidizing agent is fluorine with the largest positive standard electrode potential of +2.87V. Although halogen acids have high electrode potentials,

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they are usually too aggressive with the electrodes to be used in normal cells. Metals are commonly used in cells as anode materials, but the cathode is commonly an oxide. That is, in Table 22.2, metals appear in the left columns while oxides appear in the right columns. Gassing Cells using aqueous (containing water) electrolytes are limited in voltage to less than 2.4V because the oxygen and hydrogen in water dissociate producing H2 and O2 in the presence of voltages above this voltage. Lithium batteries use non-aqueous electrolytes hence do not have dissociation problems and are available in voltages between 2.7V and 3.7V. However, the use of non-aqueous electrolytes results in those cells having a relatively high internal impedance. 22.2.2 Intercalation Action From intercalation process studies, it is known that small ions (such as ions of lithium, sodium, and the other alkali metals) can fit in the interstitial spaces of a carbon graphite crystal. These metallic molecules force the graphitic planes apart to fit numerous layers of metallic molecules between the carbon sheets. This is an efficient way to store the metal-ion in a battery. The anode of a conventional alkali metal-ion cell is made from graphite (carbon), the cathode is a metal oxide, and the electrolyte is a metal salt in an organic solvent. Both the anode and cathode are materials into which metal-ions insert and extract, termed intercalation. The process of metal-ions moving into the anode or cathode is referred to as insertion, and the reverse process, in which metal-ions move out of the anode or cathode is referred to as extraction. Using lithium as an example, the underlying chemical reaction that allows Li-ion cells to provide electricity (equations to the right) are: anode C 6Li + xLi + + xe − R C 6Li 1+ x

LiCoO 2(s ) R Li 1− x CoO 2(s ) + xLi + + xe −

cathode

C 6LI + LiCoO 2 R Li 1− x CoO 2 + C 6Li 1+ x The lithium-ions are not oxidized; rather, they are transported to and from the cathode or anode, with the transition metal, cobalt, in LiCoO2 being oxidized from Co3+ to Co 4+ during charging, and reduced from Co 4+ to Co3+ during discharge. At no stage is any alkali lithium metal present or involved. The intercalation host electrodes have two key properties • Open crystal structures which allow the insertion and extraction of alkali metal-ions • The ability to simultaneously accept compensating electrons - conductive Lithium-ion secondary rechargeable battery Charge mechanism

discharge mechanism

Li

+

+

+

cathode

Li

+

Li

+

Li

polymer gel electrolyte

Li

+

-

separator

Li

+

LixC6

+

cathode

+

+

Li1-xCoO2 (a)

anode

+

Li

LixC6

electrons

electrons +

Li Li+

separator

conventional current

conventional current

-

anode

polymer gel electrolyte

(b)

Figure 22.1. Cells charge mechanism and discharge mechanism.

+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

Li1-xCoO2

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When discharging a cell, the metal-ions are extracted from the anode and inserted into the cathode, via the electrolyte. That is, alkali metal ions move through the electrolyte from the negative electrode to the positive electrode and attach to the carbon. The electrolyte is non-conducting to electrons. At the same time compensating electrons, which form the external circuit current, transfer from the positive to the negative electrodes, and are accepted by the internally arriving metal-ions, thereby balancing the equation. When charging the cell, the reverse process occurs: metal-ions are extracted from the cathode and inserted into the anode. The metal ions move back to the anode from the carbon cathode, while external current electrons flow from the negative to positive electrodes. The anode graphite is a twodimensional crystal structure, which under charging, is forced to laterally shift and simultaneously strain to 10% greater separation to accommodate the Li-ions. The lattice deformation is relieved when Li-ions are removed from the anode under cell discharge. 22.3

Characteristics of Secondary Batteries

A wide range of secondary batteries exist, each offering different attributes, limitations, properties, etc. The four secondary batteries to be considered are • Lead-acid • Nickel-cadmium • Nickel-metal-hydride • Lithium-ion Electrochemical lead-acid and nickel-cadmium battery technologies are mature. The lead-acid battery is economical for high power applications where weight is of little concern. It is an inexpensive, robust technology, found extensively in automotive applications and UPS equipment. The nickel-cadmium battery has a higher energy density than the lead acid battery, and offers longer lifetimes, higher discharge rates and a wider operating temperature range than the lead-acid battery. The nickelcadmium battery contains toxic metals, and is used in power tool applications. The nickel-metal-hydride battery trades a higher energy density than nickel-cadmium for reduced cycle life. Importantly it uses non-toxic metals, and is used in mobile phones and laptops. Lithium-ion, a newer, developing technology, offers higher again energy densities, but cell series connection poses sharing and balancing problems. Because of its high energy density properties, lithium-ion is increasingly being used in notebook computers, mobile phones, and power tools. Key battery technology properties and features are summarised in Table 22.3. Because of the energy density potential offered by lithium-ion technologies, three different cathode material types are presented. Two key performance aspects should be defined. Power density (specific power): Volumetric Power density is the ratio of the power available from a battery to its volume (W/litre). Specific power (or gravimetric power density) refers to the ratio of power to mass (W/kg). Comparison of power to cell mass is more common. Power Density (W/kg) indicates how much power a battery can deliver on demand. Manganese and phosphate-based lithium-ion, as well as nickel-based chemistries, give the best performance. High power density cell uses are power tools, medical devices and transportation systems. The focus is on power bursts, such as drilling through heavy steel, rather than runtime. Energy density (specific energy): Volumetric Energy density refers to the ratio of a battery's available energy to its volume (Wh/litre). Specific energy (or gravimetric energy density) refers to the ratio of energy to mass (Wh/kg). The energy W is determined by the charge q that can be stored and the cell voltage E, that is, W = q×E. Energy Density (Wh/kg) is a measure of how much energy a battery can retain or store. The higher the energy density, the longer the possible runtime. Lithium-ion cells with cobalt cathodes offers the highest energy densities. Typical applications are cell phones, laptops and digital cameras. An Ah/kg rating can be determined from the cell standard voltage, E and energy density rating Wh/kg, while power and energy densities are related by time, W = P×t, as shown in figure 22.2. An analogy between energy and power densities can be made with a water bottle. The size of the bottle is the energy density, while the opening area denotes the power density. A large volume bottle can carry a lot of water (energy), while a large opening can pour it quickly (power). A large container (energy) with a wide area mouth (power) is the best combination.

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Table 22.3 shows some typical relative energy and power per unit weight examples of some common secondary cell chemistries. In general, higher energy densities are obtained by using more reactive chemicals. But reactive chemicals tend to be unstable and require safety precautions. The energy density is also dependent on the quality of the active materials used in the cell construction, with impurities limiting the cell capacities.

Table 22.3

Basic comparison of different batteries

gravimetric energy density volumetric energy density power density cell voltage internal resistance

Nickelcadmium

sealed

sealed

Wh/kg

30-50

45-80

Wh/L

60-70

50-150

W/kg

180

150

250-1000

1800

V

2

1.25

1.25

mΩ/cell

20

30

5 0.2 80%

load current

Peak, C Optimum Depth of discharge

operating temperature range

°C

cycle lifetime fast charge Charge V limit overcharge tolerance self-discharge maintenance cool storage

80% capacity hr V

%/month @ 20°C months % charge top-up yr

toxicity cost commercialisation other features

liquid

Lithium-ion cobalt

manganese

phosphate

150-190

100-135

90-120

3.6

3.7

3.3

40

100

50

35

20 1 100%

5 0.5 80%

35 1000

8

1

3

2

>1

>1

2.4

constant I

constant I

4.2

4.2

3.7

high

moderate

low

Low – no trickle charge tolerated

5

20

30

< 10

6 100 ½

1V/cell 2 40 ½

1V/cell 3 40 ½

Thermally stable

Fuse Thermally stable

Fuse Thermally stable

H2SO4 4M

KOH 7M

Toxic lead and acid

Highly toxic

low

low

KOH 6M Low toxicity, recyclable medium

1970

1950

1990

Heavy Inexpensive Rugged

Long-life Durable

Bulky High pressure

discharge to

safety electrolyte

Nickelmetalhydride

Lead-acid

60-120 250kJ/kg

140-300 360MJ/m

3

270

-20 to 60

Not required 40 Not required Mandatory Protection protection needed needed protection Stable to Stable to Stable to 150°C 150°C 150°C LiPF6 + solvent Low toxicity high 1991

1996 2006 Low weight Low maintenance Needs temperature monitoring Needs over/under V and I protection

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Wh/kg

103 Fuel cell

10h

1h

C/10

102

0.1h

1C

10C

lithium

36s

NiMH

NiCd

101 energy density

100C

lead-acid

supercapacitors

100

10-1

10-2

3.6s

double layer capacitors

0.36s

time istic r e t rac cha

rms othe s i t stan con

101

102

aluminium electrolytics

36ms

103

Power density

104

Wh/kg

Figure 22.2. Gravimetric energy and power densities of different cells.

22.4

The lead-acid battery

Anode: Cathode: Electrolyte: Applications:

Sponge metallic lead + Antimony, tin or calcium Lead dioxide, PbO2 Dilute aqueous sulphuric acid, H2SO4 (4.5 Mole) Motive power in cars, trucks, forklifts, construction equipment, recreational water craft, standby/backup systems Typical ratings: Specific energy density: 35 to 50 Wh/kg Volumetric energy density: 60 to 70 Wh/l positive plate pack grid plate

electrolyte tight sealing ring positive terminal

negative terminal

positive plate negative plate

positive cell connection

negative cell connection

valve adapter and valve

negative plate packing

microporous separators

Figure 22.3. Cells used in the Lead Acid Battery. [Source Eurobat]

The lead-acid battery is made up of flat plates, a lead anode, and a lead oxide cathode (various other elements are used to change density, hardness, porosity, etc.) suspended in a 35% sulphuric acid and 65% water solution. This solution is called electrolyte and causes a chemical reaction that produce electrons. A fibre-glass separator between the plates prevents them from touching each other and short-circuiting.

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When testing a battery with a hydrometer, it is the amount of sulphuric acid in the electrolyte that is being measured. A low reading means that the chemistry that makes electrons is lacking. A sulphate is deposited on the battery plates when discharging but recharging the battery returns the sulphate to the electrolyte. The lead-acid battery discharge half-cell chemistry reactions shown in Table 22.4 (the reactions are reversed during charging). Table 22.4

Half-cell electro-chemical equations for the lead-acid cell Reaction

Location

(discharge)

55A-hr/kg

Potential

Anode

Negative terminal

Pb(s) + HSO4-(aq) → PbSO4(s) + H+(aq) + 2e-

E ½−cell = - 0.356V

Cathode

Positive terminal

PbO2(s) + HSO4-(aq) + 3H+ + 2e- →PbSO4(s) + 2H2O

E ½+cell = 1.685V

PbO2(s) + Pb(s) +2H2SO4 (aq) → 2PbSO4(s) + 2H2O

o E cell = 2.04 V

Net REDOX reaction

21.4.1 The Flooded lead acid cell Gassing: Traditionally there are a few problems with the basic flooded-cell lead-acid battery design. If the cell voltages exceed 2.39V, the water breaks down to hydrogen (at the anode) and oxygen (at the cathode). The chemical reactions are shown in Table 22.5. This 2.39V voltage is called the gassing voltage and is temperature and pressure dependent. This requires replacement of the cell's water. Also, as the hydrogen and oxygen vent from the cell, too high a mixture concentration could cause an explosion. Another problem arising from this open system is that fumes from the acid or hydroxide solution can have a corrosive effect on the surrounding area. These problems are mostly solved with sealed cells. In the case of lead-acid cells, the term ‘valveregulated cells’ is more accurate, because no rechargeable cell can be completely sealed. If sealed, the hydrogen gas pressure would build-up. Catalytic gas recombiners alleviate this problem by converting the hydrogen and oxygen back into water, with better than 85% efficiency. Although this does not entirely eliminate the hydrogen and oxygen gas, the water lost becomes so insignificant that no refill is needed for the life of the battery. For this reason, these cells are often referred to as maintenance-free batteries. Also, this cell design prevents corrosive electrolyte fumes from escaping. Table 22.5

Lead-acid cell gassing and corrosion equations

undesirable plate chemical reactions

reaction

positive electrode cathode

oxygen evolution

2H 2O → O 2 + 4H + + 4e −

grid corrosion

Pb + 2H 2O → PbO 2 + 4H + + 4e −

negative electrode anode

oxygen reduction

O 2 + 4H + + 4e − → 2H 2O

hydrogen evolution

2H + + 2e − → H 2

Charging: Lead-acid does not lend itself to fast charging, with a typical charge time of over 8 hours. A periodic fully saturated charge is essential to prevent sulphation and the battery must always be stored in a charged state. Leaving the battery in a discharged condition causes sulphation and a recharge may not be possible. Finding the ideal charge voltage limit is critical. A voltage above 2.40V/cell produces good battery performance but shortens the service life due to grid corrosion of the positive lead plate, as shown by the cathode chemical equation in Table 22.5. A low voltage limit is subject to sulphation on the negative plate. Leaving the battery on float charge for a prolonged time does not cause damage. Discharge: The lead-acid battery performs best at a slow 24-hour discharge. Pulsed discharge is also effective because of the non-discharge periods between the pulses that allow dispersion of the depleted acid back into the electrode plate. A discharge at 1C of the rated capacity (Ah for 1 hour) yields the poorest efficiency. The lower level of conversion, or increased polarization, manifests itself in a momentary higher internal resistance due to the depletion of active material in the reaction. The lead-acid battery has a relative low energy density, making it unsuitable for portable devices. In addition, the performance at low temperatures is marginal.

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Cycling: Lead-acid does not like deep cycling. A full discharge decreases battery service life. This deterioration characteristic also applies to other battery chemistries in varying degrees. To prevent the battery from being stressed through repetitive deep discharge, a heavier battery should be used. Leadacid is inexpensive but the operational costs can be higher than a nickel-based system if repetitive full cycles are required. Depending on the depth of discharge and operating temperature, the sealed lead-acid cell provides 200 to 300 discharge/charge cycles. The primary reasons for this relatively short cycle life are: • positive electrode grid corrosion; • active material depletion; and • positive plate expansion. These deteriorating changes are more prevalent at higher operating temperatures. The optimum operating temperature for a lead-acid battery is 25°C with higher temperatures reducing longevity. As a guideline, every 8°C temperature rise halves remaining battery life. Cycling does not prevent or reverse the trend. Self-discharge: The self-discharge is about 40% per year, which is low for rechargeable batteries. In comparison, nickel-cadmium self-discharges the same amount in three months. Plates: Lead-calcium (0.1% Ca plus 1% Sn) is a common anode material, but a lower cost alternative, lead-antimony (4-6% Sb), offers: • lower internal heat and water losses, • better mechanical strength, • longer service life, • easier to charge, • lower cost, • higher maintenance, • higher discharge depths, but • a high self-discharge rate of up to 5% per week. Lead acid batteries with electrodes modified by the addition of calcium providing the following advantages: • More resistant to corrosion, overcharging, gassing, water usage, and self-discharge, all of which shorten battery life, • Larger electrolyte reserve area above the plates, • Higher Cold Cranking Amp ratings, and • Little or No maintenance. Sulphation occurs on the negative anode lead plate if the battery is left in a partially or fully discharged state. Due to self-discharge, large, non-conducting sulphate crystals with a low surface area, build-up and block effective recharging conduction paths. With a density of 6.287gm/cc, the sulphate occupies a larger volume than the original paste, hence the plates deform under the stress associated with the increased volume. The cathode is lead oxidised to 80% lead oxide, with red lead, Pb3O4, for better conductivity. The oxide is mixed H2SO4, grid pressed, and cured to form a cohesive porous solid. The service life of a lead-acid battery can generally be measured by the thickness of the positive cathode lead plates. The thicker the plates, the longer the remaining life. During charging and discharging, the lead on the plates gets gradually eaten away and the sediment falls to the bottom. The weight of a battery is a good indication of the lead content and the life expectancy. Higher temperature, typically over 70°C and/or an uncharged state, accelerate corrosion of the lead oxide positive plate. The plates of automotive starter batteries are about 1mm thick, while the typical golf cart battery will have plates 1.8 to 2.8mm thick. Forklift and traction batteries have plates that exceed 6mm. Most industrial flooded deep-cycle batteries use lead-antimony plates, which improves plate life but increases gassing and water loss. Disposal: The high lead content makes the lead-acid battery environmentally unfriendly, although the materials are recyclable by furnace heat treatment, which recovers the metals. 22.4.2 Different lead-acid cell and battery arrangements The ‘sealed’ lead-acid battery is a maintenance-free battery that operates in any position. The liquid electrolyte is gelled into moistened separators and the enclosure is sealed. Safety valves allow venting during charge, discharge and atmospheric pressure changes. Two lead-acid systems have emerged: • the smaller Sealed Lead-Acid (SLA) cell, and • the larger Valve-Regulated-Lead-Acid (VRLA) cell.

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Both batteries are similar. Both are designed with a low over-voltage potential to prevent the battery from reaching its gas-generating potential during charge since excess charging would cause gassing and water depletion. Consequently, these batteries can never be charged to their full potential. To reduce dry-out, sealed lead-acid batteries use lead-calcium instead of the lead-antimony anode plates. The sealed lead-acid battery is typically rated at a 5-hour @ 0.2C and 20-hour @ 0.05C discharge. Longer discharge times produce higher capacity readings because of lower losses. The lead-acid cell performs well on high load currents. The Absorbed Glass Mat Battery (AGM) is a newer type of sealed lead-acid battery that uses absorbed glass mats between the plates. It is sealed, durable, maintenance-free and the plates are rigidly mounted to withstand extensive shock and vibration. AGM batteries recombine 99% of the oxygen and hydrogen, so there is almost no water is loss. The charging voltages are the same as for other lead-acid batteries. Even under severe overcharge conditions, hydrogen emission is below 4%. The low self-discharge of 1 to 3% per month allows long storage before recharging. The AGM costs twice that of the flooded version of the same capacity. In the composite carbon-graphite foam grid battery the lead metal negative grids found in the conventional lead acid battery are substituted with lightweight carbon-graphite foam, which offers a higher energy density. The high chemistry interface surface area of the carbon-graphite foam allows for greater electron flow from the battery’s chemistry, and is highly resistant to sulphation, which is a common lead-acid battery failure mode. The foam is not reactive in the lead-acid environment, so does not corrode and the graphite offers better thermal conduction properties than lead. The main restraint to lead-acid battery chemistry is the lack of reactive interface area between the active chemistry and the electrodes. The replacement of both the negative and positive plates within a battery with the stable carbon-graphite foam grid material attempts to redress this active area constraint. The bipolar lead-acid battery Virtually all lead-acid batteries are monopolar where a large number of plates are stacked in each cell, increasing the capacity of the battery, and cells are serially coupled to increase voltage. Since the current in a monopolar battery flows from one end of the battery to other, high currents will be unevenly distributed over the electrodes with maximum current flowing close to the posts, as shown in figure 22.4a. eecathode

+

Cathode active paste

anode

-

Anode active paste

+

-

cathode

anode

e-

epartition wall separator

+

- + - + - + Two mono cells (a)

+ -

+

-

Two bipolar (b)

Figure 22.4. Construction lead-acid batteries: (a) conventional cells and (b) bipolar cells.

A bipolar lead-acid battery is made up of a stack of serially coupled bipolar electrodes. Each bipolar electrode, except the ones at the ends, has one side of a conducting partitioning wall covered with porous lead, which is the negative side of the bipolar electrode, and the other side - the positive, covered with porous lead dioxide. Since current can pass only through the end electrodes, it will flow perpendicular to all electrode surfaces, also at high currents, and the active materials are efficiently utilized with minimal internal resistance. Lead-infused ceramic plates are coated with a positive paste on one side and a negative paste on the other. The plates are then stacked on top of each other with a separator between them, thus forming a battery in a bipolar design, as shown in figure 22.4b. The partitioning walls are made from porous, leadinfiltrated ceramic plates. The bipolar plates have high corrosion resistance, and the lead surface on the

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bipolar plate enables good contact to the active material in the same way as common lead acid technology. The battery contains only half the amount of lead per unit of output and offers 800W/kg discharge and 400W/kg recharge. anode paste ceramic bipolar wall separator cathode paste thermoplastic CTPE polypropylene

thermal seal pressure valve

Figure 22.5. Construction of the bipolar lead-acid battery.

22.4.3 Lead-acid battery properties General lead-acid battery properties are summarised in Table 22.2 and in the points that follow. Used mainly for engine batteries, these cells represent over half of all battery sales. Some advantages are low cost, long life cycle, and the ability to withstand electrical mistreatment. They also perform well in high and low temperatures and in high-drain applications. Lead-acid cells have a low cycle life, a quick self-discharge, and low energy densities, normally between 30 and 40Whr/kg. However, with a nominal voltage of 2V and power densities of up to 600W/kg, the lead-acid cell is adequate for automotive batteries. The lead acid chemistry of a typical lead acid battery predicts a battery theoretically capable of delivering approximately 170Whr/kg, but even the most efficient lead-acid battery version produce energy densities, on average, of no more than 30-50Whr/kg. Advantages • Inexpensive and simple to manufacture. • Mature, reliable and well-understood technology which is durable and dependable. • Self-discharge is among the lowest of rechargeable battery systems. • Capable of high discharge rates, due to low internal impedance. Limitations • Low energy density limits use to stationary and wheeled applications. • Cannot be stored in a discharged condition - the cell voltage should never fall below 2.10V. • A limited number of full discharge cycles, but is suited for standby applications. • Lead content and electrolyte make the battery environmentally unfriendly, but recyclable. • Transportation restrictions on flooded lead-acid cell due to environmental spillage concerns. • Thermal runaway can occur if improperly charged. • Heavy. 22.5

The nickel-cadmium battery

Anode: Cathode: Electrolyte: Applications:

Cadmium Nickel oxyhydroxide Ni(OH)2 Aqueous potassium hydroxide KOH 7M Calculators, digital cameras, pagers, laptops, tape recorders, flashlights, medical devices (e.g., defibrillators), electric vehicles, space applications Typical ratings: Specific energy density: 45 to 80 Wh/kg Volumetric energy density: 50 to 150 Wh/l

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The cathode is nickel-plated, woven mesh, and the anode is a cadmium-plated net. Since the cadmium is just a coating, this cell's negative environmental impact is often overstated. Rather than venting, units are sealed with the internal gases generated during charge, recombined. The half-cell chemistry reactions are shown in Table 22.6. Table 22.6

Half-cell electro-chemical equations for the nickel-cadmium cell Half-Reaction (discharge)

Location

165A-hr/kg

Potential

Anode

Negative terminal

Cd(s) + 2OH-(aq) —> Cd(OH)2(s) + 2e-

E ½−cell = - 0.76V

Cathode

Positive terminal

NiO2(s) + 2H2O + 2e- —> Ni(OH)2(s) + 2OH-

E ½+cell = 0.49V

Cd(s) +NiO2(s) + 2H2O —> Cd(OH)2(s) + Ni(OH)2(s)

o E cell = 1.25V

Net REDOX reaction

Gassing: Sealed nickel-cadmium cell technology has been developed to optimize the efficiency of the oxygen-recombination process. The chemistry is such that the cells can be operated in a starved condition (relative to valve regulated lead-acid, VRLA, systems) and under normal operating conditions, there is no venting of gases because the cells have a thin, oxygen-permeable separator with a high void volume and an overbuilt active spongy cadmium-negative electrode with a thin electrolyte film. Unlike the lead-acid system, the primary function of the electrolyte is to provide good conductivity within the cell and only water is involved in the overall cell reaction, leaving the KOH electrolyte relatively unchanged during charge/discharge cycling. Table 22.7 compares the chemistries, and Table 22.8 compares some of the critical typical cell design characteristics of lead-acid and nickel-cadmium cells. Sealed nickelcadmium cells do have self-resealing safety vents which release gas due to any pressure build-up, but they are normally intended to operate at high internal pressures with minimal gassing. The positive plate is designed to enter overcharge first, thus generating oxygen, and transport to, and recombination at the negative plate, is promoted. Because it is overbuilt, relative to the positive electrode and constantly being oxidized by oxygen, the cadmium anode electrode does not normally reach a potential where hydrogen is generated. This is also facilitated by a carefully controlled, narrow fill-weight range that is great enough to provide good conductivity and small enough so the separator and plate pores are not flooded, which would lead to a pressure build-up. Because no gases are usually given off, all of the overcharge current goes into heat generation. Therefore, charging and thermal management are critical NiCd issues; only constant-current charging is recommended for nickel-cadmium cells and only at moderate and low continuous levels, less than ⅓C (a current of one third the Ah rating for three hours). Table 22.7 Chemistry

Comparison of Nickel-Cadmium and Lead-Acid Chemistries Nickel-Cadmium

Lead-Acid PbSO4(s) + 2e- + H+ → Pb(s) + HSO4

2H2O + 2e- → H2 + 2OH-

2H+ + 2e- → H2

Ni(OH)2(s) + OH- → NiOOH(s) + e-

PbSO4(s) + 2H2O → PbO2(s) + 3H+ + HSO4- + 2e-

Overcharge

4OH- → 2H2O + O2 + 4e-

2H2O → O2 + 4H+ + 4e-

Overall Cell Process

Cd(s) + 2NiOOH(s) + 2H2O → Cd(OH)2(s) + 2Ni(OH)2(s)

Pb(s) + PbO2(s) + 2H2SO4 → 2PbSO4(s) + 2H2O

2Cd(s) + O2 + 2H2O → 2Cd(OH)2(s)

2Pb(s) + O2 + 2H2SO4 → 2PbSO4(s) + 2H2O

Overcharge Positive

Recombination Reaction

-

-

Cd(OH)2(s) + 2e → Cd(s) + 2OH

Negative

-

Memory: Possibly the most well-known NiCd limitation is the memory effect, where the cell retains the characteristics of the previous cycle. This term refers to a temporary loss of cell capacity, which occurs when recharged without being fully discharged. This can cause cadmium hydroxide crystals to passivate the anode electrode, or the battery to wear out. In the former case, a few cycles of discharging and charging the cell will correct the problem, but may shorten the lifetime. Deep discharge is not a discharge to zero volts, but to about 1V per cell. Nickel-cadmium does not like to be used in a standby mode.

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Table 22.8

Comparison of Nickel-Cadmium (Ni-Cd) and Lead-Acid constructions.

Parameter/Cell Dimension Separator Thickness

mm

Separator Material

Sealed Ni-Cd

Sealed Lead-Acid

30,000 hrs ave 105 - 106

>105 cycles

1500 to 104 hrs

150 to 1500 cycles

Weight

kg

1-2g

1 g - 10 kg

20 g to > 5 kg

1 g to > 10 kg

Gravimetric Power Density

kW/kg

10 to 100

0.25 to 10,000

0.001 to 0.1

0.005 to 0.4

Gravimetric Energy Density

Wh/kg

1 to 5

0.01 to 0.05

300 to 3000

8 to 600

Volumetric Energy Density

Wh/L

0.05-10 Wh/L

Pulse Load Pollution

A

50-250 Wh/L 2

< 100

< 1000

< 150 mA / cm

≈ 1 ) materials are not considered. Two basic types of soft magnetic materials are common, depending on the application requirements. These materials are: • •

Ferromagnetic materials based on iron and nickel, which are for lower frequencies, < 2kHz, while Ferrimagnetic materials (a subgroup of ferromagnetic materials), which are based on ceramic oxides of metals (ferrites), are applicable to frequencies from a few kilohertz to well over 80 MHz.

24.2.1 Ferromagnetic materials 24.2.1i - Steel Cold-rolled grain-oriented steel is a 3-4 per cent silicon iron, cold reduced to develop a high degree of grain orientation, which gives • increased flux for a given magnetising force and • decreased size for a given rating, hence reduced weight. Normally cores are produced in a number of material lamination thicknesses • 0.3 mm for frequencies up to 200 Hz • 0.1 mm for frequencies between 200 Hz to 2 kHz and • 0.05 mm for higher frequencies and pulse applications. Steel laminations for low frequency applications are available in different shapes. E and I laminations or strip C cores or toroids are extensively used for mains transformers and ac line inductors. Nonorientated silicon steels are extensively used for machine laminations. 24.2.1ii - Iron powders Two general forms of iron powder cores are employed • •

Cores are made by highly compacting insulated high quality spongy iron powder. High resistivity is required to reduce eddy current losses, so the iron powder is subjected to an acid treatment to produce an insulating oxide layer on the surface of each individual particle. This fine carbonyl iron is mixed with a bonding material and highly compressed. The bonding material used limits the maximum core temperature. Minute gaps appear between the particles, severely reducing the permeability. It is difficult to saturate such materials.

24.2.1iii - Alloy powders These cores are made by highly compacting insulated alloy powder. The alloy is usually 50-75 per cent nickel, the remainder being iron with a small percentage of copper and molybdenum. The higher the iron percentage, the higher the saturation flux density and the higher the core losses. Powder iron and alloy cores are available in toroidal or ring shapes, cylindrical and hollow cylindrical cores, as well as cup cores, bobbins, pot cores, and beads. 24.2.1iv - Nanocrystalline Nanocrystalline soft magnetic alloys are brittle, thin ribbon, 18µm, materials based on iron Fe, silicon Si and boron B with small additions of niobium Nb and copper Cu. They are produced via a rapid solidification technique, being initially in a precursor amorphous (non-crystalline) state and then crystallized into a precise mix of amorphous and nanocrystalline phases when subsequently heat annealed at around 500 to 600°C. An amorphous magnetic metal has high permeability due to no crystalline magnetic anisotropy. However when applying heat treatment on a typical amorphous metal at temperatures higher than its crystalline temperature, magnetic properties deteriorate for a rapid crystal growth of grains up to 1um. But if the recrystalline grains are restricted to the nano-order, about 10 nm in size, the soft magnetic crystal grains have good magnetic properties. Thus the suppressed grain growth recrystalization during annealing due to the enriching Nb and Cu gives the material it's unique magnetic properties. This extremely finegrained microstructure with grain sizes of 10 nanometres is termed nanocrystalline. Nanocrystalline alloys combine low magnetic anisotropy and low magnetostriction, both prerequisites for high magnetic permeability, with high magnetic flux density Bs and good thermal stability. Due to the exchange coupling of randomly oriented grains of Fe, the magnetocrystalline anisotropy averages out to

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zero. Magnetostriction can also be cancelled by a combination of positive values for the crystalline phase and negative values for the remaining amorphous phase, resulting in zero magnetostriction. Figure 24.2a shows permeability and saturation magnetic flux densities of representative nanocrystalline soft magnetic materials. Since the compositions of nonmagnetic elements can be reduced in the alloy design, higher saturation magnetic flux density can be obtained in the nanocrystalline soft magnetic materials compared to the existing bulk soft magnetic and amorphous materials. 24.2.2 Ferrimagnetic materials - soft ferrites Ferrites are grey/black, hard, brittle, chemically inert ceramic materials, which have a magnetic cubic (spinel) structure. The most general ferrites are polycrystalline magnetic isotropic (grains non-aligned) ceramic oxides, which are compounds of iron oxide, Fe203, about 50%, mixed with one or more oxides of bivalent transition metals such as Fe0, Ni0, Zn0, Mn0, Cu0, Ba0, Co0, and Mg0, to give the general compositional form MeFe204. At lower frequencies, below a few MHz, a Mn-Zn combination is added to iron oxide, while for higher frequencies, above a MHz, Ni-Zn is the additive. The raw pure oxide materials are mixed with organic binders, pre-sintered at 1000°C, a process called Calcining and then the partially formed ferrite structure pellets are wet ground by milling, to form a submicron particle slurry with water. After spray drying, the powder material is shaped by means of pressing and sintering at between 1150°C and 1300°C, which cause densification and substantial shrinkage. The sintering process involves raising the temperature to 1300°C in about 3 h, with 15 per cent oxygen present. The cores are cooled slowly without oxygen present to about 200°C in 20 h after entry. In producing the ferrite crystal structure, a 15 per cent linear, and 40 per cent by volume shrinkage occurs during sintering. A diverse range of ferrite core shapes is available, which include, E, I, U, toroid, drum, pot, rod, tube, and screw. Where appropriate, diamond-wheel-ground air gaps are available on the centre pole. Manufacturing yields limit the physical component in size. Toroid cores of 152 mm outside diameter are not uncommon, and exotic shapes such as motor stators are made for special applications. 24.3

Comparison of material types

Table 24.1 shows typical comparative data for the main classes of soft ferro and ferri magnetic materials. Generally, those materials with higher saturating flux densities, Bs, have higher initial permeability µi, and hence offer higher inductance but at the expense of higher core eddy current and hysteresis losses. Table 24.1. Typical comparative data of soft magnetic materials Material

T

%

A/m

Hm=800A/m

Hm=800A/m

Hm=800A/m

µr 3 ×10 1kHz Hm=0.5A/m

25°C

25°C

25°C

25°C

25°C

18

1.23

89

0.6

30

5

600

0

570

18

1.23

5

0.6

50

16

250

0

570

25

1.56

83

2.4

5

5

2200

+27

415

20

0.55

5

0.3

115

18

280

0

180

20

0.60

85

0.3

30

10

460

0

210

3% Si steel

50

1.9

85

6.0

2.7

0.8

8400

-0.8

750

6½% Si steel

50

1.3

63

45

1.2

0.8

5800

-0.1

700

25

1.5

95

12

-

-

3400

+25

500

25

0.74

55

0.5

50

5

1000

0

480

25

0.74

80

2.4

-

-

1200

0

460

-

0.44

23

8.0

5.3

5.3

1200

-0.6

150

-

0.49

29

12

2.4

2.4

680

-0.6

220

thickness

µm

Nanocrystalline Square Fe-Si Nanocrystalline hi-µr Fe-Si Fe based amorphous Co-based hi-µr amorphous Co-based square amorphous

50% Ni Permalloy 80% Ni hi-µr Permalloy 80% Ni square Permalloy Mn-Zn hi-µr ferrite Mn-Zn low-loss ferrite

Bs

Br/Bs

Hc

µr ×103 100kHz Hm=0.5A/m

Pcv

λs

100kHz 25°C

3

kW/m

10

-6

Tc °C

Bm=0.2T

Inductors and Transformers

848

In rfi suppression and filtering applications, silicon steel is not effective since the initial permeability, µi, falls rapidly with frequency hence at the high suppression frequency, inductance is small. Thus iron powder or a high iron alloy may be used, which have relatively high flux densities and high losses. For rfi suppression, a high core loss aids suppression. At inaudible frequencies, >20 kHz, for a low core loss, ferrites are extensively used. Although ferrite flux densities are relatively low, typically 0.5 T for power application ferrites, eddy current and hysteresis losses are low. The low eddy current loss results from the high core material resistivity. With ferromagnetic materials, the eddy current loss is reduced by using thinner laminations or electrically isolated powder particles. A major disadvantage of a ferrite core is its poor temperature stability and low allowable core temperature. On the other hand, high initial permeabilities, >20,000, are obtainable. Ferrite materials, application, and component design are specifically considered, although the concepts developed are generally applicable to ferromagnetic materials. ½ 10

1

1½

2

6

10

6

1kHz Permalloy

Nanocrystalline µi = 70,000

Nanocrystalline

µr

Co-based amorphous

Fe-Si

relative permeability

10

5

Fe-M-B

10

5

10

4

Fe, Co-M-B Fe-Al-Si 10

grains >1µm

4

Si-steel

10

Fe-based amorphous

Mn-Zn ferrite

3

0

½

Fe-Co alloy

1

1½

Flux density

Bs

2 (T)

(a)

(b)

Figure 24.2. Magnetic alloy characteristics: (a) permeability versus saturation magnetic flux densities and (b) B-H characteristics.

24.4

Ferrite characteristics

The definitions and explanations given are applicable to soft magnetic materials in general and are illustrated specifically by reference to ferrite materials. General mechanical and thermal properties of power ferrites are given in appendix 24.7, while typical magnetic properties are given in appendix 24.8. Table 24.2. Core effective dimensions and parameters core factor

symbol

definition

units

ℓe /Ae

c1

Σℓ/A

m

effective area

Ae

c1 / Σℓ/A2

m

effective length

le

Ae c1

m

effective volume

Ve

ℓe Ae

m

core permeance

c

µo /c1

H

-1 2

3

24.4.1 Dimensions and parameters The effective magnetic dimensions are constant for a given core and are defined in table 24.2. These effective constants are based on the length ℓ and area A of the individual limbs comprising the complete

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core. These effective dimensions are used for magnetic component design, such as transformer core loss, which is given per unit effective volume, Ve. From the parameters in table 24.2, inductance is calculated from equation (24.6) as L = µi cN 2 (H) (24.17) 24.4.2 Permeability Figure 24.2 shows that a non-linear relationship exists between B and H for magnetic materials, and is characterised by the dimensionless parameter µr - the relative permeability - according to B = µo µr H (where µo = 4π×10-7 H/m). Figure 24.3 shows a detailed B-H magnetising curve for a ferrite material along with its hysteresis loop. The case of an air core magnetic circuit, for which µr = 1, is also shown. Figure 24.3 illustrates various definitions for µr based on the ratio flux density to field strength, namely 1 B µr = (24.18) µo H

µ∆µo

0.1

µaµo

200

Figure 24.3. Hysteresis loop illustrating permeability definitions, remanence Br, and coercive force Hc.

24.4.2i - Initial or intrinsic permeability, µi The initial permeability, which is dependant on temperature and frequency, is the permeability at weak field strengths at H = 0 and ∆H tends to zero, that is  1 ∆B  µi =  (24.19)   µo ∆H  H = 0, ∆H → 0 ∧

24.4.2ii - Amplitude permeability, µa and maximum permeability, µ The amplitude permeability applies to large magnitude sinusoids, with no dc field (offset) applied, and is the ratio of the sinusoid peak B and H  1 B µa =  (24.20)   µo H  H = 0 ∧ ∧ The maximum permeability µ is the maximum µa obtainable for any H, that is, µ = max [µa] for all values of H. The variation of amplitude permeability with magnetising force or flux density is shown in figure 24.4. Because of the non-linear nature of the B-H curve loop, the amplitude permeability is highly dependant of the applied field strength magnitude. The figure 24.4 is representative of a ferrite material suitable for a wide range of power electronic applications. More technical data for this material is presented in Appendix 24.8 and in the figures that follow.


850

24.4.2iii - Reversible or incremental permeability, µrev, µ∆ When a core is magnetised with a polarising dc offset field upon which a small ac field is superimposed, the ac H field produces a small lancet-shape hysteresis loop which reduces to a straight line as the ac H field is reduced. The slope of this line, shown in figure 24.3, is called the incremental or reversible permeability 1 lim  ∆B  µ∆ = (24.21)  ∆H  ∆ → H 0 µo   H = constant The incremental permeability, µ∆ is a function of the dc magnetic bias, as shown in figure 24.5. It is usually a maximum when no dc field is present, while for a toroid it is identical with the initial permeability, µi. With increased current, µ∆, hence inductance, decreases.

µ

µ

µ

µ Figure 24.4. Temperature dependence of flux density B and amplitude permeability, µa.

Figure 24.5. Variation of permeability with field strength.

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24.4.2iv - Effective permeability, µe The inductance of a coil with a (air) gapped core of effective (or apparent) permeability µe is given by µ µ N2 L= o e = µe cN 2 = AL N 2 = µe Lo (H) (24.22) ∑ A hence L L 1 L µe = 2 = = (24.23) cN Lo µo N 2 where Lo is the coil inductance if the core is removed (air, µr =1), whence the permeability drops. The term AL is the inductance factor and is equal to µe c. Conversely N =α L (24.24) where α = 1/√ AL and is termed the turns factor. If the air gap, ε, is small compared with the core of length, ℓe, such that ε 2δ thick. A similar effect occurs within conductors carrying ac current, where the current is minimal at the conductor centre. The current density, J, is given by -x

J ( x) = J (0) e δ (A/m3 ) (24.51) Below 20-50 kHz and above a few megahertz, solid wire is preferred. In between these frequencies, stranded wire, Litz wire (after Litzendraht) is preferred; decreasing from 0.07 mm to 0.03 mm in strand diameter as the frequency increases and interwinding capacitance dominates. Copper foil can also be employed.

µ20

10% of µ20

Figure 24.9. Permeability, µi, and maximum density, B , as a function of core temperature, T.

24.4.5 Temperature effects on core characteristics Generally ferrites have poor characteristic temperature stability. At higher temperatures, at the Curie point, core materials lose their ferromagnetic magnetic properties abruptly and become paramagnetic (µe ≈ 1). The temperature causes disruption of the magnet ordering in the crystalline lattice due to molecular thermal motion. The phenomenon is reversible and below the Curie temperature, Tc, the material becomes magnetic again. Typical magnetic material Curie temperatures are:

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857

Fe

770°C

Co

1130°C

Ni

358°C

Nd2Fe14B

(N54)

120°C

Ferrite Mn-Zn

180°C

Nanocrystalline Fe-Si

570°C

The temperature effect on initial permeability in figure 24.9 illustrates the sudden loss of permeability at 212°C, whence the permeability falls to 1, to that of air. The Curie temperature is usually defined as that temperature where the initial permeability falls to 10% of that permeability at 20°C. Generally Curie temperature is inversely proportional to the initial permeability, µi. For most ferrites the initial permeability increases with temperature, and reaches a maximum just below the Curie temperature, as shown in figure 24.9. Other ferrite parameters are also affected by temperature. Increased temperature decreases flux density and hysteresis loss as shown in figures 24.4 and 24.9. The effects of temperature on total core loss per unit volume are shown in figure 24.8a. 24.4.6 Inductance stability Three factors affect inductance core stability: • Parameter effects • Time effects • Temperature effects 24.4.6i - Parameter effects From the differential of equation (24.22) dL d µe = µe L while differentiating equation (24.26) yields d µ e d µi = 2 2

µe

µi

(24.52)

(24.53)

Substituting equation (24.53) into equation (24.52) gives dL d µi AL = 2 (24.54) µi c L The factor d µi / µi2 is constant for a given temperature, hence any change in inductance is due to variations in AL and c. Thus in order to increase the stability of an inductor in a given material with ε > ε , yields equation (24.28) for the effective permeability. c 24.5

Ferrite inductor and choke design, when carrying dc current

Air gaps in magnetic circuits are introduced in order to reduce the influence of a superimposed dc current, manufacturing dispersion and/or to improve parameter stability. Saturable inductors for a semiconductor switch turn-on snubber normally do not employ an air gap, in order to reduce the stored energy, which may be subsequently dissipated, and to minimise the magnetising current magnitude. Empirical equations have been derived for cylindrical inductors with a cylindrical core, which give an inductor with a large air gap. Design equations and examples are given in appendix 24.10.

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Power Electronics

Figure 24.11. Permeability as a function of: (a) air gap, ε and (b) superimposed dc field and air gap.

24.5.1 Linear inductors and chokes The introduction of an air gap reduces the effective permeability, µe such that the coil inductance is given by the equation (24.22) L = µe cN 2 = µe Lo = AL N 2 (H) (24.72) Figure 24.11a shows the variation of the effective permeability, µe at both low flux levels and without a dc bias, as a function of the relative air gap, ε/ℓe as specified by equation (24.27). As the air gap and the superimposed dc field are varied, the incremental permeability, µ∆ varies as shown in figure 24.11b. This figure indicates how inductance varies with dc bias current (H). Figure 24.11 does not specify the optimum inductor design since for a given inductance and dc current the optimum air gap and number of turns are not specified. The minimum number of turns and air gap requirements, for a dc current, can be determined by means of the Hanna curves in figure 24.12. This figure shows experimental families of curves of per unit core energy against magnetomotive force per unit length, for different air gap widths. The resultant curves are ferrite type dependent and dimensionally independent. Hanna curves therefore allow the determination of minimum turns N and air gap ε, from the required inductance L and dc current I. Three distinct energy levels are shown in the Hanna curves in figure 24.12. i. At low dc currents (H) the per unit energy increases linearly with H. This region corresponds to the horizontal regions in figure 24.11b, where L = µ∆ cN 2 (H) (24.73) and as H varies, µ∆ is constant. ii In the mid energy region, the per unit energy can decrease with increased H. The incremental permeability decreases, causing L to decrease at a greater rate than the increase in the dc current squared, I2. This region is characterised by the fall off in µ∆, hence inductance, as H increases as shown in figure 24.11b.


iii.

862

At high dc currents, the core material saturates, and µ∆ tends to unity. Air core inductance results, where L = Lo = c N 2 (24.74)

Figure 24.12. Hanna curves, showing trajectories for different air gaps.

Example 24.3: Inductor design (ferrite) with Hanna curves A 20 µH, 10 A choke is required for a forward converter. The inductance must be constant for unidirectional currents to 10 A. An available E-core pair has the following effective parameters ℓe = 0.11 m, Ae = 175 × 10-6 m2, Ve = 19.3 × 10-6 m3 and µi = 2500 @ 25°C and 3000 @ 100°C (from figure 24.9) i.

At a core temperature of 25°C, determine the required air gap and turns. Allow a 5 per cent decrease in inductance at rated conditions. ii. Estimate the inductance at 20A dc. iii. Calculate the inductance at 10A and 20A dc, both at 100°C. Solution LI 2 20 × 10 −6 × 102 = = 104 J/m 3 Ve 19.3 × 10 −6 From figure 24.12, restricted to the constant-L region, 104 J/m3 corresponds to (a) ε/ℓe = 3 × 10-3 whence ε = 3 × 10-3× ℓe = 3 × 10-3× 0.11 The required total air gap is 0.33 mm (b) H = 650A/m Since H = NI/ ℓe N = H ℓe /I = 650 × 0.11/10 = 7.15 turns Use 7 turns and a 0.33 mm total air gap.

i.

Evaluate

ii.

At 20 A, 25°C H = NI/ ℓe = 7 × 20/0.11 = 1270A/m

863

Power Electronics

Two alternative design approaches may be used to estimate the inductance. (a) The effective permeability, µe, before saturation can be evaluated from equation (24.27) 1 1 ε 1 = + = + 3 × 10−3 µe µa le 2500 that is µe ≈ 300 From figure 24.11b, for µe = 300 it can be seen that the incremental permeability µ∆ is constant, as required to 650A/m, then µ∆ decreases as saturation commences. At H = 1270A/m, µ∆ has fallen to 75, from 300. The incremental inductance at 20 A is about ¼ of 20µH, namely 5.0µH. (b) Alternatively, a simpler approach uses only figure 24.12. H = 1270A/m projects 100 J/m3. Solving 100.0 = L20A I2 / Ve with I = 20A yields L20A = 5µH. iii. The effective permeability at 100°C is 1 1 ε 1 = + = + 3 × 10−3 µe µi le 3000 that is µe ≈ 300 It is seen that, although the initial permeability varies significantly with temperature, here the effective permeability is dominated by the air gap, hence is essentially temperature independent. Figure 24.11b, with H = 640A/m, projects µ∆ = 220 at 100°C. Using L α µ∆, the inductance falls to about 15µH at 100°C, 10 A. At 20A, 100°C, the effects of saturation are highly significant, and figure 24.11b indicates that the incremental permeability is low. The best approximation is to use the air coil curve in figure 24.12. Hence H = 1270A/m projects 9J/m3. From 9 = L20A I2 / Ve, at 20A, 100°C, an inductance of at least 0.43µH can be expected.

♣ Figure 24.5 shows how µ∆ and hence the inductance, falls off as H, and hence the current, increases for ferrite core materials. The larger the air gap, and hence the lower AL and the lower L, the higher H before inductance rolls off. Inductance rolls off faster, the wider the air gap, hence the higher the magnetic field strength, H. The decrease in effective permeability, µe and inductance factor, AL, with increase of air gap, ε, is shown in figure 24.13 for two E-cores. Figure 24.14 shows typical curves for the decrease in µ∆, hence inductance, with increased H, hence current, for both ferrites and alloy or iron powder cores. Because power ferrites have a squarer B-H curve than powder cores, the inductance of ferrites falls off faster. By increasing the core volume, the fall off rate of inductance can be reduced. Depending on core loss for a given volume, a powder core may be more effective than a ferrite; and would have better utilisation of the copper window area. The design approach previously considered in example 24.3 in fact neglects the optimisation of core size and copper I2R loss.

Figure 24.13. Characteristics of a pair of gapped E-cores. Core dimensional parameters are given in table 24.5.


864

Figure 24.14. Comparison of inductance characteristics illustrating how inductance falls off faster with ferrite cores than with iron cores, at higher currents.

2

Figure 24.15. Magnetic biasing capability I L , copper loss I2R, effective permeability µe and over-temperature ∆T of five different effective volume Ve ferrite cores.

24.5.1i - Core temperature and size considerations Figure 24.15 relates stored energy, LI2, and copper loss, I2R, for different cores of the same ferrite type. Once L and I are fixed, figure 24.15 can be used to determine the optimum core size and air gap. This figure shows that with increasing air gap (decreasing µe), the magnetic biasing capability increases along with the associated copper loss, I2R. A flowchart is shown in figure 24.16, which outlines the inductor iterative design procedure to be used in conjunction with figure 24.15.

865

Power Electronics

24.14

24.9

Figure 24.16. Linear inductor design flowchart.

Example 24.4: Inductor design including copper loss With the aid of figure 24.15, design a 20 µH, 10 A dc inductor, calculating the copper loss and temperature rise for the predicted optimum air gap and number of turns. Solution Following the procedure outline in the flowchart of figure 24.16 Evaluating LI2 = 20 ×10-6 x 102 = 2 mJ From the monogram in figure 24.15 use core # 1, with µe = 40 and I2R = 1.8 W. This copper loss will produce a 50°C temperature rise above ambient on the core surface, beneath the winding. The thick bars in figure 24.15 represent a 30-50°C temperature increase range. The core type # 1 has AL and µe values versus total air gap, and effective parameters as shown in figure 24.13 and table 24.5. For µe = 40, AL = 45 nH, a total air gap of 2.7 mm is required. From L = AL N2 N = √20 × 103/45 = 21 turns


866

For I = 10 A dc, I2RCu = 1.8 W, then RCu = 18 mΩ. The copper turns diameter is determined from RCu = N N RL (Ω) (24.75) where RL is the resistance per meter, Ω/m. ℓN is the mean turn length which is either provided for a given former or may be estimated from core physical dimensions. From table 24.5: ℓN = 52 mm RL = RCu / N ℓN = 18 ×10-3/21 × 52 × 10-3 = 0.165 Ω/m Using standard wire tables, appendix 24.11 for 0.165 Ω/m, use 28 SWG (0.154 Ω/m) which has a diameter of 0.36 mm and 0.434 when enamelled. The resultant copper current density is 77 A/mm2. In many applications 4 A/mm2 is used for finer gauge wires up to 20 A/mm2 for heavier gauge wires. These current densities represent about 5 per cent of the fusing current, Ifusing which is approximated by I fusing = 80 d 1.5 The diameter d is in mm. This constraint is unrealistic and inductor and transformer design is based on temperature rise. The approximate copper area is ACu = N × d 2 = 21× 0.434 2 = 3.88mm 2 From table 24.5, the useful winding cross-section is AN = 56 mm2 Only 8 per cent of the former window area is filled, hence the actual copper length is overestimated and I2R loss, hence temperature rise, will be less than the allowed 1.8 W and 50°C respectively.

♣ Comparing the design of examples 24.3 and 24.4, it will be seen that the same design specification can be fulfilled with the latter core of 20 per cent the volume of the former. The bigger core required an 0.33 mm air gap to give µe = 300, while the smaller core required a larger gap of 2.7 mm to give µe = 40. Both cores are of the same ferrite type. The incremental inductance of the smaller core will fall off with current, much faster than with the larger core, as indicated by figure 24.5. For a switch mode power supply application, the rms value of current is less than the peak current at which the inductance is specified. The copper loss, hence temperature rise, is then based on an rms current basis. 24.5.2 Saturable inductors Saturable inductors are used in series with semiconductor switching devices in order to delay the rise of current, thereby reducing switch turn-on stress and loss. In the case of a power transistor, the collector current is delayed until the collector voltage has fallen (see 8.3.4). For thyristor devices, the delay time allows the gate activated cathode area to spread hence giving a high initial di/dt capability. In each case the inductor supports the supply voltage, then after a finite time saturates to a very low inductance, supporting little voltage, and does not influence the switch current. Ferrites are ideal as the core of a saturable inductor because of their low magnetic field strength, Hs, at the onset of flux density saturation, Bs. While the inductor supports voltage, v, the flux density increases, moving up the B-H curve at a rate according to Faraday’s law dB v = NAe (24.76) dt A low magnetising current results. After a finite time the flux density reaches the knee of the B-H curve (Bs, Hs), the core saturates and the incremental permeability falls from an initially high value to that of air, µ∆ = 1. The high initial permeability, hence high inductance, limits the initial current. The time ts, for the core to saturate should be equal to the switch turn-on voltage fall time, tfv. The low saturation inductance allows the switch current rapidly to build up to a level dictated by the load. If the switch voltage fall is assumed linear then the inductor voltage rise is Vs t / tfv. The time ts, taken to reach core saturation (Bs, Hs) from integration of Faraday’s law is (see Chapter 8.3.4) 2 NAe Bs (24.77) ts = Vs for ts ≤ tfv.

Power Electronics

867

The flux density, hence H, and current increase quadratically with time, I s (t / t fv

)

2

. At saturation the

magnetising current magnitude (hence switch current) is  2B H V  H Is = s e  = s s e  (A) N ts Vs  

(24.78)

which should be small compared with the switch on-state full-load current magnitude. The inductance before saturation is given by L = AL N 2 (H) (24.79) and falls to that of an air-cored inductor, viz.: Lsat = c N 2 (H) (24.80) after saturation, when leakage and lead length will, in practice, dominate inductance. The energy stored in the core (pre-saturation) and subsequently dissipated at core reset is given by E = ½ Bs H sVe ( = ¼ I sVs ts ) (24.81) (J) = ½ Bs H s Ae e which must be minimised. Table 24.4 summarises saturable inductor requirements based on equations (24.77) to (24.81). Table 24.4. Design requirement of a saturable inductor Material dependent Bs Hs

Given Vs and tfv Minimise energy E = ½ Bs Hs Ae ℓe

E

(J)

low

low

low

low

×

ts

(s)

×

high

high

×

high

Is

(A)

low

×

×

low

high

L

(H)

low

high

high

low

high

Requirement

low Hs (high µr)

-

-

short ℓe

high N

Compromise

-

high Bs if Hs is low

high Ae if ℓe is short

Maximise time ts =2NAeBs / Vs Minimise mag current Is = Hs ℓe /N Maximise inductance La = N 2Ae Bs / ℓeHs

24.5.3

Core shape dependent Ae ℓe N

Saturable inductor design

Figure 24.17 shows a saturable inductor iterative design flowchart. The design starting point is the type of ferrite. The desired ferrite should have minimal high frequency loss, associated with a low magnetic field intensity, Hs, at saturation. These features would be associated with ferrites having a low coercive force, Hc and remanence, Br. The ferrite material shown in figure 24.4 fulfils these requirements with H c = 12A/m Br = 0.18T H s = 200A/m Bs = 0.4T Ferrites with lower magnetic field strengths are available but tend to be limited in size. A material with a high initial permeability is one indicator of a suitable ferrite type. The next considerations are core shape and effective core parameters such as effective length, ℓe and area, Ae. The core should have a short effective length, ℓe. The area and length are traded in maintaining sufficient copper window area, AN. A core shape without an air gap will produce the highest possible initial, hence effective, permeability. Example 24.5, which follows, illustrates that a toroid (or tube) core offers a good solution. A high number of turns, N, is desirable, and preferred to an increase in area, Ae. Design should be based on the maximum core temperature. An increase in temperature decreases Hs at a faster rate than Bs, as shown in figure 24.4. From equation (24.77), many turns are required which, in combination with decreased Hs, advantageously decrease the magnetising current, Is.


868

(24.77))

(24.78))?

(24.81))?

Figure 24.17. Saturable inductor design flowchart.

Table 24.5. Pot, toroid, and E-core design data. Applicable magnetic data are presented in appendix 24.8

Pot core do = 25 h = 16

Physical dimensions (mm) E-core (pair) Toroid See figure 24.13 do = 39 di = 24.77 h = 6.61

Ve

cm3

3.63

3.86

3.02

Ae ℓe

cm2

0.398

0.525

cm

0.999 3.64

c1

cm1

3.64

9.71 24.4

5.75 10.9

Amin

cm2

0.95

0.398

0.45

AL

nH

4300

1540

(ε = 0)1750

1245

(µi) 3000

(ε = 0)1500

µe c

nH

3.45

0.51

1.15

AN ℓN

cm2 cm

0.357 (0.266) 5.3 (5.35)

4.75 7.6

0.56 5.2

SA

cm2

18.4

48.7/58

20

Weight

g

23.4

19.3

2×8

Power Electronics

869

Example 24.5: Saturable inductor design (also see example 8.6) A pot, toroid, and E-shaped core of the same Mn-Zn ferrite as characterised in appendix 24.8, and of similar volume, have characteristics and parameters as shown in table 24.5, with Hs = 200At/m. Design a saturable inductor for each core shape, for a switch having a 200 ns linear voltage fall time at turn-on when switching on a Vs = 600 V dc supply rail. The core is to saturate when the switch voltage reaches saturation (0 V), after 200ns. Estimate the core power removed at reset if the switching frequency is 20 kHz. Solution

From equation (24.77) N = Vs tfv /2AeBs = 1.875/Ae Ae is in cm2 From equation (24.78) Is = Hs ℓe /N = 2ℓe /N (A) ℓe is in cm From equation (24.79) 2 -3 (µH) L = AL N × 10 From equation (24.80) Lsat = c N2 (nH) From equation (24.81) -1 (W) Pd = Ve×8×10 3 Ve is in cm

Pot

Toroid

E-cores (ε = 0)

2

5

4

3.64

3.85

2.83

20.2

38.5

28.0

13.8

12.75

18.4

2.90

3.09

2.42

Based on the available copper window area, AN and number of turns, the cores would be applicable to switching currents in excess of 100 A. Smaller cores could be used for lower current levels, although window area AN tends to dictate the required core. From equation (24.81), the power dissipated at 20 kHz (last row in the table) is given by Pd = ½ Bs H sVe f s .

♣

24.6

Power ferrite transformer design

Above a few kilohertz, Mn-Zn ferrite material is almost exclusively used for power transformer cores, and has been optimised by manufacturers for a wide frequency range. Specific core shapes have also been developed to cover a wide power range. In the case of voltage transformers, at 20 kHz and below 100 W, pot cores are used, or when low flux leakage and low emi are important. Such cores can be processed on automatic machines which wind and assemble the whole unit. At powers above 100 W, EE and E-I cores are extensively used. The usable power range of the pot core is increased by increasing frequency and at 500 kHz no alternative exists, because of the low leakage flux, low self-capacitance, and good shielding offered by pot cores. 24.6.1 Ferrite voltage transformer design To simplify ferrite core selection, manufacturers provide the characteristic curves given in figure 24.18 which show the power that can be transmitted by various core shapes. Specifically, these curves show power for the modes of operation commonly used in switch-mode power supplies; such as push-pull, forward, and flyback, as considered in chapter 17, versus the core plus copper volume. A formal transformer design approach based on copper and core losses is shown in the flowchart in figure 24.19 and is applicable to all smps types. Stage 1 and stage 2 The transformer, primary and secondary voltages, currents, and powers, hence efficiency, must be specified or determined. Other requirements are switching frequency, ambient temperature, and allowable temperature rise at the core to copper interface. The final specification should include V p Vs Ip

Is

Pp

Ps

η , f , Ta , ∆T


870

17.16)

17.11a)

17.11c)

(figure 24.15)

Figure 24.18. Transmissible power, P, versus volume (ferrite plus copper), V, of transformers with ferrite Mn-Zn cores.

Stage 3 The difference between input power and output power is the total power loss, PL, which comprises copper and core losses. The maximum efficiency is obtained when the copper loss equals the core loss. Stage 4 The total power loss, PL, ambient temperature, Ta, and temperature rise, ∆T, specify the exposed copper and core surface area requirements, SA, according to (see equation 5.4) PL SA = (m 2 ) (24.82) ∆T S d where Sd is a surface dissipation factor. Empirical equations are commonly provided for Sd. Based on the assumption that thermal stability is reached half by convection and half by radiation, the surface area requirement can be approximated by  1000  S A = 145 ×    Ta + 273 

2.06

PL ∆T 1.22

(cm 2 )

(24.83)

Stage 5 A core with the minimum surface area, SA, is selected using manufacturers’ data, ensuring that the ferrite type is appropriate to the operating frequency and that the core shape meets any engineering, cost or other special requirements. The manufacturers’ data required include the effective dimensional parameters, copper winding area, AN, and average turn length, ℓN. Some manufacturers provide transformer design data for each core. This specific data can be employed, rather than the general procedure that follows.

871

Power Electronics

24.7c

Figure 24.19. Voltage transformer design flowchart.

Stage 6 Using the core volume, Ve, and core loss Pc = ½PL, whence core loss per cm3, Pw = Pc /Ve the maximum allowable operating flux density, Bop, for the specified frequency can be determined from the power loss curves in figure 24.8c. Stage 7 The rated saturation flux density, Bs, cannot safely be used. For a transformer using both quadrants of the B-H characteristics, for example, a push-pull smps transformer Bop ≤ 0.8 Bs


872

while for a core used with a flux bias Bop ≤ 0.4 Bs These limits avoid operational saturation of the core in one direction. If the working flux density, Bop, is too high, either • reduce the efficiency and go to stage 1/2, or • reduce the allowable temperature rise and go to stage 4. Stage 8 The required number of primary turns, Np, can be calculated from Faraday’s law, which yields Vp (24.84) Np = k Bop Ae f where k = 4 for a square-wave voltage k = 4.44 for a sine wave. If Bop > 100 mT, the effective area, Ae, in equation (24.84) is replaced by the core minimum area section, Amin, since that portion experiences the highest flux density. The number of secondary turns is calculated according to V Ns = N p s Vp

(24.85)

Stage 9 The winding diameter, dp, for the allotted primary for a window area, Ap, is calculated according to Ap k w (m) (24.86) dp = 2 π Np where kw is a winding space factor, 0.7, which accounts for insulation, winding taps, shielding, air space, etc. A similar expression for the diameter of the secondary, dp, involves the number of secondary turns, Ns, and allotted area, AN. The total winding area Ap + As must not exceed the available winding area, AN. Standard copper wire tables, appendix 24.11, provide the resistance per meter, RL, for the calculated diameters. From equation (24.75), the dc resistance of the primary can be calculated according to R p = N p N RLp (Ω) (24.87) Similarly for calculating the secondary dc resistance, Rs. The total copper loss can be calculated as PCu = I p2 R p + I s2 Rs

(W)

(24.88)

Stage 10 The core loss, Pc, and the copper loss, PCu are compared. If (i) PCu > Pc Either decrease the number of turns and increase the copper diameter. This will reduce the copper loss and increase Bop, and hence Pc. Recalculate from stage 6. or select a larger core, which will increase the copper window area, AN, hence increasing the allowable wire diameter. Recalculate from stage 5. (ii) PCu < Pc Either increase the number of turns which will reduce diameter d, Bop hence Pc, and then recalculate from stage 6. or select a smaller core, which will require d to be reduced, and then recalculate from stage 5. Proceed if PCu ≈ Pc. Stage 11 Update the value of total losses, PL, and hence recalculate the power requirements and resultant efficiency. Calculate the actual core temperature rise from equation (24.83), rearranged 1.69

0.82

 1000   PL  ∆T = 59  (K)  ×   SA   Ta + 273  where SA is the heat dissipating area in cm2 of the chosen core.

(24.89)

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Example 24.6: Ferrite voltage transformer design Consider the design requirements for the split dc rail push-pull smps shown in figure 15.15b, which is specified as follows vo = 5 V io = 4A Po = 20 W

Vs = 48 V ± 15 per cent f = 20kHz Ta = 25°C, ∆T ≤ 35 K η = 97 per cent (excluding secondary stage losses)

Solution Based on the flowchart in figure 24.19 and the eleven stages outlined, design proceeds as follows. Stage 1 The transformer must deliver 20 W plus losses associated with an output inductor and the pair of Schottky diodes in the output rectifier. The inductor loss is estimated at 4 per cent of the output power, 0.8 W, while the diode total loss is 0.6 V × 4 A = 2.4 W. Thus the transformer output power requirement Ps is 23.2 W (20 W + 0.8 W + 2.4 W). With a 97 per cent efficiency, the transformer input power, Pp, requirement is 1/97 per cent of 23.2 W, namely 23.9 W. The nominal primary current, Ip, at the nominal voltage, 24 V is Pp 23.9W Ip = = = 1A V pn 24V The maximum primary voltage, Vp, is ½ ×1.15×Vsec = 27.6 V, since the 48 V supply is centre tapped and has + 15 per cent regulation. For worst case, it is assumed that the voltage drop across the switches is zero. The transformer secondary voltage, Vsec, for the centre tapped full-wave rectifier circuit, must be large enough to overcome the diode voltage drop, Vd, and must allow for averaging of the nominal low duty cycle switching action of the primary input power. With pwm regulation each input switch operates for approximately 25 per cent of the time, thus ½Vs = 2× (Vo + Vd ) where the ½ indicates that half of the secondary winding conducts at any one time, while the 2 approximates the pwm average on-time. Thus for Vd = 0.6 V and Vo = 5 V Vsec = 4 × ( 5 + 0.6 ) = 22.4V Stage 2 Extracting the transformer data from stage 1 Ip = 1A Vp = 27.6 V Pp= 23.9 W

Is = 4A Vsec = 22.4 V Ps = 23.2 W

η = 97 per cent, f = 20 kHz, Ta = 25°C, ∆T = 35 K Stage 3 The total transformer power loss, PL, from Ps – Pp, is 0.7 W. Thus Pc = PCu = ½ ×0.7 = 0.35 W each. Stage 4 The surface area requirement is calculated from equation (24.83) 2.06 0.7W  1000  S A = 145 ×   × 351.22 + 25 273   = 16.1 cm2 for a 35 K temperature rise Stage 5 Either the pot core in table 24.5 or the pair of E-cores in figure 24.13 have sufficient surface area, 18.4 and 20 cm2 respectively, and both are of a ferrite material suitable for a 10 to 100 kHz operating frequency range. At the low power level of 23.9 W ( ts Either increase the number of turns, using a core with a larger window AN if necessary. or increase the core area, Ae, which can be achieved with the same window area, AN, either with a core of increased thickness or by using two stacked cores. go to stage 3 ∧

(ii)

If ts >> t on Either decrease the number of turns which may allow a smaller core size. or decrease the core cross-sectional area. go to stage 3 ∧ If ts ≥ ∼ t on , proceed to stage 5

(iii) Stage 5

∧

Calculate the magnetising current at t on ∧

H t I p = s e on N p ts ∨

(24.96)

(A)

Stage 6 ∨

Calculate the secondary current, taking the magnetising current I p into account ∧

∨

I −I Is = p p nT ∧

∧

(24.97)

Is β = I p / I s sufficiently large? ∧

∧

If I p > β I s Either decrease the magnetising current by increasing core area. or increase the turns ratio, nT. go to stage∧ 3 ∧ (ii) If I p β I s Either decrease the turns ratio, nT. or decrease the core cross-sectional area. go to stage∧ 3 ∧ (iii) If I p < ∼ β I s , proceed to stage 7 (i)

Stage 7 Calculate the core reset voltage ∧

Vsr = V p

t on ∨

t off

(V)

Calculate the reflected primary on-state voltage during core reset Vsr N p ep = Ns

(24.98)

(24.99)

Example 24.7: Ferrite current transformer design A current transformer primary is used in the collector of a bipolar junction transistor switching circuit and the secondary is used to provide transistor base current as shown in figure 24.21. The maximum collector current is 100 A and the transistor has a gain of 8 at 100 A, in saturation (vbe sat = 1.2V). The transistor maximum on-time is 46 µs while the minimum off-time is 4 µs. Design a suitable current transformer using the toroid ferrite core, which has low flux leakage and is specified by the data in table 24.5 and appendix 24.8. Assume a core temperature of 25°C.

Power Electronics

879

Figure 24.21. Current transformer for BJT base drive.

Solution Based on the flowchart in figure 24.20 and the procedure previously outlined: Stage 1 The required turns ratio factor is nT = Np / Ns = β = 8/1. In allowing for the magnetising current component, choose nT = 15/2. The secondary winding voltage is the maximum transistor base to emitter voltage plus the maximum voltage drop across a series diode. Maximum voltage occurs at maximum current. Vs = Vbe + VD sat

= 1.2V + 1.2V = 2.4 V

Stage 2 The current transformer requirements can be summarised as follows ∧

nT = Np / Ns = 15/2

t on = 46µs

Vsec = 2.4V

t off = 4µs

∨

Stage 3 The ferrite toroid core specified in table 24.5, fulfils the following requirements Bs = 0.4 T at Hs = 200 A/m and A = 0.398 cm2, ℓe = 9.71cm while the available window area, AN, is 4.75 cm2. This window must accommodate two conductor turns of 100 A (plus magnetising current) each and fifteen conductor turns of 12 A each. Stage 4 The time, ts, before core saturation is given by equation (24.92), and assuming Br = 0 15×0.4×0.4T×10-4 ts = = 100 µs 2.4V ∧

Since ts > t on , that is 100 µs > 46 µs, proceed to stage 5. Stage 5 ∧

The maximum primary magnetising current, I p is specified by equation (24.96) ∧ 46µs 200×9.71×10-2 Ip = × = 4.47A 100µs 2


880

Stage 6 The 4.47 A of magnetising current detracts from the primary current available for current transformer action. The maximum available secondary current under worst-case conditions is given by equation (24.97) ∧ 100A - 4.47A Is = = 12.7A 15

2

The maximum allowable collector current is this base current, 12.7 A, multiplied by the transistor gain, 8, which yields 102 A. This is larger than the specified maximum collector current of 100 A, hence the design is correct. Stage 7 In the on-state, the secondary voltage is 2.4V and the reflected primary voltage is 0.32V. The maximum secondary voltage, Vsr, required to reset the core is given by equation (24.98) 46µs Vsr = 2.4V× = 27.6V 4µs The reflected primary voltage is 3.7 V. The available inherent circuit reset voltage is usually much larger, being clamped by a base circuit diode in avalanche. Therefore the core reset time will be shorter than 4 µs. At currents much lower than 100 A, the secondary voltage is decreased, hence the magnetising current is reduced. This reduced magnetising current could consume the full collector current at collector currents of a few amperes. It is therefore necessary to add extra base current to compensate for this deficiency at low currents. The minimum secondary voltage, Vsec, specifies the extra requirement according to ∨

∧

V Ip = s × (24.100) Vs nT ∨ For V s = 1.2 V, the extra base current requirement is 1.2 4.47 I b΄ = × = 300mA 2.4 7.5 This current can be delivered from an inductive circuit since zero extra current is initially required, and the requirement rises linearly to 300 mA in 46 µs. A base start pulse of a few microseconds duration is required initially to turn the transistor on, whence collector current is established and current transformer action commences, and is self-sustaining. I b΄

♣ 24.6.5 Current measurement: closed loop ferrite transformer Figure 24.22 shows a ferrite current measurement transformer where a compensation winding maintains the air gap flux at zero, enabling dc (as well as ac) currents to be measured. Measurement bandwidth is typically dc to 200kHz. The current to be measured, primary current Ip, produces an mmf in the ferrite toroidal core. A Hall effect transducer detects the flux in the core air gap and an op amp compensation circuit drives current through the high turns winding in an attempt to zero the core flux. The current in the compensation winding is therefore proportional to the current being measured, according to (24.101) N pI p = NsI s The same transducer can be used to measure voltage by adding an external series resistor in the primary, which produces a current that is measured, which is proportional to the voltage. The number of primary turns is usually large so as to minimize the resistor current. The resistance, in conjunction with the primary self inductance (and leakage), limit the measurement bandwidth, to the time constant L/R. Φ=o Ip

1: ηT

Is Hall

+ Is RB

Vo = Is RB = ηT Ip RB

Figure 24.22. Current measurement transducer using a flux compensated toroidal ferrite core.

Power Electronics

881

24.6.6 Current measurement: Rogowski Coil A Rogowski coil is a toroidal coil or loop of wire used to measure non-DC currents. Similar to a current transformer, the conductor carrying the current to be measured passes through the opening of the loop. Instead of measuring the short circuit current through the coil directly, the measurement is instead the integral of the open circuit voltage. No magnetically permeable core, like a standard current transformer, is used which gives low inductance. Since the coil has no permeable core to saturate, response is linear for large currents. Being of low inductance response to fast frequency pulses is excellent. A standard current transformer core can saturate at high currents, and the inductance limits its frequency response. Susceptible to external electromagnetic interference increases the closer the loop is to a perfectly symmetric circular coil. Although the topological shape can deviate significantly without significant loss of performance. It is for measuring high frequency and/or high current. Each turn of the coil produces a voltage proportional to the rate of change of the magnetic flux through the turn. Assuming a uniform magnetic field density, the rate of change magnetic flux is equal to the rate of change of magnetic field density multiplied by the cross-sectional area of the turn.

v =

dφ dB =A dt dt

while for a coil with n turns

v =N ×A

dB dt

The magnetic field due to a long straight conductor carrying current I is

B =I ×

µo 2π r

where r is the perpendicular radial distance from the conductor to the point at which the magnetic field is evaluated. The voltage of the measurement coil is then

v coil = N ×

A µo dI × 2π r dt

(24.102)

Integration, using an op-amp integrator, gives current 1 v out = ∫v coil dt

RinC b /f

=

24.7

1

RinC b /f

×N ×

(24.103)

A µo ×I 2π r

Appendix: Soft ferrite general technical data Tensile strength

20

N/mm2

Resistance to compression

100

N/mm2

Vickers hardness HV15

8000

N/mm2

Modulus of elasticity

150,000

N/mm2

Breakage modulus

80-120

N/mm2

Thermal conductivity

4 - 7× 10-3 -6

J/mm s K (W/mm/K)

Linear expansion coefficient

7-10×10

/K

Specific heat

0.75

J/g K

Density

4-5

g/cm3 (4 per cent Si, 7.63 g/cm3)

Resistivity ρ

λs =

∆

Ω cm 105

×10-16 -18

1

-1.5

*

ε r¶ / ρ § ( pu ) 10 kHz

100 kHz

1 MHz

100 MHz

300 MHz

30/1

15/1

12/1

11/0.97

11/0.95

-

-

140×103/1 50×103/0.95 30×103/0.65

* Magnetostriction, at saturation, contraction. ¶ Dielectric constant, εr → 10-20 at high frequency. § Resistivity normalised at low frequency.


24.8

882

Appendix: Technical data for a ferrite applicable to power applications Symbol

Unit

Test condition

#1

#2

Hs

T T A/m

25°C 25°C 100°C Bs, 25°C

2500±20% 0.48 0.37 Bs = 0.4T : 200

2200±25% 0.54 0.45 Bs = 0.5T : 200

H

A/m 25°C 100°C

1600 12/0.18 9.6/0.11 > 200

13/0.17 6.5/0.06 > 250

100

700

µi ∧

B

A/m

Hc /Br

/T

Tc

°C

ρ

Ω cm

η

-1

* B

-6

mT × 10

10 kHz

0.9 4.8

4.9

25°C

1.8

1.6

3

Density

g/cm

fc

MHz * - Maximum hysteresis coefficient 10 G (gauss) = 1 mT (milliTesla) 10 e = 80A/m

Appendix: Technical data for Iron, nickel, and cobalt applicable to power applications

10

1 nanocrystalline

10kHz

B

Pc

Nanocrystalline Fe-Si-B-Nb-Co Alloy

1kHz

1 FeNi 50%

0.1 25°C 1 W/kg = 7.35 mW/cm3

0.1

FeNi 80%

½

Ferrite

1

100%

B

(T)

1

(a)

(b)

(c)

(d) pu

flux density

nano crystalline

10

50

70

90

temperature °C

110

130

Bs ferrite

-100%

1000 H

10000 A/m

µi = 85,000

5

µi 30

µ

initial permeability

10

100

µi = 50,000

0 -10

10 field intensity

µ and Bs

50%

-50%

FeSi

0

0.01

% change permeability and flux density

1½

20kHz

ferrite

core power losses

50kHz

(T)

50kHz 20kHz

100

flux density

W/kg

24.9

µi = 25,000 10

nanocrystalline

4

ferrite

10

3

1

10 frequency

100

1000 f

10000

(kHz)

Figure 24.23. Typical Fe-Si nanocrystalline material characteristics: (a) core losses; (b) B-H curves; (c) temperature dependence; and (d) permeability dependence on frequency.

Power Electronics

883

alloy

grain size

saturation flux density

d

Bs

λs

nm

T

10

saturation magnetostriction

-6

coercivity

initial permeability

Hc

µi

A/m

electrical resistivity

14

1.23

0

0.4

100,000

ribbon thickness

ρ

Pc

t

µΩcm

W/kg

µm

0.2T 100kHz

@ 1 kHz

Fe73.5Si15.5

core losses

115

35

21

Fe84Nb7B9

9

1.49

0.1

8

22,000

58

76

22

Fe86Cu1Zr7B6

10

1.52

0

3.2

48,000

56

116

20

Fe91Zr7B3

17

1.63

-1.1

5.6

22,000

44

80

18

Co68Fe4(MoSiB)28

amorphous

0.55

0

0.3

150,000

135

35

23

Fe76(SiB)24

amorphous

1.45

32

3

8,000

135

50

23

80% Ni-Fe

100,000

0.75

1

0.5

100,000

55

90

50

50% Ni-Fe

100,000

1.55

25

5

40,000

45

200

70

24.10

Appendix: Cylindrical inductor design

Figures 24.24a and b show cross-sectional views of single-layer and multi-layer cylindrical inductors. The inductance of a single-layer cylindrical inductor (all dimensions are in mm) is given by µeff r 2 N 2 L= (µH) (24.104) 228.6r + 254 while for the multi-layer cylindrical inductor shown in figure 24.24b, inductance is given by µeff r 2 N 2 L= (µH) (24.105) 152.4r + 228.6 + 254b Figure 24.24d shows a family of curves used to give the effective permeability from the former l /d ratio and the core material permeability. These curves are applicable to the single-layer inductor but are a fair approximation of the multi-layer inductor. The winding is assumed to be closely wound over 95 per cent of the core length. The inductance of a flat coil as shown in figure 24.24c is virtually independent of any axial core and is given by

L=

r 2N 2 203r + 279b

(µH)

(24.106)

For inductance levels below 100 µH, an air core strip wound inductor as shown in figure 24.24e, has an inductance approximated by r2 N 2 L= (µH) (24.107) l b  + 2r  225r + 250 + 250b + 82.5   r  + 4r  Inductor design using these equations may require an iterative solution. Always attempt to maximise the winding surface area ( S A ≈ π ( d + 2b ) ) for better cooling. Example 24.8: Wound strip air core inductor An air core inductance of 50 µH is made as a wound strip of copper, 40 mm wide and 1.5 mm thick. For cooling purposes, ½ mm spacing is used between each turn with an inner diameter of 60 mm and an outer diameter of 160 mm as physical constraints: Can the required inductance be achieved? Solution First calculate the parameters shown in figure 24.24e. r = ¼ ( d o + d i ) = ¼ × (160 + 60 ) = 55 mm b = ¼ ( d o − di ) = ¼ × (160 − 60 ) = 25 mm = 40 mm b 50 = = 25 turns tCu + tair 1.5 + 0.5 Substitution of the appropriate parameters values into equation (24.107) yields L = 51.6 µH. N=

♣


884

b r

(c) start

3

4

10

2

5

11

1

6

12 finish

turns to minimise capacitance

(e)

(d) Figure 24.24. Cylindrical inductors: (a) single-layer coil; (b) multi-layer coil; (c) coil layer; (d) effective permeability for different aspect ratios, l/d; and (e) core strip wound air core inductor.

Example 24.9: Multi-layer air core inductor An air core inductor is to have the same dimensions as the inductor in example 24.8. The same conductor area (40 mm × 1.5 mm) but circular in cross-section and number of turns is to be used. Calculate the inductance. If a ferrite solid cylindrical core 42 mm long and 60 mm in diameter with a relative permeability of 25 is inserted, what will the inductance increase to? Solution From example 24.8 r = 55 mm ℓ = 40 mm b = 50mm N = 25 Substitution of these parameter values into equation (24.105) yields 62.5 µH. From figure 24.24c, ℓ / d = 40/60 = 0.66, whence µeff ≈ 3. That is, with a cylindrical core inserted, a three fold increase in inductance would be expected (188 µH). The use of end-caps and an outer magnetic sleeve would increase inductance, but importantly also help to contain the external magnetic field.

♣

Power Electronics

885

24.11

Appendix: Copper wire design data Nominal wire diameter d

Outer diameter Approximate enamelled dc resistance grade 2 at 20°C

Bare copper Fusing weight current

mm

mm

Ω/m

gm/m

A

0.1

0.129

2.195

0.070

2.5

0.2

0.245

0.5488

0.279

7

0.376

0.462

0.136

1.117

18

0.5

0.569

8.781 × 10-2

1.746

27.5

0.6

0.674

6.098 × 10-2

2.50

36

0.885

-2

4.469

57

-2

0.8 0.95

1.041

2.432 × 10

6.301

79

1

1.093

2.195 × 10-2

6.982

82

-3

1.5

1.608

9.67 × 10

15.71

145

2

2.120

5.44 × 10-3

27.93

225

2.631

-3

43.64

310

-3

2.5

3.48 × 10

3

3.142

2.42 × 10

62.84

>

4

4.160

1.36 × 10-3

111.7

>

4.668

-3

141.4

>

-4

174.6

>

4.5 5.0

24.12

3.430 × 10

5.177

1.08 × 10

8.70 × 10

Appendix: Minimisation of stray inductance

In many circuit layouts, it is essential to minimise stray and residual inductance. With high di/dt currents during switching, large voltages occur (v = L di/dt) which may impress excessive stresses on devices and components. Stray inductance within a package reduces its usable voltage rating. Stray inductance in the drain circuit of the MOSFET, within the package as shown in figure 4.11, reduces the usable voltage rail while source inductance increases the transient gate voltage. In the case of capacitors, residual inductance reduces the effectiveness of turn-off snubbers and can result in an unintentional resonant circuit. Inductance of a straight wire of length ℓ and radius r is µ  2  (H) L = o  n − ¾ (24.108) 2π  r  which as a rule of thumb is about 1µH/m. 24.12.1 Reduction in wiring residual inductance Wiring inductance can be decreased by cancelling magnetic fields in a number of ways • coaxial cable • parallel plates • parallel wiring conductors. In each case, the go and return paths are made parallel and physically close. Figure 24.25 shows the per unit length inductance for each wiring method. coaxial cable Minimum inductance results with coaxial cable, which is available for power application. The per unit inductance and capacitance are given by µµ r L= o r n o (H/m) ri 2π (24.109) ro C = 2πε o ε r / n (F/m) ri where ri is the inner radius and ro the outer radius (ri < ro).


886

Figure 24.25. Relative inductance of go and return wiring conductors.

parallel plates Very low inductance can be achieved by using parallel conducting copper plates separated by a thin insulation layer (µr ≈ 1). The inductance per unit length, neglecting skin effects, is approximated by d (H/m) L = µo w (24.110) ( w >> d ) where d is the separation of the plates and w is the plate width. The parallel plate capacitance is C = ε oε r w / d (F/m) (24.111) A complete analysis of the laminated parallel bus bar configuration is presented in appendix 24.12 parallel wiring conductors For parallel wiring cylindrical conductors of radius r and separation D, in air, µ D L = o n  ( H/m ) ( D >> r ) π r  (24.112) 2πε o C= (F/m) D n  r  When the separation is small over a long distance, ℓ, that is D/ℓ 200 V) are common in power circuits and the physical construction of a resistor places a limit to allowable voltage stress levels. Certain applications within the realm of power electronics may necessitate a power resistor with a low temperature coefficient of resistance (or even a negative temperature coefficient), a high operating temperature, a high pulse power ability or even a low thermoelectric voltage. Any one of these constraints would restrict the type and construction of resistor applicable.

CARBON

Carbon solid ceramic composition Carbon deposited film Metal thin film

fixed

Metal oxide film

RESISTORS METAL

Glazed thick film Temperature sense

WIREWOUND

Fuse Power Current sense Circuit breaker

Resistors

25.1

896

Resistor types

The resistor tree illustrates the main types of resistors used in electrical power applications. The three main resistor types are carbon/metal film, solid, and wire wound. The main electrical and thermal properties of each resistor type are summarised in table 25.1. Typical property values for power resistors are shown, which may vary significantly with physical size and resistance value. 25.2

Resistor construction

Almost all types of power resistors ( ≥1W) have a cylindrical high purity ceramic core, either rod or tube as shown in figure 25.1. The core has a high thermal conductivity, is impervious to moisture penetration, is chemically inert, and is capable of withstanding thermal shock. The resistive element is either a carbon film, a homogeneous metal-based film or a wound wire element around the ceramic body. For high accuracy and reliability, a computer-controlled helical groove is cut into the film types in order to trim the required ohmic resistance. The resistance tolerance can be typically ± 5% for wire wound resistors and better than ± 0.1% for trimmed film types. The terminations are usually nickel-plated steel, or occasionally brass, force fitted to each end of the cylindrical former in order to provide excellent electrical and thermal contact between the resistive layer and the end-cap. Tinned connecting wires of electrolytic copper or copper-clad iron are welded to the end-caps, thereby completing the terminations. Axial cylindrical resistors without leads, used as surface mount resistive devices (SMD), are termed metal electrode leadless face, MELF. All fixed resistance resistor bodies are coated with a protective moisture-resistant, high dielectric field strength, and some times conformal coating, such that the wire terminations remain clear and clean. The resistors are either colour coded by colour bands or provided with an identification stamp of alphanumeric data.

W

1

2

2.5

2

90

7

>300

2

6

2

9

Maximum temperature

Th

°C

150

125

300

175

100

235

275

160

150

200

250

Working voltage

Vm

V

500

500

500

1k

100k

650

2.5k

160

500

700

Voltage coefficient

φ

10-6/ V

200

50

5

10

-

0.1

ωo) tan δ u ≈ ω CR Rs (26.12) Both Rs and Xc are dependent on temperature and frequency as shown in figure 26.3. Figure 26.3a shows that the rated capacitance illustrated has a positive temperature coefficient, the value of which also depends on capacitance and rated voltage. Also shown is the negative temperature dependence of equivalent series resistance ESR. Figure 26.3b shows that CR and ESR both decrease with frequency. Since CR and ESR are temperature and frequency dependent, and are related to tan δ and Z, then tan δ and Z are frequency and temperature dependent as illustrated in figures 26.3c and 26.3d. Figure 26.3c shows the typical characteristics of the impedance of an oxide dielectric capacitor versus frequency, at different temperatures. At low frequencies the negative slope of Z is due to the dominance of the capacitive reactance, Z ≈ Xc = 1/ωCR, whereas the horizontal region, termed the resonance region, is where Z is represented by the ohmic resistance Rs, that is Z ≈ Rs. At higher frequencies the inductive reactance begins to dominate, whence Z ≈ ωLs and tan δ=Rs /ωsL. Figure 26.3d shows how the dissipation factor, tan δ, increases approximately proportionally with frequency to a high value at resonance, as would be expected from equation (26.9). At lower frequencies tan δ may be considered as having a linear frequency dependence, according to tan δ = tan δo + k f.

Figure 26.3. Variation of capacitor equivalent circuit parameters with frequency and temperature for a high voltage (47 µF, 350 V) metal oxide liquid dielectric:(a) Rs and CR as a function of temperature; (b) Rs and CR as a function of frequency; (c) impedance Z as a function of frequency and temperature; and (d) tan δ as a function of frequency and temperature.

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923

26.1.4 Lifetime and failure rate The service life of a capacitor occurs when its parameters fall outside the specification limit, termed degradation. Such parameters are usually the capacitance, dissipation factor, impedance, and leakage current. The service life is specified under specific operating conditions such as voltage, ambient temperature, and current, and will increase • • • •

the lower the ambient temperature, Ta the lower the ripple current or voltage, Ir the lower the operating voltage in proportion to the rated voltage, Vop / VR the higher the ac load frequency, f.

Other factors may be relevant to specific dielectrics. Lifetime is the period until a given failure rate is reached. The failure rate, λ, is the ratio of the number of failures to the service life expected. It is usually indicated in failures per 109 component hours (fit – failure in time) and is an indicator of equipment reliability. If, in a large number N of identical components, percentage ∆N fail in time ∆t, then the failure rated λ, averaged over ∆ t is expressed as 1 ∆N (/h) λ= × (26.13) N ∆t If the sample N is large, then the failure rate in time can be represented by a continuous ‘bathtub’shaped curve as shown in figure 26.4, such that 1 dN (/h) λ= (26.14) N dt This figure shows the three distinct failure periods, and the usual service life is specified according to the failure λo, which is constant. In the case of voltage, current, and other stresses including temperature, which differ from those under which λo is specified, conversion or acceleration factors are used to calculate the new failure rate. Typical conversion factors are given in table 26.2 for ambient temperature Ta, and operating voltage Vop, in relation to rated voltage VR. Alternatively conversion graphs are also used or the Arrhenius’ law n

E 1

1



 V  − K  −  λ = λo  op  e  T To   VR 

(26.15)

gradual deterioration usefull life

Figure 26.4. The bathtub curve showing variation of failure rate with operating hours.

Table 26.2. Stress conversion factors for an aluminium electrolytic capacitor

Vop

Conversion factor

Temperature Ta (°C)

100

1

≤40

1

75

0.4

55

2

VR

%

Conversion factor

50

0.2

70

5

25

0.06

Tjmax

10

10

0.04 (a)

(b)

Capacitors

924

Example 26.1: Failure rate A component has a failure rate λo = 2 x 109/h, commonly termed 2 fit (failures in time) using 109/h as reference. With reference to table 26.2, what is the failure rate if i. ii. iii.

the ambient temperature, Ta, is increased to 55°C the operating voltage is halved i. and ii. occur simultaneously?

Solution Assume λo applies to conditions at Ta ≤ 40°C and VR. i.

If the ambient temperature is increased from 40°C to 55°C, then using a conversion factor of 2 from table 26.2b λ55 = 2 × λo = 4 fit that is, the failure rate has doubled, from 2 fit to 4 fit.

ii.

Similarly, by halving the operating voltage, a conversion factor of 0.2 is employed from table 26.2a. The new failure rate is λ ½V = 0.2 × λo = 0.4 fit That is, the failure rate has decreased by a factor of 5, from 2 fit to 0.4 fit.

iii.

If simultaneously both the ambient temperature is increased to 55°C and the operating voltage is halved, then (assuming independence and superposition of factors) λ 55,½V = 2 × 0.2 × λo

= 0.8 fit The conversion factors are cumulative and the failure rate decreases from 2 fit to 0.8 failures in time.

♣ If the number of units surviving decreases exponential with time, then the probability of failure F after a service time t is given by F ( t ) = 1 − e − λt (26.16) Equipment failure rate can be calculated by summing the failure rates of the individual components, that is λtotal = λ1 + λ2 ..... + λn (26.17) If the failure rate is to be constant, then the instantaneous failure rate of the number of faults per unit time divided by the number of non-failure components must yield a constant dF ( t ) 1 =λ (26.18) 1 − F ( t ) dt For n components in a system, the probability of system survival is 1 − F ( t ) = (1 − F1 ( t ) ) × (1 − F2 ( t ) ) × .... (1 − Fn ( t ) ) = e − λ1t × e− λ2t × .....e − λnt = nλ if, since the units are identical, λ1 = λ2 = … = λn. The mean time between failure (mtbf) is given by ∞ ∞ 1 1 mtbf = = ∫ 1 − F ( t ) dt = ∫ e − λt dt =

λtotal

0

0

λ

The service operating life τ for a specified probability of failure is therefore given by 1 1 τ = An λ 1− F Example 26.2: Capacitor reliability

A capacitor has a failure rate λ of 200 x 10-9 failure/hour, 200 fit. Calculate i. the probability of the component being serviceable after one year ii. the service life if the probability of failure is chosen to be 1% or 0.1%

(26.19)

(26.20)

(26.21)

Power Electronics

925

the mean time between failure the mean time between failure for 10 parallel connected capacitors the probability of survival for 1 year and of failure for units, if 1000 units each have 10 parallel connected capacitors.

iii. iv. v. Solution

i. The probability of the capacitor being serviceable after 8760 h (1 yr) is given by 1 − F (1 yr ) = e − λt 9

= e −200×10 ×8760 = 0.998 (99.8%)

ii. Component lifetime is given by

τ=

1

λ

An

1 1− F

109 1 An = 50,000 h = 5.7 years 200 1 − 0.01 109 1 τ ( 0.1% ) = An = 5,000 h = 0.57 years 200 1 − 0.001

τ (1% ) =

iii. The mean time between failure, given by equation (26.20) is 109 mtbf = 1/ λ = = 5 x 106 h = 570 years 200 iv. The failure rate for 10 capacitors is 10λ = 2000 fit and the mtbf is 1 109 = = 57 years 10λ 2000 v. For 1000 units, each with a failure rate of 10λ, the probability of one unit surviving 1 year is −9

1 - F (1 yr) = e-10 x 200 x 10 x 8760 = 98.2 per cent The probable number of first year failures with 1000 units is −9

F (1 yr) = 1 - e-200 x 10

x 8760

= 0.002 pu = 2 units

♣ The reliability concepts considered are applicable to all electronic components (passive and active) and have been used to illustrate capacitor reliability. 26.1.5 Self-healing

One failure mode of a capacitor is voltage breakdown in a defective area of the dielectric. As a result of the applied voltage, the defective area experiences an abnormally high electric field which may cause failure by arcing within a few tens of nanoseconds. Oxide capacitors using an electrolyte and plastic film dielectric capacitors exhibit self-healing properties, which in the case of plastic film dielectrics allow the capacitor to remain functional after voltage breakdown. In the case of a defect in the dielectric oxide layer of an electrolytic capacitor, the maximum field strength is reached first in the defective region. This is effectively the process which occurs during the formation of the oxide layer, which results in the growth of new oxide, thereby repairing the defect. The reforming process is relatively slow compared with the healing time for non-polarised capacitors. By contrast, the high electric field at the defect in a plastic film capacitor causes a continuous high pressure plasma arc which pushes the dielectric layers apart and evaporates the metallisation in the breakdown region. Temperatures can reach 6000K and insulated areas are formed around the original failure area, which after the arc self-extinguishes, isolate the faulty dielectric within a few microseconds. 26.1.6 Temperature range and capacitance dependance

The operating temperature upper and lower limits are either dictated by expected service life or the allowable variation limits on the nominal capacitance. Most capacitors can be used outside their nominal temperature limits, but at reduced lifetime, hence with reduced reliability. The extremes -55°C to 125°C are common, but obviously electrolytic capacitors must be restricted to a smaller range if the electrolyte is not either to freeze or to boil. Capacitor temperature dependence can be expressed in terms of a temperature dependant capacitance co-efficient α, by

C (T ) = C 20°C (1 + α (T − 20°C ) )

(26.22)

Capacitors

926

26.1.7 Dielectric absorption

After a capacitor is discharged from a voltage Vi, a small voltage Vr reappears, due to a polarisation process in the insulating material. [This phenomena could be considered to be equivalent to remanence flux in magnetic materials]. The voltage tends to be independent of capacitance and dielelctric thickness and is defined at 20°C. The dielectric absorption factor δA is defined by

δA =

Vr × 100% Vi

(26.23)

Typical factor percentage values for various dielectric types are shown in the following table. Dielectric type δA

26.2

%

polypropylene KP 0.05 - 0.10

polyethyleneterephthalate (polyester) KT 0.21 - 0.25

mixed dielectric 0.12 - 0.15

ceramic X7R 0.60 - 1.00

Z5U 2.00 - 2.50

Liquid (organic) and solid, metal oxide dielectric capacitors

The oxides of metals such as aluminium and tantalum are capable of blocking current flow in one direction and conducting in the other. Operation of metal oxide dielectric capacitors is based on the socalled valve effect of these two metals. 26.2.1 Construction

The capacitor dielectric layer consists of aluminium oxide Al203 or tantalum oxide Tn203 which is formed by an electrochemical oxidising process of aluminium foil (0.02 to 0.1mm thick) or sintered tantalum powder. These starting metals form the capacitor anode. The oxide layer withstands high electric field strengths, typically 8 x 108 V/m for Al203 which represents 1.45 nm per volt, and are excellent insulators (hence result in a high capacitor loss factor). This field strength is initially maintained constant (with constant current) during the oxidising process (this electrochemical process is aided by weak phosphoric acid in the case of tantalum capacitors and chloride solution for electrolytic capacitors), then constant voltage, so that the oxide thickness is dependent and practically proportional to the forming voltage VF. To avoid changing the oxide thickness during normal use, the component operated rated voltage VR should always be lower than the forming voltage, as shown in figure 26.5. The difference VF - VR is the over-oxidisation voltage and substantially determines the capacitor operational reliability. For generalpurpose electrolytic capacitors, the value of VR / VF is about 0.8, while solid capacitors are rated at 0.25.

Figure 26.5. Current (leakage) dependence on voltage of Al electrolytic capacitors.

The oxide dielectric constant εr is approximately 8.5 for Al203 and 25 for Ta203, while in comparison paper-based dielectrics have a value of approximately 5. An oxide thickness of w = 0.7 µm is sufficient for high voltage capacitors (≥ 160 V) as compared with minimum practical paper dielectric thickness of about 6 µm. The metal oxide type capacitors potentially offer high capacitance per unit volume. To

Power Electronics

927

further improve the capacitance per unit volume, before oxidation, the aluminium anode surface area is enlarged 10-300 times (foil gain - depending on the voltage – 100x for low voltage and 20x for high voltage capacitors) by electrochemical deep etching processes. In the case of tantalum capacitors, the sintered tantalum sponge like lattice structure results in the same increase of area effect. In the case of tantalum capacitors, the oxide not only grows on the surface of the tantalum, about one third grows into the porous lattice. This tends to limit the maximum voltage rating of tantalum capacitors.

Ca

Ck

anode

1 cathode

C total

=

1

Ca

+

Al2O3 natural oxide

dielectric

highly etched aluminium foil

Etched aluminium foil

Electrochemical oxide layer forming

Paper spacer soaked in electrolyte

electrolyte solution

graphite

Figure 26.6. Construction of metal oxide capacitors.

1

Ck

Capacitors

928

The capacitor is formed by the placement of the cathode on to the oxide layer. In the case of the electrolytic capacitor, a highly conductive organic acid electrolytic (based on dimethylacetamide) which is impregnated into porous paper forms the capacitor cathode. The electrolyte largely determines the ESR hence it must have a low resistivity over a wide temperature range. It must also have a breakdown voltage well above the capacitor rated voltage at maximum operating temperature. For long life, electrolytes with a water content must be avoided. Teflon spacers are sometimes used rather than paper. The electrical contact to the cathode is a layer of etched aluminium, which has a thin oxide layer. In the case of solid capacitors, (with lower voltages), a high conductive cathode is formed by a solid semiconductor metal oxide, such as manganese dioxide. This is achieved by the pyrolysis (continued dipping and baking at 200°C) of manganese nitrate in to manganese dioxide. In solid oxide capacitors, the manganese dioxide is dipped into graphite which is coated with silver epoxy for soldering. The four possibilities are shown in figure 26.6. A porous paper or glass fibre is used as a space keeping agent in order to avoid short circuits and direct mechanical contact. Long strips of the cross-sections are wound into cylindrical bodies and encased as shown in figure 26.6. Operation at high voltages causes oxide growth and the production of hydrogen. Any gas pressure relief valve provided should be orientated upwards. 26.2.2 Voltage ratings

Basic electrolyte (electrolytic) capacitors are suitable only for unipolar voltages, where the anode is positive with respect to the cathode. In the case of the aluminium electrolytic capacitor, the cathode connection metal does have a thin air-oxide layer which corresponds to an anodically generated layer with a blocking voltage capability of about 2 V. Above this voltage level, an electrolytic generated dielectric oxide film would be formed on the cathode foil. The effect is to decrease the capacitance and cause high internal heating and gas formation, which can lead to failure. Solid, oxide capacitors are in principle capable of supporting bipolar voltage since the cathode is a semiconductor, manganese oxide. In practice, impurities such as moisture restrict the reverse voltage limits to 5-15 per cent of VF. The usable reverse voltage decreases with increased ambient temperature. The rated voltage VR may be exceeded under specified intermittent conditions, resulting in a maximum or peak voltage limit VP, as shown in figure 26.5, where for VR ≤ 315V VP = 1.15 VR for VR > 315V VP = 1.1 VR Both VR and VP, are derated with increasing temperature. 26.2.3 Leakage current

When a dc voltage is applied to capacitors, a low current, Iℓ k called the leakage current, flows through every capacitor, as implied by the presence of Ri in the equivalent circuit model in figure 26.2. With oxide dielectric capacitors, this current is high at first and decreases with working time to a final value, as shown in figure 26.7. A low final leakage current is the criterion of a well designed dielectric, thus leakage current can be considered as a measure for the quality of the capacitor. The current is a result of the oxidising activity within the capacitor. The leakage current depends on both dc voltage and ambient temperature, as shown in figure 26.8. The purity of the anode metal, hence oxide dielectric determines the leakage current.

0.9VR

Figure 26.7. Leakage current variation with working time for a liquid aluminium oxide capacitor.

929

Power Electronics

Figure 26.8. Typical leakage current of oxide capacitors versus: (a) voltage and (b) temperature.

Liquid, oxide capacitors have the lower leakage currents at rated voltage since when a voltage is applied; anions in the electrolyte maintain the dielectric electrochemical forming process. The Mn02 in solid oxide capacitors has lower reforming capabilities. From figure 26.8 it will be seen that leakage increases with both temperature and voltage. The increase in leakage current with temperature is lower in liquid capacitors than in the solid because, once again, the electrolyte can provide anions for the dielectric reforming process. For an aluminium electrolyte capacitor at 85°C, an expected lifetime of 2000 hours is achieved by selecting VR / VF = 0.8. However, VF is inversely proportional to absolute temperature so for the same leakage current at 125°C, the ratio of VR / VF must be decreased to VR 273 + 85 = 0.7 = 0.8 × 273 + 125 VF For higher temperature operation, a higher forming voltage is required. But since VF × CR (energy volume) is constant for any dielectric/electrode combination, CR is decreased. When connecting electrolytic capacitors in series, parallel sharing resistors are necessary to compensate for leakage current variation between the capacitors. The design of the sharing network is as for the steady-state voltage sharing for semiconductors presented in 10.1.1, where the sharing resistance is nV R −V s where ∆I A = 1.5 × 10 −3C RV R (26.24) R = ( n − 1 ) ∆I A Additionally, the resistors provide a discharge path for the stored energy at power-off. When parallel connecting capacitors, highest reliability is gained if identically rated capacitors (voltage and capacitance) are used. 26.2.4 Ripple current

The maximum superimposed alternating current, or ripple current Ir is the maximum rms value of the alternating current with which a capacitor is loaded, which produces a temperature difference of 10 K between the core and ambient. Ripple current results in power being dissipated in the ESR, according to 2 P = I R (W) (26.25) d

r

s

which results in an internal temperature rise until equilibrium with the ambient occurs. l is dependent on the thermal dissipation properties of the capacitor, The maximum power dissipation P d and from equation (5.4) l = h A ∆T P (W) (26.26) d 2 where h = heat transfer coefficient (W/m K) A = capacitor outer surface area (m2) ∆T = Ts - Ta = temperature difference between capacitor surface, Ts, and ambient, Ta (K)

Capacitors

930

Figure 26.9. Frequency and temperature ripple current conversion multipliers for: (a) liquid and (b) solid A1203 capacitors.

Thus the maximum ripple current is given by l P d I r = = Rs

hA∆Tl Rs

(A)

(26.27)

The ESR, Rs, is both temperature and frequency dependent, hence rated ripple current Iro, is specified at a given temperature and frequency, and at rated voltage VR. Due to the square root in equation (26.27), conversion to other operating conditions is performed with the frequency multiplier √r and temperature multiplier √k, such that I r = k r I ro = k r I ro (A) (26.28) .

.

Typical multiplier characteristics for aluminium oxide capacitors are shown in figure 26.9. It will be seen from figure 26.9a that electrolytic capacitors are rated at 85°C, while as seen in figure 26.9b solid types are characterised at 125°C. For each type, a reference frequency of 100 Hz is used. Alternatively, the temperature derating multiplier is expressed in terms of the ambient, core and rated temperatures by T − T amb (26.29) k = core T core − T R .

No simple expression exist for the frequency derating factor, r, although it may be used to infer ESR frequency derating

ESRfreq =

ESR100Hz

(26.30) r Electrolytic capacitors usually have a thermal time constant of minutes, which can be exploited to allow intermittent overloads. Example 26.3: Capacitor ripple current rating

A 1000 µF, 385 V liquid, aluminium oxide capacitor has an rms ripple current rating Iro of 3.7 A at 100 Hz and 85°C. Use figure 26.9a to calculate the allowable ripple current at i. 60°C and 1 kHz ii. lowest stress conditions.

Power Electronics

931

Solution i.

Using equation (26.28) Ir =

.

k r I ro = k r I ro .

(A)

where from figure 26.9a at 60°C, √k = 1.85 at 1 kHz, √r = 1.33 whence I = 1.33 × 1.85 × 3.7A r

= 9.1 A ii. This capacitor experiences lowest stressing at temperatures below 40°C, where √k = 2.25 and at frequencies in excess of 2 kHz when √r = 1.37. Under these conditions the ripple current rating is I r = 2.25 × 1.37 × 3.7A

= 11.4A

♣

Figure 26.10. Rms voltage limits of solid tantalum capacitors for different physical dimensions, temperature, voltage rating, and frequency.

Non-sinusoidal ripple currents have to be analysed such that at a given temperature, the individual frequency components satisfy 2 I2 I r ≥ ∑ n (26.31) rn n where I r is for the appropriate rated ambient and reference frequency as indicated in figure 26.9. Liquid tantalum capacitors have a ripple current rating which is determined by the physical dimensions, independent of temperature over a wide range, and independent of frequency above 50 Hz. Ripple current ratings may not be specifically given for some capacitor types, for example solid tantalum capacitors. In this case an indirect approach is used. In satisfying ac voltage limitations as illustrated in figure 26.10, and any series resistance requirement, allowable ripple currents can be specified for a given temperature.

Capacitors

932

Figure 26.11. Service life for an aluminium oxide liquid capacitor. Temperature dependence of lifetime variation with: (a) ripple current and (b) operating voltage.

26.2.5 Service lifetime and reliability 26.2.5i - Liquid, oxide capacitors

As considered in 26.1.3, the reliability and lifetime of a capacitor can be significantly improved by decreasing the thermal and electrical stresses it experiences. Stress reduction is of extreme importance in the case of liquid aluminium oxide capacitors since it is probably the least reliable and most inappropriately used common component. The reliability and service lifetime of an aluminium oxide electrolytic capacitor are dominated by its ripple current, operating temperature, and operating voltage. Figure 26.11 in conjunction with figure 26.9a, can be used to determine service life. Example 26.4: A1203 capacitor service life

A 1000 µF, 385 V dc aluminium oxide liquid capacitor with a ripple current rating Iro of 2.9 A at 100 Hz and 85°C ambient is used at 5 A, 4 kHz, in a 65°C ambient and on a 240 V dc rail. What is the expected service lifetime of the capacitor? Solution From figure 26.9a at 4 kHz, √r =1.35, whence Io 1 5A 1 × = × = 1.28 I ro r 2.9A 1.35 From figure 26.11a, the coordinates 1.28 and 65°C correspond to a 24,000 hour lifetime with less than 1 per cent failures. Since a 385 V dc rated capacitor is used on a 240 V dc rail, that is, a ratio 0.64, an increase in service lifetime of 17½ per cent can be expected, according to figure 26.11b. That is, a service lifetime of 28,000 hours or greater than 3½ years is expected with a relative failure rate of less than 1 per cent. Generally, between 40 and 85°C aluminium electrolytic capacitor lifetime doubles for every 10°C decrease in ambient temperature. A service lifetime of 7 years could be obtained by decreasing the ambient temperature from 65°C to 55°C. .

♣ With aluminium electrolytic capacitors, degradation failures are mostly due to factors such as • aggressiveness of the acidic electrolyte • diffusion of the electrolyte • material impurities.

Power Electronics

933

26.2.5ii - Solid, oxide capacitors

The failure rate of solid aluminium and tantalum capacitors is determined by the occurrence of open and short circuits (the dominant failure mode for solid tantalum capacitors) as a result of dielectric oxide layer breakdown or field crystallisation. In general, for a given oxide operating at rated conditions, liquid capacitors have a shorter lifetime than the corresponding solid type. Solid aluminium capacitors are more reliable than solid tantalum types and failure is usually the degradation of leakage current rather than a short circuit. In comparison with liquid, electrolytic capacitors, solid types, and, in particular, tantalum type capacitors, have a number of desirable characteristics:

• • •

higher capacitance per unit / volume due to the higher permittivity of Ta203 and the intrinsically high effective area per unit volume due to the sintered construction changes in parameters (C, tan δ) are less because the specific resistance of Mn02 and hence temperature coefficient, is lower than that of liquid electrolytes electrolyte is stable, does not evaporate or corrode.

The failure rate of all capacitors can be improved by decreasing the stress factors such as temperature and operating voltage. But reliability of solid tantalum capacitors can be increased by placing a series resistor (low inductance) in the circuit. The improvement is illustrated by the following design example, which compares the lifetime of both liquid and solid tantalum capacitors based on the conversion curves in figure 26.12.

(b)

Figure 26.12. Stress conversion factors for: (a) solid tantalum capacitors and (b) liquid tantalum capacitors.

Example 26.5: Lifetime of tantalum capacitors

A 22 µF tantalum capacitor is required to operate under the following conditions: ambient temperature Ta, 70°C

Capacitors

934

operating voltage Vop, 15 V i. 1 Ω circuit resistance ii. 100 Ω Calculate the expected lifetime for solid and liquid tantalum capacitors. Liquid tantalum

Solid tantalum

R

Ω

1 and 100

1

100

Ri

Ω

n/a

0.1

3

Σ Ri

(1)

12

1

Χ

2.2

at Vop/VR=0.6 and 70°C

λo

/h

λ = λo×Σ fit

4×10

2.2×4×10 -8 8.8×10

/h

τ (% failures) within λ∆t

0.10 -8

1×10 -8

12×0.1×10 -8 1.2×10

88 45,000 (0.4%)

h

0.10

-8

1×10 -8

-8

1×0.1×10 -8 0.1×10

12 83,000 (0.1%)

-8

1 100,000 (0.1%)

Solution

Capacitor used CR = 22 µF VR = 25 V For each capacitor type (solid or liquid) the voltage stress factor is Vop /VR = 0.60 For the solid tantalum, the circuit resistance factor is given by i. Ri' = 1 Ω /15 V = 0.07 Ω/V which is < 0.1 Ω/V ii.

Ri' = 100 Ω /15 V = 6.6 Ω/V which is > 3 Ω/V

Based on figure 26.12, the capacitor lifetime calculation is summarised the previous table.

♣

26.3

Plastic film dielectric capacitors

Plastic (polymer) dielectric type capacitors are non-polarised capacitors and in general offer high dv/dt and pulse rating capability compared with oxide type capacitors. The most common dielectric plastics used (hydrocarbons, as shown in figure 26.13) are: polye t hylene-terephthalate (polyester or PEPT) T poly c arbonate (now obsolete) C poly p ropylene P poly s tyrene S polyphenylene sulph i de I The letter shown after each type is the symbol generally used to designate the film type. The symbol K is used to designate plastic, which is Kunststoff in German. CH3

O

C

C

O

O

CH3 H

H

C

C

H

CH3

(a) (b)

Figure 26.13. Basic hydrocarbon structure of (a) polyethylene-terephthalate and (b) polypropylene.

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Two basic types of plastic film dielectric capacitors are common. The first type involves metallisation deposited on to the plastic and the metal forms the electrodes. Typically such a capacitor would be termed MKP, that is metallised - M, plastic - K, polypropylene - P. A foil capacitor, the second type, results when interleaved and displaced metal foil is used for the electrode. Typically such a capacitor would be termed KS, that is plastic - K, polystyrene - S. The plastic type is generally designated by the fifth letter of the plastic name, that is the letter after poly, with two exceptions. 26.3.1 Construction 26.3.1i - Metallised plastic film dielectric capacitors

The dielectric of these capacitors consists of plastic film on to which metal layers of approximately 0.020.1 µm are vacuum deposited. A margin of non-coated film is left as shown in figure 26.14a. The metallised films are either wound in a rolled cylinder or flattened to form a stacked block construction. In this construction, the metallised films are displaced so that one layer extends out at one end of the roll and the next layer extends out the other end as shown in figure 26.14a. This displaced layer construction is termed extended metallisation and facilitates electrical contact with the electrodes. A hot lead-free metal spray technique, called schooping, is used for making electrical contact to the extended edges of the metallised plastic winding. This large disk area contact method ensures good ohmic contact, hence low loss and low impedance capacitor characteristics result.

plastic film dielectric

extended single metallised film

metal sprayed contact

extended metal foil

metal foil terminal weld

‘schooping’

(a)

(b)

Doubled-sided metallised polyester carrier film polypropylene dielectric film Single-sided metallised polypropylene film

metal sprayed contact ‘schooping’

(c)

(d)

Figure 26.14. Plastic capacitor constructions: (a) extended single metallization film; (b) extended foil; (c) mixed dielectric, extended double-sided metallised carrier film; and (d) mixed dielectric, extended double-sided metallised carrier film with internal series connection.

The most common metallised plastic film capacitors are those employing polyester, MKT and polypropylene, MKP. Polyester has a higher dielectric constant than polypropylene, and because of its stronger physical characteristics it is available in thinner gauges than is polypropylene. Very high capacitance values result in the smallest possible space. But polypropylene has a higher dielectric strength and lower dielectric losses, hence is favoured at higher ac voltages and currents.

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26.3.1ii - Foil and plastic film capacitors

Foil capacitors normally use a plastic film dielectric which is a flexible bi-axially aligned electro-insulator, such as polyester. Aluminium foils and/or tin foils are used as the electrodes. The thin strips are wound to form the capacitor as shown in figure 26.14b. An extended foil technique similar to the extended metallisation method is used to enable contact to be made to the extended foil electrodes. 26.3.1iii - Mixed dielectric capacitors

To further improve the electrical stress capabilities of a capacitor, combinations of different dielectrics are commonly used. Such capacitors use combinations of metallised plastics, metallised paper, discrete foils and dielectrics, and oil impregnation. Figure 26.14c shows the layers of a mixed dielectric paper and polypropylene capacitor. A thin gauge of polypropylene dielectric is combined with textured metallised paper electrodes. The coarse porous nature of the paper allows for improved fluid impregnation of the dielectric material, which counters the occurrence of gas air bubbles in the dielectric. This construction has the electrical advantages of high dielectric strength, low losses, and a self-healing mechanism, all at high voltages. Two plastic dielectrics can be combined, as shown in figure 26.14d, to form a mixed layer capacitor. It involves a double metallised polyethyleneterephthalate film and polypropylene films. These dielectric combinations give low inductance, high dielectric strength, and low losses with high ac voltage capability.

Figure 26.15. Plastic dielectric insulation resistance temperature dependence characteristics: (a) resistance Ri and (b) time constant τ.

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26.3.2 Insulation

The insulation characteristics of a capacitor are indicated either as a resistance value Ri as shown in Figure 26.2 or as a time constant, τ = Ri CR. The resistance comprises the insulation resistance of the dielectric (layer to layer) and the insulation resistance between layer and case. This later resistance is determined by the quality of the case insulating material and by the length of the surface leakage paths. Both the time constant and resistance are dependent on voltage and temperature, as is shown in figure 26.15. These characteristics illustrate that extremely high insulation resistance values can be obtained. 26.3.3 Electrical characteristics 26.3.3i - Temperature dependence

The capacitance of plastic film capacitors changes with both temperature and frequency, as shown in figure 26.16. The dependence is strongly dependent on the dielectric film although some foil types are virtually independent of frequency. Table 26.3 summarises capacitance temperature dependence for a wide range of dielectrics. The temperature coefficient is measured in parts per million per degree Kelvin, ppm/K. The temperature dependence of dissipation factor is shown in figure 26.22a. 26.3.3ii - Dissipation factor and impedance

Figure 26.17a shows the typical frequency dependent characteristics of the dissipation factor for a range of plastic dielectric capacitor types. It is important to note that polyester types have 50-100 times the losses of polypropylene capacitors. A low loss characteristic is important in power pulse applications where capacitor package heat dissipation may be a limiting factor. f = 1kHz

Figure 26.16. Plastic film dielectric capacitance variation with: (a) ambient temperature and (b) frequency.

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Generally, tan δ rises with increased frequency and increased capacitance. Tan δ is dominated by dielectric losses and the contact resistance of the leads. The extended foil/metallisation and schooping contact methods provide not only a low and constant ohmic contact, but because of the large contact area, result in a low self-inductance. The resonant frequency of such capacitors, because of their selfinductance and their capacitance, is high as shown by the minimum impedance in figure 26.17b. Minimum impedance decreases with increased capacitance and each capacitor in the range, here 1.5 nF to 4.7 µF, has its own Y-shaped impedance curve. The self-resonant frequency decreases with increased capacitance. In figure 26.17b, the full impedance curves for maximum and minimum capacitance only have been shown. Table 26.3. Capacitor temperature coefficient for various dielectric materials Dielectric type Polypropylene Polyester Polycarbonate Polystyrene Paper Mica Ceramic Aluminium Tantalum (solid and liquid)

Temperature coefficient (ppm/K) metallised

film/foil

other

-170 400 150

-120 400 (non-linear) -50 to -150 -125 300

300 100 + 1000 to -1000 1500

(non-linear)

+200 to +1000

Figure 26.20. Frequency characteristics for plastic dielectric capacitors: (a) maximum dissipation factor, tan δ and (b) typical impedance characteristics, Z, for metallised plastic dielectric capacitors.

939

Power Electronics

26.3.3iii - Voltage derating

The ac and dc voltages which may be applied continuously to a capacitor vary with ambient temperature and also frequency in the case of ac voltage rating. Typical characteristics showing frequency and temperature dependence are shown in figure 26.18 for plastic dielectric capacitor types. It will be seen that the ac voltage rating is significantly less than the dc voltage rating, while both voltage ratings are derated above 85°C and at higher frequencies. In all situations, the sum of the dc voltage and peak value of superimposed ac voltage must not exceed the rated dc voltage. An alternative approach for calculating the maximum ac voltage, allowable Vac, for a capacitor is based on the power dissipation limits, P, of the package. If we neglect Ri and ESL in the capacitor equivalent circuit shown in figure 26.2, then VR2 (26.32) P= = I 2 Rs (W) Rs and Rs2 VR2 = Vac2 (26.33) 1 Rs2 + 2 2 ω CR Since from equation (26.12) for plastic dielectric capacitors tan δ = ω CR Rs then equation (26.32) can be written as P = ( Rs CR ) ω 2 CRVac2 (W) (26.34) s

s

or alternatively 2 P = tan δ ω CRVac2 (= I rms ESR) (W) (26.35) The value of tan δ for equation (26.35) is available from figure 26.17a or, alternatively, the value of RsCR for equation (26.34) is available from figure 26.19. l which depends on the package dimensions and ambient The maximum permissible power dissipation, P temperature, is given in figure 26.20. Thus when the power dissipation, for a given ac voltage, has been calculated, figure 26.20 can be used to specify the minimum size (dimensions) capacitor capable of dissipating that power. The following example illustrates the design approach outlined.

Figure 26.18. Plastic dielectric capacitor, voltage derating characteristics: (a) dc voltage derating with ambient temperature; (b) ac voltage derating with temperature; and (c) ac voltage derating with frequency.

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Figure 26.19. Maximum product of series resistance, Rs, and rated capacitance, CR, as a function of frequency.

Figure 26.20. Maximum power dissipation for metallised plastic capacitors as a function of ambient temperature and capacitor dimensions.

Example 26.6: Power dissipation limits - ac voltage

A 0.1 µF plastic capacitor is used in a 100 V ac, 10 kHz and 50°C ambient application. Select suitable metallised polypropylene and polyester capacitors for this application. Solution i.

Metallised polyester capacitor (MKT) From equation (26.34) P = ( Rs CR ) ω 2 CRVac2 -7

(W)

From figure 26.19, RsCR = 2 × 10 at 10 kHz. Thus P = (2 × 10-7 ) × (2π × 104 ) 2 × (0.1× 10-6 ) × (100) 2 = 780 mW

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From figure 26.20, at 50°C a MKT capacitor of dimensions 11×20×31 (mm) can dissipate 930 mW. The applicable capacitor must have an ac voltage rating in excess of 100 V ac. From figure 26.18b, it can be seen that a 0.1 µF, 400 V dc MKT capacitor is necessary, given that the dimension constraints are met. ii.

Metallised polypropylene capacitor (MKP) From equation (26.35) P = tan δ ωCRVac2 (W) From figure 26.17a, tan δ = 4.0 × 10-4 at 10 kHz, for a 600 V dc type. Thus P = (4.0 × 10-4 ) × (2π × 104 ) × (0.1× 10-6 ) × 1002 = 25.6 mW From figure 26.20, at 50°C, the smallest volume MKP capacitor, of dimensions 6.5×15×26 mm, can dissipate 300 mW. From figure 26.18c it can be seen that a 0.1 µF, 630 V dc (250 V ac) MKP capacitor is necessary. From figure 26.18c it can be seen that a 250 V dc 0.1 µF polypropylene foil capacitor (KS) is capable of 160 V ac at 10 kHz. Figure 26.17a shows the dissipation factor of KP type capacitors to be under half that of the metallised equivalent. That is, the expected losses are only P = (1.4 × 10-4 ) × (2π × 104 ) × (0.1× 10-6 ) × 1002 = 9 mW

♣ 26.3.3iv - Pulse dVR /dt rating

Related to the ac voltage rating and power handling capabilities of a capacitor is the rated pulse slope dVR /dt, which from i = CR dv / dt is specified by VR V = R (26.36) CR dV /dtmax I where R is the minimum series resistance including the ESR. The rating test is an accelerated test, carried out for 10,000 pulses at a 1Hz repetition rate. The capacitor is then dv/dt rated at 10% of that at which the pulse test was performed. R=

Generally for a given CR, dv/dt capability increases with rated voltage VR, and decreases as the distance between the metallised electrode contacts increases. If the capacitor operating voltage Vop is decreased below VR, at which voltage, dv/dt capability is specified, dv/dt capability increases according to d Vop d VR VR = × (V/s) (26.37) dt dt Vop The dv/dt capability depends on both the dielectric type and layer construction. Generally polystyrene (KS) and polyester (KT) foil type capacitors are not applicable to high dv/dt applications. Metallised polycarbonate capacitors (diminishing availability) offer slightly better dv/dt properties than those of metallised polyester. Metallised paper capacitors can withstand very high levels of dv/dt, 30-50 times higher than those for metallised polyester. Capacitors using polypropylene, or even better a mixed dielectric involving polypropylene, offer extremely high dv/dt capability. With the construction shown in figure 26.14d, a 1 µF metallised polypropylene capacitor with VR of 2000 V dc and 1000 V ac, a 2500 V/µs capability is attainable. Practically the dv/dt limit may be restricted by the external connections. Such ratings are obtainable with polypropylene because of its extremely low losses, tan δ, as indicated in figure 26.17a. Under such high dv/dt stresses, it is important to ensure that the power dissipated does not exceed the package limit. 26.3.4 Non-sinusoidal repetitive voltages

Capacitors used for repetitive transient suppression, and for turn-off snubbers on GTO thyristors and diodes, experience high-magnitude short-duration voltage and current pulses which are not sinusoidal. High dv/dt capacitors based on metallised polypropylene are used, which are limited by their internal power losses, hence temperature rise and package power dissipation limit. A restrictive graphical design approach for capacitor selection with sinusoidal, sawtooth, and trapezoidal pulse trains is shown in figure 26.21. The design approach is illustrated by the following example.

Capacitors

942

Figure 26.21. Metallised polyester capacitor selection graph for sinusoidal and non-sinusoidal voltages.

Example 26.7: Capacitor non-sinusoidal voltage rating

A 0.15 µF MKT capacitor is used to generate a 10 kHz maximum and 25 µs risetime minimum, sawtooth ac voltage waveform. What voltage rated capacitor is applicable if the output voltage maximum is 100 V p-p? Solution

Worst-case conditions are at maximum frequency, 10 kHz, and minimum risetime, 25 µs. With reference to figure 26.21, use f = 10 kHz (repetition frequency) τ = 25 µs (risetime) C = 0.15 µF (capacitance) According to the dashed line in figure 26.21, starting from f = 10 kHz, yields VR = 100 V dc gives maximum peak voltage of 27 V VR = 250 V dc gives maximum peak voltage of 38 V VR = 400 V dc gives maximum peak voltage of 47 V VR = 630 V dc gives maximum peak voltage of 59 V The peak to peak requirement is 100 V, hence only a 630 V dc 0.1 µF MKT capacitor can fulfil the specification.

♣ An alternative approach to specify the voltage limits for non-sinusoidal repetitive voltages is to sum the power contribution due to each voltage harmonic. The total power due to all harmonics must not exceed the capacitor package power limits. The non-sinusoidal voltage v can be expressed in the form (26.38) v = ∑ Vi sin ( iωt + φi ) ∀i

where Vi is the magnitude of the ith voltage harmonic, which has an rms value of V vi = i 2 From equations (26.12) and (26.34), assuming capacitance is frequency independent Pi = ( Rs CR )i ωi2 CR vi2 i

(26.39)

or Pi = tan δ i ωi CRi vi2

(26.40)

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The total power dissipated is the sum of the powers associated with each frequency. The near-linear frequency dependence of tan δ and RS CR, as shown in figures 26.17a and 26.19, may be utilised to simplify the calculation procedure. Assuming the rated capacitance is independent of frequency may be a valid and helpful simplification, while the temperature dependence of CR initially could be accounted for by using a value at 10 K above ambient. Example 26.8: Capacitor power rating for non-sinusoidal voltages

The applied voltage across a 1 µF MKP capacitor, at 40°C ambient is √2 100 sin(2π × 104t) + √2 Y sin(2π× 3 x 104t) What is the maximum allowable voltage Y? Solution From equation (26.40), the total power is given by Pi = tan δ1 ω1CR v12 + tan δ 3 ω3CR v32 1

3

From figure 26.16b we may assume that capacitance is independent of frequency for polypropylene types. From figure 26.16a, at 50°C, rated capacitance has reduced by only 1 per cent - thus temperature effects on CR may be neglected. From figure 26.17, for a 600 V MKT capacitor tan δ1 at 10 kHz (ω1) = 2.5 × 10-4 tan δ3 at 30 kHz (ω3) = 4.2 × 10-4 From figure 26.20b it can be seen that 880 mW can be dissipated in the largest package at 50°C. Total power is given by 0.88W = 2.5 × 10-4 × 2π × 104 × 1× 10-6 × 1002

+ 4.2 × 10-4 × 6π × 104 × 1× 10-6 × Y 2

(W)

Solving for Y, Y = 30.2 V rms.

♣ The key properties of plastic type non-polarised capacitors are summarised in table 26.4. The excellent dielectric properties of the polypropylene lead to metallised polypropylene capacitors being extensively used in power applications. Table 26.4. Properties of non-polarised plastic type capacitors dielectric type polypropylene polyester polystyrene polycarbonate mixed dielectric paper

εr

tanδ

λo

dv/dt

self-healing

low medium

low high

good poor

high medium

good good

low low medium high

low medium medium high

good good good very good

high medium medium high

poor good good very good

Polycarbonate film based capacitors (KC and MKC) are obsolete. Mixed dielectric alternatives, based on polyethylene-terephthalate and polypropylene are recommended, but no alternative matches the excellent temperature and high frequency properties of polycarbonate. 26.4

Emi suppression capacitors

Non-polarised capacitors are used in rfi filters for electrical appliances and equipment, as was introduced in 10.2.4. The capacitors (7 classifications in all) used between line and neutral are termed class X while those used to earth are termed class Y. 26.4.1 Class X capacitors

X capacitors are suitable for use in situations where failure of the capacitor would not lead to danger of electric shock. X capacitors, for 250V ac application, are divided into two subclasses according to the ac power line voltage applied. • The X1 subclass must support a peak voltage in excess of 1.2 kV in service, while • X2 capacitors have peak service voltage capabilities of less than 1.2 kV. In order to obtain the peak voltage requirement of X1 capacitors, a construction comprising impregnated paper dielectric and metal foil electrodes is essential. The common X1 capacitance range is 10 nF to 0.2 µF. Class X1 is impulse tested to 4kV and 2.5kV for X2. Both are tested to higher voltages if C ≥ 1µF.

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The lower peak voltage requirement of X2 capacitors allows the use of a metallised plastic dielectric, of which polyester and polypropylene are common. Impregnated paper dielectrics may also be employed. Advantageously, metallised plastic film suppression capacitors yield high dv/dt capability with low associated losses, tan δ, as shown in figure 26.17a. These films also offer good insulation properties as shown in figure 26.15. Variation of capacitance with frequency and temperature is shown in figure 26.16, while percentage variation of losses, tan δ, with frequency and temperature is shown in figure 26.22. The typical capacitance range of X2 capacitors is from 10 nF to 1 µF, rated for 250 V ac application. 26.4.2 Class Y capacitors

Class Y capacitors are suitable for use in situations where failure of the capacitor could lead to danger of electric shock. These capacitors have high electrical and mechanical safety margins so as to increase reliability and prevent short circuit. They are limited in capacitance so as to restrict any ac current flowing through the capacitor, hence decreasing the stored energy to a non-dangerous level. An impregnated paper dielectric with metal foil electrodes is a common construction and values between 2.5 nF and 35 nF are extensively used. Capacitance as low as 0.5 nF is not uncommon. A Y-class capacitor for 250 V ac application can typically withstand over 2500 V dc for 2s, layer to layer. On an ac supply, 425 V ac (√3 VR) for 1000 hours is a common continuous ac voltage test. Class Y1 is impulse voltage tested to 8kV, and 5kV for Y2. If dv/dt capability is required, polypropylene film dielectric Y-class capacitors are available, but offer lower withstand voltage capability than paper types. Generally paper dielectric capacitors offer superior insulation resistance properties, as shown in figure 26.15a. Metallised paper capacitors are also preferred to metallised plastic types because they have better selfhealing characteristics. Breakdown in metallised plastic film dielectrics causes a reduction of the insulation resistance because of a higher carbon deposit in the breakdown channel than results with paper dielectrics.

Figure 26.22. RFI capacitance variation with: (a) ambient free-air temperature and (b) frequency.

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Figure 26.23. Feed-through capacitors for RFI attenuation: (a), (b) three user terminals; (c) four terminals; and (d) coaxial feed-through capacitor construction.

26.4.3 Feed-through capacitors

Feed-through or four-terminal capacitors are capacitors in which the operating current flows through or across the electrodes. High frequency rfi is attenuated by the capacitor and the main power is transmitted unaffected. That is they suppress emi penetration into or from shielded equipment via the signal or power path. Figures 26.23a and b show three terminal feed-through capacitors while figure 26.23c is a four-terminal capacitor. A three-terminal coaxial feed-through, wound capacitor cross-section is shown in figure 26.23d. The feed-through rod is the central current-carrying conductor: the outer case performs the function of an electrode plate and connector to produce an RF seal between the capacitor case and shielding wall. These capacitors are effective from audio frequencies up to and above the SW and VHF band (>300 MHz). Current ratings from signal levels to 1600 A dc, 1200 A ac are available, in classes X1 and X2, rated at 240 V ac, 440 V ac, and 600 V dc. Class Y feed-through capacitors rated at 25 A and 440 V ac, 600 V dc are available. Important note: This section on emi-suppression capacitors does not imply those requirements necessary to conform with governmental safety and design standards.

26.5

Ceramic dielectric capacitors

Ceramic capacitors as a group have in common an oxide ceramic dielectric. The dielectric is an inorganic, non-metal polycrystalline structure formed into a solid body by high temperature sintering at 1000 to 1300°C. The resultant crystals are usually between 1 and 100 µm in diameter. The basic oxide material for ceramic capacitors is titanium dioxide (Ti02) which has a relative permittivity of about 100. This oxide together with barium oxide (Ba02) forms barium titanate (BaTi03) which is a ferro-electric material with a high permittivity, typically 104. Alternatively strontium titanate may be utilised. These same materials are used to make positive temperature coefficient resistors - thermistors, where dopants are added to allow conduction. Metal plates of silver or nickel (with minimal palladium and platinum) are used to form the capacitor. Single plate, or a disc construction, is common as is a multi-layer monolithic type construction. The ceramic dielectric is split into two classes, as shown in table 26.5.

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Table 26.5. Ceramic dielectric capacitor characteristics

Dielectric class EIA-designation* IEC/CECC designation Temperature range Dielectric constant

see table 26.7 °C εr

Temperature coefficient of CR

(typical) Dissipation factor

tan δ

I

II

(εr < 500) Low K COG CG -55 to 125

(εr > 500) Moderately high K High K X7R Z5U 2C1 2F4 -55 to 125 + 10 to 85

13 - 470 (N150) -150 ± 60 ppm 0.15% @ 1 MHz

700 (X7R) ±15% 2.5% < 4.7

Capacitance

C

nF

< 0.2

Rated voltage

VR

V

500-1k

to

50,000 (Z5U) +22% / -56%

3% < 40 100 to >2k

* In EIA designation, first letter and number indicate temperature range while last letter indicates capacitance change.

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Figure 26.24. Typical properties of commercial ceramic capacitors: (a) capacitance change with temperature; (b) dissipation variation with temperature; (c) capacitance change with dc voltage; (d) ESR change with frequency; (e) capacitance change with ac voltage; (f) dissipation factor variation with ac voltage; (g) capacitance change with frequency; and (h) dissipation factor variation with frequency.

Table 26.6. Characteristics of class I and II type dielectrics Class I

Class II

Almost linear capacitance/temperature function

Non-linear capacitance/temperature function

No voltage dependency of capacitance and loss angle No ageing

Slight ageing of capacitance

High insulation resistance

High insulation resistance Extremely high capacitance value per unit volume

Very small dielectric loss High dielectric strength Normal capacitance tolerance ±1% to ±10%

Normal capacitance tolerance ±5% to -20+80%

Table 26.7 Class II ceramic capacitor parameter coding – EIA designation

Dielectric class II (and higher) capacitor ceramic code Letter code

lower temperature

Number code 2

Z

+65°C

-30°C 5

X

+45°C

+10°C

4

Y

upper temperature

-55°C

+85°C

6

+105°C

7 8 9

+125°C +150°C +200°C

A

∆C over temperature range, ∆T ±1.0%

B

±1.5%

C

±2.2%

D

±3.3%

E

±4.7%

F

±7.5%

P

±10.0%

R

+15.0%

S

±22.0%

T

+22% to -33%

U

+22% to -56%

V

+22% to -82%

Letter code

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948

26.5.1 Class I dielectrics

This class of dielectric consists mainly of Ti02 and additions of Ba0, La203 or Nd205, which provides a virtually linear, approximately constant and low temperature coefficient as shown in figure 26.24a. COG [EIA or industry code alternative NP0] capacitors belong to the class I dielectrics and have a low temperature coefficient over a wide temperature range, as seen in table 26.5. They provide stability and minimum dissipation properties. In attaining these properties, a low dielectric constant results and these capacitors are termed low K. Because of the low dielectric constant, capacitance is limited. 26.5.2 Class II dielectrics

Ceramic capacitors in this class are usually based on a high permittivity ferroelectric dielectric, BaTi03, hence termed hi K. Large capacitance in a small volume can be attained, but only by sacrificing the temperature, frequency, and voltage properties, all of which are non-linear. Typical characteristics are shown in figure 26.24. Their characteristics are less stable, non-linear, and have higher losses than class I ceramic, as seen in table 26.5. See table 26.6 for a comparison between types and table 26.7 for class II dielectric coding for capacitance variation for different temperature ranges, e.g. X7R, Z5U. 26.5.3 Applications

Flat circular disc ceramic (Z5U dielectric, high K) capacitors have a 2000 V dc, 550 V ac rating with capacitances of up to 47 nF. An exploitable drawback of such a ceramic capacitor is that its permittivity decreases with increased voltage. That is, the capacitance decreases with increased voltage as shown in figure 26.24c. Such a capacitor can be used in the turn-off snubber for the GTO thyristor and diodes which are considered in 8.1.3 and 8.1. High snubbering action is required at the commencement of turnoff, and can subsequently diminish without adversely affecting losses or the switching area trajectory tailoring. The capacitor action is a dual to that performed by a saturable reactor, as considered in 8.3.4. Exploitation of voltage dependence capacitance is generally outside the capacitor specification. Advantageously, the disc ceramic capacitor has low inductance, but the high dissipation factor may limit the frequency of operation. Multi-layer ceramic capacitors can be used in switched mode power supply input and output filters. Piezoelectric effects (change of physical size when an electric field is applied) can cause failure due capacitor cracking in traditional X7R class II ceramic capacitors.

26.6

Mica dielectric capacitors

The dielectric mica can be one of 28 mica types. It is a naturally occurring inorganic, chemical resistant, clear mineral aluminosilicate (usually India Ruby muscovite, H2KAl3 (SiO4)3) which has a plane of easy cleavage enabling large sheets of single crystal to be split into thin 20-100 µm plates, typically 50 µm. Ultra thin silver electrodes are screen printed on to both sides of the mica (and over the edge), as shown in figure 26.25b, which is then fired in an oxidisation atmosphere to obtain a permanent plated adhesive bond between the mica and silver. Variation of silver electrode thickness affects the dissipation factor, while the overlapped printed silver area and mica thickness control the capacitance. A number of different techniques (and combination of different techniques) are used to parallel connect (parallel stack) the silver coated mica plates in order to given high capacitances.

•

Multiple layers of over-the-edge printed mica plates are stacked together (without any interposing foils), as shown in figure 26.25a. The printed silver at each opposite edge is bonded with silver paste, on to which the terminals are directly soldered. • Multiple silver printed plates are stacked interleaved with metal outer foils for contacts, The foils are made of silver, copper, brass, tin or lead. The foil alternately extends from each end and covers a portion of the plated area. Joining the extended foils at each end, parallel connects each individual mica plate. The stack is held and compressed together either by the encapsulation or by bending the extended foils over the top of the stack which is held by a brass metal (tin coated) crimp, which also acts as a heat sink. Copper clad (for at least 30% conductivity) steel leads are spot-welded to each clip, which is then solder coated. The assembled unit is encapsulated by dipping it into high melting temperature microcrystalline wax or by dipping in phenolic resin, then vacuum impregnating with liquid epoxy resin. Mica capacitors are non-magnetic, non-polar, low loss, and stable up to about 30 MHz, where the lead length and electrodes dominate as inductance, typically 5 to 10nH. They are characterised by extremely low capacitor coefficients of temperature and voltage over a very wide parameter operating range. Mica has a typical impregnated relative permittivity of 4.5 to 6.5 and a density of 1.65 g/ cm3.

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Figure 26.25. Silver mica capacitor: (a) exploded construction view and (b) electrode pattern of a silvered mica plate.

26.6.1 Properties and applications

Maximum ratings are a few nanofarads at 50 kV, to 5µF at 1500V, with dissipation factors of 0.1 per cent at 1 kHz. Low dissipation factor is countered by poor dielectric absorption. A 10nF, 50kV mica capacitor in a cylindrical volume of Φ = 150mm×H = 120mm, has 800oC) operation performed on semiconductor wafer in an inert ambient; causes motion of dopant atoms in semiconductor in the direction of concentration gradient (diffusion); used to drive dopant atoms deeper into semiconductor. Electron beam (e-beam) evaporation:- source material is evaporated as a result of highly localized heating by bombardment with high energy electrons; the electron beam is spatially confined and accelerated by electrostatic interactions. The direction and cross-section of the beam can be precisely controlled and rapidly altered to scan the target; evaporated material is very pure; bombardment of metal with electrons is accompanied by generation of low intensity X-rays which may create defects in the oxide present on the surface of the substrate; typically, an anneal is needed to eliminate those defects.

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Epi Layer:- The term epitaxial comes from the Greek word meaning 'arranged upon.' In semiconductor technology, it refers to the single crystalline structure of the film. The structure comes about when silicon atoms are deposited on a bare silicon wafer in a CVD reactor. When the chemical reactants are controlled and the system parameters are set correctly, the depositing atoms arrive at the wafer surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the wafer atoms. Thus an epitaxial film deposited on a oriented wafer will take on a orientation. Epitaxial layer:- layer grown in the course of epitaxy. Epitaxy:- process by which a thin epitaxial layer of single-crystal material is deposited on single-crystal substrate; epitaxial growth occurs in such way that the crystallographic structure of the substrate is reproduced in the growing material; also crystalline defects of the substrate are reproduced in the growing material. Although crystallographic structure of the substrate is reproduced, doping levels and the conductivity type of a epitaxial layer is controlled independently of the substrate; e.g. the epitaxial layer can be made more pure chemically than the substrate. Etching:- The process of removing silicon dioxide layers, accomplished by "wet etching" with chemicals or by "dry etching" with ionized gases. Evaporation:- common method used to deposit thin film materials; material to be deposited is heated in vacuum (10-6 - 10-7 Torr range) until it melts and starts evaporating; this vapour condenses on a cooler substrate inside the evaporation chamber forming smooth and uniform thin films; not suitable for high melting point materials; PVD method of thin film formation. External, extrinsic gettering:- process in which gettering of contaminants and defects in a semiconductor wafer is accomplished by stressing its back surface (by inducing damage or depositing material featuring different than semiconductor thermal expansion coefficient) and then thermally treating the wafer; contaminants and/or defects are relocated toward back surface and away from the front surface where semiconductor devices can be formed. Fick's law:- describe diffusion in solids; 1st and 2nd Fick's law; 1st Fick's law describes motion by diffusion of an element in the solid in the direction of the concentration gradient; 2nd Fick's law determines changes of concentration gradient in the course of diffusion (function of time and diffusion coefficient). Filament evaporation:- thermal evaporation; source material is contacted to the filament (a refractory metal) and melted by high current flowing through the filament; alternatively, a "boat" which contains material to be evaporated may be made out of refractory metal; Float-zone Crystal Growth, FZ:- method used to form single crystal semiconductor substrates (alternative to CZ); polycrystalline material is converted into single-crystal by locally melting the plane where a single crystal seed is contacting the polycrystalline material; used to make very pure, high resistance Si wafers; does not allow as large wafers (< 200mm) as CZ does; radial distribution of dopant in FZ wafer is not as uniform as in CZ wafer. Gettering:- process which moves contaminants and/or defects in a semiconductor away from its top surface into its bulk and traps them there, creating a denuded zone. HMDS:- Hexamethyldisilizane; improves adhesion of photoresist to the surface of a wafer; especially designed for adhesion of photoresist to SiO2; deposited on wafer surface immediately prior to deposition of resist. hydrogenated a-Si:- amorphous silicon (a-Si) containing substantial quantities of hydrogen; hydrogen passivated Si dangling bonds and results in substantially improved electrical properties of A-Si Ingot:- circular piece of single-crystal semiconductor material resulting from a crystal growth process; an ingot is ready to be shaped and sliced into wafers used to manufacture semiconductor devices. Intrinsic gettering:- process in which gettering of contaminants and/or defects in a semiconductor is accomplished (without any physical interactions with the wafer) by a series of heat treatments. Ion implantation:- A doping process; the dopant material is ionized and magnetically accelerated to strike the wafer surface, thereby embedding the dopant into the substrate. Lapping:- The process of mechanically grinding the surface of a sliced wafer. Lead frame:- The die attachment surface and lead attachment points that a die or chip is attached to prior to wire bonding and packaging. limited-source diffusion:- also known as drive-in; concentration of diffusant (dopant) on the surface decreases during the diffusion process, i.e. while some dopant atoms diffuse into the substrate no new dopant atoms are supplied to the surface of the wafer. Metallization:- formation of metal contacts and interconnects in the manufacturing of semiconductor devices. metal-semiconductor contact:- key component of any semiconductor device; depending on materials involved in the contact its properties can differ drastically; ohmic contact (linear, symmetric current-voltage characteristic)in the case when work function of metal matches work function of semiconductor (no potential barrier at the interface); rectifying contact(non-linear, highly asymmetric, diode-like current-voltage characteristic) in the case when work function of metal differs from the work function of semiconductor (potential barrier at the interface)- commonly referred to as a Schottky diode.

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minority carriers:- one of two carrier types (electrons of holes)whose equilibrium concentration is lower than that of the other type; holes in n-type semiconductors, electrons in p-type semiconductors. N-type semiconductor:- semiconductor in which the concentration of electrons is much higher than the concentration of holes (p>>n); electrons are majority carriers and dominate conductivity. ohmic contact:- metal-semiconductor contact with very low resistance independent of applied voltage (may be represented by constant resistance); to form an "ohmic" contact metal and semiconductor must be selected such that there is no potential barrier formed at the interface (or potential barrier is so thin that charge carriers can readily tunnel through it). Oxidation:- The process of oxidizing the wafer surface to form a thin layer of silicon dioxide. Passivation:- The process of applying a final passivating or protective layer of either silicon nitride or silicon dioxide to a wafer. Photolithography:- The process of creating patterns on a silicon substrate. The main steps of the process include photoresist application, mask alignment, photoexposure, developing, and etching the portions of the substrate that are unprotected by the resist. Photomask:- A mask that delineates the pattern applied to a substrate during photolithography. Photoresist:- A photo-sensitive material used in photolithography to transfer pattern from the mask onto the wafer; a liquid deposited on the surface of the wafer as a thin film then solidified by low temperature anneal; in the areas in which photoresist can be reached by UV radiation photochemical reactions change its properties, specifically, solubility in the developer; two types of photoresist:- positive and negative. Polishing:- process applied to either reduce roughness of the wafer surface or to remove excess material from the surface; typically polishing is a mechanical-chemical process using a chemically reactive slurry. Polycrystalline silicon:- An amorphous form of silicon with randomly oriented crystals, used to produce silicon ingots. Polycrystalline material, poly:- many (often) small single-crystal regions are randomly connected to form a solid; size of regions varies depending on the material and the method of its formation. Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices. Physical Vapour Deposition, PVD:- deposition of thin film occurs through physical transfer of material (e.g. thermal evaporation and sputtering)from the source to the substrate; chemical composition of deposited material is not altered in the process. P-type semiconductor:- semiconductor in which the concentration of holes is much higher than the concentration of electrons (n>>p); holes are majority carriers and dominate conductivity. Quartz:- single-crystal SiO2. Quartzite:- Silica sand used as a raw material to produce metallurgical grade silicon. Reactive ion etching RIE:-., RIE variation of plasma etching that uses physical sputtering and chemically reactive species in which during etching semiconductor wafer is placed on the RF powered electrode; wafer takes on potential which accelerates etching species extracted from plasma toward the etched surface; chemical etching reaction is preferentially taking place in the direction normal to the surface, i.e. etching is more anisotropic than in plasma etching but is less selective; leaves etched surface damaged; the most common etching mode in semiconductor manufacturing, also usedto remove metal layers. rectifying contact:- metal-semiconductor contact displaying asymmetric current-voltage characteristics, i.e. allowing high current to flow across under the forward bias condition and blocking current off under the reverse bias; this behavior is controlled by the bias voltage dependent changes of the potential barrier height in the contact region. Seed crystal:- single crystal material used in crystal growing to set a pattern for the growth of material in which this pattern is reproduced. Semiconductor:- solid-state material in which (unlike in metals and insulators) (1) large changes in electrical conductivity can be effected by adding very small amounts of impurity elements known as dopants, (2) electrical conductivity can be controlled by both negatively charged electrons and positively charged holes and (3) electrical conductivity is sensitive to temperature, illumination, and magnetic field. Silicon:- A semi-metallic element used to create a wafer. Silicon dioxide, SiO2:- silica; native oxide of silicon; the most common insulator in semiconductor device technology; high quality films are obtained by thermal oxidation of silicon; thermal SiO2 forms smooth, low-defect interface with Si; can be also readily deposited by CVD; Key parameters: energy gap Eg ~ 8eV; dielectric strength 5-15 x 106 V/cm; dielectric constant k = 3.9; density 2.3 g/cm3; refractive index n =1.46; melting point ~ 1700°C; prone to contamination with alkali ions and sensitive to high energy radiation (i.e. X-rays); single crystal SiO2 is known as quartz. Silicon Nitride, Si3N4:- dielectric material with energy gap = 5 eV and density ~3.0 g/cm3; excellent mask against oxidation of Si and KOH; properties depend on deposition method: dielectric strength ~107 V/cm, dielectric constant k ~6-7, bulk resistivity 1015-1017 ohm-cm; deposited by CDV. Silyation:- The process of introducing silicon atoms into the surface of an organic photoresist in order to harden the photoresist.

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Single-crystal:- crystalline solid in which atoms are arranged following specific pattern throughout the entire piece of material; in general, single crystal material features superior electronic and photonic properties as compared to polycrystalline and amorphous materials, but is more difficult to fabricate; all high-end semiconductor electronic and photonic materials are fabricated using single-crystal substrates. Slice orientation: - the angle between the surface of a slice and the growth plane of the crystal. The most common slice orientations are (100), (111) and (110). Slicing:- term refers to the process of cutting of the single-crystal ingot into wafers; high precision diamond blades are used. Slurry:- a liquid containing suspended abrasive component; used for lapping, polishing and grinding of solid surfaces; can be chemically active; key element of CMP processes. Spiking:- uncontrolled penetration of semiconductor substrate by contact metal; problem with Al in contact with silicon; may short ultra-shallow p-n junction underneath the contact. Sputtering, sputter deposition:- bombardment of a solid (target) by high energy chemically inert ions (e.g. Ar+); causes ejection of atoms from the target which are then re-deposited on the surface of a substrate purposely located in the vicinity of the target; common method of Physical Vapour Deposition of metals and oxides. Sputtering target:- source material during sputter deposition processes; typically a disc inside the vacuum chamber which is exposed to bombarding ions, knocking source atoms loose and onto samples. Sputter yield:- efficiency of the sputtering process (differs for different materials). Surface damage:- process related disruption of the crystallographic order at the surface of single-crystal semiconductor substrates; typically caused by surface interactions with high energy ions during dry etching and ion implantation. Staebler - Wronski effect:- degradation of electrical output of hydrogenated amorphous silicon solar cells as a result of prolonged illumination. stripping:- process of material removal from the wafer surface; typically implies that removal is not carried out for the pattering purpose, e.g. resist stripping in which case entire resist is removed following lithography and etching. Target:- source material used during evaporation or deposition; In sputtering, typically in the form of high purity disc. In e-Beam evaporation, typically in the form of a crucible. In thermal evaporation, the source material is typically held in a boat which is heated resistively. Thermal oxidation, thermal oxide:- growth of oxide on the substrate through oxidation of the surface at elevated temperature; thermal oxidation of silicon results in a very high quality oxide, SiO2; most other semiconductors do not form device quality thermal oxide, hence, "thermal oxidation" is almost synonymous with "thermal oxidation of silicon". Valence band:- the lower energy band in a semiconductor that is completely filled with electrons at 0 K; electrons cannot conduct in valence band. Volume defect:- voids and/or local regions featuring different phase (e.g. precipitates or amorphous phase) in crystalline materials. Wafer:- thin (thickness depends on wafer diameter, but is typically less than 1 mm), circular slice of single-crystal semiconductor material cut from the ingot of single crystal semiconductor; used in manufacturing of semiconductor devices and integrated circuits; wafer diameter may range from 25 mm to 300 mm. Wafer bonding:- process in which two semiconductor wafers are bonded to form a single substrate; commonly applied to form SOI substrates; bonding of wafers of different materials, e.g. GaAs on Si, or SiC on Si; is more difficult than bonding of similar materials. Wafer fabrication:- process in which single crystal semiconductor ingot is fabricated and transformed by cutting, grinding, polishing, and cleaning into a circular wafer with desired diameter and physical properties. Wafer flat:- flat area on the perimeter of the wafer; location and number of wafer flats contains information on crystal orientation of the wafer and the dopant type (n-type or p-type). work function difference:- defines characteristics of contact between two materials featuring different work function; for conductor-semiconductor contact w.f.d. determines height of potential barrier in the contact plane, and hence, determines whether contact is ohmic or rectifying.

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Glossary of electrochemical battery terminology Ageing:- Permanent loss of capacity with frequent use or the passage of time due to unwanted irreversible chemical reactions in the cell. AGM (Absorbed Glass Mat) battery:- A lead acid battery using a glass mat to promote recombination of the gases produced by the charging process. Ampere (A):- A unit of electrical current or rate of flow of electrons. One volt across one ohm of resistance causes a current flow of one ampere. One ampere is equal to 6.235x1018 electrons per second passing a given point in a circuit. Ampere hours (Ah):- The unit of measure used for comparing the capacity or energy content of a batteries with the same output voltage. For automotive (Lead Acid) batteries the SAE defines the Amp-hour capacity as the current delivered for a period of 20 hours until the cell voltage drops to 1.75 V. Strictly - One Ampere hour is the charge transferred by one amp flowing for one hour. 1Ah = 3600 Coulombs. One C, 1C, means Ah current for 1 hour, ½C means current of half Ah for 2 hours, etc. Anode:- The electrode in an electrochemical cell where oxidation takes place, releasing electrons. During discharge the negative electrode of the cell is the anode. During charge the situation reverses and the positive electrode of the cell is the anode. Battery:- Two or more electrochemical cells enclosed in a container and electrically inter-connected in an appropriate series/parallel arrangement to provide the required operating voltage and current levels. Under common usage, the term battery also applies to a single cell if it constitutes the entire electrochemical storage system. Battery Life:- The period during which a cell or battery is capable of operating above a specified capacity or efficiency performance level. For example, with lead-acid batteries, end-of-life is generally taken as the point in time when a fully charged cell can deliver only 80% of its rated capacity. Beyond this state of aging, deterioration and loss of capacity begins to accelerate rapidly. Life may be measured in cycles and/or years, depending on the type of service for which the cell or battery is intended. Cathode:- The electrode in an electrochemical cell where reduction takes place, gaining electrons. During discharge the positive electrode of the cell is the cathode. During charge the situation reverses and the negative electrode of the cell is the cathode. Cell reversal:- A condition which may occur multi cell series chains in which an over discharge of the battery can cause one or more cells to become completely discharged. The subsequent volt drop across the discharged cell effectively reverses its normal polarity. Charge, state of:- The available or remaining capacity of a battery expressed as a percentage of the rated capacity. Cold Cranking Amps:-A performance rating for automobile starting batteries. It is defined as the current that the battery can deliver for 30 seconds and maintain a terminal voltage greater than or equal to 1.20 volts per cell, at -18°C, when the battery is new and fully charged. Starting batteries may also be rated for Cranking Amps, which is the same thing but at a temperature of 0°C. Coulombic Efficiency:- The ratio (expressed as a percentage) between the energy removed from a battery during discharge compared with the energy used during charging to restore the original capacity. Also called Charge Efficiency or Charge Acceptance. Deep cycle battery - A battery designed to be discharged to below 80% Depth of Discharge. Used in marine, traction and EV applications. Deep discharge - Discharge of at least 80% of the rated capacity of a battery. Dendritic growth:- The formation from small crystals in the electrolyte of tree like structures which degrade the performance of the cell. Depth of discharge DOD:- The ratio of the quantity of electricity or charge removed from a cell on discharge to its rated capacity. For example, the removal of 25 ampere-hours from a fully charged 100 ampere-hours rated cell results in a 25% depth of discharge.Under certain conditions, such as discharge rates lower than that used to rate the cell, depth of discharge can exceed 100%. Discharge Factor:- A number equivalent to the time in hours during which a battery is discharged at constant current usually expressed as a percentage of the total battery capacity, i.e., C/5 indicates a discharge factor of 5 hours. Related to discharge rate. Electrochemical Cell:- A device containing two conducting electrodes, one positive and the other negative, made of dissimilar materials (usually metals) that are immersed in a chemical solution (electrolyte) that transmits positive ions from the negative to the positive electrode and thus forms an electrical charge. One or more cells constitute a battery. Electrode potential:- The voltage developed by a single electrode, determined by its propensity to gain or lose electrons. Electrolyte:- A substance which dissociates into ions (charged particles) when in aqueous solution or molten form and is thus able to conduct electricity. It is the medium which transports the ions carrying the charge between the electrodes during the electrochemical reaction in a battery.

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Energy density:- The amount of energy stored in a battery. It is expressed as the amount of energy stored per unit volume or per unit weight (Wh/L or Wh/kg). Equalisation:- The process of bringing every cell in a battery chain to the same state of charge (SOC) Flooded Lead Acid cell:- In "flooded" batteries, the oxygen created at the positive electrode is released from the cell and vented into the atmosphere. Similarly, the hydrogen created at the negative electrode is also vented into the atmosphere. This can cause an explosive atmosphere in an unventilated battery room. Furthermore the venting of the gasses causes a net loss of water from the cell. This lost water needs to be periodically replaced. Flooded batteries must be vented to prevent excess pressure from the build up of these gasses. Sealed Lead Acid (SLA) Cells which overcome these problems. Fuel Cell:- An electrochemical generator in which the reactants are stored externally and may be supplied continuously to a cell. Gassing:- The generation of a gaseous product at one or both electrodes as a result of the electrochemical action. In Lead Acid batteries gassing produces hydrogen and oxygen. Gel cell:- A battery which uses gelled electrolyte, an aqueous electrolyte that has been fixed by the addition of a gelling agent. Half Cell Reaction:- The electrochemical reaction between the electrode and the electrolyte. Hydrometer:- A tool for testing the specific-gravity of a fluid, such as the electrolyte in a flooded battery. Typically a squeeze-bulb is used to suck up a sample of the fluid, and a float indicates the specific gravity. Immobilized Electrolyte:- A lead-acid batteries technique where the electrolyte (the acid) is held in place against the plates instead of being a free-flowing liquid. The two most common techniques are gel and glass mat. Intercalation:- This insertion of ions into the crystalline lattice of a host electrode without changing its crystal structure. Memory effect:- Reversible, progressive capacity loss in nickel based batteries found in NiCad and to a lesser extent in NiMH batteries. It is caused by a change in crystalline formation from the desirable small size to a large size which occurs when the cell is recharged before it is fully discharged. Nernst equation:- Used by cell designers to calculate the voltage of a chemical cell from the standard electrode potentials, the temperature and to the concentrations of the reactants and products. Peukert's equation:- A formula that shows how the available capacity of a lead-acid battery changes according to the rate of discharge. The capacity of a battery is expressed in Amp-Hours, but it turns out that the simple formula of current times hours does not accurately represent the situation. Peukert found that the equation: C = I n×t fits the observed behaviour of batteries. "C" is the theoretical capacity of the battery, I is the current, t is time, and n is the Peukert number, a constant for the given battery. The equation captures the fact that at higher currents, there is less available energy in the battery. Peukert number:- A value that indicates how well a lead-acid battery performs under heavy currents. The Peukert number is the exponent in Peukert's equation. A value close to 1 indicates that the battery performs well; the higher the number, the more capacity is lost when the battery is discharged at high currents. The Peukert number of a battery is determined empirically. Primary cell:- A cell that is non-rechargeable. Prismatic cell:- A slim rectangular sealed cell in a metal case. The positive and negative plates are stacked usually in a rectangular shape rather than rolled in a spiral as done in a cylindrical cell. Recombinant system:- Sealed secondary cells in which gaseous products of the electrochemical charging cycle are made to recombine to recover the active chemicals. A closed cycle system preventing loss of active chemicals. Used in NiCd and SLA batteries. Sealed cells:- A cell which remains closed and does not release gas or liquid when operated within the limits of charge and temperature specified by the manufacturer. An essential component in recombinant cells. SLA Battery:- Sealed Lead Acid battery. In sealed batteries the generated oxygen combines chemically with the lead and then the hydrogen at the negative electrode, and then again with reactive agents in the electrolyte, to recreate water. A recombinant system. The net result is no significant loss of water from the cell. Sulphation:- Growth of lead sulphate crystals in Lead-Acid batteries which inhibits current flow. Sulphation is caused by storage at low state of charge.

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Glossary of Fuel Cell Terminology Alkali:- A chemical base produces negative ions, the opposite of an acid. Certain types of alkalis (especially potassium hydroxide) are used as fuel cell electrolytes. Alkaline Fuel Cell (AFC):- A type of hydrogen/oxygen fuel cell in which the electrolyte is concentrated KOH (varies between 35 to 85 wt% depending on the intended operating temperature) and hydroxide ions(OH-) are transported from the cathode to the anode. Temperature of operation can vary from