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Abstract—The present state of research in the area of low-power design methodologies and mecha- nisms of power dissipation in digital circuits are considered.
c Allerton Press, Inc., 2009. ISSN 8756-6990, Optoelectronics, Instrumentation and Data Processing, 2009, Vol. 45, No. 6, pp. 576–583.  c T. Grzes, V. Salauyou, I. Bulatova, 2009, published in Avtometriya, 2009, Vol. 45, No. 6, pp. 105–114. Original Russian Text 

PHYSICAL AND ENGINEERING FUNDAMENTALS OF MICROELECTRONICS AND OPTOELECTRONICS

Power Estimation Methods in Digital Circuit Design T. Grzes, V. Salauyou, and I. Bulatova Bialystok Technical University, Wiejska, 45A, 15-351 Bialystok, Poland E-mail: [email protected] Received July 22, 2009

Abstract—The present state of research in the area of low-power design methodologies and mechanisms of power dissipation in digital circuits are considered. The choice of the corresponding model of power estimation is demonstrated to exert a significant effect on quality, cost, and performance of designed digital circuits. An analysis of various power estimation techniques at different levels of abstraction for sequential and combinational circuit design is presented. Special attention is paid to power dissipation analysis of programmable logic devices. DOI: 10.3103/S8756699009060132 Key words: low-power design, digital circuits, power estimation.

INTRODUCTION Power estimation in digital circuits is extremely important in low-power design and power-aware design. The choice of the model and modeling method substantially affects the design quality and time. Exact methods of power estimation in the general case are rather slow and, for this reason, are not used for power estimation in large and complicated digital circuits. At the same time, fast methods contain errors because of using various approximations and simplifications in both computations and models of the digital circuit. The objective of the present paper is to review various methods of power estimation in digital circuits, which were developed for the last several years. The classical methods of modeling digital circuits for the purpose of power estimation were described in [1, 2]. New methods employ achievements in various areas of informatics, for instance, Petri networks [3], Bayesian networks [4, 5], or fractals [6, 7]. Power estimation of digital circuits involves separation into different levels of abstraction, depending on the method of circuit presentation. Most often, this separation includes three levels: 1. Gate Level (GL), where the circuit is presented as connections between gates and triggers. This is the lower level at which the model is close to the real device, but power estimation is rather labor-consuming, especially for large and complicated circuits. 2. Register Transfer Level (RTL), where the circuit is presented as data transfer between the registers. This is the middle level that ensures a good compromise between the accuracy and complexity of computations. 3. Behavioral Level (BL), where the circuit is presented as a network of actions (algorithm) performed by the circuit or connections between functional units (e.g., counters or registers) without structural details of these units. At this level, the power is estimated by means of approximating the power calculated at the lower level for this type of the functional unit. In addition, the Transistor Level is sometimes distinguished [1], which serves to model the circuit behavior at the level of individual transistors. This level allows the most accurate power estimation, but it is not used in practice for various reasons. The choice of the level is determined, in particular, by the size of the modeled circuit (in the case of very large and complicated circuits, GL modeling can be too labor-consuming) or by the required accuracy of computations. RTL power estimation is most often based on GL results. 576

POWER ESTIMATION METHODS IN DIGITAL CIRCUIT DESIGN

VCC

577

VCC Rleakage

Cload

Control

Load Fig. 1.

Gupta and Najm [8] described the method for power estimation of combinational and sequential circuits, where the power released by the circuit is considered on the basis of statistical data on switching of circuit inputs and outputs. As a result, they obtained quadratic or cubic equations of four variables, which allow the power to be estimated. The model is constructed on the basis of the GL circuit characteristic. Eiermann and Stechele [9] described a method of RTL modeling of combinational and sequential macrocircuits based on bit and word level switching properties. Using this method, they obtained a large (up to 100 times) increase in computational speed, as compared with GL computations. Wright and Shanblatt [10] described BL power estimation using the Connective Binary Decision Diagrams (CBDD). GATE-LEVEL POWER ESTIMATION To perform computations, it is necessary to use certain simplifications in the gate model. The gate model shown in Fig. 1 is used most often. In CMOS circuits, the power is mainly released on output capacitances (Cload ) and also on resistors responsible for leakage (Rleakage ). In this model, the control device supplements the load (output) of the gate with the supply voltage VCC or mass, depending on the value that should be established at the output. Each change in the output state involves passage of the current associated with recharging (charging or discharging) of the load capacitance Cload , which leads to power release. In power estimation for CMOS devices, the following assumptions should be made [2]: — the power is consumed exclusively in capacitances at the element outputs; — the current flows either from VCC to the output capacitance or from the output capacitance to the mass; — the voltage at the output of the logic element (gate or trigger) can change only from VCC to zero or from zero to VCC . Thus, the power Pa consumed by the logic element a can be calculated by the equation 1 2 V f Na Ca , (1) 2 CC where VCC is the supply voltage, f is the maximum frequency of operation (maximum frequency at which the parameters of the input and output signals are calculated), Ca is the output capacitance of the element a, and Na is the switching activity (mean number of changes in the output state during one time cycle of the synchrosignal) of the element a. All parameters in the right side of Eq. (1), except for Na , are constant quantities depending on the technology of integral circuit fabrication. For this reason, the problem of power estimation can be reduced to the problem of calculating the switching activity. The gate, as any other physical element, is responsible for a certain delay of the signal. Two basic models of the gate are used in power estimation methods: with a constant delay and with a probabilistic delay [11]. The model of the gate with a constant delay is characterized by an identical delay of the signal at the gate output with respect to the input signal for each gate within the circuit. Two cases are considered: a gate with a zero delay and a gate with a unit delay. Pa =

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(a)

x1 x2

y

x1

x1

x2

x2

y

y

(b)

Fig. 2.

The model of the gate with a probabilistic delay is characterized by a randomly changing (within a certain interval) delay of the output signal for individual gates in the system. This model is more realistic. The use of the gate model with a constant delay leads to elimination of many effects associated with the signal delay inside the circuit, in addition, hazards and glitches. The fact is that the signal generated owing to the hazard or glitch increases the power consumed by the circuit [11, 12]. This signal can be transferred to the output; alternatively, it can decay inside the circuit [13]. The effect of the signal delay at the gate input on the form of the output signal is illustrated in Fig. 2. If there is a delay, the signals reaching the output do not appear simultaneously. A pulse leading to release of additional power appears in the output signal. Power estimation at the gate level allows the most accurate estimation of the amount of power scattered by the gate. In this case, the model of connections between the gates and triggers is used, which is based on an ideal circuit model and allows the power to be estimated at each point. The computations are rather complicated in this case, because it is necessary to consider the entire structure of the circuit. This level also allows obtaining intermediate results, which can be extrapolated to higher levels of computations (RTL and BL). Two approaches to solving the problem are distinguished: static and dynamic approaches. Static Methods of Power Estimation. The static methods of power estimation are based on statistical properties of the examined circuit. The switching activity is calculated on the basis of input signal parameters, such as the probability of appearance of unity on each input line, and also multipliers of correlation between the signals for each input line separately. Combinational Circuits. In these circuits, the power estimation is based on calculating the probability of changing of the state for outputs of all gates in the system. To perform computations, it is necessary to determine the probability of the fact that the function f takes the value equal to unity: f = yt−1 y¯t + y¯t−1 yt , where yt is the output state at the time t, yt−1 is the output state at the time t − 1; y¯t , y¯t−1 is the inversion of the output states at the times t and t − 1. When f acquires the value equal to unity, the value at the output y changes. Binary decision diagrams (BDDs) and their modifications are used for modeling combinational circuits. For instance, Nourani et al. [14] used an algorithm of calculating the switching activity of combinational circuits, which involves the reduced ordered binary decision diagrams (ROBDDs) and is well suited for implementation in the form of parallel computations. The Bayesian networks are used for modeling in [5]. The switching activity of the input signals is related in time with the previous value and also has a spatial relation with other units of the circuit. The use of the Bayesian network allows modeling all space and time dependences and relations in the combinational circuit, which reduces the estimation error. Unfortunately, the requirements that refer to the transformation time become more rigorous with increasing complexity of the circuit. Logic-induced directed acyclic graphs (LIDAGs) were used in [4]. It was also shown that they correspond to the Bayesian networks; for this reason, they can be used for modeling combinational circuits. For most circuits, power estimation takes a long time. One possible approach to time reduction is splitting. In this procedure, the large circuit is divided into smaller fragments, and computations are performed for each fragment separately. The method proposed in [15] retains the entire set of connections, which maintains the computation accuracy at a high level. OPTOELECTRONICS, INSTRUMENTATION AND DATA PROCESSING

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P(x1 =1) P(x2 =1) Probabilities of input signals

. . .

P(xM =1) P(S1 =1)

Combinational part of FSM

P(S2 =1)

Probabilities of FSM memory elements

. . P(SN =1) . Fig. 3.

Sequential Circuits. In this case, the modeling is performed with the use of discrete Markov chains {X t | t ∈ T } with a finite number of states A = a1 , . . . , aM under the condition that the time T is discrete [16]. Calculations of static probabilities involve the Kolmogorov equations. For each state ai of the finite state machine (FSM) (1 ≤ i ≤ M ), we can write the equalities P (ai ) =

M 

P (ak )P (Iki ),

(2)

k=1

where P (ai ) is the static probability of the state ai , P (ak ) is the static probability of the state ak , and P (Iki ) is the probability of appearance of the input vector Iki initiating the FSM transition from the state ak to the state ai [17]. In essence, equalities (2) form a system of equations. These equations are linearly dependent, and any of them can be derived from the remaining M − 1 equations. The sum of all probabilities is equal to unity if there are no correlations between the probabilities for individual input lines. Therefore, one equation can be replaced by the equality M 

P (ai ) = 1.

(3)

i=1

The choice of the equation to be replaced by equality (3) depends on the method used to calculate the system of equations and does not affect the computation results. The solution of the system of M equations (2) and (3) is the vector of static probabilities of the FSM states. In the case of large sequential circuits, the system of equations becomes extremely complicated, which substantially increases the time needed for power estimation. The probability of changing the state from ai to aj , under the condition that the FSM is in the state ai , depends on the probability of appearance of the initiating vector Iij at the input. For this reason, the probability of the FSM transition from the state ai to the state aj can be expressed by the equation P (ai → aj ) = P (ai )P (Iij ). Determining static probabilities makes it possible to estimate the power released by the FSM memory elements (or by triggers constituting the memory). Calculating the total power requires additional estimation of the power released on the combinational part of the FSM. The structural model of the FSM with estimation of the power of its combinational circuit is shown in Fig. 3. Input signals with probabilities P1 (x1 ), . . . , P1 (xM ) of taking the unity value are supplied to the inputs of the combinational circuit of the FSM. In addition, signals from the outputs of the memory elements with probabilities P1 (S1 ), . . . , P1 (SN ) of taking the unity value are supplied to the inputs of the combinational circuit from the outputs of the memory elements. On this basis, the switching activity is calculated, and then the power released by the combinational circuit of the FSM is found. In the publications mentioned above, the correlation between the signals supplied to the inputs and the signals inside the circuit was not considered. Freitas and Oliveira [16] solved the Kolmogorov equations and OPTOELECTRONICS, INSTRUMENTATION AND DATA PROCESSING

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took into account the correlation inherent in the circuit. Owing to this fact, more accurate power estimation can be ensured. Dynamic Methods of Power Estimation. The dynamic methods of power estimation are based on simulations. A generated input sequence is supplied to the circuit inputs. This sequence can be constructed on the basis of statistical parameters or correspond to the manner of circuit operation (e.g., a sequence of encoded bytes is supplied to the encoding circuit). Simulations are performed by two methods. In the first case, a generated complete input sequence is supplied to the circuit inputs. This approach requires a full cycle of computations. It is also possible to perform simulations for an incomplete input sequence interrupted during the computations, where the mean power changes only within a given interval (convergence occurs). Models. Murugavel and Ranganathan proposed a method for modeling combinational circuits [18] and a method for modeling sequential circuits with the use of hierarchical colored hardware Petri net (HCHPN) [3]. The modeling is performed under the assumption of one input sequence. This approach allows the power to be estimated for the most realistic operation mode, without considering other possibilities, which could lead to erroneous estimation and, in some cases, to exceeding the level of admissible power (which is little probable, but not impossible). Chandramouli and Srikantam [17] described a method of identification of operation modes and calculation for each mode. In most models, the power dependence is close to the Gaussian distribution, where only one maximum is found. In some cases, however, the diagram may contain several maximums. The algorithm described in [17] determines each operation mode. Methods of Forming the Input Sequence. Before modeling, it is necessary to generate the input sequence, which is formed on the basis of statistical data that describe the probability of appearance of input signals and the correlation between them. To minimize the modeling time, the generated sequence should be as short as possible; simultaneously, the sequence should not produce any adverse effect on the modeling results (should not lead to errors). Macii et al. [19] described one possible method for generation of the input sequence. They used the spectral analysis based on the discrete Fourier transform. The coefficients of the signal spectrum X(k) are calculated by the expression N −1 1  x(n) ej(2πkn/N ) , X (k) = N N =1

where x(n) is the input sequence and N is the number of measurements (length of the sequence) and the number of spectrum coefficients. A subset is chosen among the entire sequence of coefficients, which is further used to generate the final sequence with the use of the discrete Fourier transform. The values of the sequence x(n) are calculated as N −1  x (n) = X(k) ej(2πkn/N ) . k=0

This method was studied as applied to both combinational and sequential circuits. The error was within several percent, as compared with the sequence without compaction. The method of input sequence generation based on the Markov chains is described in [20]. The sequence is generated on the basis of statistical parameters, such as the mean input probability, mean density of transitions, and also spatial correlation of the inputs. The algorithm proposed allows fast generation of the input sequence. Methods of Reduction of the Input Sequence Length. The multiply generated or real sequence is very long, which increases the modeling time. There are certain methods that allow the input sequence length to be reduced without deteriorating its properties, but with a decrease in the modeling time. Hsu et al. [21] described a method of compaction based on grouping and consecutive sampling. In the course of grouping, pairs of input vectors having approximate values of the distance are identified in the sequence of groups, for instance, with the use of the charging/discharging capacitance (CDC). After that, the sampling operation is performed to eliminate repeated fragments. The method described in [22] involves the sensitivity to power of the basic inputs Sa(xi ) determined by the expression Sa(xi ) =

∂Power(xi ) δPower(xi ) = , δa(xi ) → 0 δa(xi ) ∂a(xi ) lim

where a(xi ) is the switching activity of the input xi . OPTOELECTRONICS, INSTRUMENTATION AND DATA PROCESSING

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Methods of compaction with the use of fractals were described in [6, 7]. A fractal is an infinitely selfsimilar geometric figure with each fragment of this figure being repeated as the scale is reduced. The input sequence can be composed from self-similar fragments; in this sense, it can be considered as a fractal. Kozhaya and Najm [23] described a method of power estimation where the input sequence is divided into smaller fragments (blocks). They are chosen randomly and are supplied to the inputs of the modeled circuit. Owing to this procedure, a certain range of power values is found, where the upper and lower boundaries differ by less than 10%. Thus, the modeling time can be substantially reduced by using a fragment of the input sequence instead of the entire sequence. Effect of Peaks and Leakages in the Models. Because of the influence of the delay induced by the gate, the signal curve has peaks. Jou et al. [13] proposed a new method using the Markov chains and also the Boolean associative memory (BAM). The circuit is analyzed separately for an ideal gate and existence of peaks. The method is particularly effective for large combinational circuits. Choi and Hwang [24] proposed a method where the notion of the switching density is used. The switching density of the block that has N independent inputs xi and M outputs yi can be determined by the expression N   dyj  D(xi ). P D(yj ) = dxi i=1

Each switching density is additionally indicated by a time indicator to express dependences associated with the signal delay. Leakage is another important factor affecting the power. Its value is 10–20% of the total power released in the circuit. Acar et al. [25] described a static method of estimating the power released on leakage resistances. POWER CONSUMED IN FPGA CIRCUITS The methodology of power estimation in programmable circuits depends to a large extent on the circuit structure and configuration. According to [26], the power P of the circuit can be expressed by the dependence P = Pint + PIO , where Pint is the static power without the load and PIO is the power released in the input–output buffers. The power PIO is equal to the sum of the static PDCout (when the output value is unchanged) and dynamic PACout powers. According to [27], the dynamic power in FPGA circuits can be calculated in a simplified form as the sum of the following powers (data for the XC3020 circuit of the Xilinx company, USA): — power released on capacitances connected to the output buffers of the inputs and outputs: 25 μV/pF/MHz; — power released on the lines of the global synchrosignal: 1.7 mV/MHz; — power released by the configurable logic block (CLB): 0.36 mV/MHz (with the mean frequency of the CLB output signals); — power released by the horizontal long line: 0.09 mV/MHz; — power released by the vertical long line: 0.08 mV/MHz; — power scattered on the inputs (without pull-up resistors): 0.075 mV/MHz. The power released by the circuit can be related to its temperature dependence [28] TJ = TA + ΘJA (PAC + Pleak ), where TJ is the junction temperature, TA is the ambient temperature, ΘJA is the thermal resistance of the casing, PAC is the dynamic power, and Pleak is the leakage power. The leakage power as a function of temperature is expressed by the formula [28] Pleak = P0 e−k/TJ , where P0 and k are constants depending on the circuit fabrication technology. OPTOELECTRONICS, INSTRUMENTATION AND DATA PROCESSING

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Methods of power estimation in digital circuits have been developed recently, and new methods have appeared. Many of these methods are based on theoretical models. The main goal of investigations up to now has been to ensure the maximum speed of computations with a given accuracy. The speed and accuracy of computations depend on the level of abstraction used for circuit modeling. Static methods ensure fast and accurate computations, but require the data to be prepared in the form of probabilistic characteristics. In the case of dynamic methods, the input sequence is supplied directly to the inputs of the modeled circuit. There are many methods of reducing the length of the input sequence by decreasing the redundancy, which allows the speed of computations to be increased. Further research should include verification of the validity of the known models and methods of power estimation of real circuits, in particular, programmable logic devices. REFERENCES 1. M. Pedram, “Power Simulation and Estimation in VLSI Circuits,” in The VLSI Handbook (The CRC Press–IEEE Press, Boca Raton, 1999), pp. 18–27. 2. C.-Y. Tsui, J. Monteiro, M. Pedram, et al., “Power Estimation Methods for Sequential Logic Circuits,” IEEE Trans. VLSI Syst. 3 (3), 404–416 (1995). 3. A. K. Murugavel and N. Ranganathan, “Power Estimation of Sequential Circuits Using Hierarchical Colored Hardware Petri Net Modeling,” in Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED’02) (Monterey, 2002), pp. 267–270. 4. S. Bhanja and N. Ranganathan, “Switching Activity Estimation of VLSI Circuits Using Bayesian Networks,” IEEE Trans. VLSI Systems 11 (4), 558–567 (2003). 5. S. S. Ramani and S. Bhanja, “Any-Time Probabilistic Switching Model Using Bayesian Networks,” in Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED’04) (Newport, 2004), pp. 86–89. 6. R. Radjassamy and J. D. Carothers, “Faster Power Estimation of CMOS Designs Using Vector Compaction—a Fractal Approach,” IEEE Trans. Syst. Man Cybern., B: Cybernetics 33 (3), 476–488 (2003). 7. R. Radjassamy and J. D. Carothers, “A Fractal Compaction Algorithm for Efficient Power Estimation,” in Proc. of the Int. Conf. on Computer Design: VLSI in Computers and Processors (ICCD’98) (Austen, 1998), pp. 542–547. 8. S. Gupta and F. N. Najm, “Analytical Models for RTL Power Estimation of Combinational and Sequential Circuits,” IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 19 (7), 808–814 (2000). 9. M. Eiermann and W. Stechele, “RTL Power Modeling and Estimation Based on Bit and Word Level Switching Properties,” in IEEE Int. Midwest Symp. on Circuits and Systems (Tulsa, USA, 2002), Vol. 1, pp. 144–147. 10. R. L. Wright and M. A. Shanblatt, “Improved Power Estimation for Behavioral and Gate Level Designs,” in Proc. of the IEEE Comput. Soc. Workshop on VLSI (Orlando, USA, 2001), pp. 102–107. 11. X. Liu and M. C. Papaefthymiou, “A Statistical Model of Input Glitch Propagation and Its Application in Power Macromodeling,” in Proc. of the 45th IEEE Int. Midwest Symp. on Circuits and Systems (Tulsa, USA, 2002), Vol. 1, pp. 380–383. 12. X. Liu and M. C. Papaefthymiou, “Incorporation of Input Glitches into Power Macromodeling,” in Proc. of the IEEE Int. Symp. on Circuits and Systems (ISCAS’02) (Scottsdale, USA, 2002), Vol. 4, pp. 846–849. 13. J. M. Jou, S.-C. Chen, and C.-L. Wang, “Fast Delay-Dependent Power Estimation of Large Combinational Circuits,” in Proc. of the IEEE Int. Symp. on Circuits and Systems (ISCAS’98) (Monterey, USA, 1998), Vol. 6, pp. 53–56. 14. N. Nourani, S. Nazarian, and A. Afzali-Kusha, “A Parallel Algorithm for Power Estimation at Gate Level,” in Proc. of the 45th IEEE Int. Midwest Symp. on Circuits and Systems (Tulsa, USA, 2002), Vol. 1, pp. 511–514. 15. A. T. Freitas and A. L. Oliveira, “Circuit Partitioning Techniques for Power Estimation Using the Full Set of Input Correlations,” in Proc. of the 8th IEEE Int. Conf. on Electronics, Circuits and Systems (Malta, 2001), Vol. 2, pp. 903–907. 16. A. T. Freitas and A. L. Oliveira, “Implicit Resolution of the Chapman–Kolmogorov Equations for Sequential Circuits: an Application in Power Estimation,” in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE) (Nice, France, 2003), Vol. 1, pp. 10764. 17. R. Chandramouli and V. K. Srikantam, “Multimode Power Modeling and Maximum-Likelihood Estimation,” IEEE Trans. VLSI Syst. 12 (1), 1244–1248 (2004). 18. A. K. Murugavel and N. Ranganathan, “A Real Delay Switching Activity Simulator Based on Petri Net Modeling,” in Proc. of the Int. Conf. on VLSI Design (Bangalore, India, 2001). OPTOELECTRONICS, INSTRUMENTATION AND DATA PROCESSING

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