Power Semiconductor Application Note AN_PSM2e

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865-871. [7] S. Musumeci, A. Raciti, M. Sardo, F. Frisina, R. Letor, “PT-IGBT PSPICE model with new parame- ter extraction for lifetime and epy dependent be-.
Power Semiconductor

Application Note AN_PSM2e

IEEE Industry Applications Society Annual Meeting New Orleans, Louisiana, October 5-9, 1997

Parameter Extraction Methodology and Validation for an Electro-Thermal Physics-Based NPT IGBT Model J. Sigg, P. Türkes, R. Kraus* Corporate Technology Siemens AG Otto-Hahn-Ring 6 D-81739 Munich, Germany Phone: (+49) 89 636-41367, Fax: (+49) 89 636-46376, E-Mail: [email protected], WWW:http://www.siemens.de/ * Institute of Electronics, University of Bundeswehr Munich, D-85577 Neubiberg, Germany

Abstract - A physics-based dynamic electro-thermal non-punch through (NPT) insulated gate bipolar transistor (IGBT) model is presented. For the electrical and thermal parameters an extraction methodology is given. The model reproduces the static, dynamic and short circuit characteristics of the IGBT. I. INTRODUCTION In the field of high power conversion there is a high demand for fast semiconductor switches. IGBTs (Insulated Gate Bipolar Transistor) are applied in inverters from the kW up to the MW range and increase their market share rapidly. This device overcomes the high on-state loss of the power MOSFET but maintains the simple gate drive requirements of that power switch. Therefore the IGBT replaces the power BJT (bipolar junction transistor) and the MOSFET from parts of their application areas. The current rating of a single IGBT chip ranges from 5 to 100A. By paralleling a number of chips current capabilities of 1800A for modules with a blocking voltage 1700V are achieved. The forward blocking voltage ranges from 600V up to 3.3kV. On the high power end at the moment IGBT modules are offered with a blocking voltage of 3.3kV and a current capability of 1.2kA [1,2] and even higher blocking voltages are discussed. With these switching power capabilities the IGBT enters the application range of the GTO (gate turn off thyristor), offering three major advantages compared to that device. (I) The gate drive of the IGBT is much simpler and cheaper than the one of the GTO. (II) In contrast to the GTO, the IGBT can be used without or with a very small

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snubber circuit. (A snubber is bulky, expensive and consumes energy.) (III) Also in contrast to the GTO, the IGBT can withstand a short circuit for a certain time and turn off the load current safely without damage or destruction of the switch. The availability of very high power IGBT modules offers the power converter designer new chances and challenges for many applications. Especially it enables the use of this device in traction applications [3] offering advantages in dimensions and weight of the converter at reduced costs. As it was stressed above the IGBT is applied without a snubber circuit consequently the total amount of dissipated power is generated within the power semiconductor devices (IGBT and free wheeling diode). Therefore the device has to dissipate a considerable amount of heat. The devices will fail if the dissipated power can not be removed effectively, independently of their electrical quality. The thermal aspect of inverter design is one of the most important ones as the heat removal may limit its useful power. This means that power electronic system design considerations contain at the same time all electrical aspects and the thermal management of the power dissipated in the power semiconductor devices. These two parts can not be separated as the chip temperature influences the electrical performance of the semiconductor devices by self-heating. The analysis of circuit efficiency and power losses enforces an electro-thermal simulation. Using CAD techniques the designers of power electronic circuits are not just interested in the reproduction of the principal features of power circuits. Rather, they

Power Semiconductor want to analyze critical switching conditions as short circuit, timing errors, or the influence of the parameter spread of different devices within the circuit on its performance. For this purpose physics-based dynamic electro-thermal models are mandatory which take into account self-heating correctly.

Application Note AN_PSM2e Gate E mitter (Cathode)

n+ p+

n-

Due to its importance many IGBT models have been developed. The usefulness of most models to simulate the behavior of these device is limited as they are not physics-based or the physical approach is not adequate to describe high power IGBTs [4-10]. In [11] and [12] a quasi-static charge description is used, only the current equation contains a non-quasi-static term. All of these models just deal with the electrical part of the power semiconductor device operation. There have been a lot of activities on the modeling of the electrical behavior of the IGBT, much less work deals with the feedback of the dissipated power within the chip on its electrical performance. In [13] and [14] the coupling is described of the electrical model given in [12] with a predefined set of packages and heat sink models. The approach in [15] describes the charge transport in the base region by ambipolar transport theory and a thermal network takes self-heating into account. The availability of an electro-thermal model is a very important step towards its goal to have a model available for the design of power circuits. For this achievement two further tasks have to be fulfilled: (I) The establishment of a parameter extraction scheme and the extraction of the electrical and thermal parameters and (II) the comprehensive model validation so that it can be used for all application conditions. This paper deals with all three aspects: In the next section the model will be explained. The parameter extraction methodology is subject of the third part. In the forth section the model validation is presented. A short summary closes the paper. II. IGBT MODEL

A. Electrical Part An IGBT chip consists of a parallel connection of many thousands elementary cells. Fig. 1 shows the schematic of such a cell for a n-channel type IGBT. Superimposed is the usually used equivalent circuit consisting of a MOSFET and a bipolar transistor in a Darlington configuration.

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p+

Collector (Anode)

Fig. 1. Elementary IGBT cell with its equivalent circuit. In the blocking state the voltage drops in the wide lowdoped IGBT base (n -region). If the gate potential is higher than the threshold voltage (VT) the MOSFET formed under the gate supplies majority carriers (electrons) through the channel into the wide lightly doped n -region. These electrons cross this region and cause injection of holes into the n -zone when reaching + the p -layer. The holes diffuse and drift through the lowdoped region in the reverse direction and are swept + into the p -body of the MOSFET. By injection from both + ends, electrons from the channel and holes from the p layer, the most part of the n - zone is in high injection (n≈p>>Nb) decreasing the on-state resistance significantly compared to a MOSFET. When the device is turned off by lowering the gate potential below VT most of the charge stored in the base must be extracted before the space charge layer around the p-body can widen into the base to take over the blocking voltage. This results in a turn off delay and switching losses. There are three methods to minimize the trade-off between on-state voltage and switching losses by optimizing the device characterisitics [16]. (i) Reduction of the charge carrier lifetime in the lowdoped base, (ii) inclusion of a high doped buffer layer between the pemitter and the n -region (punch through (PT) IGBT), (iii) reduction of the injection efficiency of the p-emitter base junction (NPT IGBT). In the third concept the charge carrier lifetime in the base is so high that recombination can be neglected. Therefore, the electron and hole current components are nearly constant in the base and the charge distribution in the modulated base is triangular in shape [17]. Due to the low emitter efficiency the hole current is smaller than the electron current. This concept guarantees at the same time rugged devices and low on-state

Power Semiconductor voltages [18]. For this type of IGBT the model presented in this paper was developed. In another way of regarding the IGBT operation the MOSFET supplies the base current for the pnp bipolar transistor (Fig. 1). The structure of this transistor with its wide lightly doped base does not resemble an existing power BJT nor a signal transistor. This transistor is in high level injection condition for the current density range of all applications. Moreover the BJT has a low gain (µpIn≈µnIp). To describe the low-gain high-level injection characteristics of the bipolar transistor (of the IGBT) ambipolar transport must be used to take the transport of electrons and holes properly into account [11]. The essential features of the BJT which must be described is the plasma dynamics within the n -zone and + the emitter efficiency of the p n -junction at the collector terminal. These two aspects can be separated as depicted in Fig. 2. A voltage dependent resistor parallel to a voltage dependent capacitance can describe the current transport in the n -region and a diode connected in + series models the emitter efficiency of the p n -junction. Ip

Application Note AN_PSM2e The effect of RS on the ID(UDS) characteristics has been accounted for by the last term in eq. 1 and 2. Additionally, internal gate (RG) and source (RS) resistances as well as a detailed description of the capacitances are added to an ideal MOSFET as depicted in Fig. 3. The drain source capacitance is given by

CDS =

ε 0 ε si ADS w depl

(3)

where ADS denotes the drain source overlap area and wdepl the depletion width, ε0 is the permittivity in vacuum and εsi is the dielectric constant of silicon. The gate drain or Miller capacitance consists of a series connection of the oxid capacitance (Cox) and the gate drain depletion capacitance CGDdepl which is given by

CGDdepl =

ε 0 ε si AGD wdepl

(4)

where AGD stands for the gate drain overlap area. CGD

Rb MOS F E T : Drain

Gate

Cdiff

Cjunc

CDS

RG

p+-n--junction Rb CGS

Emitter (Cathode)

In

Collector (Anode)

IT

Temperature dependent sub-units

Fig 2. Device model of the IGBT, reduced to its electrical behavior. The essential temperature dependent elements are indicated. The IGBT model consists of a MOSFET to control the input by a voltage source. The MOSFET part is described by the usual MOSFET equations (gate voltage (VGS) > MOSFET channel voltage (VT)) [19].

V 2  2 I D = k p  (VGS − VT )VDS − DS − (RS I D )    2

(1)

VDS ≤ VGS − VT kp

2 VGS − VT − RS I D ) ( 2

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MOS F E T : S ource IGBT : E mitter

Fig. 3. Details of the MOSFET part

Gate

ID =

RS

VDS > VGS − VT

(2)

As already discussed, the charge transport in the base requires a dynamic charge calculation to model the transient behavior correctly. The ambipolar diffusion equation describes the time-dependent distribution of the excess charge densities p(x,t),

∂p ∂2p p = Da 2 − ∂t ∂x τa

(5)

where Da denotes the ambipolar diffusion constant and τa the ambipolar lifetime. In the case of a very long carrier lifetime, the second term on the right side of equation (eq.) 5 describing recombination can be neglected. The simplified ambipolar diffusion equation is equivalent to the ‘heat transport’ equation and can be solved even for moving boundary conditions [20, 21].

Power Semiconductor p( x, t ) =

 x  p0 1  p  ( x − vt ) +  0   ( x + vt ) exp v  ⋅ wb 2  wb    Da 

 x + vt   x − vt   ⋅ erfc  + (vt − x )erfc   (6 )  2 Da t   2 Da t   In eq. 6 p0 is the carrier concentration at the pn-junction at the collector terminal of the IGBT, wb is the base width, and v denotes the rate at which the boundary of the space charge layer moves into the base (switch off) or collapses (switch on). The resulting equation for the charge carrier concentration contains dependencies on the velocity of the spreading in the space charge region, on the minority carrier concentration at the emitting junction, and therefore on the voltage across this junction and on the residual modulated base width. From the mean value of this charge distribution the conductivity of the modulated base can be calculated. The integral of the charge distribution determines the charge stored in the n -zone. Due to the low base doping, the condition for high level injection is fulfilled. This means that in a one-dimensional approximation the hole (Ip) and electron (In) current components can be expressed as a function of the total current (IT) instead of the unknown electric field,

µn dp IT + qADa µn + µ p dx µp dp Ip = IT − qADa µn + µ p dx In =

(7)

(8)

where q is the elementary charge and A denotes the active area of the IGBT. The derivation of eq. 6 at the boundary towards the space charge layer is used to calculate the diffusive part of the electron and hole current components of eq. 7 and 8. The diffusion capacitance in parallel to Rb of Fig. 3 accounts for the capacitance effects connected to the variation of the charge stored in the base region. The + emitter efficiency of the p -layer is adjusted in the model by the electron saturation current ISE of the ‘ideal’ diode between Rb and the collector terminal.

B. Temperature Dependent Parameter All of the electrical model parameters are more or less dependent on temperature. The physical parameters dominating the thermal behavior of IGBTs are: temperature dependence of mobility (µ), lifetime (τ) and of the intrinsic carrier concentration (ni).

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Application Note AN_PSM2e The influence of temperature manifests itself in a variation of the three voltage components contributing to the total collector-emitter voltage as indicated in Fig. 3. The voltage of the pn-junction at the collector terminal decreases with increasing temperature [22]. At the other end of the device the variation of the transconductance kp determines the voltage change across the MOSFET. This quantity can be expressed as:

k p = µ n,Channel

w C l ox

(9)

where w and l denote the channel width and length, respectively. The scattering of charge carriers by phonons is the mechanism that dominates the mobility variation as a function of temperature. A detailed analysis reveals [23]:

µn ∝ T

−

3 2

(10)

At a given current, the voltage variation follows from that of the mobility, i.e. an increase in temperature results in a higher potential drop across the MOSFET channnel. The resistance of the base layer depends on the mobilities of holes and electrons and on the charge carrier density. The mobility decreases with increasing temperature (eq. 10). The second quantity which influences Rb is ni [23]. The intrinsic carrier concentration ni is rising steeply as a function of temperature. The variation of the lifetime can be neglected for this IGBT type as τ is chosen as high as possible [17]. The effects of mobility reduction and ni increase counteract which results in a low variation of Rb with temperature. Adding up all three effects results in a positive temperature coefficient making this type very well suited for parallel connection. The small variation of the charge stored in the base region facilitates the control of the IGBT and leads to rugged devices [18].

C. Thermal Part The temperature variation as a function of time induced by power dissipation is determined by the heat capacity and the thermal conductivity of the thermal path from chip to heatsink (Fig. 4). The structural elements of the thermal path are condensed in an electrical analogue where the thermal resistance is shown as a resistor and the heat capacitance is shown as a capacitor. The upper part of Fig. 5 shows the equivalent thermal circuit. In this circuit the elements Raν and Caν represent

Power Semiconductor the thermal resistance and capacitance of the various layers of the chip, the substrate, the heatsink and the different intermediate layers of the package. For a particular package this data may be calculated from the physical and geometrical parameters of each layer. If the chip temperature variation is of interest only a transformed equivalent circuit can be used (lower part of Fig. 5) which is equivalent to the circuit shown above [24] and is suitable for the determination of the thermal parameters by measurements. Dissipated power Tchip

Power device

Application Note AN_PSM2e D. Combination of Electrical and Thermal Part The self-consistent combination of the electrical and the thermal part leads to an electro-thermal model of the IGBT. The procedure is illustrated in Fig. 6. The power dissipated at the moment into heat is the input to the thermal network. The resulting chip temperature is fed back to the electrical model changing the temperature dependent parameter correspondingly. The dissipated power calculated with the varied parameter is the modified input to the thermal path. The system is solved consistently by iteration. The model has been implemented in the simulator SABER. Tchip Dissipated power

Chip carrier Tcase Heatsink

Tamb

UCE

Fig. 4. Power device mounted on a heatsink.

IE

For the calculation of the chip (“virtual junction“) temperature as a function of power loss, the transient thermal impedance Zth of the whole set-up is required. The curve resulting from the measurement of Zth has to be approximated by an analytical function for the extraction of Rthν and Cthν. This approximation is performed by setting:

Rth (t ) =

  t  δT (t ) = ∑ Rthν 1 − exp −   P  tν    ν

power

Tchip Ca1

Ra1 Ca2

Tchip Rth1

Ra2 Ca3

Rth2

Ra3 Tcase Ra4 Ca4

Rth3

Ca5

Rth4

Chip temperature

Cth

Tamb

Fig. 6. Thermal feedback scheme of power device model. III. PARAMETER EXTRACTION METHODOLOGY

(11)

The resistances Rthν do not correspond with the resistances Raν nor do the capacitances Cthν=tν/Rthν correspond with the Caν. Instead eq. 11 or the lower part of Fig. 5 represents a transformed equivalent circuit which exhibits the same terminal properties as the physical equivalent circuit (Fig. 5 upper part).

Dissipated

Rth

Ra5 Tamb

Rth5 Tamb

The electro-thermal model contains a number of parameters which have to be specified for each device type. The model parameters must fulfill some conditions: (i) they have to be justifiable by physics, (ii) they must be extractable from measurements or from device geometry and (iii) they have to be unambiguous. The list of parameters can be divided into several classes; Table 1 shows a summary.

A. Electrical Model Parameters The geometry and design parameters are taken from information obtained from the device manufacturer or are determined from dedicated measurements.

Dissipated power Cth1

Cth2

Cth3

Cth4

Cth5

Fig. 5. Thermal model of the power semiconductor device; model corresponding to physics (top) and transformed model for the evaluation of thermal impedance measurements (bottom).

The base width can be determined by measuring the chip widths. The p-emitter and p-body width are extremely small for this IGBT type and can be neglected or taken into account by subtracting some µm from the chip width. The device active area is given by the chip area minus the area needed for the termination system. The gate-source capacity (CGS) is obtained by taking the mean value of CGS(UDS) curve. The gate-drain over-

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Power Semiconductor

Application Note AN_PSM2e

lap capacitance (Cox) is determined from the difference of the gate-source capacitance measured at zero gatesource voltage and a negative gate voltage, respectively: (12)

The gate drain overlap capacitance CGD is calculated from the series connection of Cox (eq. 12) and CGDdepl (eq. 4). In the limit of high drain-source voltage the approximation

wdepl =

2ε 0 ε si VDS max qN b

(13)

can be used to extract a numerical value for the product ADS⋅Nb from eq. 3 and for AGD⋅Nb from eq. 4, respectively. Table 1. IGBT Model Parameters Category Parameter Symbol Unit -3 Geometry Base doping concentr. Nb m and Base width wb m 2 Design Device active area A m 2 Parameter Body region area ADS m 2 Gate-drain overlap ar. AGD m MOS Gate-drain overlap cap. Cox F Capacitan. Gate-source capacita. CGS F 2 DC MOS Transconductance kp A/V Parameter Threshold voltage UT V Source Resistance RS Ω Internal gate resistance RG Ω Bipolar Ambipolar lifetime s τa Parameter Emitter elec. sat. cur. ISE A Thermal Thermal capacitance K/W Cthν Parameter Thermal resistance K/W Rthν The DC MOS parameters transconductance (kP), threshold voltage UT and the source resistance RS are taken from the IGBT transfer characteristics. Fig. 7 shows the measured transfer characteristics and the calculated curve from which kP, UT and RS are determined. The internal gate resistance is extracted from C-V measurements or taken from manufacturer data. The bipolar parameter, lifetime (τa) and emitter electron saturation current (ISE) are extracted from the tail current of transient measurements as outlined in [11]. Alternatively, ISE can also be determined from the output characteristics at high gate voltages.

10

8

6

4

2 7.0

8.0

9.0

10.0

11.0

UGE [V]

Fig. 7. Measured (squares) and calculated (line) transfer characteristics.

B. Thermal Model Parameters The electrical IGBT parameters can be extracted from measurements performed at a single chip. Thus the handling of the high current of modern high power modules in the laboratory can be circumvented. The electrical parameters of a module are obtained by scaling the device active area A with the number of chips connected in parallel within this module. This procedure can not be applied for specification of the thermal parameters (sec. IIc). The parameters Rthν and Cthν have to be extracted from the cooling curve of the actual IGBT module (Fig. 8) [21]. The forward biased pn-junction of the IGBT’s bipolar emitter is used as temperature sensor which has to be calibrated carefully before measuring the cooling curve. The extraction of the shortest thermal time constants require to keep the gap between the end of the heating and the beginning of the temperature measurement period as close as possible. 30

∆ T thermal equilibrium [K]

− Min(CGS (U DS , UGS = 0V ))

Measurement: Squares Calculation: Line

(IC)1/2 [A1/2]

Cox = Min(CGS (U DS , UGS < 0V )) −

12

25 20 15 10 5 0 1E-5

1E-3

1E-1

1E+1

1E+3

Time [s]

Fig 8. Thermal impedance measurement: Return to thermal equilibrium of an IGBT module with a

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Power Semiconductor water-cooled heat-sink (dissipated power: 294W).

Application Note AN_PSM2e °C 120

2.5

100

2.3

80

2.1

60

1.9

40

1.7

20

1.5

The IGBT model equipped with the parameters reproduces very well the current versus collector-emitter voltage characteristics (Fig. 9). The agreement between experimental data and simulation is very well except of the range of very high currents where, despite of pulsed measurement, self-heating occurs within the chip [19]. UGE=18V

Simulation

Measurement UGE=16V

IC [A]

80

A 400

Current

IV. MODEL VALIDATION

100

kV

60

UGE=14V

40

UCE=12V

20

300

Temperature (simulated)

200

Temperature slope: 10K/µs

100

Terminalvoltage 0 0

5

10

15

20

Time [µs]

Fig. 10. Comparison of measured (noisy signals) and simulated (smooth curves) short circuit behavior of an IGBT. The temperature rise as calculated with the model is also shown.

UGE=10V

V. SUMMARY

0 0

4

8

12

16

20

UCE [V]

Fig. 9. Measured and simulated static IGBT characteristics The model has been used to investigate the series connection of IGBTs [25]. The IGBT model in combination with a physics-based diode model [26] reproduces the experimental switching transients very well. An extreme test of the model developed is the reproduction of the short circuit behavior of the IGBT. Under this condition the current can rise to a level up to 10 times the current rating. A huge increase of power dissipated within the IGBT chip lasts for a time comparable to the thermal time constants of the mounted chips [27]. Only by a physics-based dynamic electro-thermal model the short circuit of an IGBT can be simulated. The experimental data and the simulation results of a shorted IGBT are shown in Fig 10. The reduction in current is clearly visible in this experiment as expected from theory. A new feature of the thermo-electrical model is the device temperature (also given in Fig. 10) which is automatically calculated by simulation.

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This paper outlines a physics-based dynamic electrothermal NPT IGBT model. For this model a parameter extraction methodology is presented. The electrical and thermal parameters are extracted from DC, AC and transient measurements. The model reproduces the static and the transient characteristics very well. It has also been tested for the extreme case of shorting the device. This situation inevitably requires to take selfheating of the device into account. The current and voltage characteristics obtained from simulation agree very well with experimental data demonstrating the efficiency of the model. REFERENCES [1] M. Hierholzer, R. Bayerer, A. Porst, H. Brunner, “Improved characteristics of 3.3kV IGBT modules“, 34th Intern. Power Conversion Conf. (PCIM’97), Nürnberg, Germany, June 10-12, 1997, pp. 201204. [2] H. Brunner, M. Bruckmann, M. Hierholzer, T. Laska, A. Porst, “Improved 3.3kV IGBT-diode chipset and 800A module“, 27th Annual IEEE Power Electronics Specialists Conf. (PESC’96), Baveno, Italy, June 23-27, 1996, vol. 2, pp. 17481753. [3] L. Fratelli, G. Giannini, “Dual-voltage high power converter for a distributed power system in heavy traction using high voltage IGBTs“, 27th Annual IEEE Power Electronics Specialists Conf.

Power Semiconductor (PESC’96), Baveno, Italy, June 23-27, 1996, vol. 2, pp. 1414-1419. [4] F.-F. Protiwa, O. Appeldoorn, N. Groos, “New IGBT model for PSPICE“, 3th European Conf. on Power Electronics and Applications (EPE’93), Brighton, GB, 13-16 Sept. 1993, pp. 226-231. [5] F. Mihalic, K. Jezernik, K. Krischan, M. Rentmeister, “IGBT SPICE model“, IEEE Trans. on Industrial Elect., vol. 42, no. 1, pp. 98-105, Feb. 1995. [6] J.T. Hsu, K.D.T. Ngo, “A behavioral model of the IGBT for circuit simulation“, 26th Annual IEEE Power Electronics Specialists Conf. (PESC’95), Atlanta, Georgia, USA, June 18-22, 1995, vol. 2, pp. 865-871. [7] S. Musumeci, A. Raciti, M. Sardo, F. Frisina, R. Letor, “PT-IGBT PSPICE model with new parameter extraction for lifetime and epy dependent behaviour simulation“ 27th Annual IEEE Power Electronics Specialists Conf. (PESC’96), Baveno, Italy, June 23-27, 1996, vol. 2, pp. 1682-1688. [8] B. Fatemizadeh, D. Silber, “A versatile model for IGBT including thermal effects“, 24th Annual IEEE Power Electronics Specialists Conf. (PESC’93), Seattle, USA, June 20-25, 1993, pp. 85-92. [9] H. Göbel, “A unified method for modeling semiconductor power devices“, IEEE Trans. on Power Electronics, vol. 9, no. 5, pp. 497-505, Sept. 1994. [10] D. Metznr, T. Vogler, d. Schröder, “A modular concept for the circuit simulation of bipolar semiconductors“, IEEE Trans. on Power Electronics, vol. 9, no. 5, pp. 506-513, Sept. 1994. [11] A.R. Hefner, D.L. Blackburn, “An analytical model for the steady-state and transient characteristics of power insulated-gate bipolar transistor“, Solid State Electronics, vol. 31, no. 10, pp. 1513-1532, 1988. [12] A.R. Hefner, “Modeling buffer layer IGBTs for circuit simulation“, IEEE Trans. on Power Electronics, vol. 10, no. 2, pp. 111-123, March 1995. [13] A.R. Hefner, “A dynamic electro-thermal model for the IGBT“, IEEE Trans. on Industry Applications, vol. 30, no. 2, pp. 394-405, March/April 1994. [14] H.A. Mantooth, A.R. Hefner, “Electrothermal Simulation of an IGBT PWM inverter“, IEEE Trans. on Power Electronics, vol. 12, no. 3, pp. 474-484, May 1997. [15] R. Kraus, K. Hoffmann, “An analytical model of IGBTs with low emitter efficiency“, 5th Intern. Symposium on Power Semiconductor Devices and Ics (ISPSD’93)“, Monterey, USA, May 18-20, 1993, pp. 30-34. [16] R. Kraus, K. Hoffmann, P. Türkes, “Analysis and modeling of technology-dependent electro-thermal

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Application Note AN_PSM2e IGBT characteristics“, Intern. Power Electronics Conf. (IPEC’95), Yokohama, Japan, pp. 11281133. [17] G. Miller, J. Sack, “A new concept for a non punch through IGBT with MOSFET like switching characteristics“, 20th Annual IEEE Power Electronics Specialists Conf. (PESC’89), Milwaukee, Wisconsin, USA, June 26-29, 1989, vol. 1, pp. 21-25. [18] T. Laska, A. Porst, H. Brunner, W. Kiffe, “A low loss/highly rugged IGBT-generation - based on a self aligned process with double implanted n/n+emitter“, 6th Internat. Symposium on Power Semiconductor Devices & IC’s (ISPSD’94), Davos, Switzerland, May 31 - June 2, 1994, pp. 171-175. [19] D.A. Grant, J. Gowar, Power MOSFETs, New York: Wiley,1989, ch. 3, p.91-95. [20] H.S. Carslaw, J.C. Jaeger, Conduction of heat in solids, Oxford University Press, ch. 15, pp. 387420. [21] P. Türkes, Kuhnert, ’’Compact models for the circuit simulation of power devices“, Internat. Conf. Power Semiconductor and their Application, Munich, Germany, Nov. 1993, pp. 17-25. [22] W. Shockley, “The theory of pn junctions in semiconductors and pn junction transistors“, Bell System Techn. Journal, vol. 28, 1948, pp. 435-457. [23] S. M. Sze, Physics of Semiconductor Devices, J. Wiley , New York 1981, ch. 1, pp. 22-28. [24] A. Hoffmann, K. Stocker, Thyristor Handbuch, SIEMENS AG, Berlin and Munich 1976, ch. 12, pp. 84-114 (in German). [25] J. Sigg, P. Türkes, M. Bruckmann, “The series connection of IGBTs investigated by experiment and simulation“, 27th Annual IEEE Power Electronics Specialists Conf. (PESC’96), Baveno, Italy, June 23-27, 1996, vol. 2, pp. 1760-1765. [26] R. Kraus, K. Hoffmann, H.J. Mattausch, “A precise model for the transient characteristics of power diodes“, 23rd Annual IEEE Power Electronics Specialists Conf. (PESC’92), Toledo, Spain, June 29July 3, 1992, pp. 863-869. [27] P. Türkes, W. Kiffe, R. Kuhnert, ’’Critical switching condition of a non-punch-through IGBT investigated by electrothermal circuit simulation’’, 6th Internat. Symposium on Power Semiconductor Devices & IC’s, Davos, Switzerland, May 31 - June 2, 1994, pp. 51-55.