Radiation Dose Effects in Trigate SOI MOS Transistors - IEEE Xplore

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Abstract—N-channel trigate SOI MOSFETs have been irra- diated with60Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is ...

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006

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Radiation Dose Effects in Trigate SOI MOS Transistors J. P. Colinge, Fellow, IEEE, A. Orozco, Student Member, IEEE, J. Rudee, Weize Xiong, Senior Member, IEEE, C. Rinn Cleavelin, T. Schulz, K. Schrüfer, Member, IEEE, G. Knoblinger, Member, IEEE, and P. Patruno

Abstract—N-channel trigate SOI MOSFETs have been irradiated with60 Co gamma rays at doses up to 6 Mrad(SiO2 ). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 m. At 6 Mrad(SiO2 ), the current drive reduction in the same devices is 10% if VG = 0 V during irradiation and 20% if VG = 1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [ 1 Mrad(SiO2 )]. At higher doses, the usual mobility degradation caused by interface trap generation is observed.

MOSFETs show that the threshold voltage shift induced by the creation of positives charges in the BOX increases with the width of the device fins [3], [4]. If the fin is very wide the device basically operates like a “regular”, single-gate fully depleted SOI device. If the device is very narrow, the virtual back-gate effect shields the bottom of the silicon fins from the electric field created by the charges in the BOX. This virtual back-gate effect is similar to that occurring in Pi-gate SOI MOSFETs [5]. As a result, narrow devices behave like Gate-All-Around MOSFETs in which the charges in the BOX have no influence on the device characteristics.

Index Terms—MOSFETs, semiconductor device radiation effects, silicon on insulator technology.

II. DEVICE FABRICATION

I. INTRODUCTION

T

HE effects of a radiative environment on SOI devices have been studied extensively. It is possible to harden partially depleted SOI transistors such that they can withstand high doses of gamma or x-rays. Dose hardening of fully depleted SOI devices is much more elusive because of the coupling between front and back gate and the impossibility of realizing a highthreshold back interface. However, excellent total-dose hardness has been demonstrated in fully depleted Gate-All-Around (GAA) transistors because the active silicon in the channel is in contact with only gate oxide, and not with a buried oxide or a field oxide [1]. More recently, the simulated radiation response of trigate SOI MOSFETs has been reported. These devices behave like GAA transistors with a small-footprint contact between the active silicon and the buried oxide (BOX). In an n-channel device the generation of positive oxide charges in the BOX can induce the formation of a channel at the back of the device [2]. Irradiation experiments carried out on omega-gate Manuscript received July 8, 2006; revised August 21, 2006. J. P. Colinge, A. Orozco, and J. Rudee are with the Department of Electrical and Computer Engineering, University of California, Davis, Davis, CA 95616 USA (e-mail: [email protected]; [email protected]; [email protected]). W. Xiong and C. Rinn Cleavelin are with Texas Instruments Incorporated, SiTD, Dallas, TX 75243 USA (e-mail: [email protected]; [email protected]). T. Schulz and K. Schrüfer are with Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany (e-mail: [email protected]; Klaus. [email protected]). G. Knoblinger is with Infineon Technologies, Austria AG, Siemensstraße 2, Villach, Austria (e-mail: [email protected]). P. Patruno is with SOITEC S.A., Parc Technologique des Fontaines, 38190 Bernin, France (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2006.885841

Standard UNIBOND™ SOI wafers were used as starting material. The BOX thickness is 200 nm. The silicon film was doped using boron, resulting in channel doping concentration of cm . Lithography and RIE are used to etch the silicon film and define 50 nm-wide silicon fins. The devices underwent a hydrogen annealing step to smooth the silicon surfaces, round fin corners and to thin the fins [6]. The radius of curvature at the top and bottom of the fins was measured in TEM cross sections and is 5 nm and 2 nm, respectively. The final fin width and height obtained by this process is 45 nm and 82 nm, respectively. A 2 nm gate oxide was then grown by wet oxidation in an AMAT ISSG reactor. Polysilicon was then deposited and doped N-type by phosphorus ion implantation. Arsenic was implanted to form sources and drains and titanium silicide was formed on sources and drains to reduce parasitic resistance. Classical aluminum/silicon metallization was used to complete the process. The minimum printed gate length of the devices used in this study is 150 nm and each device consists of 10 fins operating in parallel. A cross section TEM view of a fin is shown in Fig. 1. III. IRRADIATION RESULTS The N-channel trigate SOI MOSFETs were exposed to gamma rays using the Co irradiator of the Defense Microelectronics Activity (DMEA) in Sacramento, California. Ten devices were irradiated in two irradiation experiments, one up to 1 Mrad(SiO ) and one up to 6 Mrad (SiO ). A constant dose rate of 100 rad(SiO )/sec was used for all irradiations. Because of the very thin gate oxide (2nm) these devices are , of 1 Volt. intended to operate with a supply voltage, Maximum degradation is expected to occur if during irradiation, all other terminals being grounded. Thus, irradiation was performed with either all terminals grounded or with a 1 V bias applied to the gate. All electrical measurements

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Fig. 1(A). TEM cross section of a trigate SOI MOSFET. The fin width is 45 nm and the fin height is 82 nm. Gate oxide thickness is 2 nm.

Fig. 1(B). Schematic cross section showing the crystal orientation of the different Si/SiO interfaces.

were performed less than one hour after each irradiation period using an HP4155B Semiconductor Parameter Analyzer. The irradiation doses used in this experiment are 30 k, 100 k, 300 k, 1 M and 6 Mrad(SiO ). The subthreshold characteristics of devices with different gate lengths and irradiated with different doses are shown in Fig. 2. A first inspection of the curves shows that there is no substantial threshold voltage, current drive loss or subthreshold slope degradation for any of the irradiation conditions. A closer examination shows that the threshold voltage varies less than 10 mV in the entire 0–6 Mrad(SiO ) dose range [Fig. 3(A)]. Threshold voltage was measured using the maxtechnique [7]. The application of a positive imum gate bias during irradiation slightly increases the threshold voltage because it helps push the positive charges created in the gate oxide during irradiation towards the Si-SiO interface [Fig. 3(A)]. The subthreshold slope, , is close to an ideal 60 mV/decade in the 0.3 m devices and varies very little with dose [Fig. 3(B)]. The initial value of in the 0.15 m device is slightly higher due to short-channel effects, but its increase with dose is also relatively small [a 3% increase at 1 Mrad(SiO )]. The output characteristics of the transistors V during irradiation the are shown in Fig. 4. When current drive is reduced by approximately 5% and 10% at 1

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006

Fig. 2(A). I (V ) characteristics of an n-channel devices with L = 0:15 m and V = 0 V during irradiation.

Fig. 2(B). I (V ) characteristics of an n-channel devices with L = 0:3 m and V = 0 V during irradiation.

Fig. 2(C). I (V ) characteristics of an n-channel devices with L = 0:3 m and V = 1 V during irradiation.

Mrad(SiO ) and 6 Mrad(SiO ), respectively. It is reduced by V during the irradiation. 20% at 6 Mrad(SiO ) when Fig. 5 shows the evolution of the peak transconductance, , . with dose for different values of the back-gate voltage, An unexpected phenomenon seems present in all devices. The curves show an increase of transconductance with dose (around

COLINGE et al.: RADIATION DOSE EFFECTS IN TRIGATE SOI MOS TRANSISTORS

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Fig. 3(A). Evolution of threshold voltage with dose for different devices and bias conditions during irradiation. The back-gate voltage, V , is equal to 0V during the measurements.

Fig. 4(B). I (V ) characteristics of an n-channel device with L = 0:3 m and V = 0 V during irradiation. V = 0 V.

Fig. 3(B). Evolution of subthreshold slope with dose for different devices and bias conditions during irradiation. The back-gate voltage, V , is equal to 0 V during the measurements.

Fig. 4(C) I (V ) characteristics of an n-channel device with L = 0:3 m and V = 1 V during irradiation. V = 0 V.

mobility. As expected, the degradation is more severe when a positive gate voltage is applied during irradiation. This increase of transconductance is very small and insignificant for any practical application, but it is a rare instance where irradiation actually improves device characteristics, albeit only slightly. It is worth noting that the transconductance increase is least noticeV, i.e., when an inversion layer is already able when present at the back interface before irradiation. IV. DISCUSSION

Fig. 4(A). I (V ) characteristics of an n-channel device with L = 0:15 m and V = 0 V during irradiation. V = 0 V.

30 krad(SiO ) to 300 krad(SiO ), depending on the sample). at higher This increase is then followed by a decrease of doses, due to the creation of interface traps that reduce surface

The initial increase of transconductance with dose can be explained as follows. In pre-rad devices, inversion channels form along the top and sidewall interfaces of the fins. The top interface has a high-mobility (100) crystal orientation and the sidewalls have a low-mobility (110) interface Fig. 1) [8]. Approximately 20% of the current flows along the top interface and 80% along the sidewalls, which yields the relatively low overall effective mobility of 150 cm /Vs [9]. Fig. 6(A) shows a 2D simulation of the electron concentration profile in the device at threshold. Aside from presence of concentration peaks at the corners one can see the formation of

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006

Fig. 6(A). Simulated electron concentration profile in a 2D cross section perpendicular to the current flow. The oxide charge density (N = 10 cm ) corresponds to the pre-rad case. V = 0 V. Fig. 5(A). Peak transconductance as a function of irradiation dose and for different values of back-gate voltage for a device with L = 0:15 m and V = 0 V during irradiation.

Fig. 6(B). Simulated electron concentration profile in a 2D cross section perpendicular to the current flow. The oxide charge density (N = 2 10 cm ) corresponds to an irradiated device. V = 0 V.

2

Fig. 5(B). Peak transconductance as a function of irradiation dose and for different values of back-gate voltage for a device with L = 0:3 m and V = 0 V during irradiation.

charges by irradiation. Fig. 6(B) shows the same simulation with C/cm a uniform positive oxide charge density of in the BOX and in the gate oxide. This corresponds to an area cm in the BOX and oxide charge density of cm in the gate oxide. This time, a channel is formed at the bottom interface as well, and approximately 35% of the current flows along the top and bottom (100) interfaces, while only 65% of the current flows along the low-mobility (110) sidewalls. As a result, a higher effective mobility is measured, which increases the transconductance. However, at high doses the overall mobility degradation takes place at all interfaces, and the transconductance decreases. V. CONCLUSION

Fig. 5(C). Peak transconductance as a function of irradiation dose and for different values of back-gate voltage for a device with L = 0:3 m and V = 1 V during irradiation.

channels at the top interface and sidewalls, but not at the bottom interface. The picture is quite different after the creation of oxide

N-channel trigate SOI MOSFETs have been irradiated with Co gamma rays at doses up to 6 Mrad(SiO ). The threshold voltage shift at 6 Mrad is less than 10 mV in 0.3 m transistors. At 6 Mrad(SiO ), the current drive reduction in the same devices is 10% if V during irradiation and 20% V during the irradiation. The generation of positive if charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons

COLINGE et al.: RADIATION DOSE EFFECTS IN TRIGATE SOI MOS TRANSISTORS

at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [ Mrad(SiO )]. At higher doses, the usual mobility degradation caused by interface trap generation is observed. REFERENCES [1] J. P. Colinge, “Gate-All-Around technology for harsh environment applications,” in Proc. NATO Advanced Research Workshop, Kyiv, Ukraine, Oct. 15–20, 2002. [2] J. P. Colinge, “SOI for hostile environment applications,” in Proc. IEEE Int. SOI Conf., Oct. 2004, pp. 1–4. [3] M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, S. Cristoloveanu, O. Faynot, and C. Jahan, “Intrinsic tolerance of FETs to total ionizing dose,” in Proc. EUROSOI, Grenoble, France, Mar. 2006, pp. 129–130. [4] M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, O. Faynot, C. Jahanand, and S. Cristoloveanu, “Total ionizing dose effects on triple-gate FETs,” IEEE Trans. Nucl. Sci., vol. 53, Dec. 2006.

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[5] J. T. Park, J. P. Colinge, and C. H. Diaz, “Pi-gate SOI MOSFET,” IEEE Electron Device Lett., vol. 22-8, pp. 405–406, Aug. 2001. [6] W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith, D. Lewis, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, T. J. King, and J. P. Colinge, “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron Devices Lett., vol. 25, no. 8, pp. 541–543, 2004. [7] P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, “Modeling of ultrathin double-gate nMOS SOI transistors,” Solid State Electron., vol. 41, no. 5, pp. 715–720, May 1994. [8] F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B. Y. Nguyen, “Coupling effects and channels separation in FinFETs,” Solid State Electron., vol. 48, no. 4, pp. 535–542, Apr. 2004. [9] J. P. Colinge, L. Floyd, A. J. Quinn, G. R. G, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, “Temperature effects on trigate SOI MOSFETs,” IEEE Electron Device Lett., vol. 27, no. 3, pp. 172–174, Mar. 2006.

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