RESURF power semiconductor devices[]

RESURF power semiconductor devices Performance and operating limits

Alessandro Ferrara

Members of the dissertation committee: prof. dr. prof. dr. prof. dr. prof. dr. prof. dr. prof. dr. dr. ir. prof. dr.

P. M. G. Apers J. Schmitz L. K. Nanver E. van Tuijl P. G. Steeneken G. Groeseneken R. J. E. Hueting F. Udrea

University of Twente (chairman and secretary) University of Twente (promotor) University of Twente University of Twente TU Delft/NXP Semiconductors KU Leuven/IMEC University of Twente (assistant promotor) University of Cambridge, UK

This work is part of the Dutch Point-One program and is supported financially by Agentschap NL, an agency of the Dutch Ministry of Economic Affairs.

MESA+ Institute for Nanotechnology, University of Twente P.O.Box 217, 7500 AE Enschede, the Netherlands

c 2015 by Alessandro Ferrara, Enschede, The Netherlands. Copyright This work is licensed under the Creative Commons Attribution-NonCommercial 3.0 Netherlands License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc/3.0/nl/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California 94105, USA. Typeset with LATEX. Printed by Gildeprint, Enschede, The Netherlands (www.gildeprint.nl). Cover designed by Nunzio Postiglione, Four Colors Process S.A.S., Casoria (NA), Italy (www.graficapostiglione.it).

ISBN DOI

978-90-365-4032-2 10.3990/1.9789036540322 http://dx.doi.org/10.3990/1.9789036540322

RESURF POWER SEMICONDUCTOR DEVICES

P ERFORMANCE AND OPERATING LIMITS

P ROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. H. Brinksma, volgens besluit van het College voor Promoties in het openbaar te verdedigen op woensdag 13 januari 2016 om 12.45 uur

door Alessandro Ferrara

geboren op 2 september 1988 te Napels, Italie

Dit proefschrift is goedgekeurd door:

prof. dr. dr. ir.

J. Schmitz (promotor) R.J.E. Hueting (assistant promotor)

To my Parents

If you want to find the secrets of the universe, think in terms of energy, frequency and vibration. (N. Tesla)

A BSTRACT Power transmission is the transfer of energy from a generating source to a load which uses the energy to perform useful work. Since the end of the 19th century, electrical power transmission has replaced mechanical power transmission in all long distance applications. The alternating current (AC) generator invented by Nikola Tesla allows to efficiently convert mechanical energy into electrical energy and is still used nowadays to power cities all over the word. The transmitted electrical energy often needs to be manipulated before it can be used by the load. For example, the electrical signal has to be amplified (or attenuated) and/or converted into a different waveform. These operations are performed by power electronic circuits acting as an interface between the source and the load. The rapid growth of the semiconductor industry started in the second half of the 20th century has allowed the large scale manufacturing of the semiconductor devices used in modern electronics. As this industry has become more and more mature, it has allowed the system integration of operations of different nature, such as analog/digital processing and electrical power manipulation. This integration is usually referred to as smart power technology. Since the 1990’s, smart power electronic systems have extensively been used in the automotive and lighting industry. In the next future, with the advent of the internet of things (IoT), smart power systems will become more complex and allow the wireless transmission of information between smart objects. This thesis aims at investigating theoretical and experimental methods for the analysis and the performance optimization of the power semiconductor devices used in smart electronic systems. The results are complimentary to those documented in the doctorate thesis of B. K. Boksteen1 . In the following, a chapter-by-chapter content overview is provided.

Overview Chapter 1 provides a brief introduction to power semiconductor devices, constituting the principal component in a power electronic circuit: the switch. A classification of the existing power devices is provided together 1 B. K. Boksteen, Field-plate assisted RESURF power devices: Gradient based optimization, degradation and analysis. PhD thesis, University of Twente, 2015.

vii

viii ABSTRACT

with an overview of their operation physics. The discussion allows to introduce the trade-offs emerging in the design of an optimized power device. The main focus of this thesis is highlighted with respect to existing work in the field and a brief outline of the following chapters is provided. Chapter 2 provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with low (ideally zero) slope. Chapter 3 focuses on the trade-off between the specific on-resistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. It is shown that a switchable field plate electrode acting on the drift extension can be used to further reduce the on-resistance without affecting the Ex -field distribution in the off-state. The device based on this principle, named the boost transistor, is discussed. In Chapter 4, three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for evaluating the junction temperature of power transistors are discussed and experimentally compared. The device under test is provided with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. In Chapter 5 a general procedure for experimentally determining the safe operating limits of power transistors is presented. It is proposed to extend the safe operating area to a volume by adding a junction temperature axis, and normalizing the drain current to the gate width. The resulting three-dimensional space comprising the safe operating points is defined as safe operating volume (SOV). In Chapter 6, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal-oxide-semiconductor (MOS) transistors. The model leads to a theoretical definition of the SOV, proposed in Chapter 5. In Chapter 7 the main results of this thesis are summarized and recommendations for future work are provided.

S AMENVATTING Vermogensomvorming is het proces waarbij energie van een bron naar een ontvanger wordt getransfereerd, zodat deze nuttige arbeid kan verrichten met de energie. Sinds het eind van de 19de eeuw heeft elektrische omvorming de plaats ingenomen van mechanische omvorming in alle langeafstandstoepassingen. De wisselstroom generator, uitgevonden door Nikola Tesla, maakt het mogelijk om efficiënt mechanische energie in elektrische energie om te zetten en wordt nu nog steeds gebruikt om steden over de hele wereld van energie te voorzien. De verzonden elektrische energie moet vaak worden bewerkt voordat het gebruikt kan worden door de ontvanger. Het elektrische signaal moet bijvoorbeeld worden versterkt (of verzwakt) en/of geconverteerd in een andere golfvorm. Deze bewerkingen worden uitgevoerd door vermogenselektronica circuits die fungeren als een interface tussen bron en ontvanger. De snelle groei van de halfgeleiderindustrie, die begonnen is in de tweede helft van de 20de eeuw, heeft het mogelijk gemaakt om grote aantallen halfgeleiderapparaten te produceren die nu gebruikt worden in moderne elektronica. Naarmate deze industrie volwassener werd, heeft dit geleid tot systeemintegratie van functies van verschillende aard, zoals analoog/digitaal verwerking en elektrische vermogensomvorming. Sinds de jaren 0 90 worden slimme vermogenselektronica circuits op grote schaal gebruikt in de auto- en verlichtingsindustrie. In de nabije toekomst, met de komst van het internet of things (IoT), zullen slimme vermogenselektronica systemen complexer worden en de draadloze verzending van informatie van informatie tussen slimme objecten faciliteren. Dit proefschrift heeft tot doel om theoretische en experimentele methoden voor de analyse en optimalisatie van vermogenshalfgeleiderapparaten in slimme elektronische systemen te bestuderen. De resultaten zijn complementair aan de resultaten in het doctoraal proefschrift van B. K. Boksteen2 . Hieronder zal per hoofdstuk een kort overzicht van de inhoud van het proefschrift gegeven worden.

2 B. K. Boksteen, Field-plate assisted RESURF power devices: Gradient based optimization, degradation and analysis. PhD thesis, University of Twente, 2015.

ix

Overzicht x SAMENVATTING

Hoofdstuk 1 geeft een korte introductie van de vermogenselektronica apparaten die de belangrijkste component in een vermogenselektronica circuit vormen: de schakelaar. Een classificatie van bestaande vermogensapparaten wordt gegeven samen met een overzicht van hun werkingsprincipes. De discussie introduceert de afwegingen die gemaakt moeten worden in de optimalisatie van vermogens apparaten en transistoren. Het hoofddoel van dit proefschrift wordt uitgelicht ten opzichte van bestaand werk in dit vakgebied en een korte samenvatting van de volgende hoofdstukken wordt gegeven. Hoofdstuk 2 geeft de theoretische achtergrond voor het ontwerp van de hoogspanningsextensie van vermogenshalfgeleiderapparaten dat de doorslagspanning maximaliseert zonder de aan-weerstand op te offeren. Dit wordt bereikt met behulp van het gereduceerd oppervlakteveld (RESURF) effect, dat erop gericht is om een elektrisch veld distributie in de richting waarin de stroom loopt ( Ex -veld) met een lage (idealiter nul) helling te bereiken. Hoofdstuk 3 richt zich op de afweging tussen de specifieke aan-weerstand en de doorslagspanning in de uit-toestand in RESURF vermogens apparaten. Analytische vergelijkingen worden afgeleid, gebaseerd op de RESURF theorie die gepresenteerd is in hoofdstuk 2, om de specifieke aan-weerstand als functie van de uit-toestand doorslagspanning in te schatten in een geoptimaliseerde RESURF hoogspanningsextensie. Het wordt aangetoond dat een schakelbare veldplaat elektrode, die op de hoogspanningsextensie inwerkt, gebruikt kan worden om de aan-weerstand verder te reduceren zonder de Ex -veld distributie in de uit-toestand te beôrnvloeden. Het apparaat dat op dit principe werkt, genaamd de boost transistor, wordt besproken. In Hoofdstuk 4, worden drie elektrische technieken (gepulste gate, ACgeleidbaarheid en sensor-diode) om de junctie temperatuur van vermogenstransistoren te bepalen besproken en experimenteel vergeleken. Het apparaat-onder-test is uitgerust met sensor-diodes in het midden en aan de rand van het apparaat om lokale temperatuurinformatie te leveren. In Hoofdstuk 5 wordt een algemene procedure gepresenteerd om de veilige bedrijfslimieten van vermogenstransistoren te bepalen. Het wordt voorgesteld om het concept van veilig bedrijfsoppervlak uit te breiden naar een volume door een junctietemperatuur-as toe te voegen en de drain stroom te normaliseren naar de gate breedte. De resulterende driedimensionale ruimte die de veilige bedrijfspunten omvat wordt gedefinieerd als het veilige bedrijfsvolume (SOV).

In Hoofdstuk 7 worden de belangrijkste resultaten van dit proefschrift samengevat en worden aanbevelingen voor toekomstig werk gegeven.

xi SAMENVATTING

In Hoofdstuk 6, wordt een fysica-gebaseerd model afgeleid, op basis van een linearisatie procedure, om de elektrische, thermische en elektrothermische instabiliteit van vermogens metaal-oxide-halfgeleider (MOS) transistoren te onderzoeken. Het model leidt tot een theoretische definitie van het SOV, voorgesteld in hoofdstuk 5.

C ONTENTS A BSTRACT · vii S AMENVATTING · ix 1

1.4

P OWER S EMICONDUCTOR D EVICES 1.1 Introduction 1.2 The switch 1.3 Power semiconductor device classification An insight into power semiconductor device physics 1.5 Design trade-offs 1.6 Thesis outline I DEAL RESURF GEOMETRIES 2.1 The principle of RESURF 2.2 Derivation of the ideal RESURF solution Examples of ideal and DIELER RESURF structures 2.4 Combined RESURF structures 2.5 Discussion 2.6 Conclusions

· · · · · · ·

13 14 15 20 24 25 27

B REAKDOWN VOLTAGE AND SPECIFIC ON - RESISTANCE 3.1 Ron V-BV trade-off in RESURF drift extensions 3.2 Improving the Ron V-BV trade-off: the boost transistor 3.3 Conclusions

· · · ·

29 30 34 41

4 J UNCTION TEMPERATURE 4.1 Self-heating in power devices Three electrical techniques for temperature evaluation 4.3 Experimental results 4.4 Benchmarking analysis 4.5 Conclusions

· · · · · ·

43 44 45 52 52 56

5 S AFE OPERATING LIMITS 5.1 Determining the safe operating limits 5.2 From Safe Operating Area to Safe Operating Volume 5.3 The general nature of the Safe Operating Volume 5.4 Prediction of SOA curves from the SOV

· · · · ·

57 58 62 62 65

2

2.3

3

4.2

xii

· 1 · 2 · 3 · 4 · 6 · 9 · 11

5.5

Conclusions · 66

6

7

S UMMARY AND RECOMMENDATIONS 7.1 Summary 7.2 Innovative contributions 7.3 Recommendations for future work

· · · · · · · ·

69 70 71 72 77 80 81 83

· · · ·

85 85 87 88

B IBLIOGRAPHY · 95 L IST OF PUBLICATIONS · 99 Peer-reviewed · 99 Other · 99 A CKNOWLEDGMENTS ·101

xiii CONTENTS

6.7

P HYSICS -B ASED S TABILITY A NALYSIS 6.1 Introduction 6.2 Origin of electro-thermal runaway 6.3 Analytical stability analysis 6.4 The Safe Operating Volume (SOV) 6.5 Discussion 6.6 Conclusions Avalanche, MOS and bipolar model equations

CHAPTER

P OWER S EMICONDUCTOR D EVICES Abstract This chapter provides a brief introduction to power semiconductor devices, constituting the principal component in a power electronic circuit: the switch. A classification of the existing power devices is provided together with an overview of their operation physics. The discussion allows to introduce the trade-offs emerging in the design of an optimized power device. The main focus of this thesis is highlighted with respect to existing work in the field and a brief outline of the following chapters is provided.

1

1

Source

Iout

Ii

Load

2 1.1. INTRODUCTION

Vi

Power processing

Vout

Figure 1.1: Schematic illustration of a power processing circuit.

1.1

Introduction

Power electronics is the branch of electronics dealing with the processing of electrical energy. An electrical source generates energy which is amplified, stored and/or converted to a different waveform by a power electronic system and eventually transferred to a user (load). A schematic of an example power conversion system is shown in Fig. 1.1 [1]. Its function is to match the current and voltage requirements of the source to those of the load. Depending on requirements of the application, a power circuit can contain different components, such as switches, amplifiers, transformers, transducers, actuators, storage and dissipative elements. The most important figure of merit of a power circuit is the power conversion efficiency, defined as the ratio between the average output and input powers. Highly-efficient power conversion can be achieved by combining a switch with energy storage elements. The switch is periodically opened and closed in order to modulate the input current from the source. The energy storage elements act as a filter selecting the desired frequency components to transfer to the load from the modulated input. For maximum efficiency, the power losses on both the switch and energy storage elements should be minimized. Since the advent of solid-state electronics, the switching function is performed by a power semiconductor device, whose behavior should be as close as possible to that of an ideal switch (defined in Section 1.2) in order to maximize the system efficiency. Energy storage is performed by inductors and capacitors, which should be ideally lossless. In practice, the filter losses are determined by the parasitics in its components. Since the 1990’s, the rapid developments in microelectronics have allowed to design and manufacture power semiconductor devices using similar technology available for digital electronics. Such integration has laid the grounds for the so-called smart power technology, allowing digital drivers, control systems, and interfaces to microprocessors to be available on the same chip as the power device [2]. This is especially useful in automotive applications [3], where different analog, digital and power conversion func-

On-state

Off-state max

Von = 0

Voff = ∞

-

+

-

Ioff = 0

Ion = ∞ Ion = Von /Ron Ron

Real switch

Cswitch

+ Von ≠ 0

Ron -

Cswitch

max

Voff = BV +

Diode

-

Diode Ioff ≠ 0

Figure 1.2: Ideal vs. real switch. tionalities are needed within the same system. The power devices experimentally investigated in this thesis have been fabricated in NXP’s 140nm Advanced Bipolar CMOS DMOS (A-BCD9 [3]) smart power technology.

1.2

The switch

As mentioned in Section 1.1, the switch is one of the main constituents of a power circuit, and its performance is critical for maximizing the power conversion efficiency. An ideal switch has the following characteristics: 1. When it is closed (on-state), it can carry an infinite amount of current without any voltage drop across it and hence without any static power dissipation; 2. When it is open (off-state), it can sustain an infinite voltage across its terminals without any leakage current; 3. It can transit (switch) from the on-state to the off-state (and vice versa) instantaneously and without any dynamic power dissipation; 4. It can operate at any (arbitrarily high) temperature; 5. It can sustain an infinite number of switching cycles without degrading (i. e., altering its performance) or being damaged. Compared to an ideal switch, a power device exhibits the following nonidealities: (Fig. 1.2):

3 CHAPTER 1. POWER SEMICONDUCTOR DEVICES

Ideal switch

+

4

1. It has a finite resistance in the on-state, which is defined as onresistance (Ron ), an important figure of merit for the static power consumption.

1.3. POWER SEMICONDUCTOR DEVICE CLASSIFICATION

2. It carries a non-zero leakage current in the off-state, which increases with the voltage across its terminals. When the off-state leakage exceeds a critical value, the transistor is in breakdown condition. The voltage for which breakdown occurs is defined as the breakdown voltage (BV). 3. Because of parasitic capacitances (Cswitch ), switching a power device from the on-state to the off-state (and vice versa) requires a finite amount of time and causes a dynamic energy dissipation. 4. There is a maximum (junction) temperature Tj a power device can withstand, which is referred to as Tjmax . Because of its thermal impedance Zth , the device heats up in the on-state and the junction temperature Tj is higher than the ambient temperature Tamb . 5. Each switching cycle degrades the device performance by affecting the values of the on-resistance, breakdown voltage, leakage current and parasitic capacitances. In order to keep the degradation within acceptable limits, only a finite number of switching cycles can be perfomed. This number is strongly dependent on operating and environmental conditions and defines the transistor lifetime.

1.3

Power semiconductor device classification

Several types of semiconductor switches have been invented in order to cover applications of different nature [4]. They can be classified based on the following criteria (Fig. 1.3): 1. Number of junctions; 2. Number of electric terminals; 3. Mechanism of current conduction. Based on the number of junctions, the most common power devices are formed by1 : 1. One junction, such as: a) The pn diode, containing a junction between a p-type and an n-type semiconductor layer; b) The Zener diode; 1 There

is no theoretical upper limit to the number of junctions a power device can have.

c) The Schottky diode, containing a junction between a (p-type or n-type) semiconductor layer and a metal;

2. Two junctions, such as: a) The metal-oxide-semiconductor field effect transistor (MOSFET) and the high electron mobility transistor (HEMT); b) The bipolar junction transistor (BJT) and the heterojunction bipolar transistor (HBT). 3. Three junctions, such as: a) The silicon(semiconductor)-controlled rectifier (SCR) (also known as thyristor); b) The gate turn-off (GTO) thyristor; c) The insulated gate bipolar transistor (IGBT). Based on the number of electric terminals, the devices can be classified as: 1. Two-terminal devices (diodes). In a diode, the current flow is regulated by the polarity of the voltage between the anode and the cathode (positive in the on-state and negative in the off-state). 2. Three-terminal devices2 (transistors and thyristors). In a transistor, the current flow is regulated by applying a voltage to a control terminal (gate) or injecting a current into it (base). A thyristor is switched on by applying a set of repetitive current pulses on the control terminal (gate) to induce positive feedback in the current flowing between the anode and the cathode (latch-up). A conventional thyristor (SCR) cannot be switched off by acting on the gate once latch-up has occurred. This limitation has been overcome by the invention of the GTO thyristor, which allows the current flow to be switched off by draining current from the gate. Based on the mechanism of current conduction, power semiconductor devices are classified as: 1. Minority carrier (bipolar) devices (pn diode, Zener diode, BJT, HBT, IGBT, SCR and GTO). The main contribution to the current is given by the diffusion of electrons in a p-type layer and holes in a n-type layer. Since both electrons and holes contribute to the current flow these devices are also referred to as bipolar devices. 2 Devices with more than three terminals are not standard, but are often used as test structures. For example, a separate body contact is useful for a more in-depth device characterization. A fourth terminal can be also used to measure the junction temperature (the embedded sense-diode, see Chapter 4).

5 CHAPTER 1. POWER SEMICONDUCTOR DEVICES

d) The junction field effect transistor (JFET) and the metal-semiconductor field effect transistor (MESFET).

Two-terminal

Three-terminal

p1d

p2d

One-junction p1ad

6

p1bd

A

A

p1cd

p1dd

1.4. AN INSIGHT INTO POWER SEMICONDUCTOR DEVICE PHYSICS

K

K

Three-junction p2bd

p2ad

D

A

D G

G K

p3d

Two-junction p3ad

C G

S

MOSFET pn ZenerF SchottkyF JFET HEMT DiodeF Diode Diode MESFET MinorityF MajorityFcarrier carrier

p3cd

A

B G

G S

p3bd

A

C

E

K

K

E

BJT HBT

SCR

GTO

IGBT

MinorityFcarrier

Figure 1.3: Nomenclature and classification of power semiconductor devices. 2. Majority carrier (unipolar) devices (Schottky diode, JFET, MESFET, MOSFET and HEMT). The main contribution to the current is governed by drift of majority charge carriers (electrons in n-type layers or holes in p-type layers). Since only one carrier type contributes to the current flow, these devices are also referred to as unipolar devices. A majority carrier device provides a lower current density compared to a minority carrier device but a better (faster and with less dynamic losses) switching performance.

1.4 1.4.1

An insight into power semiconductor device physics Intrinsic device and drift extension

All power semiconductor devices classified in Fig. 1.3 contain two main components: (1) an intrinsic device (diode, transistor or thyristor), which regulates and controls the current flow and (2) a drift extension, which sustains the breakdown voltage in the off-state (Fig. 1.4). The drift extension, as shown schematically in Fig. 1.5, is a slab of semiconductor material (n-type in an NMOS and p-type in a PMOS) which is depleted in the off-state operation. When an off-state voltage V0 is applied across the device terminals, a depletion layer is formed (green area in Fig. 1.5) which extends across the drift region by a distance x0 . As V0 increases by an amount dV, the depletion layer increases by a distance dx until breakdown occurs (i. e., V0 = BV). The relationship x = f(V) between the extension of the depletion layer and the applied voltage depends on the nature of the junction and its dimensions (1D, 2D or 3D junctions are possible). In the on-state, the drift extension simply acts as a resistor and contributes to the on-resistance. The higher the BV of the device, the longer the drift extension needed to sustain it, resulting in a larger Ron . The physics of the drift extension is responsible for the trade-off between the on-resistance times unit area A (specific on-resistance Ron A) and BV, known as the Ron A − BV trade-off.

Intrinsic device (diode, transistor or thyristor)

Anode

7

Controls the current flow

Ron

Drift extension

Diode

Cathode

Sustains the breakdown voltage Contributes to the on-resistance

Figure 1.4: Schematic of a power semiconductor device including the intrinsic device and the drift extension.

In the discussion above, it has been assumed that the only contribution to Ron comes from the drift extension. This is a simplification, since in reality the intrinsic device also has a finite resistance (see [4] for an analysis of the different resistance contributions in a power device). However, the relatively-long drift extension needed to sustain high BV values often

0

x

Junction

Metal or Semiconductor semiconductor drift region

dx

x = f (V)

V0 dV

x0 Figure 1.5: Schematic of a 1D junction adjacent to a semiconductor drift extension. When an off-state voltage V0 is applied, a depletion layer (green area) is formed which extends across the drift region by a distance x0 . As V0 increases by an amount dV, the depletion layer increases by a distance dx until breakdown occurs (i. e., V0 = BV). The relationship x = f(V) depends on the physical nature of the junction.

CHAPTER 1. POWER SEMICONDUCTOR DEVICES

(Control)

8 1.4. AN INSIGHT INTO POWER SEMICONDUCTOR DEVICE PHYSICS

results in the drift resistance being much larger than that of the intrinsic device. For practical purposes, it is possible to treat the intrinsic device as an ideal switch (see Section 1.2) and to attribute the on-resistance and off-state diode behavior to the physics occurring in the drift extension.

1.4.2

Operating limits

From a user’s point of view, the operating condition of a power device is determined by the applied voltage between the anode and cathode and the current flowing between them. In a three-terminal device, the magnitude of this current can be modified via the control terminal, e. g. by applying a gate-to-source voltage in a MOSFET. In the following, I and V refer to the current flowing through the drift region and the voltage drop across it, respectively. It is implicitly assumed that I can be voltage or current controlled. The device operation can be represented in the current-voltage (I-V) plane or in the current density-voltage (J-V) plane, by normalizing the current I to the cross-sectional area through which current flows (Aflow ). The current I density is defined as J = Aflow (Fig. 1.6) and the specific on-resistance as V Ron A = J for operation in the linear regime3 . dJ As shown in Fig. 1.6a, the J-V relationship is linear with slope dV = Ron1 A for voltage values below the saturation voltage Vsat . When V = Vsat , the current density saturates to the value Jsat because of the saturation of the carrier velocity with the electric field in the drift extension [5]. The maximum allowed value for the voltage V is defined by the breakdown voltage BV. The parameters Ron A, Vsat , Jsat and BV define a bounded area in the J-V plane, which is defined as the operating area. The operating area contains all possible operating points in the J-V plane, and can be formally defined as the area described by the following functions:  V  (a) J = Fon (V) = Ron A for V 6 Vsat  J = Fsat (V) = Jsat for V > Vsat   V = F (I) = BV BV

(b) ,

(1.1)

(c)

where Vsat = Ron AJsat . The extension of the operating area is primarily determined by the Ron A − BV trade-off. However, as shown in Fig. 1.6b, not all operating points yield a safe electrical operation, because of non-idealities in the device behavior caused by parasitic elements. In particular, the breakdown voltage is given by BV only when a negligible (ideally zero) leakage current flows into the device. In the on-state, the breakdown voltage depends on the current 3 The specific on-resistance is defined in literature as the product between R on and the device active area A rather than Aflow , since the device cost depends on the area it occupies on the wafer. This definition is correct for vertical devices where A = Aflow but has no physical meaning for lateral devices where A 6= Aflow (see Fig. 3.1). In order to deal with this issue, the on-resistance times unit volume has been introduced in Chapter 3.

density J, and might be approximated by the following linear relationship (see Chapter 6.3.1 for a physics-based expression): BV − V for BVsat 6 V 6 BV BV − BVsat

9 (1.2)

where BVsat represents the breakdown voltage when J = Jsat . The area described by the intersection of the functions Fon , Fsat , FBV and Fel is defined as the electrical safe operating area. Further limitations to the safe operating limits originate from the phenomenon called self-heating (SHE), which will be experimentally analyzed in Chapter 4. When a current flows into the device, the dissipated power Pd = I · V causes an increase in the device temperature Tj = Tamb + Zth · Pd . The Tj -increase is particularly relevant in the saturation region, where both I and V are high. Since Jsat is temperature dependent, it decreases with the applied voltage according to (see Chapter 6.3.2): J = FSHE (V) =

Jsat ≈ Jsat (1 + Zth φV) for Zth φV  1, 1 − Zth φV

(1.3)

sat where φ = ∂J ∂Tj is the (negative) temperature coefficient of Jsat [5]. As shown in Fig. 1.6c, Jsat decreases with V in the saturation region and reduces the extension of the operating area. In addition, the maximum junction temperature Tjmax the device can withstand imposes a limitation to the T −T maximum dissipated power Pdmax = j maxZth amb , where Tamb is the ambient temperature and Zth the device thermal impedance. As a result, the current density J is limited by the following hyperbolic function in the J-V plane:

J = Fth (V) =

Tjmax − Tamb . Zth · Aflow · V

(1.4)

The area described by the functions Fon , Fsat , FBV , FSHE and Fth is defined as the thermal safe operating area. Finally, the intersection of the thermal and electrical safe operating areas determines the overall safe operating area of the power device (Fig. 1.6d).

1.5

Design trade-offs

The various electrical and thermal mechanisms that characterize the operation physics make the design of an optimized power device a challenging task. Numerous trade-offs have to be considered. While optimizing the Ron A−BV trade-off, other important device parameters such as the the safe operating limits, the switching speed, the leakage current and the device lifetime have to be taken into account. A schematic overview of the design trade-offs based on the physical limits of a real switch (see Section 1.2) is given in Fig. 1.7. The main focus of this thesis is to provide the theoretical background and the experimental tools for analyzing and improving the trade-off between Ron A, BV and the

CHAPTER 1. POWER SEMICONDUCTOR DEVICES

J = Fel (V) = Jsat ·

Jsat

Operating Area Vsat

Voltage (V) BV

0

Jsat

Fel FSHE Fth BVsat

Electrical Safe Operating Area Vsat

Voltage (V) BV

(d) Current density (A/cm2) 1/R on A

(c)

on A

Jsat

1/R

1.5. DESIGN TRADE-OFFS

0

Current density (A/cm2) 1/R on A

(b)

Current density (A/cm2) 1/R on A

(a)

Current density (A/cm2)

10

Fon Fsat FBV

0

Thermal Safe Operating Area Vsat

Voltage (V)

BV

0

Jsat

BVsat

Safe Operating Area Vsat

Voltage (V) BV

Figure 1.6: Definition of the a) Operating Area, b) Electrical Safe Operating Area, c) Thermal Safe Operating Area and d) Safe Operating Area in the J-V plane.

electro-thermal safe operating limits, which P. L. Hower defines as the design triangle in [6]. When improving the Ron A − BV trade-off, larger current densities flow into the device. In particular, an increase in Jsat negatively affects the electro-thermal stability of the device (see Chapter 6.3) and results in a reduction of the corresponding safe operating areas. Reducing the resistance of the drift extension (e. g, by increasing the doping concentration or the cross-sectional area of the current flow) also results in an increase of the associated capacitance which in turn worsens the switching speed. In addition to the drift capacitance, there are other capacitance contributions depending on the physical and geometrical nature of the device. However, a detailed analysis of switching behavior of a power device is out of the scope of this work. For an overview of the figures of merit typically used for analyzing the capacitances and switching performance of power devices, the reader is referred to Refs. [7, 8]. Additional levels of complexity emerge when leakage current, reliability and lifetime considerations are made. This topic has been analyzed in detail for power MOSFETs in the doctorate thesis of B. K. Boksteen [9]. His work indicates that there is a strong correlation between the off-state leakage

Boksteen´s work [9] 11

This work

Temperature limit

Current limit

Refs. [7-8] Switching time limit

Lifetime limit

Figure 1.7: Overview of the trade-offs in the design optimization of a power semiconductor device and focus of this work. The red and green lines between the pentagon vertices indicate opposing and supporting limits, respectively. Grey lines are shown where the relationships are not clearly defined. current and the device lifetime. Optimizing the Ron A − BV trade-off yields devices with smooth electric field distributions in the drift extension (see also Chapters 2-3 of this thesis). This is beneficial for device reliability, since it reduces the impact of charge trapping mechanisms [10] which increase the leakage current and result in a shorter device lifetime.

1.6

Thesis outline

The thesis is organized as follows. Chapter 2 provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with low (ideally zero) slope. Chapter 3 focuses on the trade-off between the specific on-resistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. It is shown that a switchable field plate electrode acting on the drift extension can be used to further

CHAPTER 1. POWER SEMICONDUCTOR DEVICES

Voltage limit

12 1.6. THESIS OUTLINE

reduce the on-resistance without affecting the Ex -field distribution in the off-state. The device based on this principle, named the boost transistor, is discussed. In Chapter 4 three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for evaluating the junction temperature of power transistors are discussed and experimentally compared. The device under test is provided with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. In Chapter 5 a general procedure for experimentally determining the safe operating limits of power transistors is presented. It is proposed to extend the safe operating area to a volume by adding a junction temperature axis, and normalizing the drain current to the gate width. The resulting threedimensional space comprising the safe operating points is defined as safe operating volume (SOV). In Chapter 6 a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal-oxide-semiconductor (MOS) transistors. The model leads to a theoretical definition of the SOV, proposed in Chapter 5. In Chapter 7 the main results of this thesis are summarized and recommendations for future work are provided.

CHAPTER

I DEAL RESURF GEOMETRIES Abstract This chapter provides the theoretical background for designing the drift extension of power semiconductor devices in order to maximize the breakdown voltage without sacrificing the on-resistance. This is achieved using the REduced SURface Field (RESURF) effect, which aims at achieving an electric field distribution in the drift region along the current flow direction ( Ex -field) with minimal, ideally zero, slope. A method is demonstrated to construct devices that obey Poisson’s equation and satisfy the ideal RESURF condition giving zero slope in Ex throughout the two-dimensional (2D) device region. The designs are obtained by shaping the device geometry and the boundary and by applying the proper potentials at the boundaries. Using this method ideal designs have been derived for devices based on graded doping, graded thickness and graded field-plate potential. In addition, 2D solutions have been derived for periodic superjunction and DIELEctric Resurf (DIELER) device geometries. Solutions for devices that combine several types of field shaping are demonstrated. Finally, the effect of non-ideal geometries on the breakdown voltage in actual devices is discussed.

This chapter was published in IEEE Trans. Electron Devices [11]. For clarity it has been expanded with additional figures and explanations.

13

2

2.1

14

The principle of RESURF

2.1. THE PRINCIPLE OF RESURF

Breakdown of semiconductor devices occurs due to an avalanche of charge carriers initiated by high electric fields in reverse biased junctions [4, 12]. In order to increase the breakdown voltage of high voltage semiconductor devices, a relatively long drift extension is therefore used to reduce the electric fields [4]. It is commonly known [13] that the off-state breakdown voltage is maximized by ensuring that the electric field in the drift region along the current flow direction (x-direction) satisfies: ∂ Ex (x, y) = 0. ∂x

(2.1)

This is defined as the ideal RESURF condition for the Ex field. For most 2D device designs the solution of Poisson’s equation does not obey (2.1). As will be shown, an ideal RESURF geometry requires the device boundaries to be shaped in a special manner, an aspect that has not been dealt with in earlier work [14–20]. Since the ideal field condition is not satisfied everywhere, the breakdown voltage of these devices is lower than for those satisfying (2.1) at a given drift extension length L. For these reasons, the investigation of device designs that provide solutions of Poisson’s equation obeying (2.1) is worthwhile. Exact solutions of (2.1) are also useful for performance optimization of other semiconductor devices like FinFETs, nanowire, gate-all-around (GAA) FETs, deep submicron transistors [21] and avalanche photodiodes [22]. The RESURF (REduced SURface Field [23– 25]) principle is based on reducing the field in the current flow direction (xdirection) by introducing a perpendicular field gradient (in the y-direction) as is illustrated in Fig. 2.1. In the absence of RESURF (Fig. 2.1a), with Ex = ρε , where ρ zero Ey -field gradient, the Ex -field has a gradient ∂∂x is the charge density and ε the dielectric permittivity. In Fig. 2.1b), the ∂E RESURF effect is implemented using a ∂yy field gradient in the drift region. Since, according to Poisson’s equation, ∂Ey ∂y

∂ Ex ∂x

+

∂Ey ∂y

= ρε , it follows that for

Ex = ρε the gradient ∂∂x becomes zero and the ideal RESURF condition (2.1) is satisfied. The graphs on the right side of Fig. 2.1 illustrate that at identical maximum field and off-state breakdown voltage, an optimized 2D drift extension needs only half of the length compared to a 1D one. The breakdown voltage is equal to the grey area under the graphs. An additional advantage of the application of RESURF is that a higher doping in the drift region can be used. While increasing the doping would lead to a reduction of the breakdown voltage in a 1D device (Fig. 2.1a), the RESURF effect can be used to balance the increase in charge density by a higher ∂E vertical field gradient ∂yy . This further improves the specific on-resistance RON A-BV trade-off of power devices [26]. This chapter focuses on constructing 2D device designs that satisfy ideal RESURF (Fig. 2.1b). For the sake of generality, the x and y directions in this work respectively refer to the direction of the current flow and any of the

=

(no-RESURF)

) 15

Figure 2.1: Schematics explaining the RESURF principle by considering an infinitesimal part of the drift region containing a constant charge density ρ and dielectric constant . a) A 1D device in the absence of RESURF effect. ∂E Since ∂yy = 0, according to Poisson’s equation (2.3) the electric field Ex Ex has a slope ∂∂x = ρε . The infinitesimal variation of the Ex -field amplitude from x to x + dx is indicated by E0 (blue arrow). b) The ideal field condition can be satisfied by applying an electric field in the y-direction with gradient ∂Ey ρ ∂ Ex ∂y = ε , such that ∂x = 0 and Ex is constant.

two directions perpendicular to it, independently of the device orientation with respect to the wafer plane. Therefore, the proposed designs can be implemented in both lateral and vertical devices with RESURF fields acting either in or out of the wafer plane. The chapter is organized as follows. Section 2.2 describes ideal 2D RESURF geometries that are derived from the exact analytical solution of Poisson’s equation. Two types of geometries are discussed: 1) geometries that use field-plates to generate the field gradient ∂Ey ∂y and 2) periodic geometries that use superjunction and DIELER geometries to satisfy the ideal field condition. Section 2.3 shows implementation examples of the different types of ideal and near ideal RESURF solutions. Section 2.5 discusses the effect of deviations from the ideal case on the breakdown voltage and shows an example of a combined RESURF device. The conclusions are presented in Section 2.6.

2.2

Derivation of the ideal RESURF solution

In this section analytical solutions of Poisson’s equation are derived that Ex satisfy the ideal RESURF condition ∂∂x = 0. The assumed geometry and boundary conditions are sketched in Fig. 2.2. The structure consists of two domains, with charge densities ρ1,2 and dielectric constants ε1,2 .

CHAPTER 2. IDEAL RESURF GEOMETRIES

(ideal RESURF)

16

Domain 1

2.2. DERIVATION OF THE IDEAL RESURF SOLUTION

Domain 2

(FP-assisted RESURF)

(Periodic RESURF)

Figure 2.2: Schematic potential distribution ψ(x, y) in the drift extension of ideal RESURF devices. Only half of the symmetric structure is shown. The device is mirror symmetric in the boundary at y = 0 and a field plate (at potential VFP ) or periodic boundary condition is placed at y = t1 + t2 .

The interface between the domains is assumed to be ideal, i.e. free of interface charges. At this interface the perpendicular displacement field D⊥ , the parallel field Ek and the potential ψ need to be continuous. Domain 1 is made of a semiconductor material, that has the purpose to block current at high-voltages in the off-state and to conduct current in the on-state. The main purpose of domain 2 is to generate the field gradient ∂Ey ∂y needed for the RESURF effect in the current blocking state. In this work domain 2 is either made of a dielectric without fixed charge (ρ2 = 0) or of a semiconductor material with opposite charge density compared to that in domain 1 (ρ2 6= 0). Since the structure is intended for blocking voltages up to an off-state breakdown voltage BV, the right boundary is at a potential ψ = BV whereas the left boundary is at ground (ψ = 0). The geometry (and potential ψ(x, y)) is mirror symmetric with respect to the x-axis ( ∂ψ(x,y) |y=0 = 0). The non-periodic geometries are terminated ∂y by a field plate at the boundary y = t1 + t2 , which is held at a fieldplate potential ψ(x) = VFP (x). The periodic geometries have a periodic boundary condition along the line y = t1 + t2 and therefore require ∂ψ ∂y = 0 at this interface. The dielectric constants in both domains ε1,2 are assumed to be position independent. In both domains Gauss’ law needs to be obeyed: ∇ · D(x, y) = ρ(x, y),

(2.2)

where D = εE is the electric displacement field and ρ is the charge density.

Using E = −∇ψ, Poisson’s equation is obtained: ∇2 ψ(x, y) =

∂2 ψ(x, y) ∂2 ψ(x, y) ρ(x, y) + =− . ∂x2 ∂y2 ε

(2.3)

ρ(x, y) = ρ(x) = αx + β,

(2.4)

with α and β being constants. A function ψ(x, y) satisfying (2.3), (2.1), the conditions ψ1 (0, 0) = 0 and ψ1 (L, 0) = BV, and (2.4) for any (x,y) is found to be: BV ρ(x)y2 ψ(x, y) = x− + c1 y + c2 , (2.5) L 2ε where c1 and c2 are integration constants. In other words, equation (2.5) describes exact ideal RESURF solutions of Poisson’s equation for charge distributions ρ(x) that are either constant or have a linearly graded doping concentration in the x-direction. This solution needs to be extended to both domains and suitable boundary conditions need to be found. Using 1 the symmetric boundary conditions from Fig. 2.2, ∂ψ ∂y = 0 at y = 0, the solution ψ1 (x, y) inside domain 1 is found to be: ψ1 (x, y) =

ρ1 (x) 2 BV x− y . L 2ε1

(2.6)

This solution can be extended to domain 2 by using the continuity conditions at the interface between domains 1 and 2. These conditions ensure continuity of the displacement field perpendicular to the boundary and the electric field parallel to the boundary (see Fig. 2.2). When the interface is parallel to the x-axis (i.e., t1 does not vary with x), the potential ψ2 in domain 2 is given by:   BV ρ1 (x) ε1 ρ2 (x) (y − t1 )2 . (2.7) ψ2 (x, y) = x− t1 t1 + 2 (y − t1 ) − L 2ε1 ε2 2ε2 It thus has been shown that equations (2.6)-(2.7) satisfy both Poisson’s equation and the ideal field condition throughout both domains. Moreover they satisfy the boundary conditions along the line y = 0 and the continuity equations at the interface y = t1 . By enforcing (2.6)-(2.7) to represent solutions of Poisson’s equation two challenges remain. Firstly, the outer boundary conditions at y = t1 + t2 need to be satisfied. This will be discussed in subsection 2.2.1 for non-periodic, field-plate assisted structures and in subsection 2.2.2 for periodic structures. Secondly, the boundary conditions ψ = 0 and ψ = BV on the left and right boundaries need to be satisfied for all y. This can be achieved by geometry shaping of the boundaries as described in subsection 2.2.3.

17 CHAPTER 2. IDEAL RESURF GEOMETRIES

Potential distributions of the form ψ(x, y) = −(αx + β)f(y)/ε are consid2 f(y) = ρ(x, y). ered, which satisfy both equations (2.1) and (2.3) if (αx + β) ∂ ∂y 2 Since charge distributions with a zero or constant charge gradient are the most relevant for RESURF devices [14, 27–31] this chapter focuses on solu2 f(y) tions of the potential distribution ψ(x, y) with ∂ ∂y = 1 such that ρ(x, y) 2 is a linear function of x and is not a function of y:

2.2.1

18

Field-plate assisted RESURF

2.2. DERIVATION OF THE IDEAL RESURF SOLUTION

In non-periodic structures the RESURF gradient in the y-direction is formed by a field plate. The field plate symmetrically terminates the structure at the top and bottom of the drift extension. In order to satisfy the boundary condition, the potential on the field plate needs to match that of the solution in equation (2.7), such that ψ(x, y)|y=±(t1 +t2 ) = VFP (x). Thus, for a field plate located at y = ±(t1 + t2 ), the field plate potential VFP (x) is obtained by substituting y = ±(t1 + t2 ) in (2.7) resulting in: VFP (x) =

ρ1 (x) ρ2 (x) BV x− teq (x)2 − t2 (x)2 , L 2ε1 2ε2

(2.8)

where the equivalent thickness teq [27, 30] can be expressed in terms of t1 and t2 using: s   2ε1 teq (x) = t1 t1 + t2 (x) . (2.9) ε2

2.2.2

Periodic RESURF

As an alternative to field plates, semiconductor domains with opposite ∂E charge density can be used to generate the gradient ∂yy . These periodic structures can be formed by alternating domains 1 and 2 in an infinite stack of domains with constant thicknesses 2t1 and 2t2 . Due to the repetitive, periodic nature of the superjunction stack, it is sufficient to show that the solution satisfies the boundary and continuity conditions at y = 0, y = t1 and y = t1 + t2 . If the structure is periodic in the y-direction, the boundary conditions at y = ±(t1 + t2 ) do not only require the continuity of the potential ψ(x, y)|y=±(t1 +t2 ) , but also of its y-derivative. From symmetry considerations, this is only possible if ∂ψ ∂y |y=±(t1 +t2 ) = 0. Applying this condition to (2.7) yields the well known charge balance condition [16]: ρ1 (x)t1 + ρ2 (x)t2 = 0.

(2.10)

The equations (2.6)-(2.7) provide the RESURF solution in the field-plate assisted case together with (2.8), and describe the ideal potential distribution in the periodic domains for superjunction devices together with (2.10). In order to satisfy the ideal field condition the charge distributions in the periodic domains need to satisfy (2.10), which requires the sign of the doping charge to alternate between n-type and p-type. Therefore only superjunction devices can result in ideal periodic RESURF. In addition to superjunction devices, DIELER [32] devices will be discussed, since they represent another important type of periodic RESURF devices. In DIELER devices dielectric and semiconducting domains alternate in order to have a reduction in the slope Ex and increase BV. Since the fixed charge in the dielectric is assumed to be zero while that in the semiconductor is non-zero, DIELER devices cannot satisfy the charge balance equation (2.10) and ideal RESURF condition (2.1).

Exact solutions of Poisson’s equation for DIELER devices are shown below. For ρ2 = 0, since the RESURF is non-ideal, quadratic terms need to be added to equations (2.6)-(2.7). The following solution is found that satisfies (2.3) the boundary condition at all interfaces: =

ψ2 (x, y)

=

(2.11)

(2.12)

After having satisfied the interface boundary conditions, the geometry shaping procedure in the next section will be applied in order to satisfy the boundary conditions at the left and right terminals for both periodic and non-periodic devices.

2.2.3

Geometry shaping of the left and right boundaries

The left and right boundaries of the structure are curves in the x − y plane. They can be described by the parametric equation (x, y) = (xb (s), yb (s)), where xb (s) and yb (s) are the coordinates of the boundaries as a function of the position parameter s. The boundary potential ψb as a function of s is given by the equations (2.6)-(2.7): ψb (s) = ψ(xb (s), yb (s)).

(2.13)

The potential ψb along the left (xb0 , yb0 ) and right (xbBV , ybBV ) boundaries of domain 1 is imposed to be a constant. In order to obtain boundary designs that satisfy this condition, a geometry shaping procedure is applied, which ensures that the boundaries run along an equipotential line of equation (2.6), as shown schematically in Fig. 2.3. Thus the shape of the left and right boundaries is found according to equation (2.13) by finding the equipotential lines (xb , yb ) that satisfy the following equations:  ψ(xb0 (s), yb0 (s)) = 0 (a) . (2.14) ψ(xbBV (s), ybBV (s)) = BV (b) Some degrees of freedom are present in the choice of the shape on the left and right boundaries of domain 2. Suitable shapes can be chosen depending on the type of RESURF. In some cases equipotential lines as in equation (2.14) can be taken, in other cases a non-zero potential gradient will be present. In any case, ideal solutions are obtained as long as the boundary is shaped such that the potential along the boundary obeys equation (2.13). It should be emphasized that the shaping procedure described in this subsection is important for inducing 2D ideal RESURF solutions. Devices with straight boundaries at constant potential will not exactly obey equation (2.1) for non-zero doping ρ1 (see Sec. 2.5.1). After having derived ideal

19 CHAPTER 2. IDEAL RESURF GEOMETRIES

ψ1 (x, y)

BV ρ1 t 1 ρ1 2 x− [x2 − y2 ] − y L 2ε1 t1 + ε2 t2 2ε1 BV ρ1 t 1 x− [x2 − (y − t1 − t2 )2 ] L 2ε1 t1 + ε2 t2 ρ1 t1 t2 ε1 t2 + ε2 t1 . − 2ε1 ε1 t1 + ε2 t2

L

, �b

,�b � b0

Domain 2

)=

BV

0

��

)=

0

2.3. EXAMPLES OF IDEAL AND DIELER RESURF STRUCTURES

V

� bB

�(

Domain 1

�(

20

Figure 2.3: Schematic of an ideal RESURF structure example that can be derived from Fig. 2.2 using the geometry shaping procedure in Sec. 2.2.3. The left and right boundaries need to follow the shape of the equipotential lines in order to keep the potential distribution ideal. RESURF solutions, the next section will focus on providing examples of their implementation in several important cases.

2.3

Examples of ideal and DIELER RESURF structures

In this section several examples of ideal RESURF device architectures are given (see also [27]). In order to design a structure that yields an exact solution of Poisson’s equation and satisfies the ideal RESURF condition (2.1) the following procedure is taken: 1. Choose BV and device length L, making sure that BV L is smaller than the critical field Ecrit (see Sec. 2.5.1) to prevent breakdown. 2. Choose the semiconductor thickness t1 . 3. For field plate RESURF: a) Choose one graded parameter ρ1 , t2 or VFP . b) Fix the other two (non-graded, constant) parameters. c) Determine the gradient (x-dependence) of the graded parameter using equation (2.8). 4. For periodic (superjunction) RESURF: a) Fix ρ1 (x). b) Choose t2 and ρ2 (x) to satisfy equation (2.10). 5. Shape the left and right boundaries according to equation (2.14) making use of (2.6)-(2.7).

2

−2.5

1 2.5

2

2

−2.5 2.5

1 2

Vright2 (b) Vtop−bottom

11.7 ε0 3.9 ε0 11.7 ε0 1.5 C/cm4 · x 4.9 C/cm4 · x 2.5 µm 2.5 µm 5 µm 0V 136.2 V 54.4 V/ µm· (t1 + t2 − y) 1.5 V/ µm2 · (t1 + t2 − y)2 + 50.6 V/ µm· (t1 + t2 − y) 0V

Figure 2.4: Potential distribution ψ(x, y) in a RESURF device with graded charge. a) Dielectric RESURF. b) pn junction RESURF.

This procedure is demonstrated for several cases in this section. The procedure captures most practical cases, but does not yield all possible types of solutions, since one might also consider to grade more than one parameter, or to grade t1 [33] or the dielectric constants ε [17]. It is noted that the analytical solutions of the potential (2.6)-(2.7) are found to be in exact agreement with numerical solutions of Poisson’s equations using COMSOL [34] within numerical accuracy. A further validation has been reported in earlier work [27] using TCAD simulations for solving the semiconductor equations.

2.3.1

Field-plate assisted RESURF

By choosing one graded parameter in (2.8) (step 3a in the previous section), the ideal RESURF solutions are demonstrated in some significant cases: (1) graded doping in domain 1 ρ1 (Fig. 2.4), (2) graded field-plate potential VFP (Fig. 2.5), and (3) graded thickness t2 of domain 2 (Fig. 2.6). In each of the 3 figures the solutions are shown for dielectric RESURF (ρ2 = 0, subfigure a) and for pn junction RESURF (ρ2 6= 0, subfigure b). As can be seen, the equipotential lines are equidistant in the x direction, showing that the ideal RESURF condition (2.1) is obeyed throughout the 2D region in all cases.

2.3.2

Periodic RESURF

Examples of periodic RESURF are shown in Fig. 2.7 for superjunction (Fig. 2.7a) and DIELER (Fig. 2.7b). As discussed in step 4 of the procedure in Sec. 2.3 no graded parameters are needed for ideal periodic RESURF. The charge densities ρ1 and ρ2 , thicknesses and field-plate potentials are therefore taken to be constant.

21 CHAPTER 2. IDEAL RESURF GEOMETRIES

(b)

ε1 ε2 (a) ε2 (b) ρ1 (a) ρ1 (b) t1 t2 L Vleft Vright1 Vright2 (a)

ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 L Vleft Vright

22

Figure 2.5: Potential distribution ψ(x, y) in a RESURF device with graded field-plate. a) Dielectric RESURF. b) pn junction RESURF. Notice that in the DIELER case in Fig. 2.7b the equipotential lines are not equidistant, meaning that the Ex field is not constant, but decays linearly in the x-direction (because of the quadratic term in ψ1 and ψ2 in (2.11)-(2.12)) and has a trapezoidal shape (as shown in Fig. 2.7b). However, the DIELER solution is better than the 1D case (which also has a linearly decaying field) since the slope of the field decay is lower (Fig. 2.8). As shown earlier [32]

y [µm]

(a)

−2 −1

2 1

0 1 2 1

2

3 x [µm]

4

100 50

2 0

5

0

(b) 120

4

y [µm]

2.3. EXAMPLES OF IDEAL AND DIELER RESURF STRUCTURES

Vtop−bottom (a) Vtop−bottom (b)

11.7 ε0 3.9 ε0 11.7 ε0 8 · 10−3 C/cm3 0 −8 · 10−3 C/cm3 0.5 µm 0.5 µm 5 µm 0V 136.2 V 27.2 V/ µm· (x − 2.5 µm) 27.2 V/ µm· (x − 0.93 µm)

2

3 2 1

100 80

1

0 1 2 3

60 40

2

4

ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 (a) t2 (b) L Vleft Vright1 Vright2 (a)

20

Vright2 (b) Vtop−bottom

11.7 ε0 3.9 ε0 11.7 ε0 0.4 · 10−2 C/cm3 0 −0.4 · 10−2 C/cm3 1 µm 0.24 · (x − 0.71 µm) −1 0.085 µm · (x − 0.71 µm)2 + 0.66 · (x − 0.71 µm) 5 µm 0V 136.2 V 126 V/ µm· (t1 + t2 − y) 1.94 V/ µm2 · (t1 + t2 − y)2 + 21.2 V/ µm· (t1 + t2 − y) 0V

0 0

1

2

3 x [µm]

4

5

Figure 2.6: Potential distribution ψ(x, y) in a RESURF device with graded domain 2. a) Dielectric RESURF. b) pn junction RESURF.

Vtop−bottom (a) Vtop−bottom (b)

11.7 ε0 11.7 ε0 3.9 ε0 3.2 · 10−3 C/cm3 0 −8 · 10−4 C/cm3 0.1 µm 0.4 µm 1 µm 1.4 µm 0V 34.2 V 34.2 V/ µm· (x − 0.02 µm) −6.6 V/ µm2 · (x − 0.03 µm)2 + 33.82 V/ µm· (x − 0.03 µm)

Figure 2.7: Potential distribution ψ(x, y) in a periodic RESURF device (three periods are shown). a) superjunction. b) DIELER.

and in Fig. 2.8, the decay rate of the field reduces as the ratio tt12 is decreased (at fixed ρ1 ). In other words, as the semiconductor domain gets thinner, the charge in this domain reduces for a given doping. Theoretically, it would require t1 = 0 in order to satisfy the charge balance condition (2.10) and ideal RESURF condition (2.1). It is worth mentioning that DIELER

Superjunctiona(Fig.a2.7a)

DIELER (t1 = 0.05µm) DIELER (t1a=a0.1µm,aFig.a2.7b)

Figure 2.8: Comparison between the Ex fields in ideal 2D RESURF (superjunction in Fig. 2.7a, green), non-ideal 2D RESURF (DIELER in Fig. 2.7b, solid yellow) and 1D pn junction (red). The dashed yellow line shows the Ex field in a DIELER structure having half of the thickness t1 compared to Fig. 2.7b.

23 CHAPTER 2. IDEAL RESURF GEOMETRIES

ε1 ε2 (a) ε2 (b) ρ1 ρ2 (a) ρ2 (b) t1 t2 L (a) L (b) Vleft Vright

24

structures can in principle satisfy (2.10) if the dielectric is non-ideal (i.e., it contains fixed charge) or there is trapped charge at the interface between the semiconductor and the dielectric layer. In DIELER and superjunction devices that do not satisfy (2.10) the Ex -field will show a non-zero gradient ∂ Ex ∂x .

2.4. COMBINED RESURF STRUCTURES

2.4

Combined RESURF structures

Besides achieving ideal RESURF by grading one parameter, one can also create combined devices. Combining different methods can be useful when the grading of only one parameter requires values that are difficult to achieve in real devices. Figure 2.9 shows a semiconductor-dielectric structure (with ρ2 = 0) where the graded-field plate, graded charge and graded dielectric thickness methods have been combined. Domain 1 is assumed to be an n-type semiconductor with doping concentration ND (ρ1 = qND , where q is the elementary charge). The compound device has been constructed by, in addition to the methods discussed in section 2.3, making sure that the potential is continuous at the interfaces I-II and II-III. Thus the device satisfies equations (2.1) and (2.3) throughout the 2D region.

Figure 2.9: Exact solution of the 2D potential distribution ψ(x, y) in a compound dielectric RESURF device consisting of three regions (I, II and III). Region I (LI = 3 µm) has a linearly-graded field-plate potential from VFP = 0 V to VFP = 67.2 V, ND = 5 · 1015 cm−3 and t1 = t2 = 0.5 µm. Region II (LII = 4 µm) has a linearly-graded doping from ND = 5 · 1015 cm−3 to ND = 7.8 · 1016 cm−3 , VFP = 67.2 V and t1 = t2 = 0.5 µm. Region III (LIII = 3 µm) has a linearly-graded domain 2 thickness from t2 = 0.5 µm to t2 = 1 µm, t1 = 0.5 µm, ND = 7.8 · 1016 cm−3 and VFP = 67.2 V. Leftright boundary potentials: Vleft = 0 V, Vright1 = 246.7 V, Vright2 = 67.2 V + 179.4 V/ µm · (t1 + t2 − y).

2.5

Discussion

2.5.1

Effect of deviations from ideal RESURF on BV

The curved design of the left and right boundaries needed for ideal RESURF increases the total device length along the x axis. In Fulop’s approximation [35] breakdown occurs at a critical field Ecrit = 1/71 1/7 , where Af

L

Af = 1.8 · 10−35 cm6 /V7 is the ionization coefficient (in silicon) and L is the device length. The breakdown voltage of an ideal device with 6/7 curved boundaries is then BV curved = Ecrit L = L 1/7 . If the device has Af

straight boundaries, however, for the same length L the device will have a lower breakdown voltage because the boundaries do not have the ideal shape. The breakdown voltage with straight boundaries can be given by BV BV straight = ηBV curved , where η = BVstraight is defined as the ratio of breakcurved down voltages of a device with straight boundaries and that of a device with ideally curved boundaries with the same length L. The parameter η depends on the device length, geometry and doping profile, and can be extracted in simulations by calculating the ionization integral along the symmetry line y = 0 (where the Ex -field is maximum). In Fig. 2.10 η is shown for a device with graded field-plate voltage and ρ2 = 0 as a function of the length L for different values of the fixed charge ρ1 in Fig. 2.10a) and of the equivalent thickness teq in Fig. 2.10b). It can be seen that η reduces for increasing ρ1 and increasing thicknesses teq (assuming t1 = t2 ). The

Figure 2.10: Ratio between straight and curved Ex breakdown voltage (η = BV straight /BV curved ) for an n-type dielectric RESURF drift extension with graded field-plate potential (as in Fig. 2.5a) having a) different doping charges ρ1 = qND and b) different thicknesses teq (with t1 = t2 ).

25 CHAPTER 2. IDEAL RESURF GEOMETRIES

In Section 2.3, examples of ideal semiconductor-dielectric structures satisfying the RESURF condition have been shown. Deviations from ideal RESURF and other issues occurring in real devices are discussed in this section, which focuses on the shape of the boundaries (Sec. 2.5.1), linearly graded-potentials (Sec. 2.5.2), and premature breakdown (Sec. 2.5.3).

26 2.5. DISCUSSION

reduced values of η in these cases are caused by the more pronounced curvature of the equipotential lines, which increases the difference between the curved and straight device designs and breakdown voltages BV. As the device length increases η approaches unity because boundary shape related effects become less significant for L  t1 . The value of η is close to unity also for very short devices, since in the limit of t1  L the electric field will behave as in a parallel plate capacitor and the effect of curvature on BV becomes small. As a result, for the simulated devices in Fig. 2.10, the parameter η reaches a minimum for a device length L ≈ 1 − 5µm. This is a significant result since devices with drift lengths in this range have a breakdown voltage of BV ≈ 20 V − 100 V, which is typical in smart power and automotive applications [3].

2.5.2

Boundary conditions with graded potential

A gradient is needed to achieve the optimal RESURF condition using the methods shown in Sec. 2.3. Grading the potential at the field-plate, dielectric boundaries and/or at the left and right boundaries is possible. In practice, graded potentials are not easily implemented. A possibility is to split the graded potential in a number of constant voltage field-plates [36], or to use conductive resistive elements [37]. It is also possible to exploit structural symmetries to achieve a graded potential on a boundary without a field plate. For example, the periodicity in the y-direction is exploited in superjunctions resulting in the charge balance condition (2.10). Similarly, a symmetric design around the x = L line can be used to mimic a linearly graded potential on the right boundary.

2.5.3

Junction, vertical and dielectric breakdown

Besides breakdown caused by the Ex -field, device breakdown could also be caused by the Ey -field [27]. In order to arrive at an optimized device design, it is therefore necessary to design the RESURF device such that the ionization integral along the electric field lines in the y-direction is negligible compared to the x-direction. In addition, avalanche breakdown of the pn junction comprising the pwell (for an NMOS) of the power transistor and the drift extension has to be taken into account. As shown in [27], the condition ND (x = 0) · t1 6 1012 cm−2 [24] limiting the RESURF dose at x = 0 can be used for this purpose in silicon-based devices. In the presence of dielectrics, the magnitude of the electric field should not exceed the critical value for dielectric breakdown. Finally, it is worth mentioning that for electric field magnitudes exceeding 70 V/ µm in silicon band to band tunneling also limits the breakdown voltage [29, 38].

2.6

Conclusions

27 CHAPTER 2. IDEAL RESURF GEOMETRIES

In this chapter, 2D analytical solutions of Poisson’s equation have been derived that satisfy the ideal RESURF condition (2.1). Several examples of how these solutions can be used for ideally shaping the geometry of fieldplate and periodic RESURF devices have been demonstrated. In addition, an analytical solution for optimizing DIELER RESURF devices has been derived. The analytical solutions provide insight in the physics and facilitate device optimization. The different geometry shaping procedures demonstrate the degrees of freedom available for optimizing RESURF devices. Moreover, the derivation of the shape of idealized structures allows analysis of deviations from the ideal shape in practical devices. For instance, it is shown that devices with curved boundaries can have a higher breakdown than devices with straight boundaries. With sufficient technological control over device dimensions and doping profiles, the demonstrated device geometries with curved boundaries and field plates can lead to optimized RESURF drift extensions.

CHAPTER

B REAKDOWN VOLTAGE AND SPECIFIC ON - RESISTANCE Abstract This chapter focuses on the trade-off between the specific onresistance and the off-state breakdown voltage in RESURF power devices. Analytical equations are derived based on the RESURF theory presented in Chapter 2 to estimate the specific on-resistance as a function of the off-state breakdown voltage in an optimized RESURF drift extension. In order to provide equations that are independent of the device orientation with respect to the wafer plane, the on-resistance times volume (rather than times unit area) is considered. It is shown that a switchable field plate electrode acting on the drift extension can be used to further reduce the on-resistance without affecting the Ex -field distribution in the off-state. Applying a positive potential (in case of an n-type MOSFET) on the field-plate boosts the on-state performance by creating an accumulation layer in the drain extension which reduces the on-resistance. This concept is practically demonstrated in a silicon-on-insulator (SOI) Laterally Diffused MOS (LDMOS) transistor fabricated in NXP’s 140nm Advanced Bipolar CMOS DMOS (A-BCD9 [3]) technology which features a controllable field-plate electrode which is separated from the gate electrode. This device is referred to as the boost transistor. It provides a specific on-resistance Ron V reduction of 15% compared to the single gate device without requiring any process modification, as is demonstrated by measurements and TCAD simulations. The on-state power dissipation with respect to standard LDMOS designs is reduced and a driving circuit is proposed maintaining the breakdown voltage at the nominal value of 70 V in the off-state. This chapter was partly published in the ISPSD Proceedings [39]. For clarity it has been expanded with additional figures and explanations.

29

3

wafer reference frame

L = device length in the current flow direction (x) t = device thickness in the RESURF field direction (y) W = device width in the direction orthogonal to the x-y plane

Domain 2

Domain 2

3.1. Ron V -BV TRADE-OFF IN RESURF DRIFT EXTENSIONS

Domain 1

Domain 1

Domain 2

t

Domain 2 Domain 1 Domain 2 Domain 2

30

t

Figure 3.1: Wafer plane and possible spatial orientations for a 2D RESURF device. The half-thicknesses of each domain are denoted as t1 and t2 as in Fig. 2.2.

3.1 Ron V-BV trade-off in RESURF drift extensions In order to improve the performance of power transistors, the specific onresistance Ron A has to be reduced without affecting the off-state breakdown voltage BV [? ]. In this section, the trade-off between Ron A and BV of the elementary RESURF configurations shown in Sec. 2.3 are analyzed. For this purpose, non-ideal RESURF devices with straight electrodes are considered using the parameter η defined in Sec. 2.5.1 for calculating the breakdown voltage BV straight . The specific Ron A (and therefore the Ron A − BV trade-off) depends on the orientation of the device with respect to the plane of the wafer. In order to provide equations that are independent of the orientation of the device, the product between the on-resistance Ron and the device volume V (V = W · L · t, see Fig. 3.1) is considered and defined as Ron V. From Ron V it is possible to derive Ron A for different device orientations with respect to the wafer plane. The device dimensions are defined as follows: L is the device length in the direction of the current flow (x-direction, see Fig. 2.2), t is the device thickness in the direction perpendicular to the interface plane between layer 1 and layer 2 (y-direction), and W is the device width in the z-direction perpendicular to the x-y plane. The wafer plane is named the xw -yw plane, and zw is the direction perpendicular to it. As shown in Fig. 3.1, three possible device orientations are possible for a 2D device (assuming that the wafer directions xw and yw are equivalent). 1. Lateral device with out-of-plane RESURF: x = xw , y = zw and z = yw [9, 39]. The device area is named ALk = tVav = W · L, where tav is the

average device thickness along the length L in the x-direction. 2. Lateral device with in-plane RESURF: x = xw , y = yw and z = zw V [32]. The device area is named AL⊥ = W = L · tav . 3. Vertical device: x = zw , y = yw and z = xw [40]. The device area is named AV = VL = W · tav .

Af

where t1 and t2 are half the thicknesses of domains 1 and 2, respectively (see Fig. 2.2). The parameter η represents the ratio between the off-breakdown voltage of a real device with straight boundaries and that of an ideal device with curved boundaries (see Section 2.5.1). Using the definitions (3.1), the Ron V trade-off is estimated for the elementary RESURF structures presented in Sec. 2.3. In order to analytically evaluate the conductance σeff in all cases, it is assumed for simplicity that the mobility µn is independent of the doping charge (ρ1 = qND for an n-type semiconductor and ρ1 = qNA for a p-type semiconductor, where q is the elementary charge and ND and NA are the ionized donor and acceptor concentrations, respectively). The Ron V expressions for field-plate assisted RESURF are:    Af 1/3    7  t2 η 7/3  (graded VFP ) R V = 1 +  on  µn ρ1 t1 · BV  !      Af 1/3 t  teq 2 1+ t2 η7 BV 1 Ron V = ln 1 − BV 4/3 (graded ρ1 ) . ρ2 t2 2ε1 µn 2  V + FP  2ε2     Af 7/3     7  t (BV) Ron V = η 1 + 2,avt1 · BV 7/3 (graded t2 ) µn ρ1 (3.2) The Ron V expressions for periodic RESURF are:    Af 1/3    7  Ron V = ηµn ρ1 1 + tt12 · BV 7/3 (superjunction) . (3.3)    t2 2 Ron V = 1 (DIELER) 1 + · L(BV) µn ρ1 t1

CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

In a lateral device, the current flows parallel to the wafer plane, in a vertical device it flows perpendicular to it. Out-of-plane RESURF means that the RESURF field Ey in Fig. 2.1 acts in the direction perpendicular to the wafer plane, while in-plane RESURF means that Ey is in the wafer plane. In a vertical device, the RESURF field is always in-plane. The following definitions are introduced:  RL  t2,av = L1 0 t2 (x) dx        V = W · L · 2t1 · 1 + tt2,av   1     Aflow = 2t1 · W    −1  R L σeff = L1 0 µn ρ11 (x) dx , (3.1)    L  Ron = σeff A   flow   2    Ron V = σLeff · 1 + tt2,av  1    BV = η L6/7 1/7

31

3.1.1

32

Design of optimized devices

3.1. Ron V -BV TRADE-OFF IN RESURF DRIFT EXTENSIONS

Numerous trade-offs need to be considered in order to design drift extensions that are optimized in terms of Ron V − BV. Analytical and/or numerical optimization routines can be used in order to find stationary points in the parameter space comprising the design parameters (ε1 , ε2 , t1 , t2 , ρ1 , ρ2 , L, VFP ). Despite the mathematical complexity of the problem, some optimization guidelines can be provided based on practical considerations and the RESURF theory in Chapter 2. For a more detailed analysis, the reader can refer to [26, 27] and Chapter 2 of [9]. We assume that the material of domain 1 is known and determined by the technology. Hence, the dielectric constant ε1 is fixed. The dielectric constant ε2 of domain 2 depends on whether one wants to use dielectric RESURF or pn junction RESURF. Assuming that the choice depends on the available technology, the value of ε2 is also fixed. In the case of dielectric RESURF, the charge density will be ρ2 = 0, while in pn junction RESURF ρ2 6= 0 and its sign will be opposite to the sign of ρ1 . Using these assumptions, the parameter space is reduced to (t1 , t2 , ρ1 , ρ2 , L, VFP ). At this point, the procedure outlined in Section 2.3 can be followed depending on the type of RESURF one wants to achieve (field-plate assisted or periodic RESURF). However, the proposed procedure does not allow to uniquely determine all parameters since some degrees of freedom are available in the choice. In other words, infinite combinations of devices that satisfy the ideal RESURF condition (2.1) exist in theory for each RESURF type. In order to narrow down the possibilities and to arrive to a unique optimized device, the following constraints can be introduced: 1. The semiconductor in domain 1 should be fully depleted in order to prevent pn junction breakdown. 2. The vertical field Ey in domain 1 should not exceed the critical value for vertical breakdown. 3. Ron V should be minimized for a given BV. These constraints can be translated into mathematical inequalities which restrict the space of available options for the design parameters. Constraint (1) is a fundamental assumption underlying the entire RESURF theory presented in Chapter 2. The whole semiconductor volume has to be occupied by fixed charge in order to assume that the fixed charge ρ1 is a tunable parameter only depending on the doping concentration. Both constraints (1) and (2) set a limit to the maximum doping dose (ND · t1 for n-type and NA · t1 for p-type) allowed inside domain 1. In other words, the parameters ρ1 and t1 cannot be chosen independently and arbitrarily large, since if their product exceeds a critical value premature breakdown will occur. This is a crucial aspect with major implications on the Ron V − BV trade-off. By simply considering the ideal RESURF theory based on the optimization

ρ1 (x = 0) · t1 (x = 0) 6

ε1 Ecrit , q

(3.4)

where Ecrit is the critical field at which breakdown occurs. For an n-type silicon drift extension, assuming Ecrit ≈ 2·105 V/cm the maximum RESURF dose is ND · t1 ≈ 1012 cm−2 [24, 27]. The inequality for constraint (2) can be found by using the Fulop’s approximation [35] to evaluate the ionization integral along the y-direction at x = L (drain side of the device), where the magnitude of Ey is maximum. The integration yields: ρ1 (x = L) · t1 (x = L)7/8 6



8 Af

1/8

7/8

ε1 ,

(3.5)

for both dielectric and pn junction RESURF. A final comment is given on the choice of the thickness t2 . Since domain 2 does not carry any current in the on-state 1 , t2 does not affect Ron but only the device volume V. Therefore, in order to minimize Ron V for a given BV, the value of t2 should be as small as possible. Using a thin dielectric or semiconductor layer t2 reduces the voltage drop across domain 2 and increases the magnitude of the Ey -field across domain 1 for a given BV. A larger Ey in domain 1 results in a better RESURF effect allowing to increase the charge density QRESURF (i.e., the doping dose), resulting in a lower Ron . On the other hand, it might cause premature vertical breakdown. For this reason, t2 cannot be chosen arbitrarily small. Further limitations to the minimum allowed thickness t2 are imposed by (1) the available technology, (2) the occurrence of dielectric or avalanche breakdown inside domain 1 There are some exceptions, see e. g. [41], in which the p-layer is also used as a conductive layer.

33 CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

of the lateral field Ex , one might arrive to the erroneous conclusion that the specific on-resistance can be arbitrarily minimized by increasing the doping dose in domain 1. For instance, Fig. 2.1 suggests that a higher ∂E vertical field gradient ∂yy can be used to compensate the larger charge density ρ while still satisfying the ideal RESURF condition (2.1). In practice, increasing the value of ρ1 for a fixed t1 results in a higher doping dose which might cause the RESURF effect not to occur at all and could lead to pn junction breakdown at the source side of the device. On the other hand, if ρ1 is kept constant and a higher doping dose is achieved by increasing t1 , the magnitude of the vertical field Ey might become too large and vertical breakdown will occur towards the drain of the device. The maximum RESURF dose allowed by the constraint (1) can be calculated by imposing that the thickness t1 (x) does not exceed the extension of the depletion layer in the y-direction at any abscissa x. Since the magnitude of the vertical field Ey increases along the x-direction, it is sufficient to meet this condition at x = 0 (source side of the device), where the magnitude of Ey is the lowest, giving [16]:

Source

p+

Gate

Field plate (VFP)

n+ pwell

STI Racc Rdrift BOX

34

Drain

n+

Ron A BV Ldrift Lpitch Nfingers Wgate A

70 mΩ mm2 [48] 70 V 3 µm 10 µm 4 100 µm 500 µm2

3.2. IMPROVING THE Ron V -BV TRADE-OFF: THE BOOST TRANSISTOR

Figure 3.2: Schematic cross section of the LDMOS boost transistor and main device parameters. The field plate is connected to an additional boost electrode to achieve separate control over the drift resistance below the STI (Rdrift ). When a positive voltage on the field plate is applied, an accumulation of electrons occurs in the drift extension below the STI. This increased electron concentration reduces the on-state drift resistance. The table summarizes the key parameters of the LDMOS under study (see also Fig. 4.1). 2 and (3) material reliability issues which become relevant when large electric fields are applied to a semiconductor or dielectric layer for long stress times.

3.2

Improving the Ron V-BV trade-off: the boost transistor

As shown in Chapter 2, the breakdown voltage of power transistors can be improved using field plates to optimize the field distribution in the off-state. A controllable field-plate can also be used in the on-state to improve the current capability and/or switching characteristics of the device [27, 42– 47]. In the following, the operation of an n-type silicon-on-insulator (SOI) LDMOS with a separate field plate electrode on top of a shallow trench isolation (STI) region is discussed (Fig. 3.2) for improving the specific onresistance Ron V. A positive potential on the field-plate boosts the on-state performance by creating an electron accumulation layer in the drift region which reduces the on-resistance. For this reason, the device is referred to as the boost transistor, which is discussed in the next section. The proposed geometry has the advantage that it does not require complex processing to allow electrostatic control over isolated electrodes below the buried oxide, and is thus implemented in an existing SOI CMOS technology [3] without process changes. Although the required boost potential is high, it is shown that it can be taken from the supply without needing DC-DC converters or charge pumps to generate it. In this way, the driving circuit of the boost transistor can be kept relatively small.

3.2.1

Operation principle

Figure 3.2 shows a schematic cross-section of the boost transistor and its operation principle. The essential device modification with respect to the conventional LDMOS transistor is that the field plate on the STI region is

VFP = + 70V VFP = 0 V VFP = - 70V 35

Gate-to-source voltage (V)

Vgs = 3.3 V

VFP = + 70V VFP = 0 V VFP = - 70V Drain-to-source voltage (V) Figure 3.3: Measured a) Id − Vgs and b) Id − Vds DC characteristics at Tamb = 25 ◦ C for different field plate potentials. separated from the gate electrode and connected to an additional boost electrode. The operation principle is basically that a positive voltage on the boost electrode increases the electron concentration in the drain extension and thus reduces Ron . Figure 3.3 shows the effects of the field plate bias on the measured device Id − Vgs and Id − Vds DC characteristics, with positive field-plate voltages corresponding to higher on-state currents. The current increase for a large positive field plate potential is a result of the boosting effect on the on-resistance. The negative differential resistance in the Id − Vds characteristics (Fig. 3.3b) is due to self-heating [49–51]. The relatively-small change in the threshold voltage could be attributed to capacitive effects from the terminal connections.

3.2.2

Effect of VFP on Ron and BV

This section focuses on the effect of the boost electrode on the behavior of the boost transistor. Figure 3.4 shows an on-state TCAD simulation [52] for both a negative

CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

Vds = 50 mV

36 3.2. IMPROVING THE Ron V -BV TRADE-OFF: THE BOOST TRANSISTOR

Figure 3.4: On-state TCAD simulation results [52] showing electron concentration (color scale, Vgs = 3.3 V and Vds = 50 mV) for a) negative (VFP = −70 V) and b) positive field plate potential (VFP = +70 V). The solid black lines indicate the edge of the depletion region. For negative VFP a depletion region forms below the STI, increasing the on-resistance (see Fig. 3.7a), whereas for positive VFP an accumulation region forms that reduces the on-resistance.

Figure 3.5: Off-state TCAD simulation showing impact ionization rates (color scales) at breakdown (Vgs = 0 V and Vds = BV) with the field plate connected to the gate.

Figure 3.6: Off-state TCAD simulations showing impact ionization rates (color scales) at breakdown (Vgs = 0 V and Vds = BV) for a) negative field plate potential (VFP = −70 V) and b) positive field plate potential (VFP = +70 V). The solid black lines indicate the edge of the depletion region.

200 180

Measured Simulated

160 140

Ref. device w/o f. plate electrode

(Fig.63.4b)

120 Vgs6=63.36V 100

(b)

Off−state6breakdown6voltage6(V)

(Fig.63.4a)

Vds6=6506mV −60 −40 −20 0 20 40 Field 6 plate6potential6(V)

Vgs6=606V 80 Ioff6=616nA/66m µ 70 60 50

∆Ron/Ron = 15%

On6resistance6(Ω)

(a)

60

Measured Simulated

Ref. device w/o f. plate electrode

(Fig.63.6a)

(Fig.63.5)

(Fig.63.6b)

40 30

−60 −40 −20 0 20 40 Field plate6potential6(V)

60

Figure 3.7: Comparison of measurement and TCAD simulation results. a) On-resistance and b) off-state breakdown voltage of the boost transistor as a function of the field plate potential. The maximum on resistance improvement for VFP = +70 V is 15% with respect to a measurement (red dashed line) on a reference device with identical layout, but without a slit separating the field plate electrode and gate (thus VFP = Vgs ).

37 CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

(Fig. 3.4a) and a positive (Fig. 3.4b) field plate potential. For a negative VFP a depletion region forms below the STI region, increasing the on-resistance, whereas for positive VFP an accumulation region forms that reduces the on-resistance. Figure 3.5 shows off-state TCAD simulation results showing impact ionization rates at breakdown (Vgs = 0 V and Vgs = BV) when the field plate is connected to the gate. The impact ionization rate is fairly uniform across the drift extension due to the RESURF effect. However, when the field

3.2. IMPROVING THE Ron V -BV TRADE-OFF: THE BOOST TRANSISTOR

3.2.3

Driving circuit

Since the boost transistor requires independent electrostatic control over the field plate potential a dedicated driver circuit is required. An example of a schematic diagram of such a dedicated driver circuit (proposed by A. van der Wel in [39]) is sketched in Fig. 3.8. The load Zload can be driven

Floating supply

Vsupply Zload

Level Boost transistor shifter driving circuit

VFP Vgate

Boost transistor

38

plate is biased, the impact ionization rate locally increases, as shown in Figure 3.6. Off-state TCAD simulation results are shown in Fig. 3.6a for a negative field plate potential (VFP = −70 V) and in Fig. 3.6b for a positive field plate potential (VFP = +70 V). For negative VFP large vertical electric fields Ey near the drain increase the impact ionization rate and hence lower the off-state breakdown voltage (see Fig. 3.6a). For positive VFP the drain extension does not fully deplete, resulting in a smaller effective sourcedrain distance that causes higher lateral electric fields Ex , increases the impact ionization rate and lowers the breakdown voltage (see Fig. 3.6b). Figure 3.7 shows measurements of on-resistance Ron (Fig. 3.7a) and off-state breakdown voltage BV (Fig. 3.7b) as a function of the boost voltage. Good agreement is obtained between measured and simulated results for VFP ranging between −70 V and +70 V. An on-resistance reduction of 15% is measured at VFP = +70 V with respect to the design where the field plate is connected to the gate electrode. Since the positive field plate voltages needed for low Ron result in a significant BV reduction due to the non-fully depleted drain extension in the off-state (Fig. 3.6b), one needs to ensure that VFP = 0 V in the off-state.

Vcontrol Delay block

Figure 3.8: Circuit diagram of an example implementation of the boost transistor driver.

transients

delay

FP

FP

delay

Figure 3.9: Measurement of resistive load switching with the boost transistor. A 15%-reduction in the power dissipated in the transistor (Pdiss ) can be achieved by driving the boost electrode during the on-state. The figures below show a zoom in the turn-on and turn-off boost transients. using a control voltage Vcontrol . An inverter is used to set the potential VFP . A high-side gate driver with level shifter and floating supply is used to drive the PMOST of the inverter. A delay block is used to make sure that the boost voltage is only applied in the on-state and VFP = 0 V in the off-state. Since the boost voltage is taken from the supply, no DC-DC

CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

FP

39

40 3.2. IMPROVING THE Ron V -BV TRADE-OFF: THE BOOST TRANSISTOR

converters or charge pumps are needed to apply a high boost voltage. In order to experimentally demonstrate the transient operation of the boost transistor, the boost and gate waveforms of the driving circuit in Fig. 3.8 have been applied using function generators as is shown in Fig. 3.9 by the red and blue dashed lines. While driving a resistive load, the power dissipated in the boost transistor (green line) has been measured by monitoring its current and voltage using an oscilloscope. The experiment has shown that applying 50 V on the boost electrode reduces the power dissipation by 15% in agreement with the DC measurements in Fig. 3.7a. As shown in the zoomed-in plots of Fig. 3.9, the transient time of 3 µs needed for the power reduction in the boost transistor is equal to the time of the voltage ramp on the boost electrode. This shows that the intrinsic response time of the boost effect is significantly less than 3 µs. Further research is needed to investigate the transient behavior and the switching losses of the proposed device at higher ramp rates and frequencies (see 7.3).

3.2.4

Advantages and disadvantages

For a practical application of the boost transistor it is important to evaluate whether the effective specific on-resistance Ron V of the boost transistor is still smaller than that of a conventional transistor when the added area needed for the driver circuit is taken into account. If the voltage from the system power supply is used for boosting, the driving circuit can be kept small since it does not require a DC-DC converter or charge pump. For a 1 mm2 boost transistor, the boost driving circuit (Fig. 3.8) is estimated to have an area of 0.05 mm2 , only 5% of the total area. Hence, the increase in additional area is less than the 15% reduction in the Ron and therefore the effective Ron A (and Ron V) of the boost transistor is clearly lower than that of the conventional (non-boosted) LDMOS. In terms of on-state power dissipation it is therefore better to use the boost transistor than to increase the transistor area by 5%. However, for high frequency applications it expected that switching losses are higher in the boost transistor than in the conventional LDMOS counterpart. The reason for this is that the voltage on the boost electrode (70 V) is much higher than the voltage on the gate (and connected field-plate) of a conventional transistor (3.3 V). This increases the total charging energy 12 CV 2 and associated switching losses. At high frequency operation this increase in switching losses can become substantial. Therefore the application potential and benefits of the boost transistor will be largest in applications with low switching rates. It is concluded that for these applications the boost transistor can offer lower on-state power dissipation and smaller system area. The boost transistor does not require any process modifications. It can be implemented in almost any type of smart power technology ([2]) by a small device layout modification. Further Ron V reduction (> 15%) can

be achieved by process modifications such as thinner field plate oxides or thinner SOI drift regions.

3.3

Conclusions 41 CHAPTER 3. BREAKDOWN VOLTAGE AND SPECIFIC ON-RESISTANCE

In this chapter, the trade-off between the specific on-resistance expressed in units volume Ron V and the off-state breakdown voltage BV of RESURFbased power devices has been analyzed. Analytical expressions for evaluating this trade-off have been provided for ideal RESURF structures. It has been shown with measurements and TCAD simulations that a switchable field-plate electrode, separated from the gate, can be used to further reduce the on-resistance of an LDMOS transistor without affecting the off-state breakdown voltage. The device based on this concept, namely the boost transistor, has been analyzed in detail by sweeping the field-plate potential from negative to positive values and evaluating its effect on the off-state electric field and on the on-state carrier concentrations. A driving circuit with minimal area for the additional field-plate electrode has been proposed to reduce the on-state power dissipation in applications with relatively-low switching frequencies.

CHAPTER

J UNCTION TEMPERATURE Abstract In this chapter, three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for evaluating the junction temperature of an SOI LDMOS power transistor are discussed and experimentally compared. The device under test is provided with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. On wafer measurements have been performed on a thermal chuck in the temperature range 25 − 200 ◦ C to extract self-heating information and to predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques has been achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.

This chapter was published in the ICMTS Proceedings [51]. For clarity it has been expanded with additional explanations.

43

4

2Ldrift

Wgate = Nfingers·W A = 0.5Wgate·Lpitch

Lpitch

W

44 4.1. SELF-HEATING IN POWER DEVICES

Ron A BV Ldrift Lpitch Nfingers Wgate A

70 mΩ mm2 70 V 3 µm 10 µm 8 140 µm 700 µm2

Figure 4.1: Top. Schematic top view of the LDMOS with embedded center and edge sense-diodes. Bottom. Cross-section of the center LDMOS cell showing that the diode is connected between the p-well contact B (shorted to the source S, and representing the anode A) and the cathode K. The table on the right summarizes the main device parameters and dimensions.

4.1

Self-heating in power devices

Since optimization and shrinking of the geometry has pushed the current densities and operating temperatures of power devices close to the physical limits [4], the issues related to self-heating (see Sec. 1.4.2) have become more and more relevant. In order to guarantee high-performance and reliable transistor operation, it is essential to maximize the current density without exceeding a certain temperature value that could lead to device failure. Therefore, good techniques for transistor temperature measurements are crucial. Several techniques for temperature measurements based on different physical principles (electrical, optical or physical contacting) have been reported [53]. Among these, electrical techniques allow a quick, inexpensive and noninvasive estimation of the device thermal properties by exploiting standard electrical equipment. The advantage is that electro-thermal device characterization can be performed on a single setup allowing for simultaneous extraction of electrical and thermal device parameters. This information can then be used for extracting the thermal network parameters used by electro-thermal simulators in circuit design. This chapter aims at benchmarking three electrical techniques reported earlier [54–56] for accurate temperature estimation by reporting a direct comparison on the same device. The device under test (Fig. 4.11 ) is an SOI-LDMOS transistor with embedded sense diodes in the center and at 1 Dimensions relative to the device cross section are NXP confidential and cannot be provided. Some information can be inferred from [57].

the edge for providing local temperature information. The schematic electrical configurations of the selected techniques (pulsedgate, AC-conductance and sense-diode, Fig. 4.2) are presented in Section 4.2 while the experimental results are compared in Section 4.3. Based on these results, in Section 4.4 a benchmarking analysis is provided, which aims at establishing guidelines for the appropriate choice of the temperature measurement technique according to specified criteria. Finally, the chapter is summarized in Section 4.5.

Three electrical techniques for temperature evaluation

Three electrical techniques for temperature evaluation are compared: (a) the pulsed-gate technique (Fig. 4.2a), which determines the junction temperature Tj based on the comparison of pulsed (self-heating free) Id0 -Vds curves and DC Id -Vds curves [54]; (b) the AC-conductance (gac ) technique (Fig. 4.2b), which determines the thermal impedance Zth , by ACmodulation of the dissipated power Pd , from the frequency-dependent output conductance gac [55, 58]; and (c) the sense-diode technique (Fig. 4.2c), exploiting the linear voltage-temperature relationship in diode sensors embedded in the LDMOS [56]. For each technique, on-wafer measurements were performed in the chuck temperature range Tamb = 25 − 200 ◦ C and the extracted junction temperatures Tj in the steady-state (DC) limit are compared in Section 4.3.

4.2.1

Pulsed-gate technique

The pulsed-gate technique is based on the comparison of the time-domain response of the LDMOS when driven by pulses having either a much shorter or a much longer duration than the device thermal time constant (τth ). For the device under test, this value is τth ≈ 10 µs, as can be estimated from the exponential behavior of the transient current and temperature in

Vdd

Vg

Vdd

Vg

Vdd

Bias-T

(a)

(b)

(c)

Figure 4.2: Schematic electrical configurations for: a) pulsed-gate technique, b) AC-conductance technique, c) sense-diode technique.

CHAPTER 4. JUNCTION TEMPERATURE

4.2

45

a) Pulsed ( Tamb) DC (Tamb = 25 °C)

40 = b

° 25

C

20 T am

b

=

10

50

5

50

Vds = 2.5 -12.5 V

4.2. THREE ELECTRICAL TECHNIQUES FOR TEMPERATURE EVALUATION

C

0° 20

Drain current (mA)

T am

30

0 0

Pulsed drain current Id0 (mA)

46

Drain current (mA)

50

40 30 20 10 0

10

0

20 40 60 80 100 Time (ns)

15

Drain-to-source voltage (V)

20

b)

Vds = 2.5-12.5 V

Data Fit (4.1)

40 30 20 10 25

50 75 100 125 150 175 200 Chuck temperature Tamb(°C)

Figure 4.3: Operating principle of the pulsed-gate technique. a) Determination of the junction temperature Tj by comparison between the isothermal Id0 -Vds calibration curves obtained from 50-ns pulsed measurements at different chuck temperatures (dashed lines) and Id -Vds DC characteristics at Tamb = 25 ◦ C (solid line). The circles represent the intersection points where calibration data are available. Inset shows the 50-ns pulsed measurements at different Vds -values (Tamb = 25 ◦ C), from which the isothermal Id0 -Vds characteristics were extracted. b) Current-temperature (Id0 − Tamb ) calibration curves for different drain voltages Vds fitted according to (4.1).

Id0 (Tamb ) = Id0 (Tref ) · e−

Tamb −Tref θ

,

(4.1)

where Tref is an arbitrary reference temperature (Tref = 25 ◦ C in this work) and θ is a fitting temperature depending on Vds . Id0 represents the selfheating free current, while the actual DC current is denoted by Id . The exponential behavior in the Id0 − Tamb relationship (4.1) originates from the temperature dependence of the saturated carrier velocity in the drift region [59]. By fitting the parameter θ to experimental data, the exponential fit can also be extended to the linear operating region, where self-heating is less relevant. The DC Id -Vds characteristics, affected by self-heating, have been extracted using 2 ms pulses and then compared to the Id0 -Tamb calibration curves in order to extract the junction temperature Tj (for each Vds ), as follows: Id (Tj ) = Id0 (Tamb ) · e−  Tj = Tamb + θ · ln

Tj −Tamb θ

Id0 Id

,

(4.2)

 ,

(4.3)

A graphical representation of the method is shown in Fig. 4.3a. The exponential fit also allows to extrapolate the junction temperature Tj outside the Id0 -Tamb calibration range, making it especially useful for devices in strong self-heating conditions. Although the accuracy of the extrapolated temperature cannot be easily predicted, good quantitative agreement is obtained between the three different techniques (see Sec. 4.3) also outside the calibration range.

4.2.2

AC-conductance technique

The AC-conductance technique relies on a frequency-domain characterization of the differential (small-signal or AC) output (or drain) conductance

47 CHAPTER 4. JUNCTION TEMPERATURE

Fig. 4.5b (see Sec. 4.2.3). The schematics of the experimental setup for the pulsed-gate technique is shown in Fig. 4.2a. A signal generator has been used to switch on and off the gate while a DC bias Vdd has been applied to the drain. For each drain bias, the drain current has been monitored by measuring the potential drop across a 50 Ω resistor (the ammeter in Fig. 4.2a) as a function of time. The output characteristics have been extracted for two different pulse widths: a) 50 ns (self-heating free characteristics, Id0 -Vds ) and b) 10 ms (DC characteristics, Id -Vds ). A pulse width of 10 ns is shorter than the thermal time constant τth of the LDMOS, and self-heating is negligible in this time frame. As a result, the isothermal Id0 -Vds characteristics (for Tamb = 25 − 200 ◦ C) have been obtained, from which current-temperature (Id0 -Tamb ) calibration curves (Fig. 4.3b) have been extracted (for each Vds ) using the following exponential fit (see Section 4.4 on temperature calibration):

48 4.2. THREE ELECTRICAL TECHNIQUES FOR TEMPERATURE EVALUATION

gac to extract self-heating information. The differential output conductance gac represents the frequency-dependent slope of the Id -Vds characteristics at a given bias condition (i. e. , fixed DC gate and drain potentials). The experimental setup for the AC-conductance technique is shown in Fig. 4.2b). While the gate and drain are DC-biased, a small AC signal is coupled to the drain via a bias-tee, and gac is measured while sweeping the frequency of the AC source. An impedance (or vectorial) analyzer (Agilent 4204A in this work) can be used for the purpose. An intuitive explanation of the technique (Fig. 4.4) can be given as follows [58]. The drain conductance gac is a measure of the small-signal temperature fluctuations (around a DC junction temperature Tj 6= Tamb ) induced when AC power is dissipated inside the LDMOS. If the frequency f of the AC source is much higher than 1 1 τth (f  τth ), the device does not respond thermally to the dissipated AC power and its temperature does not vary during the small-signal operation. Under these conditions, there is no dynamic self-heating, and the high-frequency AC-conductance (ghf in Fig. 4.4a) is simply determined the current fluctuations induced by the AC variation of the drain potential Vds . On the other hand, if f  τ1th , the junction temperature responds to the dynamic drain voltage variation and fluctuates around a DC value. A temperature fluctuation will induce a current fluctuation (since the current is temperature dependent) leading to a variation of the DC-conductance (gdc ) with respect to the high-frequency conductance (ghf ). Under strong self-heating conditions, the DC drain conductance can become negative, meaning that Tj -fluctuations induce a 180◦ phase-shift between the AC current and voltage on the drain. This behavior is responsible for the negative slope of the DC output characteristics observed in saturation. The frequency dependent thermal impedance Zth (Fig. 4.4) is extracted according to [60]: (gac (f) − ghf ) · (Id + gdc Vds ) . (4.4) Zth (f) = SI · (Id + gac (f)Vds ) · (Id + ghf Vds ) From (4.4), the DC thermal resistance Rth and the junction temperature Tj are given by: Rth = Zth (f = 0) =

(gdc − ghf ) , SI · (Id + ghf Vds )

Tj = Tamb + Zth Vds Id

(4.5)

(4.6)

where: gdc = gac (f = 0) =

  dId dId 1 , SI = and ghf = gac f  . dVds dTamb τth

(4.7)

In order to apply (4.4)- (4.5), a DC calibration of the derivative of the DCcurrent Id with respect to the chuck temperature Tamb (SI -Tamb calibration) is needed.

a) C

C

am

0=°

Pulsed DC

mb

10

0.2

Tj=200=°C

=2 0

T

20

0

0

5 10 15 Drain=voltage=CV0

°C Tamb =25=°C

0

g dc

500

g hf

b

=2

5=°

30

−0.2 0 10

Thermaliimpedancei(°C/W)

g hf g dc

Ta

0.4

Drain=current=CmA0

0.6

40

2

10

∆g

20

Vgs=3.3=V Vds=11.5=V 4

10 Frequency=CHz0

6

10

b)

Tamb =25i°C Vgs =3.3iV Vds=11.5iV

400 300 200 100 0 0 10

2

10

4

10 Frequencyi(Hz)

6

10

Figure 4.4: Operating principle of the AC-conductance technique. a) Differential output conductance gac as a function of the frequency. The difference between the high-frequency value (ghf ) and the DC value (gdc ) of gac (∆g = ghf − gdc , see also inset) is used to extract information about the device self-heating . b) Frequency-dependent thermal impedance Zth according to (4.4).

49 CHAPTER 4. JUNCTION TEMPERATURE

Output=conductance=CmS0

0.8

4.2.3

50

Sense-diode technique

4.2. THREE ELECTRICAL TECHNIQUES FOR TEMPERATURE EVALUATION

The sense-diode technique exploits the voltage drop across a forwardbiased pn junction as a temperature sensitive parameter. Such a temperature sensor can be integrated in the LDMOS design with minimal area occupation by introducing an additional n+ -diffusion (the cathode K) in the p-well of the active cell where the temperature Tj has to be detected (see Fig. 4.1). In this way, a pn junction is formed between the body/anode (B/A) and the cathode (K) contacts. This principle can be applied to both vertical (VDMOS) and horizontal (LDMOS) devices [56]. When a constant current is injected through a pn junction, the forward voltage drop Vf is temperature dependent. In particular in this diode Vf linearly decays with a rate of approximately 2 mV/K, representing the diode sensitivity. The experimental setup for exploiting the integrated diode-sensor during the LDMOS operation is depicted in Fig. 4.2c). While the device is biased in the desired operating condition, a 50 µA-current is injected through the sense-diode and the forward voltage drop is measured. Then, the junction temperature Tj is inferred from the Vf -Tamb calibration curve (Fig. 4.5a). In this work, the sense-diode technique has been applied while driving the gate with long (2 ms) pulses in the DC limit. Such a configuration has the following advantages: (a) it allows to analyze thermal transients by monitoring Vf with an oscilloscope (Fig.4.5b); (b) it does not require a prior diode calibration, since the calibration curves are obtained from the Vf waveforms when the device is switched off (Vgs = 0 V) and cooled down (Tj = Tamb ). In order to obtain accurate experimental results, the following assumptions should be verified in the test-structure design and experimental setup: • The sense-diode should be located as close as possible to the active area of the LDMOS cell. • The sensing current across the diode should be low enough to prevent self-heating of the diode itself. A more detailed analysis [61] shows that the optimal choice of the diode current derives from a trade-off between negligible diode self-heating and sensitivity and linearity of the Vf -Tamb calibration curve. Based on this trade-off, a value of 50 µA has been selected for the measurements. • The LDMOS and the diode operation should not mutually interfere. Since the diode current is about three orders of magnitudes smaller than the on-state LDMOS current, its influence on the on-state LDMOS behavior is not relevant. On the other hand, the diode is not affected by the LDMOS electron current since the cathode K is junction isolated from the channel region.

a)

250

30 200 ForwardTdropT(V)

20 10 0 0

0.8

150

0.7

100

0.6 0.5

50 50 100 150 200 TemperatureT(°C)

JunctionTtemperatureT(°C)

300

Tamb =25T°C Vgs=3.3TV

0 5 10 15 20 Drain-to-sourceTvoltageT(V)

40

300

30

225

20 10 0 0

Tamb =258°C Vgs =3.38V Vds =188V 40

80 Time8(µs)

150 75

120

Junction8temperature8(°C)

Drain8current8(mA)

b)

0

Figure 4.5: Operating principle of the sense-diode technique. a) The forward voltage drop Vf for 50 µA injected current is measured while sweeping the drain voltage during the Id -Vds characterization (left axis), and the junction temperature (right axis) is obtained from the Vf -Tamb calibration scale (see inset). b) Transient behavior of the drain current (left axis) and junction temperature (right axis) during pulsed-gate operation with an ontime of 100 µs. The temperature spikes occuring at turn-on (t = 20 µs) and turn-off (t = 120 µs) are artifacts induced by the non-ideal diode behavior.

51 CHAPTER 4. JUNCTION TEMPERATURE

DrainTcurrentTId (mA)

40

4.3

52

Experimental results

4.3. EXPERIMENTAL RESULTS

The measurement results obtained with the three techniques are shown in Figs. 4.6-4.7. Good agreement is obtained between the pulsed-gate, ACconductance and center diode results. The side diode measures a lower temperature because of the temperature gradient between the center and the side cell of the device. A minor mismatch is noted between the sensediode and the other techniques (Fig. 4.6a and 4.7a) for Tamb = 200 ◦ C and Tj > 350 ◦ C, a temperature range where calibration data are not available and extrapolation has been used. A possible explanation for the mismatch can be given as follows: both the pulsed-gate and AC-conductance techniques extract a weighted-average temperature across the LDMOS (see Section 4.4), underestimating the temperature with respect to the center sense-diode, which is positioned very close to the hottest region of the device. This is supported by the results in Fig. 4.6d, showing the extracted thermal resistance as a function of the junction temperature for the different techniques. The center diode measures a more uniform Rth -value across a wide Tj -range as a result of the better linearity of its Pd -Tj curves. Finite element simulations using COMSOL [34] have been performed to better investigate this aspect. The results (not shown) indicate that the thermal resistance of the structure is not significantly affected by the junction temperature, even when accounting for the temperature dependent thermal conductivity of silicon. The non-linearity of the Pd -Tj relationship has been found to be a measurement artifact occurring when the measured temperature is lower than the maximum temperature inside the device cross-section. Such as artifact can be the result of averaging effects, but can also occur when using sensors which are located too far away from the hottest spot. In the device under test, the maximum temperature is reached in the middle of the drift region, while the sense-diode is located in the p-well. However, the temperature gradient between these two regions is small given the compact geometry of the device, which has a drift length of L ≈ 3 µm for an off-state breakdown voltage of BV ≈ 70 V. As the device drift length (and the corresponding breakdown voltage) is increased, the sense-diode in the p-well becomes less and less accurate. This results in a worse linearity in the measured Pd -Tj curves.

4.4

Benchmarking analysis

A detailed benchmarking analysis aimed at understanding which technique is best-suited for the application of interest should consider the following aspects: (1) ease of application, (2) temperature calibration, (3) accuracy of the results. • Ease of application. From the setup point of view, the easiest technique to apply is the sense-diode technique, as it can be carried out

Junctionctemperaturec(°C)

400

a)

Vgs=3.3cV c°C 200 = C b T am 150c° = °C b T am =100c b T am 50c°C = b T am

350 300 250 200 150

Center diode Pulsed−gate

100 50 0 450 400

53

0.2 0.4 Dissipatedcpowerc(W)

0.6

b)

Vgs =3.3cV

350 300 250 200

c°C 200 = T amb 0c°C =15 b T am 0c°C =10 b T am c°C =50 b T am

150 100 50 0

Center diode Side diode

0.2 0.4 Dissipatedcpowerc(W)

0.6

Figure 4.6: Device temperature (Tj ) vs. dissipated power (Pd ) for different chuck temperatures (Tamb ) for: a) center sense-diode vs. pulsed-gate; b) center sense-diode vs. edge sense-diode.

with simple DC measurements when transient thermal information is not needed. The main drawback is the need for a special test structure (MOSFET with integrated diode sensor) which requires extra area and additional measurement terminals. On the other hand, the pulsed-gate and AC-conductance technique can be applied to standard devices, but they require time-domain and frequency-domain measurements, respectively. The pulsed-gate technique allows for direct extraction of the average temperature Tj , but it can be difficult to apply to devices with short thermal constants, since very short pulses are needed to acquire the isothermal Id0 -Vds characteristics. The AC-conductance technique is an indirect temperature measurement, but it is simple to perform since it only requires an impedance (or network) analyzer and can be applied to devices with various

CHAPTER 4. JUNCTION TEMPERATURE

Junctionctemperaturec(°C)

450

Junctionctemperaturec(°C)

4.4. BENCHMARKING ANALYSIS

Thermal resistance (°C/W)

54

450 400

a)

Vgs=3.3cV

350

c°C 200 = C b T am 150c° = C b T am 100c° = b c°C T am =50 b T am

300 250 200 150

Pulsed−gate AC−conductance

100 50 0 600 550

0.2 0.4 Dissipatedcpowerc(W)

0.6

b)

Tamb =50 °C Vgs=3.3 V

500

Center diode Pulsed−gate AC−conductance Side diode

450 400 350 300

50

100 150 200 250 300 Junction temperature (°C)

Figure 4.7: a) Device temperature (Tj ) vs. dissipated power (Pd ) pulsed-gate vs. AC-conductance. b) Temperature (Tj )-dependent thermal resistance Rth for the different techniques at Tamb = 50 ◦ C.

sizes and thermal constants without particular limitations. • Temperature calibration. While the pulsed-gate technique requires a pulsed temperature calibration of the transistor isothermal Id0 -Vds curves (Id0 -Tamb calibration), a simpler DC calibration is needed for the AC-conductance and sense-diode techniques. In particular, the AC-conductance technique requires calibrating the derivative of the DC current (SI ) as a function of the temperature Tamb , whereas for the sense-diode technique the Vf -Tamb calibration curve is needed. If the sense-diode technique is applied in DC conditions, the diode has to be calibrated before (or after) the temperature measurements are performed. As suggested in Sec. 4.2.3, a possible alternative consists of switching the transistor on and off and obtaining the calibration

• Accuracy of the results. It is generally recognized that temperature measurements in the electrical domain can only provide a weightedaverage temperature across the transistor. The pulsed-gate and ACconductance technique respectively rely on measuring the current and the output conductance, which are global parameters of the transistor and therefore do not contain any local information. The sense-diode technique also performs a sort of averaging, since the temperature could be non-uniformly distributed across the diode area. Moreover, the diode is not exactly located in the hottest spot (the drift region) of the active cell where the temperature has to be sensed. As a result, temperature gradients could also affect the accuracy of the diode measurements. However, since the diode area is negligible compared to the LDMOS area, averaging effects are less pronounced than in the pulsed-gate and AC-conductance techniques. As a result, multiple diodes can be used to extract temperature gradients between different active cells, but temperature gradients within a single active cell cannot be resolved.

The advantages and disadvantages of the reported electrical techniques are summarized in Table 4.1.

55 CHAPTER 4. JUNCTION TEMPERATURE

data from the off-state waveforms. An important calibration issue is related to the possibility to make temperature predictions outside the calibration range. As shown in Fig. 4.6, power SOI devices can withstand junction temperatures up to 400 ◦ C, and getting calibration data in this temperature range can be rather difficult, especially for on-wafer measurements. In fact, standard thermal chucks cannot be heated up above 300 ◦ C, and the maximum junction temperature transistors can withstand is typically higher than this value. Therefore, a physically-based fitting routine for extrapolating data outside the calibration range is very useful. In the pulsed-gate technique, it is possible to exploit the exponential temperature dependence of the saturated carrier velocity in the drift region, from which the exponential decay of the saturation current with temperature originates [59]. A similar fitting routine can be applied also to the SI -Tamb calibration in the ACconductance technique. In fact, if the current exponentially depends on the temperature, also its temperature derivative will exhibit the same behavior. Calibration issues are less relevant in the sense-diode technique, since the linearity range of the forward voltage drop with temperature extends well beyond 200 ◦ C and can cover the full Tj measurement range of interest if the diode current is properly selected [61].

56

Pros

Cons

Pulsed-gate

Directqtemperatuteqmeasurement Simpleqdataqprocessing

Weighted-averageqtemperatureqacrossqtransistor Pulsedqcalibration Difficultqonqdevicesqwithqfastqthermalqtransientsq

AC-conductance

Simpleqsetup DCqcalibration Generalqpurpose

Weighted-avarageqtemperatureqacrossqtransistor Indirectqtemperatureqmeasurement

Sense-diode

Localqprobe DCqcalibration

Requiresqextra-diode Requiresqextraqmeasurementqterminals

4.5. CONCLUSIONS

Table 4.1: Overview of the advantages and disadvantages of the electrical techniques for temperature evaluation.

4.5

Conclusions

Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature measurements in power MOS transistors have been compared showing good quantitative agreement across a large junction temperature range (from room temperature up to 400 ◦ C). For each technique, the measurement setup and the operating principle have been presented, and the experimental results have been discussed. The advantages and the disadvantages of the investigated techniques have been compared in a benchmarking analysis accounting for setup simplicity, calibration issues and experimental accuracy. The pulsed-gate and sense-diode techniques allow direct temperature extraction but require short-pulse calibration measurements and a dedicated test structure, respectively. The AC-conductance benefits from a simpler setup and a broader application range, but relies on an indirect temperature estimation. The added value of using embedded diode-sensors lies in the possibility to measure temperature gradients between adjacent active cells, which might play an important role in device reliability.

CHAPTER

S AFE OPERATING LIMITS Abstract In this chapter a general measure is proposed for experimentally determining the safe operating limits of power transistors. The conventional characterization of the safe operating area (SOA) in the current-voltage plane has the disadvantage of being dependent on measurement conditions and device geometry. In order to overcome this problem, it is proposed to extend the safe operating area to a volume by adding a junction temperature axis, and normalizing the drain current to the gate width. The resulting three-dimensional space comprising the safe operating points is defined as safe operating volume (SOV). Extensive measurements of the safe operating limits of SOI LDMOS transistors have been conducted using integrated temperature sensors to measure the junction temperature of the devices up to the edge of the operating range. By comparing measured SOV data for devices with identical cross-section, it is demonstrated that the SOV is nearly independent of operating conditions and device area. This establishes the SOV as a general measure for the safe operating limits of transistors. The usefulness of the SOV is demonstrated by showing how conventional two-dimensional SOA curves for different operating conditions and device areas can be predicted once the SOV and the effective thermal impedance of the LDMOS transistor have been determined.

This chapter was published in the IEDM Proceedings [62]. For clarity it has been expanded with additional figures and explanations.

57

5

5.1

58

Determining the safe operating limits

5.1. DETERMINING THE SAFE OPERATING LIMITS

The operating limits of a transistor are conventionally determined by characterization of the curves that form the boundary of the safe operating area (SOA) in the two-dimensional drain current-voltage (Id -Vds ) plane [4, 12]. The shape of these SOA curves depends on parameters such as pulse time tpulse , ambient temperature Tamb and area of the transistor A [6, 63]. Consequently, this way of characterizing the safe operating limits does not result in a single safe operating range for the transistor, but in many different curves that depend on operating conditions and transistor geometry. Besides the drain-source voltage Vds and the gate-width Wgate d normalized drain current Idn (Idn = WIgate ), the junction temperature Tj also plays an essential role in determining the safe operating limits of a transistor with a certain cross-section. Therefore, it is proposed to extend the SOA concept by adding a temperature Tj -axis. In this way, the safe operating range can be represented by a volume in the three dimensional (Idn ,Vds ,Tj ) space, which is defined as the safe operating volume (SOV). In order to experimentally determine the SOV, an extensive investigation of silicon-on-insulator (SOI) LDMOS transistors with identical cross-sections (see Fig. 4.1) is carried out over a five-dimensional parameter space comprising the drain voltage (Vds ), gate voltage (Vgs ), tpulse , Tamb and A. Four square devices with different areas and gate widths have been tested (see Fig. 5.1). While scanning the safe operating range, the operating junction temperature Tj is measured using an integrated diode sensor [51, 56, 64]. The schematic circuit diagram of the experimental setup is shown in Fig. 5.2. It is similar to the pulsed-gate setup described in Chapter 4.2.1. A single pulse is applied to the LDMOS gate while the voltage Vds is supplied by Vdd through the load Rd . Using an oscilloscope, the drain current Id is determined from the voltage drop across the load Rd , while the junction temperature Tj is determined from the voltage drop across the sense-diode, biased at current of 100 µA. A 1 kΩ gate resistor Rg is used to prevent oscillations. Using this procedure the safe operating range is scanned for 20 Vgs values in the range (1 V, 5 V) by pulsing Vg for increasing Vds (in steps of 0.1 V) until the safe operating limit is reached. To limit measurement time and number of required samples, it is highly desirable to have a way to determine the safe operating limits of transistors without actually destroying them. For this purpose a method has been developed that is based on monitoring electrical and thermal runaway conditions during characterization. The method is based on the determination of the stability factor at the end of each pulse. A detailed theoretical analysis of the electrical, thermal and electro-thermal stability factors is proposed in Chapter 6. For experimental purposes, the thermal stability factor [65] ∂Id Sth = Zth Vds (5.1) ∂Tj V ds

RonA4=4704mΩmm² BV4=4704V Ldrift4=434µm A = 0.48Aref

A = 3.31Aref A = Aref

A = 0.15Aref

59

W

W4=4Wgate44/4Nfingers4 Dev. 1 L4=40.5Nfingers·Lpitch4 Dev. 2 W4=4L Dev. 3 44 4 Dev. Lpitch4=4104µm

Nfingers Wgate4[µm] A [µm2] 4 8 12 20

108 346 720 2380

540 1730 3600 11900

L

Figure 5.1: Schematic top view of the devices under test for the characterization of the safe operating limits. The cross section is the same as in Fig. 4.1.

has been used. It can be determined using the time dependence of the diode temperature Tj (t) measured by the scope to evaluate the partial derivative Tj −Tamb dId /dt ∂Id ∂Tj |Vds = dTj /dt and the relation Zth = Vds Id at t = tpulse (Fig. 5.3). As a practical electrical stability [66] factor Se , the product of on-resistance and

Figure 5.2: Schematic circuit diagram of the experimental setup for the characterization of the safe operating limits.

CHAPTER 5. SAFE OPERATING LIMITS

Lpitch

(a)

200

100 Tamb = 25 °C Vds =10 V Vgs = 3 V

50 0

0

20 40 time (µs)

100

0 60

600

1 Tamb = 25 °C tpulse = 50 µs

450

0.5

Fig. 5.4

0

−0.5 0

Junction temp. Tj (°C)

150

300 150

Junction temp. Tj (°C)

Drain current Id (mA)

5.1. DETERMINING THE SAFE OPERATING LIMITS

(b) Id/I max & S − factor d

60

tpulse = 50 µs

0 10 20 30 40 Drain voltage Vds (V)

Figure 5.3: Experimental procedure for determining the edges of the SOV. a) For each Vgs and Vds , Id and Tj are monitored for a fixed gate pulse time. From (5.1) at t = tpulse the stability factor Sth [65] is determined after each pulse and plotted in Fig. 5.3b. b) (Id ,Vds ,Tj ) characterization at Vgs = 3 V for tpulse = 50 µs including the stability factor. In order to ensure safe operation, Vds is increased until the practical safe operating limit is reached at Sth = 0.2 and the SOA edge point is plotted in Fig. 5.4. differential conductance Se = Ron

dId dVds

(5.2)

has been used. Although theoretically breakdown is only expected to occur at Sth > 1 or Se = ∞, experimentally it was found that safe device characterization was only possible if the Vds sweeps were stopped when either Sth = 0.2 or Se > 1 for steps of 0.1 V in Vds . When either of these conditions occurs, the corresponding SOA edge point is plotted as in

tpulse = 5 µs tpulse = 50 µs tpulse = 100 µs tpulse = 500 µs

Junct.°temp.°Tj°°(°C)°

Vgs = 1-5 V A = Aref

(d)

b

am

b

(c)

=

30 0

=

50 °C

°C

Drain°voltage°Vds°(V) Vgs=1-5V tpulse=50µs Tamb=25°C

A = 0.15Aref A = 0.48Aref A = Aref A = 3.31Aref

Drain°voltage°Vds°(V)

(e)

Junct.°temp.°Tj°°(°C)°

am

T

Norm.°current°Idn°(A/mm)

T

Norm.°current°Idn°(A/mm)

Norm.°current°Idn°(A/mm) Norm.°current°Idn°(A/mm)

tpulse = 50 µs A = Aref

Tstep = 50 °C Vgs = 1-5 V

(f)

Drain°voltage°Vds°(V)

Drain°voltage°Vds°(V)

Figure 5.4: Comparison between conventional SOA curves and the proposed SOV surfaces. a) SOA curves for a device with reference area A = Aref at Tamb = 25 ◦ C for different pulse times tpulse . b) SOA curves for the reference device (A = Aref ) for tpulse = 50 µs and different ambient temperatures Tamb . c) SOA curves for tpulse = 50 µs and Tamb = 25 ◦ C as a function of the device area. The shown SOA curves have been derived from 22,515 pulsed measurements similar to Fig. 5.3a. d)-f) The SOA curves in a)-c) are converted to SOV surfaces by adding the junction temperature Tj measured by the diode as a 3rd dimension (in color). The generality of the SOV representation is further investigated in Fig. 5.5.

Figs. 5.4a-c and the procedure is repeated for 20 Vgs values in the range (1 V, 5 V) to obtain a full SOA curve. By using this approach, the operating limits of the transistor can be determined while preventing thermal and electrical runaway of the drain current Id which occur when Sth or Se becomes too large.

CHAPTER 5. SAFE OPERATING LIMITS

(b)

61

Drain°voltage°Vds°(V)

Drain°voltage°Vds°(V)

Junct.°temp.°Tj°°(°C)°

Tamb = 25 °C

Safe°Operating°Volume Norm.°current°Idn°(A/mm)

Norm.°current°Idn°(A/mm)

Safe°Operating°Area (a)

5.2

62

From Safe Operating Area to Safe Operating Volume

5.2. FROM SAFE OPERATING AREA TO SAFE OPERATING VOLUME

Figures 5.4a-c show the conventional SOA plots of the transistor for tpulse = 5 µs, 50 µs, 100 µs, 500 µs (Fig. 5.4a), Tamb = 50 ◦ C − 300 ◦ C with a temperature step Tstep = 50 ◦ C (Fig. 5.4b) and A = 0.15·Aref , 0.48·Aref , Aref , 3.31·Aref with Aref ≈ 3600 µm2 (Fig. 5.4c). The measured temperatures Tj,edge at the edge of the operating range are added as a 3rd dimension (in color) in Figs. 5.4d-f and show how a single SOV surface can be generated from a set of SOA curves if Tj,edge is known. The similarity between the colored areas presents evidence for the generality of the SOV representation and has been quantitatively investigated in Fig. 5.5. All data in Figs. 5.4d-f have been fitted with a numerical function FSOV describing a single surface in the (Idn ,Vds ,Tj ) space. This surface represents the boundary between safe and unsafe operating volume (Fig. 5.5a). The standard deviation of the error between the data and the fit (Fig. 5.5b) is 20 ◦ C. The error is larger when strong electric fields are present within the device and the temperature Tj is close to Tamb . The overall agreement between the data and the numerical fit supports the hypothesis that the SOV is independent of tpulse , Tamb and A. Note that in this chapter the SOV is treated as a numerical function and all the mathematical operations performed with it (see, e. g., Table 5.1 and Fig. 5.8) are carried out numerically using MATLAB [67]. A closed-form analytical description of the SOV function has been derived in Chapter 6 by means of a physics-based stability analysis.

5.3

The general nature of the Safe Operating Volume

Since the physics inside the transistor is dominated by the variables Idn , Vds and Tj , its SOV is practically independent of other parameters and can be seen an intrinsic property of the LDMOS with a particular cross section. In accordance, the SOV can be described by the equation: FSOV (Idn , Vds , Tj ) = 0

(5.3)

representing the boundary surface between safe operation (FSOV > 0) and unsafe operation (FSOV < 0). An experimental clarification of this assumption is provided in Fig. 5.6, which shows how the electrical behavior of the LDMOS is completely determined by the cross-section (see Figs. 5.6ab at t=0), while the thermal properties are area and time dependent. The effect of the gate voltage Vgs is implicitly included in the SOV via the relation Vgs = f(Idn , Vds , Tj ), which uniquely links each point in the SOV to a specific Vgs . Other parameters such as tpulse , Tamb and A influence Tj according to: Z tpulse Tj (tpulse , Tamb , A) = Tamb + Zth (tpulse −t, A)Pd (t) dt ≈ Tamb +Zth,eff (tpulse , A)Pd 0

(5.4)

Unsafe Operating Volume

-V ( ds V)-

1 Norm.-Occurrences

(b)

mm -(A/ n I d nt urre m.-c

63 CHAPTER 5. SAFE OPERATING LIMITS

Dra in-vo ltage

Safe Operating Volume

Junction-temp.-Tj-(°C)

Vgs=1-5V

Junction-temp.-Tj-(°C)

(a)

)

Nor

σ = 20 °C

0.8 0.6 0.4 0.2 0

−60 −20 20 60 Temperature-error-(°C)

Figure 5.5: Validation of the SOV concept. a) Fit of all the data points from Figs. 5.4d-f by a single surface in the (Idn ,Vds ,Tj ) space. This surface represents the boundary between the safe and the unsafe operating volumes. b) Distribution of the error between the data and the fit showing a standard deviation σ = 20 ◦ C, thus supporting the general nature of the SOV.

assuming that Pd (t) ≈ Pd = Id Vds , and where Zth is the impulse response of the thermal system. The effective thermal impedance Zth,eff is defined as: Z tpulse Zth,eff (tpulse , A) =

Zth (tpulse − t, A) dt

(5.5)

0

and can be determined from measurements using sense-diodes (Fig. 5.7) or other techniques [51], but also accurately obtained from simulations [50]. The generality of the SOV representation has been further investigated by means of physics-based stability analysis reported in Chapter 6.

Vgs = 2 V Vds = 15 V

0.09

Tamb = 25 °C A = 0.15Aref

0.08

A = 0.48Aref A = Aref

5.3. THE GENERAL NATURE OF THE SAFE OPERATING VOLUME

0.07

A = 3.31Aref

0 250 Junct. temp. Tj (°C)

64

Norm. current I

dn

(A/mm)

(a)

10

20 30 time (µs)

40

50

(b) A = 3.31Aref

200

A = Aref

150

A = 0.48Aref

100

A = 0.15Aref

50 0

10

20 30 time (µs)

40

50

Figure 5.6: Explanation of the general nature of the SOV. a) Normalized drain current Idn and b) junction temperature Tj as a function of time for devices with different areas at the same bias point (Vgs = 2 V, Vds = 15 V, Tamb = 25 ◦ C). The differences in Idn are only caused by Tj because the electrical properties are solely determined by the cross-section.

It is worth mentioning that there are conditions under which failure will not be univoquely determined by the three parameters (Idn ,Vds ,Tj ). In particular, with pulse times significantly shorter than the runaway breakdown time constants or in presence of large current density or Tj variations over the transistor area, the SOV can also depend on pulse time, temperature or current distribution, which can lead to a breakdown of the general nature of the SOV. If such conditions do not occur the SOA curves for LDMOS transistors of arbitrary areas and operating conditions can be predicted by combining the FSOV and Zth,eff functions. This straightforward approach is illustrated and validated in the following section.

(a)

Vgs = 2 V 0.8 Vds = 15 V 0.6 0.4

65

A = 3.31Aref A = 0.48Aref A = Aref A = 0.15Aref

0.2 0

0

10

20 30 time (µs)

40

50

(b)

1

tpulse = 5 µs tpulse = 10 µs tpulse = 50 µs

0.8 0.6

Z

th,eff

⋅A (°C/W⋅mm2)

Tamb = 25 °C

0.4 0

1

2

3 4 A /A

5

6

7

ref

Figure 5.7: Determination of the effective thermal impedance Zth,eff (tpulse , A). a) Time behavior of Zth,eff for devices with different areas determined using the sense diode from the bias point in Fig. 5.6. b) Area dependence of Zth,eff for different pulse times.

5.4

Prediction of SOA curves from the SOV

Combining (5.3)-(5.4) leads to the following equation for the SOA curve FSOA : FSOA |tpulse ,Tamb ,A (Idn , Vds ) = FSOV (Idn , Vds , Tamb +Zth,eff (tpulse , A)Wgate Idn Vds ) = 0, (5.6) which enables one to predict all conventional SOA curves once the FSOV and Zth,eff functions are known. The procedure is summarized step-by-step in Table 5.1 and carried out in Figs. 5.7-5.8. In order to investigate the validity of this SOA extraction method and

CHAPTER 5. SAFE OPERATING LIMITS

Zth,eff⋅A(°C/W⋅mm2)

1

66 5.5. CONCLUSIONS

show its usefulness, it is demonstrated how the SOA curves for devices of different areas can be predicted by characterizing the SOV of a reference device only (data only from Figs. 5.4d-e). The function Zth,eff (tpulse , A) is determined in a single bias point using the sense diode (Fig. 5.7). The results are shown in Fig. 5.8. Figure 5.8a shows a graphical solution of (5.6) obtained by intersecting (5.3)-(5.4) for a device with A = 0.48 · Aref and for tpulse = 50 µs. Both equations (5.3) and (5.4) represent surfaces in the (Idn , Vds , Tj ) space. Equation (5.3) is the edge of the SOV for the reference device with A = Aref . As discussed in Section 5.3, this surface is the same for devices with different areas. Equation (5.4) is used to determine Tj as a function of Vds and Idn using Zth,eff as a parameter. Since Zth,eff depends on tpulse and A, the surface (5.4) plotted in Fig. 5.8a is specific for a device with A = 0.48 · Aref and for tpulse = 50 µs. As can be seen, the intersection line between (5.3) and (5.4) is in good agreement with the measured data (markers) from Fig. 5.4f for the specified device and pulse time. In order to obtain an SOA curve, the intersection line in the (Idn , Vds , Tj ) space has to be projected in the (Idn ,Vds ) plane. By repeating this procedure on devices with different areas the SOA curves have been predicted in Fig. 5.8b. The agreement between predicted and measured (from Fig. 5.4c and Fig. 5.4f) SOA curves demonstrates the predictive power of the SOV for determining the SOA for arbitrary device area and operating conditions.

5.5

Conclusions

In this chapter, the concept of safe operating volume (SOV) has been introduced for characterizing the operating limits of LDMOS transistors as an extension of the safe operating area (SOA). It has been shown that the SOV is nearly independent of device area and operating conditions and enables SOA predictions on devices with identical cross section but with different areas and operating parameters. Since the assumptions underlying the SOV concept are quite general, it is anticipated that the SOV can also prove itself to be useful for other types of transistors. A theoretical Determine the edge of SOV as a surface (5.3) from measurements at different pulse times and/or ambient temperatures (Figs. 5.4d-e) on a device with reference area Aref . Determine the function Zth,eff (tpulse , A) (5.5) from measurements (Fig. 5.7) [51, 56] or thermal simulations [50]. Solve (5.6) (Fig. 5.8a). Project the solution in the (Idn ,Vds ) plane to determine the SOA curves (Fig. 5.8b). Repeat for different tpulse , Tamb and A. Table 5.1: Procedure for determining SOA curves from the SOV.

(5.3)

(5.4)

Data6for A6=60.486Aref (Fig.65.4f)

tpulse=6506μs6

Dra

in°vo

67

(A/m

ltage

°V

ds

(V)

m)

nt°I dn curre

.° Norm

Lines:6predictions6from6data6in6Figs.65.4d-e6 66666666666and6Fig.65.76(solutions6of6(5.6))6 Markers:6data6from6Fig.65.4c

Norm.°current°Idn (A/mm)

(b) 0.2

A6=60.15Aref A6=60.48Aref

0.15 0.1 0.05 0 20

A6=6Aref A6=63.31Aref 30 40 50 60 Drain°voltage°V (V) ds

Figure 5.8: Practical implementation of the procedure for determining the SOA curves from the SOV. a) Graphical solution of (5.6) for determining the SOA curves from the SOV. The edge of the SOV has been determined only for the reference device with A = Aref (Figs. 5.4d-e), while the symbols are data for a device A = 0.48 · Aref (Fig. 5.4f), showing good agreement between the measured and the predicted intersection line. b) Projection of the solution from Fig. 5.8a in the (Idn ,Vds ) plane for devices with different areas, showing how SOA predictions can be made using the SOV and Zth,eff . The dashed lines are the projections in the (Idn ,Vds ) plane of the intersection lines between the surfaces (5.3) and (5.4), while the markers represent measured data from Fig. 5.4c. analysis of the SOV is presented in Chapter 6.

CHAPTER 5. SAFE OPERATING LIMITS

Junction°temp.°Tj°(°C)

(a)

CHAPTER

P HYSICS -B ASED S TABILITY A NALYSIS Abstract In this chapter, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal-oxide-semiconductor (MOS) transistors. The proposed model can be easily interfaced with a circuit or device simulator to perform a failure analysis, making it particularly useful for power transistors. Furthermore, it allows mapping the failure points on a three-dimensional (3D) space defined by the gate-width normalized drain current, drain voltage and junction temperature. This leads to the theoretical definition of the Safe Operating Volume (SOV), which was introduced in Chapter 5 on an experimental basis. A comparison between the modeled and the measured SOV of SOI LDMOS transistors is reported to support the validity of the proposed stability analysis.

This chapter was published in Solid-State Electron. [68]. For clarity it has been expanded with additional explanations.

69

6

6.1

70

Introduction

6.1. INTRODUCTION

In power transistors, failure is often associated with instability, which causes one or more device parameters, such as current, voltage or temperature, to runaway [65]. As shown in Chapter 5, stability can be experimentally investigated by measuring the device characteristics close to the failure limit [6, 62, 64, 69, 70]. This allows calculation of a stability factor that is a measure of the device sensitivity to runaway. However, such a procedure has two drawbacks: (1) it can affect the device performance by changing parameters such as threshold voltage, on-resistance and breakdown voltage; (2) it detects the occurrence of instability but not its physical origin (electrical or thermal). In order to overcome the first drawback, physics-based models [6, 50, 64, 69, 71] or TCAD simulations [18] have been used to predict and quantify instability. However, modeling and simulating runaway effects causes the output parameters to diverge and makes it difficult to identify the physical origin of the numerical instability. A physics-based stability analysis can be used to identify the boundary between electrical and thermal failure mechanisms in LDMOS transistors (Fig. 6.1), hence to distinguish the root cause of device failure [72]. In this chapter, a detailed mathematical derivation of the stability factors is elaborated, which is generally applicable to any kind of MOS transistor. The electrical and thermal stability factors are defined assuming that selfheating does not play a role in the electrical runaway, while avalanche breakdown and the internal parasitic bipolar transistor of the MOS transistor do not affect thermal stability. Device failure can be related to an electro-thermal stability factor that includes both the electrical and thermal failure mechanisms (Fig. 6.2). The individual analysis of runaway mechanisms allows determination of the relative contributions of electrical and thermal phenomena to failure, thus identifying the primary cause of runaway. This knowledge allows one to determine, depending on the operating conditions, whether the electrical or thermal device properties, or both, need to be improved to increase the SOA, i.e. the two-dimensional (2D) frame work in the current-voltage plane where it is safe to operate the LDMOS [4, 12]. The stability equations need to be combined with models of the different MOS current contributions (intrinsic MOS current IdMOS , bipolar base and collector currents Ib and Ic , and impact ionization current Iii ) including their temperature dependencies. For this purpose analytical models for MOS transistors, TCAD simulations, experimental data or combinations can be used [6, 18, 50, 64, 69, 71, 73]. In this chapter, physics-based analytical expressions [74, 75] with experimental fitting parameters [62] (see also Chapter 5) have been used (see Sec. 6.7). As shown in [72] for SOI LDMOS transistors, the proposed model allows mapping the failure points onto a 3D space defined by the gate-width normalized drain current, drain

(a)

Gate

Source p+ n+

STI Iii

B

RB Ib

IdMOS

C

E

Ibg

Drain n+

Ic=βIb

VBE

BOX (b)

71

Drain current (A) Ron l imit

LDMOS Fop operation

SOA

Fe

self-hea

ting

electrical runaway

avalanche + bipolar electro-thermal runaway

Feth

thermal runaway

Fth

Drain voltage (V)

Figure 6.1: a) Parasitic bipolar and avalanche multiplication in the operation of an LDMOS transistor. b) Schematic of the Safe Operating Area (SOA), showing the failure and operating functions which are analytically investigated in this work.

voltage and junction temperature. This leads to the definition of the failure functions and allows to define the Safe Operating Volume introduced in Chapter 5 on a theoretical basis.

6.2

Origin of electro-thermal runaway

A general overview of the positive electrical and thermal feedback mechanisms leading to instability and runaway is provided in Fig. 6.2. At high drain voltages Vds , the MOS electron current IdMOS generates electron-hole pairs contributing to an impact ionization current Iii with an electron and a hole component. The electrons flow towards the highly doped drain contact, the holes flow towards the body contact inducing a voltage drop Vbe over the base resistance RB . This switches on the internal parasitic bipolar with a base current Ib and a corresponding collector current Ic ≈ βIb , where β is the current gain. This current Ic is in turn multiplied by avalanche when flowing in the drift extension, resulting in a positive feedback behavior. Self-heating [50, 51, 64] is included in the model by introducing an effective thermal impedance Zth,eff ≈ (Tj − Tamb )/Pd [62], where it is assumed for simplicity that the dissipated power Pd is independent of the pulse time tpulse . Electrical failure occurs because of the interaction of the parasitic bipolar

CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

Isat limit

72 6.3. ANALYTICAL STABILITY ANALYSIS

with the current Iii . Part of this current flows through the base of the bipolar and contributes to Ic ≈ βIb , which is avalanche multiplied and fed back into the base. Thermal failure can occur because of thermal runaway in each of the current components IdMOS , Ic or Iii . The temperature coefficient of IdMOS depends on Vgs [76], Iii has a slightly-negative temperature coefficient [77] (not included in the model), and Ic has a positive temperature coefficient [78]. In most cases, the increase in Ic (also including thermal leakage) induced by self-heating determines thermal instability [6, 50, 64, 69]. However, for Vgs below the zero-temperature coefficient point, IdMOS also contributes to instability [50, 64, 76]. For studying the failure mechanisms the so-called stability factors [65] are required. The complete derivation of the stability factors is carried out in Sec. 6.3. Although electrical and thermal failure mechanisms often both play a role in transistor failure, their relative contributions can be identified using the analytical stability analysis described in the same section. The electro-thermal behavior of the MOS transistor is described by combining the electrical and thermal contributions to stability in a coupled equation system. The large signal behavior of the MOS transistor including the parasitic bipolar transistor and self-heating can be described as follows: 
+Ic ) Idn = M · (IdMOS = fe Vgs , Vds , Vbe , Tj (a) Wgate (6.1) Tj = Tamb + Zth,eff (tpulse , A)Wgate Vds Idn (b), where Idn is the drain current per unit gate width Wgate , IdMOS is the internal MOS drain current, Vgs the gate-source voltage, Vds is the drain-source voltage, Vbe is the base-emitter voltage, Tj is the junction temperature, and Tamb is the ambient temperature. The effective thermal impedance Zth,eff depends on the pulse time tpulse and the device area A, and the multiplication factor M is a parameter that is a measure for the increased drain current caused by impact-ionization. The function fe describes the electrical operation of the MOS-bipolar system depending on the applied biasing and junction temperature Tj . It can be constructed based on compact modeling, TCAD simulations or measurements on special test structures including a temperature sensor and/or a separate body contact. Hence, the electro-thermal behavior of the MOS transistor is described by (6.1) in case of large signal biasing.

6.3 6.3.1

Analytical stability analysis Derivation of the electrical stability factor

In order to quantify the relative contributions of electrical [66] and thermal [50, 64] runaway to coupled electro-thermal [18, 63, 69] failure mechanisms, analytical stability equations are derived following a linearization procedure. In this section, it is shown how the electrical stability factor can be derived assuming an isothermal operation of the transistor (i. e., no self-

BipolarG feedback

BJT

Ib Ib

+

Ihole,source

C

-

Ibg

VBE

B E

×

��d ��j

3GthermalG feedbackGloops

Pd

Ic

Ib +

S

Ibg Iii,hole

+

73

Tj Tamb

Figure 6.2: a) Schematic representation of the origin of electrical and thermal runaway. b) Electro-thermal circuit model of the MOS-bipolar system. heating). For this purpose, it is useful to refer to the electrical equivalent circuit shown in Fig. 6.2b. The feedback equation for electrical stability is obtained by solving the node equation at the base of the parasitic bipolar: Iii = Ib + Ibg ,

with Iii = (M − 1)(Ic + IdMOS ),

(6.2)

where Ibg is the (hole) back-gate current and M is the multiplication factor1 . Further,   Ic Vbe Vbe Ib = and Ibg = = IS exp , (6.3) β VT RB where IS is the saturation current of the reverse-biased base-collector junckT tion of the parasitic bipolar, and VT is the thermal voltage (VT = q j , with k being the Boltzmann constant and q the elementary charge). The electrical feedback equation for large signal operation is rewritten as: [1 − β(M − 1)] Ic + β

Vbe (Ic ) = β(M − 1)IdMOS , RB

(6.4)

which is nonlinear because of the dependence Vbe (Ic ). In order to find the electrical instability condition, the problem can be linearized around a fixed bias point (this procedure is referred to small-signal analysis). Generally 1 As noted by A. J. Scholten, there is an additional contribution to electrical stability due to the threshold voltage modulation induced by the voltage drop over the p-well. This effect has been neglected in this work, but it can be included in the linearization procedure by introducing the body effect in the stability analysis.

CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

D G

AvalancheG feedback

Iii

IdMOS

(b)

-

+

Zth,eff

Ic

IdMOS+Ic

Iii,el

IdMOS +

× Zth,effVds

(a) ElectricalGrunaway Id=IdMOS+Ic+Iii ThermalGrunaway

it can be stated for the current that (neglecting higher order and crossed terms): I(V, T ) ≈ I(V0 , T0 ) + g (V − V0 ) + φ (T − T0 ) = I(V0 , T0 ) + gv + φt, (6.5) where V0 is the fixed (DC) bias point and T0 is the fixed (ambient) temperature. Hence the small-signal parameters are introduced: i = I − I0 , v = V − V0 and t = T − T0 . 74

(6.6)

6.3. ANALYTICAL STABILITY ANALYSIS

Further, the transconductance and the temperature coefficient can be respectively written as ∂I ∂I and φ = . (6.7) g= ∂V T0 ∂T V0 More specifically, the parameters Vbe , Ib , Ic and IdMOS are written as the sum of DC bias points and small signal parameters as follows: Vbe = VBE + vbe , Ic = IC + ic , Ib = IB + ib and IdMOS = IDMOS + idMOS . (6.8) Then, the following small signal parameters of the parasitic bipolar transistor are introduced: vbe ic ∂Ic ic β rb = , β= and gm = = = , (6.9) ib ib ∂Vbe T0 vbe rb where rb is the differential base resistance of the parasitic bipolar (notice that rb 6= RB ), β is the current gain and gm is the collector transconductance. Equation (6.4) can be written in terms of small signal variations at each bias point as: [1 − β(M − 1)] ic +

rb ic = β(M − 1)idMOS , RB

(6.10)

giving ic =

β(M − 1) h 1 − β(M − 1) −

rb RB

i idMOS .

(6.11)

From (6.11), the electrical stability factor Se for the collector current is given by rb Se = β(M − 1) − . (6.12) RB Using the calculated collector current ic , the total electron drain current id including the MOS, bipolar transistor and avalanche contributions can 1 be calculated by introducing the multiplication factor M = 1−α (α is the spatial integral of the avalanche coefficient [79]) as follows: 1 + RrbB 1 id = M (idMOS + ic ) = · idMOS . 1 − α 1 − Se

(6.13)

Electrical instability occurs when an infinitesimal increment in the drain voltage causes the drain current to diverge. This corresponds to the condi ∂Id tion ∂Vds → ∞. From (6.13), it can be seen that the drain current diverges Tj

when α = 1 (avalanche breakdown) or when Se = 1 (electrical runaway of the collector current). In practical cases, avalanche breakdown dominates the electrical failure for low gate voltages when the drain current is low and the electric field magnitude is large, while bipolar runaway mainly occurs at high gate voltages and can be significantly enhanced by self-heating, as discussed in the next subsections. 75

Derivation of the thermal stability factor

In order to find an expression for the thermal stability factor, small signal temperature variations should also be included in the analysis. The junction temperature Tj is split into a DC and a small signal component according to: Tj = T J + t j .

(6.14)

Relating the junction temperature Tj to the dissipated power Pd = Id Vds through the thermal impedance Zth,eff and separating the DC from the small signal components yields: Tj = Tamb + Zth,eff Id Vds = Tamb + Zth,eff (ID + id )(VDS + vds ).

(6.15)

From (6.15), the small signal temperature variation can be expressed (neglecting second order terms) as: tj = Zth,eff (ID vds + VDS id ).

(6.16)

The small signal drain current id is related to tj via its temperature coefficient φd according to (see (6.5) and (6.7)) : id = gd vds + φd tj ,

(6.17)

where gd is the drain conductance. In this section, only runaway caused by thermal instability is investigated and electrical effects are neglected. Substituting id from (6.17) into (6.16) and setting vds = 0 (meaning that the device operates at constant drain voltage VDS ) gives tj = Zth,eff VDS φd tj ,

(6.18)

which is a feedback equation for the small signal temperature increase tj . d Thermal instability occurs when ∂I → ∞. From (6.18) it follows that ∂Tj Vds

the junction temperature diverges when the thermal stability factor Sth = Zth,eff VDS φd

(6.19)

CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

6.3.2

reaches unity. The temperature coefficient φd includes both the MOS contribution φdMOS and the bipolar contribution φcNPN and can be expressed as the sum of the two in the calculation of Sth : φd = φdMOS + φcNPN .

(6.20)

In (6.20), the temperature dependence of the multiplication factor M has been neglected. More specifically, the total derivative of M with respect to the drain voltage Vds can be expressed as: 76 6.3. ANALYTICAL STABILITY ANALYSIS

dM(Tj , Vds ) ∂M dTj ∂M = · + . (6.21) dVds ∂Tj dVds ∂Vds ∂M At first order, ∂M ∂Tj  ∂Vds since M strongly increases with the drain bias Vds . For this reason, the assumption M(Tj , Vds ) ≈ M(Vds ) is taken in this work, which also simplifies the algebra for the calculation of the electro-thermal stability factor derived in the next subsection.

6.3.3

Derivation of the electro-thermal stability factor

By combining the electrical and thermal contributions to stability, the electro-thermal stability factor Seth is derived in this subsection. For this purpose, (6.16) and (6.17) are combined in a coupled small-signal system giving:  id = gd vds + φd tj (a) (6.22) tj = Zth,eff (ID vds + VDS id ) (b) The conductance gd and the temperature coefficient φd need to be expressed as a function of the MOS (gdMOS and φdMOS ) and bipolar (gc and φc ) contributions by accounting for the electrical feedback equation (6.10). The small signal electro-thermal equations for the MOS drain current idMOS and the collector current ic are: idMOS = gdMOS vds + φdMOS tj

(6.23)

ic = gm vbe + φcNPN tj

(6.24)

Since ic is a function of vbe while idMOS is a function of vds , we first look for an expression where ic is also expressed as a function of vds in the form: ic = gc vds + φc tj .

(6.25)

For this purpose, (6.23) and (6.24) are substituted into (6.10), yielding, after some algebraic manipulations: β(M − 1)gdMOS h i 1 − β(M − 1) − RrbB

(6.26)

β(M − 1)φdMOS + RrbB φcNPN h i φc = . 1 − β(M − 1) − RrbB

(6.27)

gc =

The total drain current id is calculated as in (6.13) giving the following expressions for gd and φd : gd = M 1+ φd = M

rb RB

1+

rb RB

1 − Se  1+ 1 − Se

(6.28)

gdMOS

φcNPN φdMOS

 φdMOS .

(6.29)

Electro-thermal runaway occurs when vidsd → ∞, which can happen in two cases: (1) gd → ∞; (2) Zth,eff VDS φd = 1. Condition (1) occurs when M → ∞ (α = 1) or Se = 1 (see (6.28)) and corresponds to the electrical runaway discussed in Sec. 6.3.1. Condition (2) corresponds to the thermal runaway condition discussed in Sec. 6.3.2. However, in this case, the expression for the temperature coefficient φd is not given by (6.20), which only accounts for thermal phenomena, but by (6.29), which also accounts for the electrical feedback occurring at the base node of the bipolar. For this reason, it is natural to define the electrothermal stability factor as (compare with (6.19)):    φcNPN 1 + RrbB 1 + φ dMOS  φdMOS . (6.31) Seth = Zth,eff V DS φd = Zth,eff V DS M 1 − Se In this expression it can be seen how electrical instability can trigger thermal runaway, since Se appears as a feedback term in Seth (electrically-induced thermal instability [69]).

6.4 6.4.1

The Safe Operating Volume (SOV) The failure functions

The stability factors Se , Sth and Seth derived in the previous section can be associated to the corresponding failure functions Fe , Fth and Feth defined such that that Fx (Idn , Vds , Tj ) = Sx − 1, with x = e, th, eth. The operating bias points up to which device failure does not occur define a volume described by:  Vx = (Idn , Vds , Tj ) ∈ R3 : Fx (Idn , Vds , Tj ) < 0 . (6.32) For safe operation, all failure functions need to obey Fx < 0, and failure occurs when Feth = 0. Since Feth includes both the electrical and the thermal failure mechanisms, the condition Feth = 0 always occurs before Fe = 0 and Fth = 0. This can be seen in Fig. 6.3b. The temperature corresponding to

77 CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

By substituting (6.22)b into (6.22)a, the drain current id can finally be expressed as:   d gd 1 + Zth,eff ID φ gd id = vds . (6.30) 1 − Zth,eff Vds φd

78 6.4. THE SAFE OPERATING VOLUME (SOV)

electro-thermal failure is lower than the theoretical electrical and thermal failure temperatures in each bias point. The electro-thermal failure function Feth can be determined in two ways. One possibility is to use the large-signal model described by the system (6.1) to numerically find the Vds -values where the current Id and the temperature Tj stop converging for different ambient temperatures Tamb . However, this is not very useful for failure prediction, since it is is equivalent to performing measurements on the transistor up to the point where it fails. A better alternative is to use the results of the small-signal analysis to calculate Feth in each DC bias point. The DC failure condition can then be determined by solving the equation Feth = 0. A comparison between the two methods is illustrated in Fig. 6.3. Figure 6.3a shows the modeled Idn -Vds and Tj -Vds curves for Vgs = 2V at three different ambient temperatures Tamb for an LDMOS transistor. The gate-width (Wgate ) normalized drain current Idn and the junction temperature Tj are found in each bias condition by solving the system (6.1). The base-emitter voltage Vbe has to be determined numerically [71] in order to calculate Ic . The expressions used in this work for M, IdMOS , Ic , Ib and their temperature dependencies are provided in Sec. 6.7. The failure points at the edge of the SOA (Feth = 0) where the large signal model stops converging are investigated by analyzing the temperature (Tj ) behavior of failure functions as indicated by the circles in Fig. 6.3b. This analysis allows determination of the failure junction temperatures (Tj,fail ) corresponding to electrical (Tje ), electro-thermal (Tjeth ) and thermal failure (Tjth ). In all cases failure is limited by Feth = 0 (Tj,fail = Tjeth ), but there is a gradual transition between thermal to electrical runaway as Vds , and hence the multiplication factor M, increases and Tj reduces.

6.4.2

Influence of the device area and operating conditions

In Fig. 6.3c, the dependence of Feth = Seth − 1 upon the effective thermal impedance Zth,eff is investigated. The failure temperature is affected by Zth,eff mainly for low Vds , where failure is thermally induced, while it tends to become independent of Zth,eff for large Vds , where failure is electrically induced. However, if a safer operating failure criterion is used (Seth = 0 rather than Seth = 1, red line in Fig. 6.3c), the failure temperature becomes independent of Zth,eff and therefore of ambient temperature, pulse time and device area. This is a significant result of this work. While in theory the electro-thermal runaway condition is given by Seth = 1 [65] (Feth = 0), experiments [62] show that the range 0 < Seth < 1 is often unsafe due to the eth high value of dS dVds . Therefore, a safer operating condition can be introduced that is given by Seth = 0, which leads to a reduction of the estimated safe operating limits (mainly in the thermal runaway regime) but makes the SOV independent of Zth,eff (Fig. 6.3c). In practice, the condition Seth = 0 cannot be achieved for Vgs values below the zero temperature coefficient

500

,e1 400 300

0.04

200

0.02

0

Tamb=252°C Tamb=2002°C 100 Tamb=3002°C 10 20 30 40 Drain2voltage V ,V1

50

ds

,b12Small2signal2model2,failure2functions1

,th1

,eth1

,e1 F

et

h=

02 ,T

je

th 1

,c12Feth=02,Tjeth12for

Zth,eff

Zth,eff=1902°C/W2,b1 Seth=02,indep.2of2Zth,eff1

Figure 6.3: a) Modeled Idn -Vds and Tj -Vds curves for Vgs = 2 V and three ambient temperatures Tamb until the edge of the SOA. b) Failure temperature (Tj,fail ) vs. Vds for Vgs = 2V showing the gradual boundary between thermal and electrical failure as Vds increases and Tj,fail reduces. c) Same as b) for different values of the effective thermal impedance Zth,eff . The red line corresponds to a safer operating condition obtained for Seth = 0 rather than Seth = 1.

79 CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

0

Junction2temp. Tj ,°C1

Norm.2current Idn ,A/mm1

,a12Large2signal2model Vgs=2V ,eth1 ,th1 0.06

point [76] since the temperature coefficient of the MOS current is positive in this range. A practical value of Seth = 0.2 was used in [62] and Chapter 5 for the different operating conditions, yielding a good trade-off between transistor safety and experimental accuracy.

6.4.3

80

Mapping electro-thermal failure

6.5. DISCUSSION

In Fig. 6.4a, it is shown how electrical and thermal failure mechanisms are mapped on the failure function Feth . The black dash-dotted line (Fe = Fth = 0) indicates the boundary between electrical and thermal failure regions, and the three crosses correspond to the failure points in Fig. 6.3a. In addition, the operating range is limited by the on-resistance and saturation current that are included using the operating function Fop :  
 Fop = (Idn , Vds , Tj ) ∈ R3 : Idn − fe Vgs,max , Vbe = 0 = 0 .(6.33) This is defined for Vgs = Vgs,max , Vbe = 0 (so excluding the parasitic bipolar transistor) at different temperatures in absence of self-heating. In Fig. 6.4, the operating and failure functions Fop and Feth are mapped onto a 3D space comprising gate-width normalized drain-current Idn , drain voltage Vds and junction temperature Tj . Intersecting the corresponding volumes Vop and Veth yields a new frame work describing the operating limits of LDMOS transistors, which was defined as Safe Operating Volume (SOV) in earlier work [62] (see also Chapter 5): VSOV = Veth ∩ Vop .

(6.34)

For comparison with measurement results, the total SOV has been constructed using the system of equations (6.1) and compared with the experimental data from [62] and Chapter 5 in Fig. 6.5.

6.5

Discussion

The presented analysis is useful for the following reasons. 1. It allows identification of the main failure mechanism (electrical, thermal, electro-thermal) of MOS transistors on a theoretical basis, which is important for device optimization. 2. It shows that there is a gradual boundary between an electrical failure region at high drain voltage Vds and a thermal failure region at high junction temperature Tj . 3. It explains why the SOV can be used as a general framework for the operating range of transistors, which is to a large extent independent of the size and operating conditions. 4. It suggests that the failure functions can be combined with the model results in Fig. 6.5a to reduce the number of measurements needed to construct the experimental SOV in Fig. 6.5b.

Vgs=1-5V

(a)jFeth=0

Electrically-induced failure (e) (th)

(eth)

Vgs=5V Junctionjtemp.jTjj(°C)

(b)jFop=0

Figure 6.4: a) Color plot of the surface Feth = 0 for different Vgs values. The black line corresponds to the bias points where Fe = Fth = 0 and allows for separation of the regions of electrically and thermally induced failure. b) The MOS operating function Fop = 0 for various junction temperatures defined for Vgs,max = 5 V and Vbe = 0 V.

6.6

Conclusions

In this chapter, an analytical procedure for identifying failure mechanisms in MOS transistors has been presented. Expressions for the electrical, thermal and electro-thermal stability factors have been derived, which can be used together with an electro-thermal characterization of the MOS and

81 CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

Thermally-induced failure

Junctionjtemp.jTjj(°C)

Fe=Fth=0

Fop=0

inhv

Feth=0

olta

gehV

ds EVx

h

mx hEA/m n I h d t urren

.hc

Norm

Ebx ExperimentalhSOVh[62] Vgs=1]5V Feth=0 Fop=0

Dra

inhvo

ltage

hV E ds Vxh

mx EA/m

h thI dn

n

urre m.hc r o N

Junctionhtemp.hTjhE°Cx

6.6. CONCLUSIONS

Dra

Junctionhtemp.hTjhE°Cx

82

Junctionhtemp.hTjhE°Cx

Vgs=1]5V

Junctionhtemp.hTjhE°Cx

Eax ModeledhSOV

Figure 6.5: Comparison between a) modeled and b) experimental [62] SOV (see also Chapter 5), showing qualitative agreement across a wide range of bias conditions. its parasitic bipolar to perform a failure analysis and determine the main root of instability. The results allow the operating limits to be mapped on the Safe Operating Volume (SOV), an analysis concept which is defined as an extension of the Safe Operating Area (SOA).

6.7

Avalanche, MOS and bipolar model equations

The model parameters have been fitted to experimental data [62], also presented in Chapter 5. M=

 1 m Vds 1− BV

BV m

(A1)

Vdsat (Tj ) = Ron (Tj ) · Idsat (Tj )    K·(V −V )αch   Ich = 1+θV gs(Vgsth−Vth ) · h  V 1 ηch i1/ηch   gs ch  1+ Vgs −V  th    (Vds −Vch ) 1+gac (Vds −Vch )  · I = I ·  i h   drift dsat Vdsat  V −Vch ηdrift 1/ηdrift  1+ ds  Vdsat   I dMOS (Vds ) = Ich (Vch ) = Idrift (Vds − Vch )

h  i  Eg 1 1  I (T ) = I (T ) · exp − −  s j s ref k T T  ref i h j    IR (Tj ) = IR (Tref ) · exp − Eg 1 − 1  2k Tj Tref    m  npn  RB (Tj ) = RB (Tref ) · Tj ref  Tm β Tj   β(T ) = β(T ) j ref  T ref      be  Ib (Vbe , Tj ) = IβS (Tj ) · exp V    VT    be  Ic (Vbe , Tj ) = IS (Tj ) · exp V + IR (Tj ) VT

(M1) (M2) (M3) (M4) (M5) (M6) (M7) (M8)

(B1) (B2) (B3) (B4) (B5) (B6)

Tref K(Tref ) mch Vth (Tref ) kth Ron (Tref ) mdrift θ Idsat (Tref ) αch θVgs ηch gac ηdrift

IS (Tref ) Eg IR (Tref ) RB (Tref ) mnpn β(Tref ) mβ

300 K 0.032 A/V2 1.5 0.82 V 1.36 · 10−3 V/K 27 Ω 1.5 750 K 0.127 A 2 0.05 V−1 1.6 3 · 10−3 V−1 1.6

10−15 A 1.12 eV [12] 10−12 A 5Ω 1.5 5 2

83 CHAPTER 6. PHYSICS-BASED STABILITY ANALYSIS

  −mch T   K(Tj ) = K(Tref ) Trefj   
  Vth (Tj ) = Vth (Tref ) − kth Tj − Tref       Tj mdrift   Ron (Tj ) = Ron (Tref ) · Tref      I (T ) = I (T ) · exp − Tj −Tref   dsat j dsat ref θ

70 V 4

CHAPTER

S UMMARY AND RECOMMENDATIONS

7.1

Summary

Chapter 1 A general overview of power semiconductor devices has been provided with emphasis on their classification and operating principle. The concepts of specific on-resistance (Ron A), breakdown voltage (BV) and safe operating area (SOA) have been introduced. They have been used throughout the thesis to analyze the limitations imposed by current, voltage and temperature to the device performance.

Chapter 2 A physics-based theory has been presented for maximizing the breakdown voltage BV of 2D RESURF drift extensions in the current flow direction without sacrificing the on-resistance per unit volume V. Using the derived analytical solutions, a procedure has been developed for designing field-plate assisted and periodic RESURF devices. The effect of deviations from ideal solutions resulting from non-optimal boundary conditions in practical devices has been analyzed with the help of numerical simulations. It has been shown that devices with curved boundaries can have a higher breakdown than devices with straight boundaries. Design guidelines for preventing other forms of breakdown (pn-junction, vertical and dielectric breakdown) have also been provided. Given sufficient technological control over the design dimensions and doping profiles, the demonstrated geometries may be implemented in both discrete and integrated power semiconductor devices.

85

7

Chapter 3

86 7.1. SUMMARY

The trade-off between the specific on-resistance expressed in units volume Ron V and the off-state breakdown voltage BV of the ideal RESURF drift extensions has been analyzed. Analytical expressions for evaluating this trade-off have been provided for the ideal RESURF structures presented in Chapter 2. The technological degrees of freedom needed for achieving ideal RESURF drift extensions are not always available in standard smart power technologies. Nonetheless, the Ron V-BV trade-off can still be improved by layout modifications in standard technology. It has been shown with measurements and TCAD simulations that a switchable field-plate electrode, separated from the gate, can be used to reduce the on-resistance of an LDMOS transistor without affecting the off-state breakdown voltage. The device based on this concept, named the boost transistor, has been analyzed in detail by sweeping the field-plate potential from negative to positive values and evaluating its effect on the off-state electric field and on the on-state carrier concentrations. A driving circuit with minimal area for the additional field-plate electrode has been proposed to reduce the on-state power dissipation. Because of the dynamic power dissipation occurring while switching the field-plate potential (see Section 7.3), the boost transistor is suited for applications with relatively-low switching frequencies.

Chapter 4 The problem of measuring the junction temperature using standard electrical equipment has been addressed. Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature measurements in power MOS transistors have been compared showing good quantitative agreement across a large junction temperature range (from room temperature up to 400 ◦ C). For each technique, the measurement setup and the operating principle have been presented, and the experimental results have been discussed. The advantages and the disadvantages of the investigated techniques have been compared in a benchmarking analysis accounting for setup simplicity, calibration issues and experimental accuracy.

Chapter 5 An extensive experimental investigation of the electro-thermal behavior of LDMOS transistors up to the edge of the operating limits has been performed. Devices having the same cross-section but different areas have been characterized in various operating conditions. By comparing the obtained results in the parameter space comprising the gate-width normalized drain current Idn , the drain-to-source voltage Vds and the junction temperature Tj , the concept of safe operating volume (SOV) has been derived as a measure of the operating limits which is more general than

commonly specified safe operating area (SOA). It has been shown that the SOV is nearly independent of device area and operating conditions and enables SOA predictions on devices with identical cross section but with different areas and operating parameters.

Chapter 6

7.2

Innovative contributions

The main contributions of this work are: • The mathematical theory for optimizing the BV trade-off of 2D RESURF drift extensions. • The concept of Safe Operating Volume (SOV) as a general measure of the operating limits of MOS transistors. • A physics-based stability analysis to distinguish between electrical, thermal and electro-thermal failure mechanisms. These contributions can be regarded as conceptual tools allowing to tailor the design of power semiconductor devices to a given mission profile. Optimizing the Ron V − BV trade-off typically constitutes the first step in the device design. However, a device having an optimal Ron V − BV trade-off can carry significant current densities in a compact structure, resulting in both thermal and electrical reliability issues. Using the proposed stability analysis, the electrical and thermal operating limits can be estimated and visualized in the SOV. It is possible that the SOV resulting from a straightforward Ron V − BV optimization does not match the requirements of the application. The device might have to operate in conditions where the electro-thermal stability factor is close to unity, making it susceptible to failure. A typical example for this occurs in automotive applications where a power transistor has to switch an inductive load. In order to prevent high-voltage spikes exceeding BV when the inductor current is switched

87 CHAPTER 7. SUMMARY AND RECOMMENDATIONS

The operating limits of MOS transistors have been investigated on a theoretical basis in order to gain insights on the physical origin of the SOV. The failure mechanisms of MOS transistors have been identified using an analytical perturbation approach. Expressions for the electrical, thermal and electro-thermal stability factors have been derived, which can be used together with an electro-thermal characterization of the MOS and its parasitic bipolar to perform a failure analysis and determine the root cause of instability. The theoretical results show that, within reasonable approximations, the operating limits can be mapped on the SOV. A comparison between the modeled and the measured SOV of SOI LDMOS transistors (from Chapter 5) has been reported to support the validity of the proposed stability analysis.

88 7.3. RECOMMENDATIONS FOR FUTURE WORK

off, a protection circuit clamping the drain voltage to a desired value (lower than BV) is used (Clamped Inductive Switching, CIS [80]). During clamping, the inductor discharges its energy on the transistor and causes its junction temperature Tj to rise. Furthermore, the clamping voltage initiates avalanche multiplication and increases the electrical stability factor. In CIS applications, the transistor area is typically overdesigned in order to reduce the thermal impedance Zth,eff and keep self-heating under control. As a result of the larger area, the Ron of the transistor is lower than what is needed by the application. This example suggests that in CIS applications optimizing the transistor for optimal Ron V −BV trade-off might not be the best choice. It would be better to tailor the design parameters in such a way to reduce the electro-thermal stability factor in the operating conditions needed by the application. More specifically, the SOV can be estimated for different design parameters using the proposed RESURF theory to obtain the Ron V − BV trade-off (and the operating function Fop ), and the stability analysis to obtain the failure function Feth . The relative contributions of Fop and Feth to the shape and extension of the SOV can be weighted according to the needs of the application. The connection between the device physical and geometrical parameters and the shape of the SOV constitutes the main outcome of this work.

7.3

Recommendations for future work

3D RESURF theory The RESURF theory presented in Chapter 2 can be extended to 3D structures and the charge density modulation caused by the on-state current can be included. The 3D Poisson’s equation in the drift extension including the on-state current density can be expressed as: ∇2 ψ(x, y, z) = −

ρ(x, y, z) − ε

|J(x,y,z)| q|v(x,y,z)|

(7.1)

where J and v are the current density and carrier drift velocity vectors, respectively. It is assumed that the fixed charge density is a linear function of x in the form ρ(x, y, z) = ρ(x) = a · x + b and that carrier velocity is saturated (|v(x, y, z)| = vsat ), resulting in a uniform |J| (simply denoted as J) across the drift extension. Applying the ideal RESURF condition (2.1) to (7.1) yields: ρ(x) − qvJsat ∂2 ψ ∂2 ψ + =− . (7.2) ∂y2 ∂z2 ε Using the lowest-order mode Fourier expansion to calculate the homogeneous solution [81], the general solution for a symmetric structure in the y − z plane can be written as: J

ψ(x, y, z) =

y z ρ(x) − qvsat 2 2 BV x− (y +z )+c1 ·cos +c2 ·cosh , (7.3) L 2ε λ λ

Switching behavior and dynamic power dissipation of the boost transistor In Section 3.2.3, a schematic example of a driving circuit for the boost transistor has been proposed by A. van der Wel. However, the circuit has not been implemented and the transient measurements in Fig. 3.9 have been performed using a signal generator and a power amplifier to drive the boost gate (field-plate). Because of the long response time of the amplifier (t ≈ 3 µs), the switching speed and the dynamic power dissipation of the boost transistor have not yet been quantified. The study of the transient behavior of the boost transistor is relevant to estimate the maximum operating frequency beyond which the dynamic losses on the boost gate become much larger than the losses on the standard gate. TCAD simulations can be performed by varying the main device parameters (doping of the drift extension, length of the field-plate, thickness of the gate/field-plate oxides and separation between gate and field-plate) to gain insight on the relationships between Ron V, BV and the switching behavior of the device, which remains one of the open questions of this work. Furthermore, issues related to the correct synchronization of the two gate signals need to be properly addressed in the driver implementation in order to avoid device breakdown during switching.

Impact of interface charge on the shape of SOV In [30], a model has been proposed to analyze the impact of interface charge on the electric field and potential of a RESURF drift extension. Charge can be present at the interface between the semiconductor and the dielectric layer as a result of the fabrication process. In addition, a buildup of interface charge can occur as a consequence of device degradation due to hot-carrier injection (HCI [9, 10]). The presence of interface charge

89 CHAPTER 7. SUMMARY AND RECOMMENDATIONS

where c1 and c2 are integration constants determined by the boundary conditions. The λ-parameter [30] is related to the transverse dimensions and plays the same role as teq (see Section 2.2.1) in determining the coupling strength of the transverse RESURF field components Ey and Ez . Applying a RESURF field in both the y and z directions allows to meet the ideal RESURF condition using a larger doping in the drift extension, thus further improving the Ron V − BV trade-off. Furthermore, including the drift current density J into (7.1) allows to maximize the breakdown voltage not only in the off-state (where J = 0) but also in the on-state (where J 6= 0). Obviously, since J affects the charge balance in the drift extension, it is not possible to achieve a flat Ex -field in both conditions and a choice of the J-value has to be made in the optimization routine. A similar 3D analysis can be performed in cylindrical coordinates to analyze and optimize the behavior of radially symmetric extensions in the y − z plane, such as nanowires [21, 81].

affects the electrical stability of the device by varying the impact ionization coefficient α (see Section 6.3.1). This results in a variation of the electrical stability factor Se , which in turn modifies Seth and the failure function Feth (defined in Sec. 6.4.1). In the stability model proposed in Chapter 6.3 this effect has not been considered and electrical failure due to impact ionization has simply been modeled using a Vds -dependent impact ionization coefficient M(Vds ). A more accurate model accounting for the full field dependence of the impact ionization coefficient can be expressed in the form: M= 90

1 , 1 − α(E(Nit ))

(7.4)

7.3. RECOMMENDATIONS FOR FUTURE WORK

where α is the spatial integral of the impact ionization coefficient, E is the electric field vector, and Nit is the interface charge density [30]. Using (7.4), the shape of the failure function Feth (and therefore of the SOV) can be calculated as a function of the interface charge. In addition, the SOV can be characterized over time during stress measurements aimed at studying device degradation in order to link the shape variation of the failure volume Veth to the build up of interface charge. For details about the extraction of interface charge from electrical measurements, the reader is invited to consult [82] and Chapter 4 of [9].

Existence of the SOV in bipolar devices In Chapters 5-6, the general nature of the SOV has been investigated both experimentally and theoretically. In particular, it has been shown that a physics based analysis based on a compact model of a MOS transistor and its parasitics can predict the existence of the SOV and allow to determine its shape. A similar stability analysis can be performed on bipolar devices [78]. By plotting the results in [78] in the (normalized) current-voltagetemperature space, the bipolar SOV can be determined. However, the fact that the SOV can be obtained based on a compact model does not prove its general nature of being independent of geometry and operating conditions. The main assumption underlying the existence of the SOV is that the physics inside the transistor is uniquely determined by the normalized current, the anode-to-cathode voltage and the junction temperature. This is only true if the spatial variations in the current density, electric field and the temperature distribution over the transistor geometry can be neglected and hysteresis does not occur in the I − V curves. If this is the case, it is possible to associate unique values of normalized current, anode-to-cathode voltage and junction temperature to a current density, electric field and temperature distribution, respectively. This association is implicit when using a compact model and works well on MOS transistors in the operating regime where the current behavior is dominated by the drift current, which has a negative temperature coefficient. This means that

Extrinsic failure mechanisms In this work, the operating limits of power semiconductor devices have only been related to their intrinsic electro-thermal properties. Extrinsic failure mechanisms due to the device embedding in more complex systems (for example, a power conversion circuit) have not been considered since they require prior knowledge about the nature and the dynamics of system itself. Nonetheless, it is worth mentioning a critical thermo-mechanical failure mechanism occurring on the device back-end and related to the metal interconnects between the current carrying terminals. When the junction temperature rises because of self-heating, the semiconductor and metal layers expand in volume and exert mechanical pressure on the backend dielectric. As a result of this pressure, voids are formed in the dielectric. This voids can be filled with metal and cause short circuits between the interconnects [83]. The temperature rise in the interconnects when the device is subjected to high power current pulses determines a gradual change in both the shape and the chemical composition of the metal lines. The resulting change in the

91 CHAPTER 7. SUMMARY AND RECOMMENDATIONS

the current decreases as the junction temperature increases. If an inhomogeneity in the current distribution occurs, the device becomes locally hotter in the regions where the current density and the electric field are larger in magnitude, and vice versa. As a result of the temperature variation, the hot spots start carrying less current than the cold ones, and a negative feedback mechanism occurs which makes the current density and the temperature distribution approximately uniform across the device area. In bipolar devices, when a base current is applied, the current behavior is dominated by the diffusion of charge carriers if series resistance effects in the base and the emitter can be neglected. Since the diffusion temperature coefficient is positive, the current in hot spots increases rather than reducing. This leads to a positive feedback mechanism which can result in current crowding and localized heating. When these conditions occur, the general nature of the SOV breaks down. As shown in Chapters 5-6, electrothermal failure in MOS devices is often associated to the positive feedback induced by the parasitic bipolar (latch-up). When latch-up occurs, a significant portion of the device current is carried by the bipolar rather than the MOS, and the electro-thermal stability factors quickly approaches unity. In order to experimentally determine the SOV at the edge of instability, it is necessary to limit the maximum allowed value for the electro-thermal stability factor Seth . Using Seth = 0.2 as a failure condition rather than Seth = 1 limits the bipolar contribution to the overall current and preserves the general nature of the SOV in MOS transistors (as well as their physical integrity!). It would be of interest to repeat the SOV investigation on BJTs and experimentally determine the limitations imposed by the diffusion current to the existence and general nature of the SOV.

interconnect resistivity can be used as a monitor for back-end degradation [84].

Wide bandgap semiconductors

92 7.3. RECOMMENDATIONS FOR FUTURE WORK

While the experimental investigations of this work have been limited to silicon devices, the RESURF theory and the SOV concept are generally applicable to other types of power semiconductor devices. In recent years, there has been a growing interest in wide bandgap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), for power applications [85]. These materials can sustain larger critical fields because of their wider band gap, and exhibit a higher electron mobility than silicon. As a result, they can provide a better Ron V − BV trade-off. At present time, there is plenty of research activity in both industry and academia [86] aimed at manufacturing reliable GaN power devices. Issues related to current collapse [87, 88] and optimization of the metal contacts [89] are gradually being solved and the costs of the manufacturing process have been significantly reduced. As suggested in [90], it is expected that GaN transistors will dominate the market of discrete power devices in the near future (GaN is ready to fire!). Regarding smart power applications where integrated devices are needed, silicon is still expected to be the leading material due to the difficulties in manufacturing a reliable and performant pMOS (needed to implement logic gates) in a GaN process.

Genetic optimization of RESURF devices In the last section of this work, the possibility to optimize the trade-off between Ron V, BV and the operating limits using genetic optimization algorithms is explored. Genetic algorithms are stochastic search techniques modeled on the principles and concepts of natural selection and evolution [91]. They are often applied to the design of microwave and optical systems because of their robustness and their capability to deal with highly non-linear and non differentiable functions [92, 93]. They are also used in the design of electrical power systems [94], and they have been applied to the extraction of transistor parameters [95]. Nonetheless, to the author’s best knowledge, the problem of the evolutionary design of semiconductor devices has never been addressed in literature. In this work, a connection has been established between the overall shape of the SOV and the physical and geometrical parameters of the transistor. In Chapter 6, it has been shown how the SOV can be calculated based on a compact model of the transistor. The problem can be reversed by starting with a given SOV and determining the compact model parameters needed to obtain the specific SOV shape. This reasoning can be further extended to the determination of the shape and material composition of a power semiconductor having the desired SOV.

93 CHAPTER 7. SUMMARY AND RECOMMENDATIONS

In principle, TCAD simulations could be used to determine the SOV for each device cross-section produced by the genetic algorithm. However, the computational time would be enormous, making a TCAD based procedure not very attractive. The proposed alternative to TCAD consists in using the RESURF model of the drift extension (see Chapter 2), expanded with the suggestions of this Chapter for modeling the on-state breakdown voltage and electrical stability. Thermal effects and the parasitic bipolar latch-up can be included by means of physics-based compact models as shown in Section 6.2. The genetic approach has the potential to unravel optimal device configurations that have never been considered because of the limitations on the number of available degrees of freedom imposed by the fabrication process. At present time, the space of design parameters is not large enough to justify evolutionary approaches and optimized devices can easily be obtained using faster optimization routines. Nevertheless, the author thinks that the investigation of the ultimate theoretical limits of power semiconductor devices can lead to significant advances in the field of power electronics once the necessary technology for manufacturing complex structures is readily available.

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L IST OF PUBLICATIONS Peer-reviewed [AF:1] A. Ferrara, B. K. Boksteen, A. Heringa, R. J. E. Hueting, and P. G. Steeneken, “Ideal RESURF geometries,” IEEE Trans. Electron Devices , vol. 62, no. 10, pp. 3341–3347, 2015. [AF:2] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz, and R. Hueting, “Physics-based stability analysis of MOS transistors,” Solid-State Electron., vol. 113, pp. 28–34, 2015. [AF:3] A. Ferrara, A. Heringa, B. K. Boksteen, J. Claes, A. van der Wel, J. Schmitz, R. J. E. Hueting, and P. G. Steeneken, “The boost transistor: a field plate controlled LDMOST,” in ISPSD Proc., pp. 165–168, 2015. [AF:4] A. Ferrara, J. Claes, M. Swanenberg, L. van Dijk, P. G. Steeneken “Accelerated Resistance Degradation in Aluminum by Pulsed Power Cycling,” in ISPSD Proc., pp. 301–304, 2015. [AF:5] B. K. Boksteen, A. Heringa, A. Ferrara, P. G. Steeneken, J. Schmitz, and R. J. E. Hueting, “Electric field and interface charge extraction in field-plate assited RESURF devices,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 662–628, 2015. [AF:6] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, and R. J. E. Hueting, “Impact of interface charge on the electrostatics of field-plate assisted RESURF devices,” IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2859–2866, 2014. [AF:7] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz, and R. Hueting, “Identifying failure mechanisms in LDMOS transistors by analytical stability analysis,” in ESSDERC Proc., pp. 321–324, 2014. [AF:8] A. Ferrara, P. G. Steeneken, A. Heringa, B. K. Boksteen, M. Swanenberg, A. J. Scholten, L. van Dijk, J. Schmitz, and R. J. E. Hueting, “The safe operating volume as a general measure for the operating limits of LDMOS transistors,” in IEDM Proc., pp. 6.7.1–6.7.4, 2013. [AF:9] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, G. E. J. Koops, and R. J. E. Hueting, “Design optimization of field-plate assisted RESURF devices,” in ISPSD Proc., pp. 237–240, 2013. [AF:10] A. Ferrara, P. G. Steeneken, K. Reimann, A. Heringa, L. Yan, B. K. Boksteen, G. E. J. Koops, A. J. Scholten, R. Surdeanu, J. Schmitz, and R. J. E. Hueting, “Comparison of electrical techniques for temperature evaluation in power MOS transistors,” in ICMTS Proc., pp. 115–120, 2013. [AF:11] B. K. Boksteen, S. Dhar, A. Ferrara, A. Heringa, R. J. E. Hueting, G. E. J. Koops, C. Salm, and J. Schmitz, “On the degradation of field-plate assisted RESURF power devices,” in IEDM Proc., pp. 13.4.1–13.4.4, 2012. [AF:12] A. Cutolo, A. Ferrara, A. Cusano, M. Pisco, D. Mascolo and A. Ricciardi, “Compact tunable terahertz source: perspectives on planar configurations,” in SPIE Europe Security and Defence Proc., vol. 7485, 2009.

Other [AF:13] A. Ferrara, P. G. Steeneken and L. van Dijk, “Sensor controlled transistor protection ,” U.S. Patent US20 150 098 163 A1, 9 Apr 2015. [AF:14] A. Heringa, G. Koops, B. K. Boksteen, and A. Ferrara, “Field plate assisted resistance reduction in a semiconductor device,” U.S. Patent US20 140 103 968 A1, 17 Apr 2014.

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A CKNOWLEDGMENTS Four years of phD have passed. To be honest, I was not sure I would have gone as far as to write this section. Now that I am writing it, I am not sure weather A CKNOWLEDGMENTS is the appropriate title. Perhaps I should name it A CKNOWLEDGMENTS & A POLOGIES, but it does not sound very professional. I had to pleasure to work with great colleagues both in Enschede and Eindhoven. I am aware I have not always been a good colleague myself, and I truly appreciate the professional and human support I received from all of you, especially during my mid PhD crisis. Starting from my promoter Jurriaan Schmitz. Jurriaan, you have been the first person I had contact with in the Netherlands and believed in me since the beginning. When I was back to Enschede after my two-year internship at NXP in Eindhoven, you realized my behavior and working attitude had changed for the worse. You have tried your best to help me find my work enthusiasm back and convince me to have a more regular daily routine. I have always found your advice very precious, although we both know I have not always listened to it. Thanks and sorry for that. I have met some phD students who complained about their daily supervisor. I had two of them, Ray Hueting in Enschede and Peter Steeneken in Eindhoven, and hardly ever had a chance to complain about them. Ray, thank you for always supporting my plans and for the very precious help in revising and finalizing my paper drafts. I realize you would have liked to see me around more often, but unfortunately we are very different in the fact that you are an early morning person while I am a late night one. I cannot forget the times when I was sending you an abstract in the middle of the night before a conference deadline just to find your reply in the mailbox a few hours later. Peter, thank you for your daily supervision at NXP. Working with you has helped my growth as a scientist. You have shown me how to practically and efficiently solve problems under time pressure. You have inserted me in the company environment by introducing me to most of your colleagues and allowing me to participate to interesting internal meetings. Not to mention the countless times you have helped me with measurements, simulations and writing. Thank you also for the advice you gave me when I was having some personal trouble. As for Jurriaan, I have not always acted accordingly, but I have at least taken your words into consideration. To the reader. If you happen to come across this work and find its content useful, you are strongly encouraged to read it together with the thesis of Boni K. Boksteen. Our collaboration has produced most of our phD results. Boni, you are a great 101

102 ACKNOWLEDGMENTS

colleague and friend. Four years ago, when I first came to Enschede for interviews, you were halfway your phD and spent a full afternoon explaining your research to me. The enthusiasm in your words has been the main reason why I started this project. I am very happy about the results we have achieved together, which meant hours of technical discussions and scribbling on a whiteboard. A special thank goes to Anco Heringa, who has been actively involved in my project. Anco, your experience and expertise have been a strong added value. You are very meticulous and investigate problems very deeply, often questioning assumptions we all give for granted and spotting mistakes while doing that. This feature of yours has sometimes put my patience to proof, but it helped to consistently improve the quality of our work. You have kept an eye on my research also after your retirement, which I really appreciated. I would also like to thank the scientists in NXP who followed my project giving me useful advice and material to work on: Martijn Goossens, Klaus Reimann, Andreis Scholten, Maarten Swanenberg, Jan Claes, Steve Sque, Joeren Croon, Fred Hurkx, Olaf Wunnicke, Radu Surdeanu, Luc van Dijk, Piet Wessels, Liang Yan, Phil Rutter. Last but not least, my acknowledgments to the members of the semiconductor components group of the University of Twente I had the chance to work with, including those who are no longer part of it: Cora, Alexey, Sander, Tom, Dirk, Rob, Remke, Annemiek, Jiahui, Marcin, Satadal, Sourish, Mendgi, Frank, Oguzhan, Svetlana, Hao, Tom Tom, Balaji, Buket, Sumi, Vidhu, Giulia. Ah, I was almost forgetting about some friends who have not been directly involved in my work but have been close to me in good and bad times: Jorge, Danielle, Alia and Luca. If you feel your name should also be here but you do not see it, feel free to take a pencil (not a pen please!) and add it to the list. Alessandro Ferrara 9 November 2015 Enschede

Propositions Accompanying the thesis

RESURF power semiconductor devices Performance and operating limits Alessandro Ferrara

1.

A proper definition of RESURF involves the slope of the longitudinal component of the electric field rather than its magnitude (Chapter 2 of this thesis).

2.

Defining the specific on-resistance times unit volume rather than times unit area makes it independent of the device orientation relative to the wafer (Chapter 3 of this thesis).

3.

Time and frequency domain approaches are equally suitable for measuring the junction temperature of transistors (Chapter 4 of this thesis).

4.

The inconvenient test condition dependence of the safe operating area can be resolved by consideration of the instantaneous junction temperature (Chapters 56 of this thesis).

5.

Genetic algorithms can be applied to optimization of RESURF power devices (Chapter 7 of this thesis).

6.

The main purpose of a model is to develop intuition for the interactions between physical phenomena. The accurate reproduction of experimental results is a desirable side effect.

7.

Collecting measurement data on a notebook is more enjoyable than downloading them from a file.

8.

Sharing knowledge is instinctive. Information theft should be an oxymoron rather than a crime.

9.

Competition is a healthy way to stimulate progress, but collaboration is far superior.

10. Unlike laws of nature, which make sense if there are systems obeying them, legislative laws only make sense if there are individuals willing to break them.