Ring-gate MOSFET Test Structures for Measuring ... - IEEE Xplore

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Ring-gate MOSFET test structures have been developed with which a differential measurement technique can be used to accurately determine the ...
2006 International Conference on Microelectronic Test Structures

Ring-gate MOSFET Test Structures for Measuring Surface-Charge-Layer Sheet Resistance on High-Resistivity-Silicon Substrates S. B. Evseev, L. K. Nanver and S. Milosavljević Laboratory of ECTM, DIMES, Delft University of Technology, P.O. Box 5053, 2600 GB Delft, The Netherlands. measurements have been applied but neither methods give a direct measurement of the charge conductance at the surface itself, nor is the biasing dependence characterized [2, 7].

ABSTRACT Ring-gate MOSFET test structures have been developed with which a differential measurement technique can be used to accurately determine the surface-charge-layer sheet resistance on high-resistivity-silicon substrates. The difference in substrate properties and influence of special surface passivation techniques that are designed to suppress the otherwise conductive surface channel can thus be monitored and characterized for RF transmission line applications.

TEST STRUCTURE FABRICATION AND MEASUREMENT With the available masks in DIMES-04 several different types of ring-gate MOSFET structures can be designed, the most straightforward of which is shown in Fig. 1(a). The HRS substrate is a p-type 2 − 4 kΩ ⋅ cm 100 mm wafer. For comparison, test structures are also processed on 2 − 5 Ω ⋅ cm p-type low-resistivity (LRS) wafers. Source and drain regions are high-dose phosphorus implants that are connected via the first metallization layer in which the gate is also patterned. The results reported here are for the “ideal” situation where the surface isolation is 25 nm high quality gate oxide. Thus, the gate capacitance per area is high, the oxide charge is low and the analysis is focused on the coupling with the substrate. Circular ring-gate MOSFETs are designed with the purpose of extracting parameters related to the laterally uniform part of the gate region by subtracting peripheral contributions, associated with the source and drain regions, from the measurements. Sets of test structures are designed for which the radius rg to the center of the gate is always the same. Thus, the width of the gate, W, can be defined at the center and the total gate perimeter is 2W in all cases. The on-mask metal gate length is varied and because the depletion widths around the S/D reverse biased n+p- diodes are very wide in HRS, around 20 µm at zero bias, much larger L’s are designed. For the results presented here rg = 164 µm, W = 1030.5 µm and L = 10 µm, 20 µm, 40 µm, 100 µm, and 200 µm. The argon implant is performed through the gate oxide just before metallization with energy of 180 keV to a dose of 1015 cm-2, which amorphizes about 300 nm of the surface silicon. As shown in Fig. 1(b) the implant is placed at the center of the gate and thus also has a center radius of rg. In these experiments the length of the argon implanted region, LAr, is 0, 2 µm, 5 µm or 199 µm and is implemented for different gate length values. The current-voltage measurements are performed with Agilent 4156C Parameter Analyzer on Cascade Microtech probe station equipped with DCM200 probes that have a negligible probing series resistance.

INTRODUCTION High-resistivity silicon (HRS) is an attractive substrate material for the integration of radio-frequency (RF) passive components because the RF losses to the substrate can be kept low. To achieve ideally low coupling to the substrate the use of HRS must, however, be combined with special surface treatments to avoid parasitic losses along the Si surface. These are associated with conduction in accumulation or inversion layers that readily form in lowdoped semiconductors in the vicinity of the semiconductordielectric interface. Elimination of these parasitic losses can be achieved by modifying either the composition of the dielectric [1, 2] or the surface quality of the Si by, for example, amorphization via ion implantation or by depositing polysilicon or α-Si [3]. A valuable parameter for the characterization of such surface treatments, both for process development/control and for circuit simulation, is the charge carrier effective mobility at the interface [4], which together with the charge storage at the interface determines the sheet resistance, RSH , of the surface channel charge. In this paper, we present ring-gate MOSFET test structures for the direct determination of RSH as a function of the gate biasing conditions. These structures have been designed and integrated in the DIMES-04 bipolar process on HRS [5] that includes a high-dose argon implantation to suppress the surface channel. The transmission lines fabricated in this process, also as part of active RF circuits, have demonstrated the great effectiveness of this type of surface passivation [6]. However, to understand the physical mechanisms of the surface channel charge transport other test structures are needed. In the past capacitance-voltage and four-point resistivity

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Fig. 1. (a) Photo of a ring-gate MOSFET test structure with L = 200 µm. (b) Schematic cross-section of a structure with argon implantation, drawn from the center through to the p+ contact to the HRS substrate, (c) Schematic cross-section of the method used to extract Rij when either the proportionality factor

α ijlinear or α ijcenter is used to calculate RSH , (d) Schematic cross-section of the method used to extract Rij when the proportionality factor α ijedge is used to calculate RSH .

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1 1  rg + 2 Lij  ln  (3) . 2π  rg − 12 Lij  (iii) Third, in the case where Li VT , 0 < VDS < V pinch −off . (1) I DS Below VT the device is in accumulation/depletion and only S/D reverse leakage currents contribute to Rm . To extract RSH a differential measurement technique is applied to eliminate the series resistance associated with the S/D contacts that cannot be measured directly. Since the sets of ring-gate structures are designed with a total gate perimeter 2W that is independent of the gate length, only two variables per MOSFET are important for the extraction, i.e., Rmi and Li , where the indices i = 1,…,n refer to each specific test structure in the given set of n structures. For the following calculations the structures are organized so that Li < Li +1 , and i < j . Since the structures are ringshaped, the radial spreading of the current must be taken into account. Below, three methods of performing the differential extraction, each with an increasing degree of complexity and validity, are described:

perimeter regions that have a total length of Lij . This extraction procedure is accurate if the lateral nonuniformities at the perimeter of the gate, as defined by the on-mask dimensions, can be neglected. If this is not the case, a ∆L can be defined so that Li − 2∆L and L j − 2∆L are perfectly uniform gate regions. Then a modified relationship between Rij and RSH can be found by

(i) First, a linear approximation can be made if L j ≈ Li