Ronald E. Giachetti Department of Industrial and

O PTIMIZING P RINTED C IRCUIT B OARD A SSEMBLY D URING

THE

D ESIGN P ROCESS

Ronald E. Giachetti Department of Industrial and Systems Engineering Florida International University Miami, FL 33174

Abstract: This paper investigates the incorporation of optimization techniques early in the design process for the manufacturing process of printed circuit board (PCB) assembly. PCB design is a long process in which many sequential optimizations are performed with assembly optimization being the last. Since assembly optimization is not performed until the PCB design is completed it tends to be sub-optimal; however, engineers are reluctant to change the PCB design at that late stage due to market pressure for quick product introduction. This paper proposes a model which incorporates a PCB assembly optimization model into the PCB design stage when board layout occurs. The mathematical optimization model utilizes the available incomplete design information and provides a satisficing PCB layout with respect to routing performance and assembly objectives. A decision-making model is applied to facilitate the design engineer in harmonizing differences between the optimal assembly layout and the optimal electrical performance (routing) layout. The approach will enable the design engineer to analyze the trade-offs between cost (assembly) and performance (routing). The expected benefits are to reduce manufacturing cost and improve firstpass yield of the PCB. The methodology will be benchmarked against current approaches to quantify the improvements in manufacturability. Results of this work are illustrated and validated with several test cases.

INTRODUCTION Electronics is the largest and most global industry in the world. The worldwide market is $993 billion and is expected to be $2 trillion within a decade [Tummala, 1998]. No other manufacturing sector is experiencing such growth. A primary component of electronic products is the substrate or printed circuit board (PCB) which is custom-made and provides the interconnection for the circuit. The industry competes based on functionality, quality, cost, and time to market. It is the later, time to market, that is increasingly become the most important factor in the success of electronics companies and this places an excessive burden on the product development teams in these companies to rapidly design and manufacture new products. The paper specifically targets PCB design and assembly because it is a significant component of the overall cycle-time, a high cost component of electronic products, and the source of many quality problems. The designs of PCB assemblies rely on highly interdisciplinary teams with expertise in electrical, mechanical, thermal, quality, and manufacturing engineering. Current design procedures focus on partitioning the PCB design into a series of mathematical optimization problems with a single performance metric that serves as the objective function. However, considering the context of the

integrated product and process design (IPPD) team a more relevant approach is decision-based design. The decision-based design approach has gained enthusiastic support recently and appears to be a promising approach in PCB design. In decision-based design theory the designer makes decisions in an environment of uncertainty and risk. The objectives shifts from finding a single optimal solution to finding a solution that satisfies many and oftentimes conflicting objectives to arrive at an efficient design. Salient characteristics of the decision-based design problem are; (1) design decisions occur sequentially in time; (2) preliminary design information contains greater uncertainty and imprecision than later design information; (3) earlier design decisions constrain later design decisions; and (4) design decisions have multiple and often conflicting criteria. When these characteristics are considered deficiencies in current design practice and design systems become evident. Current design approaches are based on the theory of quickly narrowing down all the design alternative concepts to a single concept and then iteratively improving that design concept. Most existing design systems require the assigning of precise values to design parameters, which forces designers to, in many cases, arbitrarily assign values that impose unnecessary restrictions on the design due to inherent uncertainty. In this paper we examine the PCB design process. A new design methodology is developed to explicitly include assembly in the early decisions and optimization problem formulation. The goal is to design in a good assembly layout early in the design process and therefore reduce the overall time-to-market.

PCB DESIGN AND PROCESS PLANNING BACK GROUND PCB design consists of the following phases; schematic logic design, packaging design, component layout and conductor routing, and design rule check [Ginsberg, 1991]. Logic design is creation of the electrical circuit necessary to meet the functional design requirements. Packaging design is a process of mapping logic functions to physical components. Component layout and routing is design of the physical location of components on the PCB and the interconnections on the PCB, respectively. The component layout problem is to place the components to minimize the overall area of the PCB and to minimize the wiring required for interconnection. Routing is then usually performed with autorouters that attempt to minimize total wire length. The focus here is on PCB layout because not only does it effect electrical performance but it also impacts assembly. Process planning of PCBs includes the following related problems; group allocation, feeder assignment, and assembly-sequencing [McGinnis et al., 1992]. Group allocation is the problem of organizing PCBs into families that will have a common setup and assigning these families to different machines so to minimize changeover time between jobs. The feeder allocation problem is to assign component part numbers to feeders so as to minimize assembly time. The assemblysequencing problem determines the optimal sequence of component onsertions to minimize assembly time. The three process planning problems are interdependent; however, optimization procedures generally only consider isolated sub-problems. Askin et al., (1994) address the group allocation problem using a heuristic algorithm to form part families with nearly identical component onsertion times. Ammons et al., (1991) provide a methodology for assigning components to feeders and assembly sequencing for a family of PCBs on a concurrent placement machine. The assembly sequencing problem for sequential machines has been studied by Ball and Magazine (1988) who assume the feeder allocation is fixed and model the problem as a traveling salesmen problem. Dresner and Nof (1984) also addressed the sequential machine. Concurrent or multi-head machines are more complicated. Leipala and Nevalainen (1989) developed an algorithm for a turret type multi-head assembly machine. Sohn and Park (1996) improved the multi-head algorithm. Grotzinger (1988) optimize a concurrent machine using an integer problem formulation for feeder assignment and assembly sequencing. Most machines and algorithms assume a fixed pick up and fixed place location. Both the feeder assignment and assembly sequencing problems are NP-hard and the mathematical programming research has been performed towards the development of heuristic algorithms to minimize assembly time. As noted

by De Souza and Wu (1995), the mathematical programming approaches are unique for a particular machine configuration, are not extendable to the general problem, and have a single objective, thus ignoring the multi-objective decisions that must be made. Few researchers have investigated incorporating assembly considerations into the PCB design phase. Krishnan and Srihari (1995) present a knowledge based design for assembly system. Kim et al. (1992) present a constraint based system for PCB assembly. These systems integrate with the layout problem by providing additional rules or constraints on component location. They can prevent designers from poor designs with respect to assembly but they cannot lead the designer to a better design. Kusiak and He (1997) recognize this problem and propose a design for agile assembly methodology based on optimization. They build an integer programming model to assign components to feeders and board locations. However, they do not consider how these decisions affect the routing. The PCB component layout problem attempts to layout components to minimize total wire length and board area. A second objective of the IPPD team should be to layout the components so as to minimize assembly time. These two objectives are incommensurate and a trade-off between them is required. As noted in the literature review current approaches use mathematical optimization and only consider the wire length objective. Moreover, the current algorithms require the layout of components to exact coordinates. Consequently, layout is performed without considering impact on cost, i.e. assembly. The examination of the PCB design and process planning activities leads to two observations: (1) PCB design and process planning is disjoint. (2) Optimizations are performed sequentially ignoring the interdependencies between each phase. This paper addresses these two issues by performing a two-stage combined optimization of both component layout and assembly. In the next section we present the methodology. Section 4 presents computational results which is followed by a discussion of results.

COMBINED PCB WIRE LENGTH AND ASSEMBLY TIME OPTIMIZATION A two-stage optimization model for minimizing assembly time and total wire length is presented here. The first stage optimization algorithm will assign components to partitions based on assembly objectives. Within each partition the IPPD team is indifferent to component location with respect to the assembly objective. The layout problem is thus changed to an assignment problem and narrows the layout solution set from the entire PCB area to a specific partition. The second optimization stage locates each component within its assigned area to minimize total wire length according to electrical performance objectives. In the two-stage optimization both performance criteria and assembly criteria are considered in the developing the component layout. STAGE 1: ASSEMBLY TIME MINIMIZATION MODEL

The problem configuration is shown in Figure 1. The PCB has area A, partitioned into m disjoint m

areas called P1, …, Pm such that

UP

j

= A . Model assumptions are derived from the Manncorp

j =1

ECM 97 Chip Placer machine [Manncorp, 1998]. This assembly machine is a gantry style robot with the component feeders arranged on two sides of the PCB. A feeder can feed only one component part type. The head moves between feeder and location to place each component while the PCB remains stationary. The assembly head is controlled by independent servo motors in the x and y direction. The time between two points is the maximum time to move in either axis. Time is assumed to be proportional to the Tchebychev distance of Dij = max xi − x j , y i − y j between two

(

)

points. In this case, between the feeder’s pick up location i and the centroid of each partition j.

P1 F1

Fi P2

F2

Fn P3

Pm

Figure 3. Problem configuration The following variables describe the problem; Dij = distance between feeder i and PCB partition j n = number of feeders m = number of PCB partitions Pj = area of partition j Qk = quantity of component type k to be placed The problem can be modeled as a variation of the quadratic assignment problem. The first set of decision variables assign components to feeders. The second set of decision variables assign components to partitions on the PCB. The objective function is to minimize the summation of distances traveled to assemble each component from its assigned feeder to its assigned PCB partition. The decision variables are defined as: 1 component k is feed by feeder i x ki =  0 otherwise 1 component k is in location j x kj =  0 otherwise The model is presented here: n n m

∑∑ ∑ Dij xki xkj

Min

k =1i =1 j =1

subject to: n

∑ xki = 1;

for k = 1, ... , n

(1)

i =1 n

∑x k =1

ki

n

∑s k =1

k

= 1; for i = 1, ... , n

x kj ≤ C j ; for j = 1, ... , m

(2) (3)

n

∑x k =1

kj

= Q j ; for j = 1, …, m

(4)

Constraint 1 states that each feeder i has only one component type k assigned to it. Constraint 2 states that each component k is assigned to only one feeder i. Constraint 3 limits the area of all the components assigned to a partition to fit within the partition area. Constraint 4 ensures that all the components of a particular type k are assigned to partitions on the PCB. The solution assigns components to feeders and components to the partitions such that the total assembly time is minimized. STAGE 2: TOTAL WIRE LENGTH MINIMIZATION MODEL

The second phase is based on electrical performance; to minimize total wire length. A reasonable heuristic is that components with many connections between them should be placed close together and components with few or no connections should be placed far apart. Quinn and Breuer (1979) took this basic approach but instead of considering wire length they considered thermal management. The number of connections between components is modeled as the flow fij between component i and component j. The objective function is to minimize the summation of weighted flow and distance. Wire routing is performed on a grid with all x-directional wires on one layer and all y-directional wires on another layer. Therefore, in this model the rectilinear distance measures the interconnection length between any two components. The model is:

∑ ∑ f (x n −1

min

n

i =1 j = i +1

ij

i

− x j + yi − y j

)

subject to xi − x j + Mz ij ≥

1 (li + l j ) + cij 2

yi − y j + M (1 − z ij ) ≥

(5)

1 (hi + h j ) + cij 2

(6)

z ij (1 − z ij ) = 0

(7)

Constraints 5 and 6 prevent the components from overlapping in either the x or y axis. M is a very large integer and cij is the clearance spacing required between components to allow access for assembly heads. Constraint 7 ensures that zij is either 0 or 1, which in turn will ensure that only one of constraints 5 or 6 are active. The solution to this model will layout the components so as to minimize the total interconnection wire length without regard to the assembly solution. To maintain consistency with the stage one model further constraints are necessary. The additional constraint states that the x and y coordinate of component i must be in the subset defined by the partition Pj it was assigned to. The constraint is, xi , y i ∈ Pj ⊆ A

[

]

[

]

The boundaries of Pj are defined in the x-axis as x −j , x +j and in the y-axis as y −j , y +j . The model is locating the centroid of the components so the component locations must be offset from the partition boundaries by half their length in that axis. The constraints become, − xCk +

li l + ≤ xi ≤ xCk − i 2 2

(8)

− y Ck +

hi h + ≤ y i ≤ y Ck − i 2 2

(9)

The complete wire length minimization model finds a component layout such that the total wire length interconnecting the components is minimized whilst the components stay within their partitions as assigned in the assembly time minimization.

SOLUTION METHODOLOGY The stage 1 and stage 2 models are both non-linear. In the stage 1 model the problem complexity is related to the number of component types, which is less than the total number of components. A PCB may have 100 components but only 30 to 40 distinct part numbers. Thus, when modeling and solving the problem using Hyper Lingo 5.0 commercial software solutions were found in a reasonable time. The stage 2 model is non-linear due to the absolute value function in the objective function and the constraints and is difficult to solve except for small problems (number of components less than 20). To overcome this three strategies are available: (1) reduce problem size; (2) linearize model; (3) use a heuristic solution algorithm. Option 1 is the simplest and also frequently feasible. Treating several components as a group can reduce problem size. The following heuristic rules are used to define suitable groups. 1. group bypass capacitors with the DIPs they serve 2. group memory components together 3. group resistors together 4. group component pairs that have high interconnect between them Capacitors are small in relation to the DIPs so grouping them with the DIPs reduces the problem size without affecting the solution. Rule two is justified since this is a common design restriction imposed on layouts. Resistors also are small relative to other components and can be grouped together. Rule four recognizes that the objective of layout is to minimize wire length by locating components with high interconnect close together. Often, the designer can identify these components together and then treat them as a pair in the model. Using these rules problem size as measured by number of components can routinely be reduced by 30% to 40%. Oftentimes, this is sufficient to obtain a feasible solution.

ILLUSTRATIVE EXAMPLE AND RESULTS An illustrative PCB design example is presented in order to present the two-stage methodology. A PCB with 11 components is partitioned into 6 areas with 6 feeders. A traditional layout without considering assembly leads to a routing optimal total wire length of 26 units. The routing optimal layout has an assembly time of 20 units. The solution to the two-stage assembly and routing model has a total wire length of 35 units and an assembly time of 12 units. The solution to the two-stage approach is 35% worse in terms of routing length but 66% better for assembly. Hence, an increase in wire length was traded off for an improvement in assembly time. The two solutions: a routing optimal (traditional) and a combined assembly/routing solution provide alternatives for negotiation within the IPPD team. Depending on the product, assembly time may be more important than wire length; it is the decision of the IPPD team to determine these importance weights which will lead to different layouts.

CONCLUSIONS The example IPPD problem, while rudimentary, served to illustrate a two-stage model and algorithm for minimizing both assembly time and total wire length. The purpose of the model is to provide a framework for the IPPD team to consider all aspects of the PCB design to manufacturing process early in the design process. Flexibility is achieved by assigning components to partitions for assembly and then using these partitions as constraints on location in the second stage wire minimization model. The approach holds promise for minimizing the number of design iterations necessary and by considering product assembly during layout. The benefit of the model is solid information on which to make design trade-offs. In this case, trading off wire length versus assembly time. The preliminary results are promising and suggest that far greater improvements in PCB design can be achieved by more detailed and formal methodologies.

REFERENCES Ammons, J.C., McGinnis, L.F., and Tovey, C.A., Process planning for surface mount, Proceedings SMI ’91, San Jose, CA (August 28, 1991). Askin, R.G., Dror, M., and Vakharia, A.J., Printed circuit board family grouping and component allocation for a multimachine, open-shop assembly cell, Naval Research Logistics, 41, 587-608, 1994. Ball, M.O., and Magazine, M.J., Sequencing of insertions in printed circuit board assembly, Operations Research, 36, 192-201, 1988. De Souza, R., and Wu, Lijan, Intelligent optimization of component onsertion in multi-head concurrent operation PCBA machines, Journal of Intelligent Manufacturing, 6, 235-243, 1995. Drezner, Z., and Nof, S., On optimizing bin picking and insertion plans for assembly robots, IIE Transactions, 16(3), 262-270, 1984. Grotzinger, S., Feeder assignment models for concurrent placement machines, IIE Transactions, 24(4), 31-46, 1992. Kim, C., O’Grady, P. and Young, R.E., Test: A design for testability system for printed wiring boards, Journal of Electronics Manufacturing, 2, 61-70, 1992. Krishnan, S., and Srihari, K., A knowledge-based object oriented DFM advisor for surface mount PCB assembly, International Journal of Advanced Manufacturing Technology, 10, 317-329, 1995. Kusiak, A., and He, D., Design for agile assembly: an operational perspective, International Journal of Production Research, 35(1), 157-178, 1997. Ginsberg, G.L., Printed Circuit Design, (Mc-Graw Hill, NY, 1991). Quinn, N.R., and Breuer, M.A., A force directed component placement procedure for printed circuit boards, IEEE Transactions on Circuits and Systems, CAS-26(6), 377-388, 1979. Tummala, Roa, Packaging Research Center’s 4th Annual NSF Review, Georgia Tech, Oct. 20-22, 1998 Atlanta, GA. Sohn, J., and Park, S., Efficient operation of a surface mounting machine with a multi-head turret, International Journal of Production Research, 34(4), 1131-1143, 1996.

Su, Y.C., Wang, C., Egbelu, P.J., and Cannon, D.J., A dynamic point specification approach to sequencing robot moves for PCB assembly, International Journal of Computer Integrated Manufacturing, 8(6), 448-456, 1995.