In B+ - implanted silicon-on-sapphire (SOS) capac- itors, extended range MIS C(V) measurements have been used to characterize the interfacial charge as a ...
DecembeA 1978
IEEE T4itnaction6 on NuCZeIaV Science, Vot.NS-25, No.6,
RADIATION EFFECTS IN ION-IMPLANTED SOS CAPACITORS WITH NEGATIVE CHARGE James L. Repace Naval Research Laboratory, Washington, D.C., 20375
Abstract
S
In B+ - implanted silicon-on-sapphire (SOS) capacitors, extended range MIS C(V) measurements have been
used to characterize the interfacial charge as a function of Si epitaxial growth temperature (9600 - 9750C) for slow growth rate (.3 - 1 68 m/min) films, before and after 1 Mrad (A1203) of Co4 gamma radiation, under a radiation-bias stress of 10 V/cm. Before radiation, it was found that, for a given temperature, the amount of negative charge in the SOS capacitors decreased with increasing epitaxial growth rate, and conversely, for a given slow growth rate, the amount of negative charge in the SOS capacitors increased with increasing growth After irradiation under bias, it was temperature. found that the radiation-induced positive charge linearly added to the negative interfacial charge. The implications of these results upon the radiationinduced backchannel problem in NMOS devices are discussed.
Introduction SOS technology is currently being utilized for static 1024-bit RAM counters; ROMs, microprocessors, watch ICs, and high speed VLSI circuits utilizing SOS are currently being developed. For military radiationhardened applications, SOS technology offers advantages over bulk silicon technology which permit greater design flexibility, application of higher voltages, higher packing density, and easier realization of complementary circuits, as a result of its high dielectric There is also elimination of latch-up isolation. effects and reduction of logic upset due to the thinfilm-on-insulator structure. NMOS transistors may be fabricated in an SOS structure, N-channel inversion However, the SOS transistors are normally off. structure introduces an extra interface, relative to bulk MOS, at which radiation-induced charge storage can create a back-channel leakage surrent(-which can be (See Figure significant after as little as 10 rads.
1.)
A preliminary study by Repace and Goodman(3) of the effect of process variations on the interfacial and radiation-induced charge in SOS capacitors concluded that both the magnitude and polarity of the interfacial charge in SOS films are affected by the Si epitaxial growth rate, that increasing the Si deposition temperature from 9750C to 1075°C reduces the positive interfacial charge, and that, by slowing the growth rate to 0.3 pm/min, from the standard 3 pm/min, negative charge can be built into SOS films. This study tentatively concluded that the negative charge could be made of such magnitude so as to offset the radiation-induced positive charge generated by large doses of gamm yadiwas ation. A limitation of the preliminary study that the irradiations were done under zero bias, which causes a negligible buildup of radiation-induced positive charge. Irradiation under positive gate bias is necessary to conclusively demonstrate whether the radi-
ation-induced positive charge can in fact be offset by the process-induced built-in negative charge layer.
The purpose of the present work is to explore the linearity of negative charge developed by variations in growth rate (.3 m/min to 1.0 m/min), to determine the effect on the built-in negative charge of epitaxial growth temperatures in the range 9600C to 975°C, and to perform irradiations of negative charge layer capacitors under bias. The technique of the extended range
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I.RADIATION
3.BACKCHANNEL LOCATION
SILICON SAPPHIRE;
l2 SAPPHIRE CHARGE-UP
B.BACKCHANNEL FORMATION Fig. 1. Creation of a "backchannel" leakage current in
an N-channel SOS transistor by ionizing radiation. The normal conductive channel appears in the P-silicon adjacent to the Sio2 when the gate is biased positively, inverting the P-silicon. The backchannel leakage current appears at the Si-sapphire interface as a result of radiation charging of the sapphire. Such leakage currents can rendes N-channel devices inoperative after as little as 10 rads (Si) of radiation. MIS C(V) measurement(5) on B+ ion-implanted SOS capacitors is used to determine the process-induced and radiation-induced fixed charge residing in the A1 203 close to the interface region.
Experimental Methods The SOS wafers used in these experiments were fabricated by Union Carbide in a matrix of growth rates, R, and growth temperatures, T, using a vertical epitaxial reactor, as described in Table I: there were 9 wafers, with 4 capacitors each. The samples were processed according to the following prescription: Sapphire substrates were polished smooth to 5 mils thickness. At T0C,t an epitaxial Si film was deposited at R pm/min,** subsequent to a 5 min H2 prefire at 1150°C. The resultant Si epitaxial layer was 0.55 pIm in The thickness, (100) orientation, and intrinsic. remainder of the processing was done at NRL: At this doping level, the maximum width of the depletion region, £D, was about 200 pm, far in excess of the layer thickness. In order to reduce tD the epitaxia+l layer was subjected1jo ian-implantation doping with B at 150 at 35 keV to keV tq2 6110 /cm , followed by B 1.4xlO cm , a standard commercial procedure.
It is not anticipated that the B+ implant would affect the quality of the Si-Al 03 interface, as the projected range of the 30 keV implant is less than .1 pm, and the projected range of the 150 keV implant is 0.42+.08 pm. Even taking into account the thickness of the aluminosilicate laym)in the interfacial transithe maximum range of the tion region (.02-.04 m), depth. The implantation B+ is less than the interface for 30 min. Assuming the was annealed in N at 1050°C resultant doping io be uni'rm9 the calculated impurity concentration is 3.6 x 10 /cm , with QD = 0.2 vm. Each Si surface was coated with a thick ( 4000X) layer electrode of filament-deposited Al. On the opposite side, Al was evaporated through an etched foil mask to form thick ( 4000k) circular (0.8 cm diameter) counter-electrodes, on each sapphire surface. tPyrometer temperature; controlled to within + 1 C. ** Growth rate varied by dilution of silane in H2 carrier gas.
U.S. Governrent work not protected by U.S.
copyright.
ALUMINUM ALm
125p.m TI-
SOS CAPACITOR STRUCTURE Fig. 2.
Tlim
The structure of the SOS capacitors used in these experiments.
After fabrication, these wafers were made into capacitors of dimensions described in Figure 2, and 1 MHz CCV) gffves were made. The results were used to determine the average values of the density of interfacial charges at the flat-band condition for the silicon-sapphire interface. A total of 36 capacitors were measured in ambient air, and in the dark. They were then irradiated at0320 rads/min under a field of 10 V/cm, in the NRL Co pool, to 1 Mrad (A1203), and were remeasured approximately 20 hotrs post-irradiation. The radiation-bias field of 10 V/cm was chosen for the following reasons: a reasonable channel length for a MSI-LSI CMOS-SOS device is 5-10 ,um, and a conservative source-drain potential is 1OV. Thus, the maximum fringing field that the sapphire interface sees must be of the order of 10 V/cm. Results
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SAMPLE BIAS, KILOVOLTS
Fig. 3.
A typical C(V) curve for SOS capacitors grown under standard owth rates and temperature used in SOS technologyK , (R = 3 im/min, T = 9750C). Note that the inter f e -harge at the flatband condition is about 2 x 10 /cm .
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