Scaling SOI MESFETs to 150-nm CMOS Technologies - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 6, JUNE 2011

Scaling SOI MESFETs to 150-nm CMOS Technologies William Lepkowski, Member, IEEE, M. Reza Ghajar, Seth J. Wilk, Member, IEEE, Nicholas Summers, Trevor J. Thornton, Member, IEEE, and Paul S. Fechner, Member, IEEE

Abstract—Metal–semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal–oxide– semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT > 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ∼70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg < 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200–300 nm. Index Terms—Metal–semiconductor field-effect transistors (MESFETs), partially depleted (PD), Schottky junction, silicon-on-insulator (SOI).

I. I NTRODUCTION

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ETAL–semiconductor field-effect transistors (MESFETs) can be integrated with commercial siliconon-insulator (SOI) or silicon-on-sapphire (SOS) complementary metal–oxide–semiconductor (CMOS) processes [1]–[4] without altering the fabrication flow or adding additional mask layers. Although MESFETs cannot compete with highly scaled metal–oxide–semiconductor FETs (MOSFETs) that are optimized for high-speed/high-current drive capability, they have several unique characteristics, including high-voltage compliance and depletion-mode operation. These characteristics complement conventional CMOS technologies and enable certain analog circuits that would otherwise be difficult or prohibitively expensive to implement. One such application is the use of an n-channel MESFET as the pass transistor of a low-dropout regulator [4]. A question that arises is how well do MESFETs scale with each new technology node? To address this question, we focus

Manuscript received April 26, 2010; accepted February 24, 2011. Date of publication May 13, 2011; date of current version May 20, 2011. This work was supported by the Defense Advanced Research Projects Agency under Small Business Technology Transfer Contract W31P4Q-07-C-0256. The review of this paper was arranged by Editor R. Huang. W. Lepkowski, M. R. Ghajar, N. Summers, and T. J. Thornton are with the School of Electrical, Computer, and Energy Engineering, Center for Solid State Electronics Research, Arizona State University, Tempe, AZ 85287 USA (e-mail: [email protected]). S. J. Wilk is with SJT Micropower Inc., Fountain Hills, AZ 85268 USA. P. S. Fechner is with Honeywell Aerospace-Plymouth, Plymouth, MN 55441 USA. Digital Object Identifier 10.1109/TED.2011.2125965

here on MESFETs fabricated using a 150-nm partially depleted (PD) SOI CMOS process. Earlier MESFET demonstrations have been completed at the 600- [3] and 350-nm SOI CMOS technology nodes [1]. The work described here builds on preliminary results [5], with new data showing how layout choices impact the direct-current (dc) and radio-frequency (RF) performance of aggressively scaled MESFETs with gate lengths as short as 150 nm. The new results are compared with those from devices fabricated using an earlier 350-nm technology. This comparison between different technology nodes within the same foundry provides insight into the MESFET performance improvement from one technology node to the next. This paper is organized as follows: In Section II, the SOI MESFET architecture is described with particular emphasis on how the CMOS design rules influence MESFET dimensions. The dc characteristics of the MESFETs are then presented in Section III, with a discussion on the apparent short-channel effects (SCEs). This is followed by the measured RF characteristics in Section IV and the breakdown characteristics in Section V. II. PD-SOI MESFET A RCHITECTURE Other reports [6]–[9] have considered silicon MESFETs on SOI, SOS, and bulk CMOS processes, but in each case, none of them used a standard CMOS process flow. Our approach is different in that it uses the self-aligned silicide (salicide) step to form a near-ideal Schottky contact over the lightly doped region at the gate, with no changes to the CMOS process flow. The salicide step is used in CMOS processing to form the lowresistive contacts at the source, gate, and drain of a MOSFET. Additionally, a key step in the MESFET fabrication process is the patterning of the silicide layers to create spacers between the source and the gate and between the gate and the drain, as illustrated in Fig. 1. This prevents shorting between the three terminals and gives the MESFET its characteristic high breakdown capability. The distance between the two spacers defines the gate length Lg , whereas the length of the spacer on the drain (LaD ) and the source (LaS ) ends defines the access lengths. As will be shown in subsequent sections, the sizing and spacing of LaD and LaS is one of the most important determinants in defining the performance of a MESFET. Like those of a CMOS transistor, the RF performance and current drive capability of a MESFET are highly dependent on the minimum gate length that can be achieved. In addition to the design rules that dictate the minimum dimensions of the

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LEPKOWSKI et al.: SCALING SOI MESFETs TO 150-nm CMOS TECHNOLOGIES

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TABLE I S CALING OF K EY MESFET L AYOUT RULES

Fig. 1.

Cross section of a PD-MESFET structure.

TABLE II S CALING OF G ATE AND ACCESS L ENGTHS

Fig. 2. Top view of PD-MESFET layouts. (a) Gate is contacted inside the access region. (b) Gate is connected outside the access region to reduce Lg .

patterned silicide layers, other possible limiting factors on gate length are as follows: the size of the contact layer that contacts the silicide layer at the gate to Metal 1 (the first level of metal in process), the required Metal 1 overlap of the contact, and the spacing between the contact layer and the spacer [see Fig. 2(a)]. Fortunately, the limitations imposed by these backend-of-line (BEOL) design rule constraints can be overcome by moving the gate contact outside the access regions. This is made possible by the PD-MESFET’s continuous gate structure [see Fig. 2(b)] and is a critical layout tactic needed to achieve high-performance MESFETs. It is particularly important in processes with large BEOL design rules. Without it, the minimum gate length of the MESFET on the 150-nm process becomes 340 nm. It is expected, however, that the device in Fig. 2(b) will have a higher gate resistance RG due to the gate contact extension and the dramatic reduction in the number of contact vias between the silicide gate and Metal 1. The increase in RG will increase the RF noise figure and also reduce the maximum operating frequency fmax . For applications that require low noise figures and the highest fmax , the geometry of Fig. 2(a) would probably be a more advisable layout option. Even so, the drastic reduction in contact size (see Table I) in the newer process still allows for a relatively high performing device. From Table II, that was clearly not the case for the 350-nm process whose minimum Lg would be 1.1 μm with the layout of Fig. 2(a). III. DC C HARACTERIZATION The Gummel plots in Fig. 3(a) and (b) show the drain and gate currents (magnitudes) for the most aggressively sized

Fig. 3. Gummel plots for the smallest gate lengths on each process: (a) 350-nm SOI CMOS and (b) 150-nm SOI CMOS.

devices in both the 350- and 150-nm processes, respectively. As expected, significantly higher drain currents are possible on the 150-nm process as a result of the smaller achievable gate lengths. The Lg = 150 nm device, for example, shows an excellent current drive, about 3× larger (at Vd = 2 V and Vg = 0 V), which was then the highest current device from the 350-nm process (Lg = 400 nm). However, it exhibits weak gate control and is hard to turn off. Accordingly, its use in applications would be probably limited. We note here that each of the devices from Fig. 3 used the layout structure shown in

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Fig. 4. Threshold voltage as a function Lg for different CMOS technologies.

Fig. 2(b) so that the performance of devices with the same architecture can be compared. Interestingly, when comparing the two devices in Fig. 3(a) and (b) with gate lengths of 400 nm, the device on the 150-nm process has a noticeably smaller drain current. At first sight, this is surprising because the device on the 150-nm process has shorter access lengths, which correspond to a smaller parasitic resistance in each access region. It would therefore be expected to have a higher current drive. However, the 400-nm gate length device on the 350-nm CMOS process already manifests SCEs. As a result, it has a more negative threshold voltage Vt and a reduced saturated output impedance, both of which contribute to the higher drive current. Nevertheless, the current drive per die area will be significantly higher on the newer process due to the scaled BEOL rules and access lengths. From Fig. 3(b), it is evident that the most aggressively sized gate lengths on the 150-nm process were heavily affected by SCEs. The gate length at which SCEs cease to be an issue becomes clearer in Fig. 4, which extracts the threshold voltage for each of the MESFETs in Fig. 3(a) and (b). From the figure, we conclude that gate lengths of Lg ≥ 400 nm are required to avoid SCEs altogether in the 150-nm technology, whereas Lg ≥ 600 nm is required for the 350-nm process. These conclusions are consistent with a model developed by Chiang et al. for short-channel SOI MESFETs, which shows that SCEs become apparent as the gate length approaches the thickness of the Si channel [10]. It is reasonable to assume that the Si channel in the 150-nm technology is thinner than in the older 350-nm technology, and hence, SCEs only become apparent in shorter gate-length devices. Based on the measured results from four different CMOS technologies, our MESFETs typically demonstrate SCEs for gate lengths less than 1.5–2× the minimum feature size of the process. It slightly varies on different processes due to channel thickness, doping densities, and the silicide step, which consumes a portion of the silicon channel. By interpolating the data in Fig. 4, a MESFET with a gate length of 250 nm fabricated using the 150-nm node would have a threshold voltage of approximately −1 V and represents a good tradeoff between high-speed performance and practical depletion-mode operation.

Fig. 5. (a)–(d) Measured family of curve plots corresponding to the four devices shown in Fig. 4(b). In all cases, LaS = LaD = 300 nm. In each graph, the gate voltage is stepped from +0.5 V (uppermost curve) to −0.5 V in 0.25-V steps.

Fig. 6. Tradeoffs in current drive and output resistance for the MESFETs in Fig. 5(a)–(d).

Pronounced SCEs are also apparent in the family of curves plotted in Fig. 5(a)–(d). For example, the slope of the draincurrent curves for the Lg = 150 nm MESFET in the saturation region is indicative of a device with a low output resistance. In addition, the requirement of a large drain voltage, i.e., ∼2 V, before it reaches saturation suggests that it has a large negative threshold, which is consistent with the data in Fig. 4. Fig. 6 plots the extracted output resistances of the devices considered in Fig. 5. Again, it appears that an ideal gate length is probably between 200 and 300 nm. IV. RF C HARACTERIZATION RF characterization was performed by on-wafer probing using select devices with ground–signal–ground (GSG) pad configurations. In addition, included on the die was an accompanying set of open- and short-circuit test structures to


Fig. 7. Rolloff of transconductance gain as LaD increases from 300 nm to 1 μm on the 150-nm SOI CMOS process.

deembed the devices and remove the parasitics of the GSG pads. Measurements were taken with an Agilent 8510C vector network analyzer and an HP 8515a S-parameter test set. From the deembedded S-parameters, WinCal [11] was used to extract the fT of the MESFETs, which was defined as the point where the current gain |h21 |2 is equal to 0 dB. Since the Agilent 8510C only had a measuring range of 0.45–20.3 GHz, devices with |h21 |2 > 0 dB at 20.3 GHz had to be carefully extrapolated to determine fT . From a circuit perspective, LaS and LaD appear as parasitic resistors in series with the channel of the MESFET [12]. Fig. 7 shows the rolloff in peak transconductance gain gm for a set of devices with Lg = 200 nm and LaS = 300 nm, as LaD increases from 300 nm to 1 μm. It underlines the importance of appropriately sizing LaS and LaD and that overdesigning a MESFET for one specification can limit it in several others. As we will discuss in Section V, all three devices in Fig. 7 will have a breakdown that is approximately the same due to LaS being 300 nm. Therefore, there is no reason not to size LaD = 300 nm. If the breakdown of these devices is insufficient, LaS should be sized to the critical length discussed in Section V, and LaD should be sized accordingly. The peak cutoff frequencies of devices manufactured using the different technologies are shown in Fig. 8 as a function of gate length. Based on a simple square-law model for the MESFET drain current and the fact that fT ∼ gm /2πCgs , we would expect the peak fT to vary as L−2 g . For both technologies, the scaling of fT with Lg is less pronounced than this, as shown by the power-law fits to the data in Fig. 8, which for the 150-nm technology and fT ∼ L−1.2 gives fT ∼ L−1.1 g g for the 350-nm process. Nevertheless, the observed scaling is encouraging for the next technology node that might permit sub-100-nm gate-length MESFETs with fT approaching 100 GHz. Fig. 8 illustrates the importance of the BEOL design rules for reducing the MESFET parasitics in the scaled technology. The 150-nm process allows for access lengths LaS and LaD , which are approximately 2× smaller than those of the older technology. The corresponding reduction in the parasitic resistances at the source and drain ends of the channel leads to an increase in

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Fig. 8. Scaling with the gate length of the peak cutoff frequencies for MESFETs manufactured using different SOI CMOS processes. The error bars show the variation in fT across three different die from the 150-nm technology. The data for the 350 nm process are taken from [1]. The dashed lines are powerlaw fits to the data.

Fig. 9. Comparison of the fT and fmax dependence on drain current for three MESFETs of different gate lengths. In all cases, LaS = LaD = 300 nm. (Inset) Extracted gate resistance for each transistor.

the peak cutoff frequency of ∼20%, as shown for devices with Lg = 400 and 600 nm. The measured cutoff frequency and fmax are plotted in Fig. 9 as a function of drain current for the three most highly scaled devices. These data show the impact of RG on fmax as gate lengths are scaled and can√be explained using the wellknown approximation fmax = [fT /(8πCgs RG )]. Values for RG have been extracted for each device using the cold-FET technique [12], [13] and are shown in the inset of Fig. 9. A power-law fit shows that RG ∼ 1/Lg , as indicated by the solid line in the inset. For the 300-nm gate-length device, the peak fmax is ∼30% higher than the peak fT . However, as RG increases with decreasing Lg , this trend is reversed, with the peak fmax of the 150-nm device being 30% lower than the peak fT . We note here that, due to the design rule constraints of the 150-nm technology, all of the devices shown in Fig. 9 used the gate geometry of Fig. 2(b). By adopting the geometry of

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Fig. 10. Breakdown voltage of MESFETs with Lg = 400 and 600 nm fabricated using a 150-nm SOI CMOS process.

Fig. 2(a) and placing via contacts along the width of the gate, it should be possible to reduce RG and increase fmax to the point that it is again larger than fT . Of course, this will require the use of a more highly scaled CMOS process. V. MESFET B REAKDOWN MESFETs naturally have a high breakdown ability due to their nonself-aligned structure and Schottky gate, which can tolerate high current flow. Furthermore, without a fragile thin gate oxide, MESFETs do not have some of the breakdown mechanisms seen in MOSFETs such as the electric field gateoxide breakdown and snapback. Breakdown in the MESFET is thought to be caused mostly by avalanche ionization and tunneling mechanisms. As the MESFET approaches soft breakdown, the surface electric field can become large enough to lower the barrier height at the gate and allow electrons to tunnel into the channel from the gate metal. Consequently, this leads to an exponential increase in drain-to-gate current [1], [14]. If the drain voltage is further increased and/or the gate becomes more negatively biased, the electric field will become even larger, and avalanche ionization will begin to occur. Eventually, this will lead to an irreversible hard breakdown for the MESFET. To be consistent with the breakdown measurements reported in [1], the drain-current injection technique [15] was used to quantify the breakdown voltage of the MESFET. Once again, the biasing metric of 1 mA/mm was used as the constant current forced into the drain. Since each MESFET presented in this paper had a width of 100 μm, this resulted in a drain biasing of 100 μA. Under these bias conditions, the peak measured breakdown on the 150-nm process is ∼12 V, as shown in Fig. 10. This is considerably lower than ∼55 V [1] achieved on the 350-nm process. As a reference, the maximum steadystate operating voltages of the CMOS devices are 1.95 V for the 150-nm technology and 3.5 V for the 350-nm technology. The key factor in this variance probably lies in the difference in doping densities of the two processes. While the exact doping profile is unknown in either process, it can be assumed that the 150-nm process had a higher doping level to combat the expected increase in SCEs for a more scaled process. This would increase the electric field and enhance the avalanche

Fig. 11. Enhanced voltage family of curves for a MESFET with Lg = 400 nm, LaS = 600 nm, and LaD = 1 μm. The gate voltage is stepped from +0.4 V (uppermost curve) to −0.4 V in 0.1-V steps.

phenomenon. Consequently, the devices would break down at a lower voltage. Second, the increased doping would reduce the depletion region at the n/n+ junction between the gate and the drain. This, in turn, would reduce the significance of increasing LaD , which helps reduce the electric field at the junction and increase the point at which the device breaks down. In any process, however, LaD can only be increased so much before it no longer has an effect. In the 350-nm technology, this rolloff occurs around LaD = 5 μm [1], as compared with the LaD ∼ 1 μm in the 150-nm process. Without much positive impact of LaD beyond 1 μm, the 150-nm process cannot be expected to reach breakdown voltages as high as those of the 350-nm process. For devices with LaD ≤ 1 μm, it is expected that the breakdown voltage would only be moderately reduced by higher doping. This is observed in the measured results, e.g., the MESFET with Lg = LaS = LaD = 600 nm is ∼8 V in the 150-nm process, which is only a 4-V reduction from the 350-nm process [1]. It had been suggested in previous works [1], [2] that the breakdown event happened almost exclusively at the drain end of the channel and was independent of the access region at the source side. Clearly, this is not the case for the 150-nm technology, as shown in Fig. 10. The breakdown is about twice as large, with LaS = 600 nm, as compared with LaS = 300 nm for Lg = 600 nm and LaD > 1 μm. Furthermore, for devices with LaS = 300 nm, the breakdown is essentially independent of LaD . This suggests that there is another form of breakdown happening on the source side. Presumably, the breakdown event is not the result of tunneling/avalanche breakdown since the electric field should be significantly lower at the gate–source junction. In the worst case scenario, the reverse bias would not exceed 1–1.5 V, whereas for the gate–drain junction, it would be 3.5–6 V. Thus, there must be a critical length for LaS greater than 300 nm but less than 600 nm on the 150-nm process, in which this new breakdown is no longer an issue. This issue was not seen in earlier process runs since the lithography rules prevented the width of the spacers from being reduced below 600 nm. Since there are no devices with LaS other than 260, 300, and 600 nm, there are insufficient data to confirm this assumption.


To demonstrate the tradeoffs between current drive, breakdown voltage, and RF performance, we plot the family of curves for drain voltages up to 10 V for a device with Lg = 400 nm, LaS = 600 nm, and LaD = 1.0 μm in Fig. 11. This device is similar to the one used for Fig. 5(d), but the longer LaS and LaD give it a higher breakdown voltage of ∼11.5 V. Although the device has soft output saturation at the higher gate voltages, it shows good output characteristics up to 10 V when operated in depletion mode. The drive current is reduced, as compared with Fig. 5(d), but with a peak fT of ∼5 GHz, the data in Fig. 11 demonstrate the enhanced voltage capability of this MESFET geometry for high-speed switching applications. VI. C ONCLUSION SOI MESFETs have been scaled to the 150-nm node using a standard SOI CMOS process. The tightening of design rules led to significantly higher performing and more compact MESFET devices than have been reported using earlier technologies. Encouragingly, the devices showed continued scaling of fT with respect to the gate length, leading to the belief that 100-GHz MESFETs might be possible with sub-100-nm gate-length devices. However, as the MESFET gate length approaches the limit of the technology node, SCEs and parasitic components degrade dc and RF performance. As with previous technology demonstrations, the optimum MESFET performance is achieved with gate lengths that are 1.5–2× larger than the minimum achievable MOSFET gate length.

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[13] M. Berroth and R. Bosch, “High-frequency equivalent circuit of GaAs FETs for large-signal applications,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 2, pp. 224–229, Feb. 1991. [14] A. Balijepalli, J. Ervin, W. Lepkowski, Y. Cao, and T. J. Thornton, “Compact modeling of a PD SOI MESFET for wide temperature designs,” Microelectron. J., vol. 40, no. 9, pp. 1264–1273, Sep. 2009. [15] S. R. Bahl and J. A. del Alamo, “A new drain-current injection technique for the measurement of OFF-state breakdown voltage in FETs,” IEEE Trans. Electron Devices, vol. 40, no. 8, pp. 1558–1560, Aug. 1993.

William Lepkowski (M’11) received the Ph.D. degree in electrical engineering from Arizona State University (ASU), Tempe, in 2010. He is currently working as a Senior Design Engineer and a Researcher with SJT Micropower Inc., Fountain Hills, AZ, and an Adjunct Faculty Member with ASU. His research interests include the optimization of the layout and the device structure of Si metal–semiconductor field-effect transistors (MESFETs), as well as integrating those MESFETs into direct-current–direct-current power converters.

M. Reza Ghajar received the M.S. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2009, with a focus on high-efficiency power amplifiers for drainmodulated transmitters. He is currently working toward the Ph.D. degree with Arizona State University, Tempe. Since 2010, for his doctoral study, he has been working on silicon-on-insulator metal– semiconductor-field-effect-transistor-based power amplifiers and modeling.

R EFERENCES [1] J. Ervin, A. Balijepalli, P. Joshi, V. Kushner, J. Yang, and T. J. Thornton, “CMOS-compatible SOI MESFETs with high breakdown voltage,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3129–3135, Dec. 2006. [2] W. Lepkowski, J. Ervin, S. J. Wilk, and T. J. Thornton, “SOI MESFETs fabricated using fully depleted CMOS technologies,” IEEE Electron Device Lett., vol. 30, no. 6, pp. 678–680, Jun. 2009. [3] J. Yang, A. Balijepalli, T. J. Thornton, J. Vandersand, B. J. Blalock, M. Mojarradi, and M. E. Wood, “Silicon-based integrated MOSFETs and MESFETs: A new paradigm for low power, mixed signal, monolithic systems using commercially available SOI,” Int. J. High Speed Electron. Syst., vol. 16, no. 2, pp. 723–732, 2006. [4] W. Lepkowski, S. J. Wilk, S. Kim, B. Bakkaloglu, and T. J. Thornton, “A capacitor-free LDO using a FD Si-MESFET pass transistor,” in Proc. 52nd IEEE MWSCAS Conf., Cancun, Mexico, Aug. 2–5, 2009, pp. 953–956. [5] W. Lepkowski, S. J. Wilk, and T. J. Thornton, “45 GHz silicon MESFETs on a 0.15 μm SOI CMOS process,” in Proc. IEEE SOI Conf., Foster City, CA, Oct. 5–8, 2009, pp. 1–2. [6] K. P. MacWilliams and J. D. Plummer, “Device physics and technology of complementary silicon MESFET’s for VLSI applications,” IEEE Trans. Electron Devices, vol. 38, no. 12, pp. 2619–2631, Dec. 1991. [7] H. Vogt, G. Burbach, J. Belz, and G. Zimmer, “MESFETs in thin silicon on SIMOX,” Electron. Lett., vol. 25, no. 23, pp. 1580–1581, Nov. 1989. [8] D. P. Vu and A. Sono, “Self-aligned Si MESFETs fabricated in thin silicon-on-insulator films,” Electron. Lett., vol. 23, no. 7, pp. 354–355, Mar. 1987. [9] T. J. Thornton, “Physics and applications of the Schottky junction transistor,” IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2421–2427, Oct. 2001. [10] T. K. Chiang, Y. H. Wang, and M. P. Houng, “Modeling of threshold voltage and subthreshold swing of short-channel SOI MESFETs,” Solid State Electron., vol. 43, no. 1, pp. 123–129, Jan. 1999. [11] WinCal 3.1, Cascade Microtech, Inc., Beaverton, OR, 2002. [12] A. Balijepalli, R. Vijayaraghavan, J. Ervin, J. Yang, S. K. Islam, and T. J. Thornton, “Large-signal modeling of SOI MESFETs,” Solid State Electron., vol. 50, no. 6, pp. 943–950, Jun. 2006.

Seth J. Wilk (M’11) received the Ph.D. degree in electrical engineering from Arizona State University (ASU), Tempe, in 2005. He is currently with SJT Micropower Inc., Fountain Hills, AZ, focusing on the research and the commercialization of Si-metal–semiconductor-fieldeffect-transistor technology, and an Adjunct Faculty member with ASU. His research interests include radio-frequency wireless design, ultralow power circuitry, and power regulation.

Nicholas Summers received the B.S. degree in electrical engineering from the University of Idaho, Moscow, in 2008 and the M.S. degree in electrical engineering from Arizona State University (ASU), Tempe, in 2010. While with ASU, his research focused on integrating Si-based metal– semiconductor field-effect transistors with SiC power electronic devices for a system-on-a-chip gate-switching solution. He is currently with the Salt River Project as a Power Quality Engineer.

Trevor J. Thornton (M’99) received the B.A. and Ph.D. degrees in physics from the University of Cambridge, Cambridge, U.K. After his postdoctoral research with Cavendish Laboratory, Department of Physics, University of Cambridge, and with Bellcore, Morristown, NJ, he joined the Department of Electrical Engineering, Imperial College, London, U.K. Since 1998, he has been with Arizona State University (ASU), Tempe, where he is currently a Professor with the School of Electrical, Computer, and Energy Engineering, and the Director with the ASU Center for Solid-State Electronics Research.

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Paul S. Fechner (M’84) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Wisconsin–Madison, Madison, in 1977, 1980, and 1985, respectively. After 18 months as a Postdoctoral Research Associate with the Wisconsin Center for Applied Microelectronics, in July 1986, he joined the Solid State Electronics Division, Honeywell International Inc., Plymouth, MN, where he began working on silicon-on-insulator (SOI) material and complementary metal–oxide–semiconductor (CMOS) process development. In May 1987, he assumed full leadership responsibility for process integration/development on Honeywell’s SOI CMOS technology. He has continued to serve as a Lead Process-Integration Engineer developing Honeywell’s 0.8/0.7 μm, SOI-V (0.35 μm), and S150 (0.15 μm) Radhard SOI CMOS technologies. He is cur-


rently continuing his work in the development of Honeywell’s next-generation radiation-hardened CMOS processes. He is the author of multiple publications and the holder of 13 patents in the fields of SOI material characterization and SOI process technology, device, and circuit design. Dr. Felchner is a member of the Electrochemical Society. He served in the IEEE International SOI Conference Technical Committee in 2003–2005. He was a recipient of the H.W. Sweatt Award for outstanding achievement in 1996 and 1999, and the Hardened Electronics and Radiation Technology Conference Best Paper Award in 1989 for his conference presentation entitled “Retrofitting a Radiation-Hardened Bulk CMOS Technology to SOI,” describing Honeywell’s SOI RICMOS-III 1.2 μm Radhard technology. The latter was published in the Journal of Radiation Effects, Research and Engineering.