Scavenging Thermal-Noise Energy for Implementing Long-Term Self

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Energy scavenging sensors which operate by harvesting energy from .... (b) a leaky floating-gate structure with a metallic contact and its energy-band diagram.

Scavenging Thermal-noise Energy for Implementing Long-term Self-powered CMOS Timers Liang Zhou, Pikul Sarkar and Shantanu Chakrabartty Department of Electrical and Computer Engineering Michigan State University East Lansing, U.S.A. {zhoulia2,sarkarpi,shantanu} Abstract—One of the major challenges in remotely powered sensors is that events being monitored can not be time-stamped due to the unavailability of a continuously active timer or system clock. Implementing such a timer would require access to a perennial source of energy, which for a structural health monitoring (SHM) application, could easily span several years. In this paper, we present a novel approach to implement selfpowered timers that only requires presence of ambient thermal energy. The operational principle of the timer is based on the physics of trap-assisted electron transportation in floating-gate capacitors which yields leakage currents down to 10−21 A. Using a differential architecture the proposed timer compensates for the effects of temperature variations during the timer read-out. In this paper we validate the proof-of-concept using measurement results obtained from different timer topologies which have been prototyped in a 0.5µm CMOS process.

10-2 W


10-12 W

Energy scavenging sensors which operate by harvesting energy from its ambient environment are useful for long-term sensing applications where the use of batteries (rechargeable or non-rechargeable) is considered to be impractical. Depending on the level of ambient energy that is available, the sensor can implement different functionalities that range from complex signal-processing to wirelessly transmitting data to an external radio-receiver. Fig. 1 shows a typical range of scavengeable power and different sensor functionalities that can be achieved at these power levels. For instance, the self-powered sensor which was reported in [1] can scavenge nanowatts of power from ambient strain variations and can compute and store the statistics of the strain-signal. As the scavengeable power level is increased, the stored statistics can be wirelessly transmitted, as shown in Fig. 1. However, a major limitation of remotely powered sensor (for e.g. using strain variations or using RF) is that events being monitored by the sensor can not be time-stamped. This is because the sensor does not have access to a system timer or clock that is continuously active for the entire monitoring period, which for a typical SHM application, could easily span more than 20 years. One method to achieve continuous powering is to scavenge energy from perennial sources of power like ambient thermal-noise, as illustrate in Fig. 1. Also shown in Fig. 1, that the typical power-level of ambient thermal-noise is ≈ 10−18 W, which is orders of magnitude lower for operating any conventional electronic device, let

978-1-4673-5762-3/13/$31.00 ©2013 IEEE

RF signal

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uplink & power

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Thermal Noise Energy

Fig. 1. Scale showing different amounts of scavengeable power-levels and the corresponding sensor functionalities that can be achieved

alone scavenge the energy. In this regards, biology serves as a motivation providing several examples where many biochemical computations (for e.g. DNA hybridization) are directly driven by thermal-noise [2] without buffering or scavenging energy from thermal-noise. Thermally-driven and diffusionbased information processing was also proposed by Charles Bennett [3] as a way to approach fundamental limits of computation (in terms of energy-efficiency). In this paper, we present a proof-of-concept thermal-noise driven self-powered timer that exploits the operational physics of electron transport in oxide traps. In section II, we describe the proof-of-concept where the oxide leakage current is used to discharge a floating polysilicon gate and the rate of discharge can be controlled by synthetically creating lattice imperfections at the metal-polysilicon interface. We also present a differential architecture for reading out the output of the selfpowered timer. In section III, we present measurement results


from prototypes fabricated in a 0.5μm CMOS process and in section IV we conclude with paper with future research directions. II. T RAP - ASSISTED E LECTRON T RANSPORT AND F LOATING - GATE L EAKAGE



Polysilicon Trap-state





Silicon di oxide


A floating-gate is formed by completely insulating a piece of polysilicon by silicon-dioxide as shown in Fig. 2(a). Also shown in Fig. 2(a) is the energy band-diagram corresponding to an ideal floating-gate where the oxide forms an energy barrier that prevents the electrons to surmount or tunnel through the barrier. The quality of the barrier is determined by the quality of the polysilicon silicon-di-oxide interface, which for thermally grown oxide exhibits ultra-low density of imperfections. Therefore, any electrons that is injected onto the floating-gate can be retained for a long-period of time (retention of 8 bits over 8 years) [4].

Metal via

Lattice Imperfection

(b) Fig. 2. (a) An ideal floating-gate structure and its energy-band diagram; (b) a leaky floating-gate structure with a metallic contact and its energy-band diagram.

However, when a metallic contact is formed on polysilicon (as shown in Fig. 2(b)), the polysilicon surface is strained due to metal-polysilicon lattice mismatch and creates spurious traps at the interface. Therefore, even if the metallic junction is left unconnected, the charge on the polysilicon floating-gate leaks out slowly and over a long-duration of time (as shown in Fig. 2(b)). In literature, this leakage is typically considered to be a nuisance and several methods have been proposed [5] to reduce this artifact. In this paper, we exploit the leakage characteristics to implement timers that can continuously operate over long-durations of time.

When a potential difference exits between the floating-gate and the surrounding metal the electrons can leak out of the floating-gate due to the following three physical phenomena [6]: (a) trap-assisted tunneling where the electrons move to an unoccupied trap-state by defects close to the metalpolysilicon-oxide interface; (b)Modified Poole-Frenkel(MPF) or internal Schottky emission of the trapped electrons into the conduction band of the silicon-di-oxide; and (c) Thermalfield emission of Fermi-level electrons from the metal directly into the conduction band of the silicon-di-oxide. While trapassisted tunneling mainly affects the leakage current on short time-scales, MPF and thermal-field emission of electrons are dominant for long time-scales. For this preliminary application our focus will be to exploit on the combined effect of all the different leakage mechanism. However, a common attribute of different leakage mechanism is that the leakage current increases with the increase in the number of defects at the polysilicon interface. We can thus control the leakage by effectively controlling the number of metallic vias connected the floating-gate. Exploiting the oxide-leakage current to implement integrators and timers would, however require precision measurement of the drift in floating-gate voltage. For instance, a timer that discharges by 1V over a period of 20 years would drift by less than 10μV/hour. In this paper, we couple the floating-gate to the gate of a pMOS transistor and measure the transistor draincurrent to infer the residual charge on the floating-gate. The layout and schematic of the timer is shown in Fig. 3 which shows a differential architecture with an ideal floating-gate transistor M2 (with no metallic vias) acting as a reference structure. Note that the floating-gate of transistor M1 has multiple floating metallic contacts. Ideally, the current through M2 should remain unchanged (no leakage) once the charge on its floating-gate has been programmed. The common method for programming floating-gates is by using FowlerNordheim (FN) tunneling or by using hot-electron injection. FN tunneling removes the electrons from the floating-gate node by applying a high-voltage ( 15 V in 0.5μm CMOS process) across a parasitic nMOS capacitor Ctun (as shown in Fig. 3). Hotelectron injection, however, requires lower voltage ( 4.2 V in 0.5μm CMOS process) than tunneling and hence is the primary mechanism for precision programming of floating-gates. The hot-electron programming procedure, involves applying greater than 4.2 V across the source and drain terminals of the transistors M1 and M2 . The large electric field near the drain of the pMOS transistor creates impact-ionized hot-electrons whose energy when exceeds the gateoxide potential barrier (3.2 eV) can get injected onto the floating-gate. Because the hot-electron injection in a pMOS transistor is a positive feedback process and can only be used to add electrons to the floating gate, the process needs to be carefully controlled and periodically monitored to ensure the floating-gate voltage is programmed to a desired precision. The methods proposed in literature achieve the desired precision either by adjusting the duration for which the FG transistor is injected or by adjusting the magnitude of the injection pulses [4].


Under sub-threshold biasing, the drain current Iref through M2 can be expressed in terms of its floating-gate charge Qref as κQref Vs − Iref = I0 e UT CT e UT (1) where I0 is the characteristic current, κ is the gate-efficiency factor, CT is the total capacitance of floating-gate and UT = kT /e is the thermal-voltage and is directly proportional to the ambient temperature. The reference current Iref is used to compensate for the effects of temperature variations after the current Iout is read-out. The compensation procedure involves measuring Iref and Iout at two different values of the source voltage Vs1 , Vs2 . Assuming an ideal matching of the transistors M1 and M2 , the change in floating-gate charge from timeinstant ti to time-instant ti+1 can be estimated to be ΔQF G,i = QF G,i+1 − QF G,i CT Iout,i+1 Iout,i [UT,i+1 ln =− − UT,i ln ] κ Iref,i+1 Iref,i

M1 Vs

Iout Iref M2



The index i represents the ith measurement and UT,i is the thermal voltage at time ti . Because the ambient temperature typically varies slowly, UT,i can be assumed to be constant if the time-duration between successive measurements is small. By measuring the reference currents Iref,s1 , Iref,s2 at two different source voltages Vs1 and Vs2 , the value of UT,i can be estimated as Vs1 − Vs2 UT,i = . (3) ln Iref,s1 − ln Iref,s2 By combining equation 3 with equation 2, the effect of temperature variations on timer-readout can be compensated. Note that the oxide-leakage current is still a function of temperature and our future work in this area will focus on compensating for effects of temperature variation of oxideleakage current. The accurate estimation and compensation of UT makes it possible to isolate the effect of oxide-leakage from ambient effects. Since κ and CT are almost constant FG with respect to time and temperature, we can estimate κΔQ CT instead of ΔQF G . Now we present an empirical model of the oxide-leakage current. The leakage current Ilkg is proportional to the potential difference ΔV across the floating-gate and the surrounding metal. This can be expressed as Ilkg = kΔV




where k is a proportionality constant determined by defect state distribution and temperature. Deduced from equation 4 we can compute the change in QF G as a function of time according to κΔQF G κQF G,0 − k t (t) = (1 − e CT ) (5) CT CT The equation implies the charge on the FG will change exponentially with respect to time and is similar to the transient response of an RC circuit. The time constant of this exponential decay can be estimated to be τ = CkT . By varying

Fig. 3.


V cg Timer Read-out Module



tout Vtun









Schematic and layout of a differential self-powered timer

CT and k we can obtain timers with different time-constants and different discharge characteristics. As indicated earlier, the parameter k can be modified by changing the density of the traps and the distance between the floating-gate and the surrounding metal. The density of traps can be increased by adding more metallic contacts in the timer layout. III. M ESUREMENT RESULTS Two different topologies of the proposed timer have been fabricated in a 0.5µm standard CMOS process. Fig. 4 shows the micrograph of the timers showing that the size and orientation of the timer structure (leaky floating-gates) and the corresponding reference structure (ideal floating-gates) well matched. The reference floating-gate structure has no vias where as the floating-gate labeled “timer1” has 35 vias and the floating-gate labeled “timer2” has only one via. In the first set of experiments, the reference floating-gate and the timer1 floating-gate were precisely programmed to the same current (using hot-electron injection). The powersource to the timer-circuit was disabled by setting the source voltage Vs to zero. The structure was periodically energized


Normalized Voltage Change






300um 1 0.8 0.6 0.4 Timer1 Fitting for Timer1 Timer2 Fitting for Timer2

0.2 0 5

Fig. 4.

Micro-photograph of the fabricated timer structures

(every hour) by setting Vs to Vs1 -Vs3 . For each value of Vs , the output current Iout and the reference current Iref is measured using a Keithley 2400 source meter. Fig. 5(a) shows the measured Iref with respect to time. Note that the ideal floating-gate structure should exhibit negligible leakage. Therefore, the variations in the measured Iref can be attributed to variations in temperature. Fig. 5(b) plots the measured Iref with respect to time and also shows variability due to temperature variations. The temperature compensation method described in the previous section was applied and Fig. 6 shows the estimated leakage characteristics corresponding to the timer1 and timer2.



20 25 Time (hours)





Fig. 6. Temperature compensated leakage characteristics corresponding to timer1 and timer2.

output of timer1. It is because that the initial voltage difference between the floating-gate and surrounding metal for timer2 is relatively smaller than that timer1, thus the measurement is more vulnerable to the noise. The error could be reduced by using more sophisticated measurement techniques as proposed by [7]. An exponential fit to the measured data is used for estimating the the time-constants for timer1 and timer2 and was found to be equal to 3.6 hours and 24.5 hours respectively. This result verifies the conclusion that the number of metallic contacts could affect the leakage current, thus more contacts lead to a smaller time-constant or vice-versa.


x 10


current (A)


In this paper, we proposed a proof-of-concept self-powered timers that are driven by thermal processes and thermal energy. The timer exploits charge leakage induced in high-quality VS2 oxide layers by introduction of defects at the metal-polysilicon VS1 interface. As a result, a floating-gate capacitor can be slowly discharged over a long-period of time resulting in the function of a timer. Our future work will focus on increasing the time70 constants of the timers to more than 20 years which will facilitate use of these structures in our previously reported self-powered micro-data-logging circuits [1]. VS3

10 Temperature variance

8 6 4 2 0



30 40 time (hours)



(a) −8

x 10


2.5 current (A)

2 1.5 1


0.5 0



30 40 time (hours)




(b) Fig. 5. Measured source-to-drain currents with respect to time corresponding to:(a) reference structure; and (b) timer1 structure.

[1] C. Huang and S. Chakrabartty, “An asynchronous analog self-powered cmos sensor-data-logger with a 13.56 mhz rf programming interface,” Solid-State Circuits, IEEE Journal of, no. 99, pp. 1–1, 2012. [2] H. Berg, Random walks in biology. Princeton University Press, 1993. [3] C. Bennett, “The thermodynamics of computationa review,” International Journal of Theoretical Physics, vol. 21, no. 12, pp. 905–940, 1982. [4] C. Huang, P. Sarkar, and S. Chakrabartty, “Rail-to-rail, linear hot-electron injection programming of floating-gate voltage bias generators at 13-bit resolution,” Solid-State Circuits, IEEE Journal of, no. 99, pp. 1–1, 2011. [5] I. StJohn and R. Fox, “Leakage effects in metal-connected floating-gate circuits,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53, no. 7, pp. 577–579, 2006. [6] R. Ramprasad, “Phenomenological theory to model leakage currents in metal–insulator–metal capacitor systems,” physica status solidi (b), vol. 239, no. 1, pp. 59–70, 2003. [7] M. O’Halloran and R. Sarpeshkar, “A 10-nw 12-bit accurate analog storage cell with 10-aa leakage,” Solid-State Circuits, IEEE Journal of, vol. 39, no. 11, pp. 1985–1996, 2004.

The measured results show that the timer leakage characteristics match the empirical exponential model. It can also be observed that the output of timer2 more noisier than the


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