Ichiro Fujimori, Broadcom, Irvine, CA. The advancement in CMOS ... Andy Joy, Texas Instruments, Northampton, Northants,. United Kingdom. The general drift ...
ISSCC 2009 / EVENING DISCUSSION SESSION / SE3 SE3: Will ADCs Overtake Binary Frontends in Backplane Signaling? Co-Organizer: Co-Organizer: Chair:
Ali Sheikholeslami, University of Toronto, Toronto, Ontario, Canada Robert Payne, Texas Instruments, Dallas, TX Jerry Lin, Ralink Technology, Hsinchu, Taiwan
Receivers with an ADC front end are now competing against conventional receivers with a binary front end, but they consume larger silicon area and possibly larger power. This session discusses the pros and cons and the design tradeoffs between the two approaches in backplane electrical signaling. Each of our five panelists will predict whether the switchover to ADC-based designs will become inevitable.
Panelists Statements ADCs will Dominate at 20Gb/s and Beyond Ichiro Fujimori, Broadcom, Irvine, CA The advancement in CMOS technology has made interleaved ADC’s assisted by calibration a viable solution for wired transceivers at a 10Gb/s data rate. Combined with the scaling of the DSP engine, the die area and power of the ADC based front end has been rapidly approaching that of a conventional binary front end. For applications at 10Gb/s or lower, where most standards define “open-eye” compliance based on NRZ coding, the binary front end remains the most economical solution. The ADC front end is limited to niche situations like legacy backplanes and 10G LRM. At data rates of 20Gb/s and beyond, an ADC front end becomes main stream. Analog equalization will be prohibitive in many applications even with the advancement in backplane technologies. The main driver will be the adoption of multi-level coding, which effectively lowers the Nyquist rate. Since less equalization gain is needed to compensate channel loss, the quantization noise budget is relaxed for the target SNR. As a result, the ADC complexity will show a flatter dependency to data rate for higher-order coding (more levels). Preliminary analysis over a moderate backplane shows that an ADC front end with PAM32 coding can be a common choice at 100Gb/s data rate. This transition to higherorder coding has been seen before in other highly successful technologies such as voice-band modems, and Digital Subscriber Loops. Are Serdes as We Know Them Dead? Andy Joy, Texas Instruments, Northampton, Northants, United Kingdom The general drift towards ADCs in Serdes is seen by many as inevitable as this reflects what has happened in the past with the HDD read channel, for example. However, I think we have a slightly different case here where channel speeds and equalization needs are pushing forward at different rates. The need for an ADC on the front end is only justified when large amounts of equalization are needed. This happens to be the case today where legacy backplanes are requiring more and more techniques to squeeze the most out of them. There will then be a new set of backplanes developed with better materials and more learning that will push the speeds up. The newer backplanes will then allow back a certain level of binary front ends again. These will then turn into the next generation of legacy and ADCs will again bear fruit. When and how this will change in the future? Can we rely on materials improvements much further and how will we get 50Gb/s across cabinet sized distances? i.e. are Serdes as we know them dead?
Let the Market Decide Michael Sorna, IBM, Hopewell Junction, NY The overriding factor in determining whether a binary or an ADC-based approach will be a better solution is the nature of the market a given serial link will serve. For high link-count backplane applications, binary serial link solutions will tend to be preferred to ADC-based ones. This preference will be driven by system-driven critical metrics and application constraints for links, including: present and expected future channel sets; tight area budgets; and tight power budgets. As the disparity between serial data rate and supportable digital logic clock frequencies grows, managing post-processingdriven latency associated with ADC-based links will emerge as a further challenge. ADC-based links are likely to thrive in areas where equalization requirements are more exotic and link counts are lower, including, for example, realizations of electronic dispersion compensation for optical systems. In the near to medium term, the area and power cost associated with highly sophisticated ADC-enabled equalizers will limit the degree to which this approach will be adopted in the mainstream backplane environment. History Repeats Itself: ADCs Will Dominate Hirotaka Tamura, Fujitsu Laboratories, Kawasaki, Kanagawa, Japan In mid to late 90’s, there was controversy over ADC front end versus pure analog one in the area of HDD read-channel ICs. ADC front end won over analog, because the increasing bit density in the recording media called for complex signal processing that can only be achieved with digital circuits. History just rhymes. The data rate, or bit density per time, is increasing while the loss in the backplane channel is not improved at the same pace. This acts in favor of the ADC camp in the field of high-speed transceivers. Are They Really That Different? Jared Zerbe, Rambus, Los Altos, CA The only rational answer to this question is the classic engineering “it depends”. This time, however, it depends on three critical factors - the environment, the desired speed, and the current performance process node. The reason we now have ADC front ends on backplane transceivers is because process evolution, marching along with a relentless obedience to Moore’s law with the entire industry behind it, has outpaced real demand for higher performance links and backplane systems upgrades. How long has 10Gb/s been ‘the number’ for backplanes? If customers were demanding 20Gb/s today instead we wouldn’t see ADCs in the solution space; they would simply blow any realistic power & area budget. Independently, when building either a bit-serial or high-speed A/D front-end for a medium-equalization performance link one rapidly comes to the conclusion that they are fundamentally not that different. I will point out some of the few real differences and advantages/disadvantages.
514
• 2009 IEEE International Solid-State Circuits Conference
978-1-4244-3457-2/09/$25.00 ©2009 IEEE
