Architecture for 90nm Technology and Beyond. A. Pirovano1 ... Intel Corp., 2200 Mission College Blvd., Santa Clara, CA, USA. Abstractâ ... programming currents of 300µA and good distributions, ... appealing features of the PCM technology.
Self-Aligned µTrench Phase-Change Memory Cell Architecture for 90nm Technology and Beyond A. Pirovano1, F. Pellizzer1, I. Tortorelli1, R. Harrigan2, M. Magistretti1, P. Petruzza1, E. Varesi1, D. Erbetta1, T. Marangon1, F. Bedeschi1, R. Fackenthal2, G. Atwood2 and R. Bez1 1. FMG, NVMTD, STMicroelectronics, via C. Olivetti 2, 20041 Agrate Brianza (Mi), Italy 2. Intel Corp., 2200 Mission College Blvd., Santa Clara, CA, USA Abstract— A novel self-aligned µTrench-based cell architecture for Phase Change Memory (PCM) process is presented. The low-programming current and the good dimensional control of the sub-lithographic features achieved with the µTrench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90nm 128Mb vehicle with programming currents of 300µA and good distributions, demonstrating its suitability for the production of highdensity PCM arrays at 90nm and beyond. I. INTRODUCTION Flash memories have been able to scale for more than 15 years, boosting the recent impressive growth of the portable equipment market and becoming the mainstream Non-Volatile Memory (NVM) technology. Projecting into the next decade, though, there are several fundamental limitations that must be solved to push the floating-gate concept beyond the 32nm technology node. The increasing complexity of floating gate scaling leaves room for the investigation of alternative NVM concepts that promise better scalability, improved performances, and competitive cost with Flash. Phase-Change Memories (PCM), are one of the most promising candidates for next-generation NVM, having the potentiality to improve the performance compared to Flash - random access time, fast read throughput, write throughput, direct write, bit granularity, endurance - as well as to be scalable in the deca-nanometer range [1]. Despite the high potential of the PCM concept and the good integration results so far achieved [2,3], some practical challenges must still be addressed. In particular, large efforts are being dedicated to the integration of a compact PCM cell structure with the chalcogenide compound, to achieve a full compatibility with an advanced CMOS technology and to reduce the programming current without degrading the appealing features of the PCM technology. Several
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approaches have been so far proposed to achieve low reset currents [4-7], none of them being completely satisfactory. The so called lateral cell approach has demonstrated currents as low as 200 µA [4], but its integration in multi-megabit arrays has not yet been proven. Nitrogen doping [5] is another effective technique to reduce the programming current, but with the drawback to largely increase the set resistance, thus degrading the capability for a fast random read out of the cell status. The in-line memory cell [6,7] with the self-heating concept promises enhanced performance in terms of programming currents (less than 100 µA), but the reported results are not well understood and its potentiality at this stage cannot be clearly assessed. Among these alternatives, the µTrench PCM cell architecture represents a well-tempered fusion of all the appealing features of the PCM technology, having been demonstrated to simultaneously achieve low programming currents, small cell size, good dimensional control, and proven multi-megabit manufacturability [8]. Moreover, the fine tuning capabilities of the PCM µTrench cell and its potentialities to obtain very low programming currents have been largely demonstrated, with an optimized µTrench cell that achieved a programming current of 450 µA at 180nm [9]. Despite the good results so far achieved and the capability to scale the µTrench PCM cell at 90nm with good electrical characteristics [2], the more stringent lithographic alignment requirements of this architecture with respect to other options could impact the integration in multi-megabit array and the final manufacturing yield of PCM products. Aim of this work is to discuss the feasibility of a costeffective µTrench PCM solution capable of simplifying the integration process at 90nm and beyond by reducing the lithographic requirements, still preserving the very nice features of the standard (STD) µTrench PCM concept. This novel architecture, called Self-Aligned (SA) µTrench, is characterized by much less demanding requirements for the lithographic steps employed in the cell fabrication, still providing far superior electrical performances in term of low
programming currents with good reproducibility. The electrical performances of this novel architecture are then reported, showing programming currents of 300µA at 90nm. Finally, the successful integration of a SA-µTrench 128Mb vehicle definitely demonstrates its suitability for the production of high-density PCM array at 90nm and beyond. II. STORAGE ELEMENT ARCHITECTURE The 90nm PCM architecture has been originally developed considering the small cell size requirements, the process cost, and the high performance characteristics, in particular in terms of fast random access-time typical of NOR Flash applications [8,9,2]. In the STD µTrench storage element proposed for the 90nm platform, the storage active region is achieved at the intersection between a vertical thin-film metallic layer, called the heater and deposited inside an opening on a tungsten plug, and the thin layer of chalcogenide material - actually the compound Ge2Sb2Te5 (GST) - capped with a TiN barrier and deposited inside a sub-lithographic trench, the so called µTrench. Although this architecture has been demonstrated to get quite superior results in term of programming current and dimensional control of the sub-lithographic features, the integration in an array architecture demands additional
lithographic requirements, mainly in term of alignment tolerance with the world-line plugs, to avoid short circuits in the array. Moreover, these constraints are expected to become more and more pressing with the scaling of the technological node, thus being a potential yield detractor in next-generation PCM products manufacturability. In order to reduce the lithographic constraints and simplify the µTrench cell fabrication, a self-aligned approach has been successfully adopted. Fig.1 shows cross-sections along both directions depicting the fabrication steps for both the STD and the SA µTrench architecture. In the first step reported (Fig.1-a), called the heater opening, it can be clearly appreciated that in the SA µTrench architecture larger trenches are opened to host the heater, while in the STD approach almost minimum size holes must be opened in the dielectric. After the heater thin-film deposition, in the SA approach a dep-etch step is performed to electrically isolate heaters belonging to different cells, thus obtaining vertical metallic layers along the x-directions that, at this stage, put in contact plugs along the same wordline direction (as clearly seen in the x-direction cross section in Fig.1-c). In the STD µTrench approach, the heater thin film is deposited in small openings, followed by a dielectric filling and a final planarization.
Figure 1. Schematic description of the STD and SA µTrench fabrication steps.
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Fig.2 finally reports the SEM picture of the SA µTrench array after the GST etching step. With this approach, the wordline plugs are directly aligned on the storage elements, thus intrinsically avoiding short circuits between the WL plug and the heater element. Moreover, as reported in the crosssection along the y-direction of Fig.3, the heater formation is achieved through the opening of trenches of width 2F, where F is the technology node, thus saving a critical mask with respect to the STD µTrench approach, where the heater element is patterned at the minimum lithographic size. III.
ELECTRICAL RESULTS
The SA µTrench architecture has been fabricated at 90nm and the electrical characteristics are reported in this section. One of the key aspects that makes the µTrench approach far superior with respect to other storage architectures is its capability to achieve very low programming current while allowing control of the sub-lithographic features and to tailor the geometrical parameters to optimize the cell electrical characteristics. This aspect is of fundamental importance for the PCM technology, directly impacting the overall performance in term of write throughput and the costcompetitiveness in term of cell area to build a selector with suitable current driving capabilities.
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Fig.1-c reports the µTrench opening. For this process step, the SA approach allows the definition of a continuous trench that runs along the whole bitline, while in the STD µTrench small elongated rectangles with a sub-lithograpghic dimension must be patterned to separate cells belonging to the same bitline. Finally, the GST layer is deposited and the cell structure is finished (Fig.1-d). For the STD µTrench the final etching procedure is required to define the bitline, and the wordline plugs are subsequently opened and filled. On the other hand, in the SA approach the heater along the wordline is not yet defined. The SA approach thus consists of a single etching step that defines the GST bitline and segments at the same time the heater along the wordline. The wordline plugs are then defined with a direct alignment over the SA bitline architecture.
Figure 3. TEM cross-section (along y-direction) of the SA µTrench array, showing the large distance between two adjacent heater that allows to use a non-critical mask for their definition.
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Figure 2. SEM picture of the SA µTrench array after the GST self-aligned etching step.
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Fig.4 reports a typical current-voltage (I-V) curve of a SA µTrench, while the programming characteristic of the same cell is shown in Fig.5. The small contact area of the µTrench heater combined with several geometrical optimizations is very effective in reducing the programming current down to 300uA with 1.6Vvoltage drop on the cell. The proposed PCM cell architecture has been integrated in a 128Mb vehicle with a 90nm CMOS technology. A die photo is shown in Fig.6. The PCM cell is a 1T/1R structure, where the select transistor is a vertical pnp-BJT, and the resistor is the SA µTrench storage element. The base of the pnp-BJT constitutes the wordline, while the emitter is connected to the bottom electrode of the storage element through a tungsten plug. The collector is formed by the common ground. The STI depth is 270nm to optimize the BJT active and passive characteristics. The cell layout is fully self-aligned, using a cross-point architecture between the active area and the emitter and base implant stripes. Emitter and base contact resistance has been optimized keeping both active areas salicided with CoSi2. Considering the STI depth requirement of the PCM cell, single STI approach has been used. The transistor architecture is defined considering the memory specification: 8nm gate oxide CMOS with dual-flavor CoSi2 transistor, in order to maximize the current and to sustain the 3V operation needed to program the cell. The metallization has been chosen considering the cell layout and the compatibility with the state-of-the-art NOR Flash technology. 3 Cu lines have been integrated with line1 used in cell array for wordline (WL), line2 used in cell array as main bitline, and line3 used only in periphery (or as global WL). Finally, the contact between line2 and GST line is formed using an ad-hoc strap. The resulting statistical distributions for both the set and reset states have been collected and are reported in Fig.7. A good current window is demonstrated, assessing the 128Mb vehicle functionality and providing the experimental evidence of the feasibility of high-density stand-alone PCM based on the SA µTrench architecture.
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Figure 7. Statistcial distributions for the set and reset programmed states collected on one tile of the 128Mb vehicle.
IV.
CONCLUSIONS
A novel SA µTrench-based cell architecture for PCM integrated at 90nm technology node has been reported for the first time. The low-programming current and the good dimensional control of the sub-lithographic features achieved with the µTrench structure are combined with a self-aligned patterning strategy that simplifies the integration process in term of lithographic requirements and fabrication costs. The proposed architecture has been electrically characterized, showing typical programming currents of 300µA at 1.6V. A 128Mb vehicle has been fabricated in a 90nm CMOS process and its functionality has been demonstrated with wellseparated distributions for the set and reset programmed states. The SA µTrench architecture is thus a promising candidate for a cost-effective manufacturing of PCM arrays at 90nm and beyond. REFERENCES [1] [2]
[3] [4] [5] [6] [7] [8]
[9]
R. Bez and G. Atwood, “Chalcogenide Phase Change Memory: Scalable NVM for the Next Decade?”, NVSMW 06., pp. 12-15, 2006. F. Pellizzer et al., “A 90nm Phase-Change Memory Technology for Stand-Alone Non-Volatile Memory Applications”, Symp. on VLSI Tech., pp. 122-123, 2006. S. Kang et al., “A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM”, ISSCC Tech. Dig., pp. 140-141, 2006. Y. H. Ha et al., “An edge contact type cell for phase change RAM featuring very low power consumption”, VLSI Symp. on Tech., 2003. S. J. Ahn et al., “Highly manufacturable high density phase change memory of 64Mb and beyond”, IEDM Tech. Dig., pp. 907-910, 2004. K. Elissa, F. Merget et al. “Novel lateral cell design for low current phase change RAM memories”, NVSMW 04, pp. 30-31, 2004. M. H. R. Lankhorst et al.., “Low-cost and nanoscale non-volatile memory concept for future silicon chips”, Nature Materials, xxx, 2005. F. Pellizzer et al., “Novel µTrench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications.”, Symp. on VLSI Tech., pp. 18-19, 2004. A. Pirovano et al., “µTrench Phase-Change Memory Cell Engineering and Optimization”, Proc. ESSDERC 05, pp. 313-316, 2005.
