semiconductor devices - JKU

JOURNAL OF APPLIED PHYSICS 106, 114505 共2009兲

Electrical response of highly ordered organic thin film metal-insulatorsemiconductor devices Mujeeb Ullah,1 D. M. Taylor,2,a兲 R. Schwödiauer,3 H. Sitter,1 S. Bauer,3 N. S. Sariciftci,4 and Th. B. Singh4,b兲 1

Institute of Semiconductor and Solid State Physics, Johannes Kepler University, A-4040 Linz, Austria School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT, United Kingdom 3 Soft Matter Physics, Johannes Kepler University, A-4040 Linz, Austria 4 Linz Institute for Organic Solar Cells (LIOS), Physical Chemistry, Johannes Kepler University, A-4040 Linz, Austria 2

共Received 9 September 2009; accepted 28 October 2009; published online 10 December 2009兲 We report a detailed investigation of the electrical properties of organic field-effect transistors 共OFETs兲 and metal-insulator-semiconductor 共MIS兲 capacitors formed from highly ordered thin films of C60 as the active semiconductor and divinyltetramethyl disiloxane-bis共benzocyclobutene兲共BCB兲 as the gate dielectric. Current-voltage measurements show the OFETs to be n-channel devices characterized by a high electron mobility 共⬃6 cm2 / V s兲. An equivalent circuit model is developed which describes well both the frequency and voltage dependences of the small-signal admittance data obtained from the corresponding MIS capacitors. By fitting the circuit response to experimental data, we deduce that increasing gate voltages increases the injection of extrinsic charge carriers 共electrons兲 into the C60. Simultaneously, the insulation resistance of the BCB decreases, presumably by electron injection into the insulator. Furthermore, the admittance spectra suggest that the capacitance-voltage 共C-V兲 behavior originates from a parasitic, lateral conduction effect occurring at the perimeter of the capacitor, rather than from the formation of a conventional depletion region. © 2009 American Institute of Physics. 关doi:10.1063/1.3267045兴 I. INTRODUCTION

Thin-film organic field-effect transistors 共OFETs兲 based on the symmetric C60 molecule have shown high charge carrier mobility in the range 3 – 6 cm2 / V s, thus establishing a benchmark for n-type organic semiconductors.1–7 The electrical response of OFETs is generally probed by modulating the conductance at the semiconductor-insulator interface with a gate voltage, VG, applied normally to the interface. In particular, the dependences of source-drain current ID, on VG, temperature, and source-drain gap L are used to establish the nature of charge injection and transport mechanism in such devices. However, large variations in the experimental data on even nominally the same sample8,9 make it difficult to draw unambiguous conclusions as to processes occurring in the device. Small-signal measurements on metal-insulatorsemiconductor 共MIS兲 capacitors and directly on OFETs10–18 provide an alternative method for investigating such processes. A combination of admittance spectra and capacitance-voltage 共C-V兲 data provides a wealth of information not only on the semiconductor layer, e.g., doping density and bulk mobility,11 but also on the interface between semiconductor and gate dielectric,10,11,19 e.g., the density of states for interface traps.20 Admittance spectroscopy and C-V a兲

Author to whom correspondence should be addressed. Electronic mail: [email protected]. b兲 Present address: Ian Wark Laboratory, Molecular and Health Technologies, CSIRO, Bayview Ave., Clayton, Victoria 3168, Australia. Electronic mail: [email protected]. 0021-8979/2009/106共11兲/114505/6/$25.00

measurements on p-type pentacene18 and poly 共3hexylthiophene兲16,21 based MIS capacitors and OFETs have been reported already. However, no reports have yet appeared of similar measurements on MIS capacitors fabricated from high mobility electron transporting materials such as thin crystalline films of C60. In this paper, we present both the output and transfer characteristics of OFETs formed from highly crystalline thin films of C60 grown on divinyltetramethyl disiloxanebis共benzocyclobutene兲共BCB兲 together with the admittance spectra of MIS capacitors employing the same materials. The results show that the threshold voltage is related to the injection of extrinsic charge carriers into the semiconductor and that “depletion” arises from reduced injection rather than from the formation of a space-charge layer of ionized dopants that is typical of conventional silicon devices. II. EXPERIMENTAL

OFETs and MIS diodes were fabricated using patterned indium tin oxide 共ITO兲-coated glass slides as the gate electrode/substrate. The slides were cleaned using acetone, 2-propanol, Helmanex glass cleaning solution, and finally with de-ionized H2O in an ultrasonic bath. The gate dielectric, BCB2–4 purchased from Dow Chemicals, was dissolved in mesitylene and spin coated onto the ITO substrate and cured at 250 ° C for 2 h in a vacuum oven. C60 cleaned by sublimation was used as received from MER Corp. After curing the BCB, a 300 nm thick film of C60 was grown by hot wall epitaxy at a temperature Ts = 250 ° C and with a base vacuum of 10−6 mbar. A shadow mask was used to pattern

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© 2009 American Institute of Physics

Author complimentary copy. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp

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FIG. 2. 共Color online兲 Gate voltage dependence of the mobility 共open diamonds兲 calculated from the local slope of the OFET transfer characteristic in Fig. 1共b兲. Also shown 共closed diamonds兲 is the reciprocal of the sheet resistance of the semiconductor contributing to the lateral conduction effects at the perimeter of the MIS capacitor.

organic layers were measured under ambient conditions with a Digital Instrument Dimension 3100 atomic force microscope. III. RESULTS AND DISCUSSION FIG. 1. 共Color online兲共a兲 Output characteristics of the C60 OFET. The device structure is shown in the inset. 共b兲 The transfer characteristics of the same device obtained at VD = 60 V, plotted as log ID vs VG 共main diagram兲 and as ID0.5 vs VG in the inset.

the C60 film which was of the same high crystalline quality as that reported previously.2 Devices were completed by evaporating top-contact electrodes consisting of LiF/Al 共0.6 and 60 nm thick, respectively兲 under high vacuum 共⬃10−6 mbar兲 using a shadow mask placed in the same holder as before to ensure optimum registration with the gate electrode under the C60 film. The structure of the devices is shown in the insets of Figs. 1 and 3. The channel length 共L兲 and width 共W兲 in the OFET were 30 ␮m and 1.5 mm, respectively. The MIS capacitors were prepared in such a way that all the layers had an active area of 3 ⫻ 3 mm2. The average thickness of the dielectric was typically in the range 1 – 1.5 ␮m. Device transportation from the hot-wall reactor to the glove box for top-contact evaporation was carried out under ambient conditions. Electrical characterization of the OFETs was carried out in an Oxford Instrument DNV Optistat with a base pressure of 10−6 mbar. An Agilent parametric measurement system 共model E5273A with two source-measure units兲 was employed for the steady-state current-voltage measurements. All measurements were performed at a scan rate of 2 V/s. The small-signal response of the MIS capacitors was measured over a wide frequency range using an HP 4248A precision LCR meter and applying to the gate electrode a probe signal of 0.1 V superimposed on a bias voltage, VG. Capacitance-voltage 共C-V兲 measurements were made at 1.2 kHz by incrementing/decrementing VG through the range ⫾40 V at a rate of 0.02 V/s. Admittance spectra were obtained over a wide range of frequencies at several predetermined values of VG. The thicknesses of the dielectric and

A. dc characteristics of the OFETs

Figure 1 shows 共a兲 the output and 共b兲 the transfer characteristics of the C60 OFETs. These are well described by the conventional equations for the dependence of drain current ID on gate voltage VG and drain voltage VD, i.e.,

冋

ID =

V2 W ␮Ci 共VG − VT兲VD − D 2 L

ID =

共VG − VT兲2 W ␮Ci 2 L

册

共1兲

and 共2兲

in the linear and saturation regimes, respectively. Here, W / L共⬃50兲 is the aspect ratio of the OFET, ␮ is the effective mobility in the channel, and Ci共⬃1.4⫾ 0.2 nF/ cm2兲 is the capacitance per unit area of the gate dielectric. From the plot of 冑ID versus VG, 关inset of Fig. 1共b兲兴, the threshold voltage VT is deduced to be ⬃11 V. Transport in the accumulation channel of OFETs is generally assumed to occur by hopping through localized states so that ␮ depends on VG, through control of state occupancy. The form of the gate-voltage dependence may be deduced from the local slope of the 冑ID versus VG plot,22 i.e.,

␮=

冉冊

W d冑ID 2LCi dVG

2

共3兲

and is plotted in Fig. 2. As can be seen, ␮ increases rapidly through the subthreshold region 共VG ⬍ 11 V兲 attaining a maximum value of ⬃5.8 cm2 / V s when VG ⬃ 45 V but then decreases slowly above ⬃50 V. Departure from this maximum value may be expected, since Eq. 共3兲 ceases to be valid as device operation moves from the saturation to the linear regime at higher VG. Contact resistance effects may also be a factor in such behavior.23


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FIG. 3. 共Color online兲 Capacitance 共C兲 and loss 共G / ␻兲 measured at 1.2 kHz when sweeping the gate voltage VG from ⫺40 V 共closed symbols兲 and then from +40 V 共open symbols兲. The inset 共top left兲 depicts the structure of the MIS capacitor. When plotted in Mott–Schottky format 共Ref. 24兲, the capacitance data show good linear behavior over part of the range 共right inset兲.

B. Voltage dependence of capacitance and conductance

In Fig. 3 the capacitance C and loss G / ␻ 共conductance/ angular frequency兲 of the C60 MIS capacitors measured at 1.2 kHz are plotted as functions of VG. The sharp decrease in capacitance as VG sweeps from positive to negative bias is consistent with the formation of a depletion region in the C60 film. Furthermore, the peak occurring in the G / ␻ versus VG plot for depletion voltages is consistent with the presence of interface states.20 Replotting the capacitance data in the Mott–Schottky format,24 1 2 1 共VG − VFB兲, 2 = 2 + C CI ␧␧0qNDA2

共4兲

where ␧ is the relative permittivity of the C60 film, ␧0 is the permittivity of free space, CI is the capacitance of the insulator, q is the electronic charge, ND is the donor doping density, A is the device area, and VFB is the flat band voltage, yields a linear region for VG in the range ⫾5 V 共see inset of Fig. 3兲 from which a donor doping density, ND ⬃ 2 ⫻ 1016 cm−3, is deduced. Although this is a reasonable value, we show in Sec. III C that the step change in capacitance in Fig. 3 does not arise from the creation of a spacecharge layer of ionized donors in the semiconductor.

FIG. 4. 共Color online兲 Frequency dependence of 共a兲 capacitance C and 共b兲 loss G / ␻ measured for various voltages applied to the ITO electrode. The solid curves are numerically generated fits based on Eqs. 共5兲–共9兲 and the parameters in Table I.

resistance, RC, associated with the electrodes.11 In the following, we concentrate on the origin of the two main dispersions. An ideal MIS capacitor is composed of two dielectric layers 关Fig. 5共a兲兴 and may be represented by the section of the equivalent circuit labeled “Diode” in Fig. 5共b兲. Here, RB and CB represent the resistance and capacitance of the bulk C60 layer, RI and CI, and the resistance and capacitance of the insulator, all defined by the area of the LiF/Al electrode 关Fig. 5共a兲兴. RC is a series resistance associated with the con-

C. Frequency dependence of capacitance and loss

The frequency dependence of capacitance and loss of the MIS diode are plotted in Fig. 4 for a range of VG. Two dispersions are clearly visible: 共i兲共ii兲

a high frequency process whose central frequency shifts from ⬃50 to ⬃100 kHz for increasing accumulation voltages and a process which occurs at low frequency for depletion voltages but shifts to higher frequencies, eventually merging with the high frequency process, as VG increases in the accumulation regime.

The rapid rise in loss at the highest frequencies suggests also the presence of a third dispersion arising from a series

FIG. 5. 共a兲 Partial cross section of the MIS capacitor showing the origin of the edge effect. 共b兲 The equivalent circuit of the diode showing the contributions from the main capacitor structure and from the presence of excess semiconductor of width LE at the electrode perimeter.


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Ullah et al. TABLE I. Parameter values used to obtain the theoretical plots in Fig. 4. VG 共V兲 CI 共pF兲 RI 共⍀兲 CB 共nF兲 RB 共⍀兲 RC 共⍀兲 CE 共pF兲 RSL2E / AE 共⍀兲

⫺20 143.8 1 ⫻ 1013 11.0 160 52 2.44 5 ⫻ 109

⫺10 143.8 1 ⫻ 1013 11.0 160 50 2.44 3 ⫻ 109

0 143.7 1 ⫻ 1013 11.0 160 53 2.44 5.5⫻ 108

tacts. It is known from recent studies of parasitic effects in MIS capacitors25–27 that lateral conduction at the electrode edge can make significant contributions to the low frequency capacitance of MIS capacitors with unpatterned bottom electrodes. In the present work, an attempt was made to eliminate this effect by creating a “mesa” structure in which the top contact was aligned with the patterned semiconductor layer. However, we believe that sufficient semiconductor was left uncovered to give rise to an edge effect in which carriers drifting through the protruding semiconductor of length LE 关Fig. 5共a兲兴 charge the insulator capacitance lying under the excess semiconductor. The effect of such lateral conduction is represented by the distributed RC network in Fig. 5共b兲, where RS is the sheet resistance 共⍀ / sq兲 of the semiconductor layer and Ci is the capacitance per unit area of the insulator. The total admittance, Y, presented by the circuit in Fig. 5共b兲 is given by Y = G + j␻C = 共Y I−1 + Y B−1 + RC兲−1 ,

共5兲

where j = 冑−1, G and C are the measured conductance and capacitance of the device 共assumed to be in parallel兲, and where Y B = 共RB−1 + j␻CB兲

共6兲

Y I = 共RI−1 + j␻CI兲 + 共Ge + j␻Ce兲.

共7兲

and

Ce and Ge represent the edge effect and are given by26 Ce =

CE sinh ␣ + sin ␣ · ␣ cosh ␣ + cos ␣

共8兲

and Ge CE sinh ␣ − sin ␣ = · , ␻ ␣ cosh ␣ + cos ␣

共9兲

where ␣2 = 2␻CERSLE2 / AE is a normalized relaxation frequency inversely proportional to the carrier transit time across the distance LE, and CE is the geometric capacitance of the area AE of insulator covered by the excess semiconductor. Normally, the edge effect is a low frequency process and is well separated from the main relaxation which occurs when charge carriers in the semiconductor are unable to follow the applied signal voltage. The latter gives rise to the classic Maxwell–Wagner relaxation28 which, for RI Ⰷ RB, occurs at a frequency, f B, given by

10 143.5 8 ⫻ 109 12.0 220 50 2.30 8 ⫻ 106

fB =

20 143.4 8 ⫻ 109 11.5 113 47 2.44 3.2⫻ 106

30 143.5 8 ⫻ 109 11.0 80 49 2.44 2.5⫻ 106

40 143.5 8 ⫻ 109 10.5 75 48 2.44 2 ⫻ 106

1 . 2␲RB共CI + CB兲

共10兲

The dispersion caused by the series resistance, RC, is generally centered at a frequency, f C, well above the measurement range and is given by fB =

共CI + CB兲 1 · . 2␲RC C IC B

共11兲

In the presence of a depletion region, CI must be replaced by the series sum of CI and CD, the depletion region capacitance.11,25 However, the data in Fig. 4 do not support the presence of a conventional depletion region when VG is below threshold. For example, according to the C-V plot in Fig. 3, the device is well into “depletion” when VG = 0 V. Nevertheless, the low frequency capacitance continues to rise to ⬃146 pF, the value observed for accumulation voltages. If a siliconlike depletion region had formed, then the low frequency capacitance should saturate at a lower value corresponding to that observed in the C-V plot.11 A similar upward trend in capacitance for decreasing frequencies also occurs for negative values of VG. Furthermore, increasingly negative values of VG do not reduce the low frequency capacitance to the value observed at high frequencies 共⬃142 pF兲. Also for VG = 0, ⫺10 and ⫺20 V, the capacitance plots merge into a single curve at ⬃10 kHz, again contrary to expectation for true depletion.11 From the above observations, we conclude therefore that for these C60 devices, depletion is a consequence of reduced injection from the contact into the bulk semiconductor. Thus, the suite of Eqs. 共5兲–共9兲 can be used without modification to generate numerical fits to the data presented in Fig. 4. In attempting this seven-parameter fit, it should be noted that a given parameter set must simultaneously provide good agreement with both the capacitance 关Fig. 4共a兲兴 and loss 关Fig. 4共b兲兴 data. Furthermore, it would be expected that the values chosen for CI, CB, and CE should remain essentially constant for all applied voltages. Within these constraints, the best fits that could be achieved are shown by the full curves in Fig. 4, which were generated using the parameter values given in Table I. For VG ⬎ 10 V, an excellent fit is obtained to the data and significantly better than could be obtained by ignoring the edge effect. For VG below 10 V, the numerical curves reproduce the general features of the data but not the broad nature of the two main dispersions. Insofar as the edge effect is concerned, this is probably because of variations in the length, LE, along the perimeter of the electrode. The broader


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than the expected Maxwell–Wagner dispersion most likely arises from a frequency-dependent, hopping conductance in the C60 layer. Notwithstanding these limitations, the numerical fits are illuminating. For example, from CI we deduce that the capacitance per unit area, Ci, is ⬃1.6 nF/ cm2 and almost independent of VG. Interestingly, the insulator resistance is much lower when the device is in accumulation, suggesting facile electron injection into the BCB. This is probably the origin of the slight hysteresis in the C-V plot in Fig. 3 when cycling VG. The shift of the Maxwell–Wagner dispersion to higher frequencies is caused by a decrease in the resistance of the C60 layer from 220 to 75 ⍀ for increasing accumulation voltages. This is indicative of an increasing concentration of injected, extrinsic charge carriers 共electrons兲 in the semiconductor at higher accumulation voltages. The capacitance, CB, of the C60 layer decreases slowly with increasing accumulation voltages. The series resistance of the contacts is ⬃50 ⍀ and is probably associated with the short length of ITO track 共⬃15 mm long⫻ 3 mm wide兲 between the contact point and the electrode itself. Finally, we note that the overall contribution, CE, of the edge effect to the total capacitance is 2.44 pF 共=0.017CI兲 so that AE is deduced to be 0.153 mm2. Since the C60 layer overlaps the underlying gate stripe only on two sides, then LE = 25.5 ␮m. We note that the factor RSLE2 / AE decreases by more than three orders of magnitude over the range ⫺20 V to +40 V. This latter observation is easily explained by the shunting effect of the accumulation channel25 on the sheet resistance of the excess “intrinsic” semiconductor 共LE in Fig. 5兲. This is confirmed in Fig. 2, where R−1 S deduced from Table I scales remarkably well with the OFET mobility calculated from the transfer characteristics. From the above then, we may deduce that the 1.2 kHz C-V plot in Fig. 3, together with its associated maximum in loss, simply reflects the voltage dependence of the dispersion arising from the edge effect. Although the above evidence is convincing, a voltagedependent, low frequency dispersion, such as that attributed here to a parasitic effect arising at the perimeter of the MIS capacitor, can also arise from the tunneling of majority carriers into insulator trap states located close to the interface with the semiconductor.29 Indeed, the slow increase in capacitance for decreasing frequencies when VG ⱖ 10 V 共semiconductor in accumulation兲 may well arise from such an effect. This being the case, additional elements of the form C=

冋

冉

1+␻ ␶ qNt arctan共␻␶兲 arctan共u兲 1 − + ln 2 2K ␻␶ u ␻ 2␶ 2

冉冊册

2 2

冊

1 1 + u2 − ln 2 u2 and

冋

ln共1 + u2兲 ln共1 + ␻2␶2兲 G + = arctan共u兲 − arctan共␻␶兲 − ␻ 2u 2␻␶

共12兲

册共13兲

should be included in the equivalent circuit. Here Nt is the volume density of insulator traps in a layer of width x at the

interface, K is a tunneling constant, and the parameter u = ␻␶e2Kx where ␶ is a time constant given by ␶ = 共␴nvns兲−1, where ␴n is the electron capture cross section, v is the thermal velocity, and ns is the concentration of electrons on the semiconductor side of the interface. To study the effects arising from such a process requires MIS capacitors to be fabricated in which the edge effects believed to dominate in the present work are entirely eliminated.

IV. CONCLUSIONS

High mobility, n-channel OFETs based on highly crystalline C60 films deposited onto the insulator BCB have been fabricated. Classic capacitance-voltage plots obtained at 1.2 kHz from MIS capacitors show behavior normally associated with the formation of a depletion region in the semiconductor. However, even though the donor doping density extracted from the measurement is reasonable, the decrease in capacitance for depletion voltages arises from a different effect. This is confirmed by measuring the capacitance and conductance of the devices over a wide range of frequency and applied voltage. An equivalent circuit for the MIS capacitor is presented which accounts for well-recognized processes occurring in the bulk of the device. The circuit also includes a distributed RC network to account for the charging of additional insulator capacitance by lateral carrier transport through excess semiconductor protruding beyond the perimeter of the top contact. By fitting numerically generated plots based on the circuit, we provide evidence for the following: 共a兲共b兲共c兲

enhanced electron injection from the top contact into the C60 for increasingly higher accumulation voltages; a reduction in the insulation resistance of the BCB layer under accumulation voltages, presumably due to electron injection from the C60 layer; and a voltage-dependent dispersion associated with the perimeter of the capacitor that shifts to higher frequencies as the gate voltage moves through the range ⫺20 to 40 V. It is this dispersion that gives rise to the observed C-V and G / ␻-V plots rather than a conventional depletion region with interface states.

Furthermore, our results suggest that the threshold voltage of the OFETs is related to the injection of extrinsic charge carriers into the semiconductor and that the subthreshold region and “off” state of the transistor reflect reduced electrode injection rather than the formation of a space-charge layer of ionized dopants. While the evidence presented strongly supports the presence of a parasitic edge effect, tunneling of electrons from C60 into insulator states could give similar behavior and cannot definitively be ruled out. Finally, this study has shown that the unambiguous interpretation of C-V data requires supporting evidence from admittance spectroscopy. It has also been demonstrated that care is required when designing and fabricating MIS devices if artifacts connected to parasitic effects are to be avoided.


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ACKNOWLEDGMENTS

Financial support for this work was provided by FWF, the Austrian Foundation for Science and Research 共NFN Project Nos. S9706, S9711, 9712, and P20772000兲 and the Higher Education Funding Council for Wales. 1

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