4OGbithec Circuits Built From a 120GHz f T SiGe Technology G. Freeman, Y . Kwark*, M. Meghelli*, S. Zier, A. Rylyako?, M. Soma, T. Tanji’, 0. SchreiveF, K. Walter, J. Rieh, B. Jagannathan, A. Joseph, S. Subbanna IBM Microelectronics, 2070 Rt. 52, Hopewell Junction, NY 12533 *IBM Research,Yorktown Hts, NY.# A M C C Corp e-mail:
[email protected] Phone: 845-892-4690 FAX: 845-892-3039 specifications can and are being achieved with a SiGe HBT technology. The concerns typically relate to two device properties that are required to achieve high speed operation: a reduction in BVCEO and an increase in the peak-fT current density. On the first point, it is common practice for designers to conservatively consider the BVCEOvalue (1.8V for an fF120GHz SiGe device) a limit for biasing. This is truly not the case, and is only true for a very high base input impedance (see [4]). For the 120 GHz technology of herest, this is illustrated in Fig. 2, where the measured IC vs. VCEoutput characteristic turn-up (or “breakdown”) point is plotted for various input impedance values, for a forced VBEcondition. The figure indicates that typical circuits are constrained to breakdown limits 1.5-2X higher than the conservative BVCEO value, which are well within typical load line operating conditions. Realizing the full voltage potential of this device opens up interesting design possibilities, as will be shown.
Abstract Product designs for 40GbitIsec applications fabricated fiom SiGe BiCMOS technologies are now becoming available. This paper will briefly discuss technology aspects relating to HBT device operation at high speed, acting to dispel some common misperceptions regarding SiGe HBT technology applicability to 40GbitIsec circuits. The high speed portions of the 40Gbit/sec system are then addressed individually, demonstrating substantial results toward product offerings, on each of the critical high speed elements.
SiGe HBT Technology SiGe HBT devices, now well established through several generations of production technologies, have recently moved to production devices with 120GHzfT values, up to 210 [l]. Furthermore, higher peak GHz, have been demonstrated and are expected to be in production in about two years [2]. These SiGe devices are achieving results believed previously to be attainable only in 111-V technologies such as InP and GaAs (Fig. l), and demonstrate the extendibility of the SiGe HBT technologies into high speed wired communication applications. 220 200
,
1. Vcs= 1V
.
t4
,
.
*Rb=O Rb=lOO f Rb=lK =@ Rb=lOK
*
.......... .....IBM SiGe .
0
1
2
3
4
VCE (V)
1E 4
~-
I
1E-3
Fig. 2: Map of “breakdowns”, where dIc/dVcE=4e-3, from various forced VBE common emitter output characteristics, as a function of base resistance in Ohms.
1E-2
The second often cited concern - that of high current densities - is similarly misplaced and comes fi-om experience in 111-V systems where current densities in the semiconductor have historically been a reliability issue. Unlike in 111-V systems, dopant difision does not take place at operating conditions in silicon systems due to the highly stable Si bonding. (It is interesting to note that base dopant diffusion coefficients in InP systems are approximately 18
IC (A)
Fig. 1: fTcharacteristics for prior, subject, and next generation SiGe HBT devices at low current, and comparison to InP HBT low current results 131. Yet there is still some concern about issues relating to high speed operation of these devices. We will first briefly discuss aspects of the device operation to dispel these concerns, and follow this with numerous application results to demonstrate that circuit results achieving high speed and other important
0-7803-6663-8/01/$10.0002001 IEEE
89
2001 IEEE GaAs Digest
a
orders of magnitude higher than in silicon at device operating temperatures). One other concern relating to the current density is metal electromigration, and this must be managed through circuit layout and chip thermal management, but is well within the limits of the metal technology for expected product operating conditions. Strong points to the SiGe technology are the reproducibility, yield, and integration with a wide variety of other devices, including resistors, multiple varactor types, inductors, multiple capacitor types, and high performance FET devices. Of particular note is the capability for design of first-pass successful circuits through accurate predictive models of all device types, together with full parasitic extraction and design verification. As a demonstration, shown in Fig. 3 is a modeVharware comparison across temperature of ring oscillator gate delay. Excellent agreement within about 2% is observed.
-B
9.6 9.4
photodiode
Fig. 4: High speed elements of a 40Gbidsec TDM system in a half-clock rate architecture. OIF SFI-5 standard bodies) make an even more compelling argument for high yield SiGe technologies (as opposed to lower yielding 111-V technologies) at these M W E M U X interfaces. Further integration is shown in the figure, to include the post amplifier and clock extract functions on the DEMUX chip. Such on-chip elements require analog features available through the SiGe technologies, which are principally signal amplification and a tunable oscillator. The transimpedance amplifier, which converts the current signal from the photo diode to a voltage input to the post amplifier, requires a large bandwidth to capture the fill signal from the fiber. The modulator driver must provide sufficient voltage (3Vp-p) to drive the modulator. Results from each of these elements will be discussed next.
Pi /
*
post amp clock extract 2o GHr
I
-
preamp (transimp)
I
3: ECL gate delay vs. temperature comparison to model prediction.
Fig.
MU2UDEMUX 4: 1 and 1:4 multiplexing and demultiplexing circuits have been fabricated. Die photographs are shown in Fig. 5 . With the multiplexer consuming 370mA and the demultiplexer consuming 36011~4 at VEE= -3.3V, circuits have been shown to function error-free with a wide-open eye diagram to SOGbidsec at room temperature. Such speeds in excess of the 4OGbidsec nominal bit rate allow for forward error
Elements of a 40GbWsec System All critical circuit elements of a 40Gbidsec system have been fabricated in IBM’s 120GHz SiGe technology. Shown in Fig. 4 is a diagram of the high speed elements in a typical 40Gbidsec system. Multiplexing elements, typically relying on the raw speed of the technology, interface to the lower bit rates. Shown in the diagram are 10Gbidsec interfaces - yet 2.5 Gbidsec rates, resulting from 16:l and 1:16 MUXlDEMUX functions, are targeted as production parts so that standard 2.5Gb/sec interfaces are utilized. These require thousands of active devices, which is well within the yield capability of the SiGe technology. Packing as much on a single chip saves power, cost and complexity, since most off-chip 50n traces and driving circuits are eliminated. Integrating additional digital functions (such as 2.5 Gbps DLL-based I/O macros and the skew compensation logic that is required to support the SERDES-to-Framer interface as currently defined in
Fig. 5 : Chip micrographs of 1:4 DMUX and 4: 1 MUX
90
Fig. 6: 20GHz clock input and 3OOmVpp 40Gbit/s 4: 1 MUX output eye diagram measured at a temperature of 1OOC on wafer. correction in the system. The circuits have also been shown to be robust to temperature, tested to lOOC with negligible degradation (Fig. 6).
0
10
20
30
40
50
60
70
freg, GHz
Amplifiers Amplifiers have been fabricated, both as lumped amplifiers and as distributed amplifiers. A lumped limiting amplifier demonstrates 28dB differential voltage gain to a single-ended input of 30mV, and a bandwidth of 35GHz (Fig. 7). Frequency response of a distributed transimpedance amplifier, demonstrating S2 1 gains of 11.4dB to a -3dB gain frequency of 49.lGHz and a transimpedance gain of 220Q is shown in Fig. 8. SI 1 and S22 reflections are below -15dB. This part consumes lOOmA at a power supply of VEE= -5.2V. A critical technology element enabling distributed amplification is the planar 4p-1thick aluminum wiring level, placed l o p above a copper metal ground plane. This extremely low-loss and well controlled transmission-line configuration supports the predictive capability and repeatability needed for high yields and first-pass success.
F!g. 8: S21 frequency characteristics for distributed TIA, on-wafer probe. Couresty of AMCC corp. temperature was measured at 3.1MHdC. Under worst case conditions, a fine voltage control provided 427MHz of variation, and a coarse control provided 1.98GHz of variation with a step frequency that varied from 102 to 130 MHz. All the above functionality and specs are obtained together with excellent phase noise of -100dBclHz at lMhz, obtained across coarse frequency control setting and temperature (Fig. 9). This low phase noise translates into very low jitter added by the PLL, which is essential to maintaining low overall system jitter.
Modulator Driver Perhaps the most skepticism is toward application of the SiGe technologies toward the higher voltage -60
Oscillators An element of the clock regeneration phase-locked loop (PLL) is the voltage-controlled oscillator (VCO), which critically depends on the low phase noise and high frequency aspects of the SiGe HBT, as well as a high Q inductor (which at high frequencies is a line, or C-shaped segment), and a high Q varactor for voltage tuning. Working VCO and PLL circuits have been verified on-wafer, and operated at a nominal power supply of -4V (and verified over -2.9 to -6V). These operate at a center frequency of 21.5 GHz (i.e. for a 40Gbidsec half clock rate architecture). Frequency variation due to power supply was measured at 58 MHz and due to
h
N
-70
5m,
-80
;-90 .z" -100
i 100'C 1000
v)
%
r m
'
-110 -120 I
0.1
1
10
100
Offset Frequency (MHz) Fig. 9: 20GHz VCO Phase noise as a hnction of temperature and 4-bit coarse frequency control. 91
more sophisticated test setup will be required to demonstrate the expected 40Gb/s waveforms and is being pursued. A representative eye diagram at 20Gb/s is shown in Fig. 11. For both channels, a 20dB pad was used to protect the scope sampling heads which accounts for the noise in the waveforms. Banding is visible in the output waveform, but further packaging experiments will be needed to determine the source of these reflections. The driver circuit dissipates less than 3W under these drive conditions. The driver was “stressed” by increasing output drive levels to 4V p-p and then by increasing the power supply from -7.5V to -lOV. Although waveform fidelity suffered under these conditions, neither of these stress conditions led to a discernible change in output waveform morphology when the correct bias settings were restored. Operation under these conditions requires some of the SiGe bipolar devices to operate with 4V to SVp-p VCE - well in excess of their nominal rated DC BVcEo. Further testing is needed to address the long term reliability implications of operating under these conditions, but these measurements indicate that SiGe bipolar technology may be able to address higher voltage drive applicationsthan is currently perceived.
Fig. 10: On-wafer testing of EAM driver
Conclusions All the critical non-optical elements of the high-speed 40Gbidsec system have been fabricated and excellent performance demonstrated in the IBM 120GHz SiGe technology. Owing to IBM’s design kit predictive modelling capability, design verification, and good yield, in nearly every case, first pass success was achieved. The high yield and device integration capability in SiGe enables the designers as a next step to integrate the demonstrated pieces into more highly integrated parts, adding CMOS and increasing HBT count.
Fig. 11: 20Gbidsec input waverform at SOOmVp-p and 200mV/division (top) and output waveform into a 50R load at 3.2V p-p and 1Vldivision (bottom). swings of the modulator driver. Discussed here is a SiGe driver which is demonstrated to provide over the nominal 3V p-p drive levels into an external SO ohm load while operating with a single -7.5V power supply. The circuit was optimized to,drive an external EAM (ElectroAbsorption Modulator) and as such provides the required DC offset as well as a nominal DC adjustment to accommodate some variation in EAM optical threshold. The single ended input and output are both interfaced to the external package through on-chip 500 CPW launches. For both input and output, 50 ohm DC coupling (CML topology) was adopted to permit direct coupling to CML type signal levels without the need for AC coupling. An input offset adjustment is provided to correct for waveform symmetry and the output amplitude can also be varied with an external control voltage. The circuit was tested on-wafer at 10 and 20Gb/s using high speed 40 GHz G-S-G on-wafer CPW probes for both input and output signals (Fig. 10). A
Acknowledgments The authors acknowledge the project management team for managing the successful multi-project wafers, the measurement team for outstanding device measurements, and the multitude of designers and companies who provided input to this technology development, some of whom provided inputs to this paper, but wished to remain anonymous.
References [I] A. Joseph et. al., BCTM 2001 to be published [2] B. Jagannathan et.al.,IEDM 2001, to be published [3] M. Sokolich, et. al. IEEE Electron Device Lett., Vol22, pp 8-10, Jan. 2001. [4] Rickelt and H.M. Rein, Proc. BCTM 1999, p.54
92
