SII-PFC: series inductance interval converters for single-stage power ...

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Feb 22, 2002 - An equivalent input noise current density (iJ of the APD/pre-module is shown in Fig. 2. .... 1 SII-B converter scheme and main functional features.
Module configuration: The InAlAs APD which has a gain-bandwidth product of 120 GHz and a back-illuminated structure, was flip-chip mounted on an AIN submount. The AIN submount was connected to a pad on an Al2O3 substrate by AuSn soldering. The SiGe-HBT preamplifier which has a transirnpedance of 61dBQ and a wide frequency response of 10 GHz was mounted on the A1203 substrate. The electrical connections of the preamplifier were made by Au wirebonds instead of solder bumps. The APD/pre-module consisted of a 5 0 R microstripline on the A1203 substrate terminating in a K-connector for the RF output. The optical-to-electrical signal was output through the K-connector to the following stage. To mitigate a significant influence on high-frequency characteristics caused by an LC resonance due to the inductance and parasitic capacitance of the bonding wire in the APD bias circuit, damping resistors were inserted into the resonance-loops. The frequency responses of the APD/ pre-module are shown in Fig. 1. The 3 dB bandwidths with M= 12 and M = 2 were 8.2 and 9.3 GHz, respectively. An equivalent input noise current density ( i J of the APD/pre-module is shown in Fig. 2. The insertion of damping resistors for the mitigation was found not to degrade the noise characteristics. The noise current averaged up to 8.2 GHz was 6.3 pA/1/Hz. These performances were sufficient for 10 Gbit/s operation. Sensitivity measurement and results: To measure BER characteristics of the APD/pre-module, it was incorporated into a full-receiver consisting of a Si-bipolar automatic-gain-control (AGC) IC, a hybrid voltage-controlled-oscillator (VCO) IC, and a Si-bipolar clock-data-recovery (CDR) IC, except the APD/pre-module. As an optical signal source for sensitivity measurement, a commercially available LiNb03 Mach-Zehnder external modulator and CW light source with a wavelength of 1550 nm were used. Fig. 3 shows eyc patterns of the APD/pre-module at the optical received power (Pr) -28.5 dBm with M= 12, and at the Pr -0.5 dBm with M = 2, respectively. Excellent eye openings were confirmed. The BER curves are shown in Fig. 4. For practical use, a PRBS of Z3' - 1 word length was used. Minimum sensitivity was -29.5dBm with PRBS of 23' - I at BER of IOp9. The optical overload was +0.4dBm with the same conditions. These values corresponded to a dynamic range of 29.9 dB. Conclusion: We have realised a high-sensitivity and wide-dynamicrange APD/pre-module which has a sensitivity of -29.5 dBrn with PRBS of 231- 1 at BER of IO-' and a dynamic range of 29.9dB. To our knowledge, thesc measured values are the best performances to date.

0 IEE 2002 Electronics Letters Online No: 20020434 D o l : 10.1049/el:ZO020434

22 February 2002

H. Matsuda, A. Miura and H. Irie (Transmission Modtile Center, OpNext Japan Inc., 21 6 Totsuka-cho, Totsuka-ku, Yokohanza 244-8567, Japan)

E-mail: [email protected] S. Tanaka, S. Fujisaki and R. Takeyari (Central Research Laboratory, Hitachi Ltd., 1-280 Higashi-loigakubo, Kokiibunji-shi, 185-8601, Japun)

and MAKITA, K.: ' IO-Gigabit-per-second high-sensitivity and wide-dynamic-range APD-HEMT optical receiver', IEEE Photonics Technol. Lett., 1996, 8, pp. 1232-1234 NAKATA, T., TAKEUCHI, T., WATANABE, I., MAKITA. K., and TORIKAI, T.: ' 10 Gbit/s high sensitivity and low-voltage-operation avalanche photodiodes with thin InAlAs multiplication layer and waveguide structure', Electron. Letf.,2000, 36, pp. 2033-2034 YUN, T.Y., PARK, M.S., HAN, J.H., WATANABE, I . ,

WASHIO, K., OHUE, E., SHIMAMOTO, H., ODA, K., HAYAMI, R., KIYOTA, Y., TANABE, M., HASHIMOTO, T., and IIARADA, T.: 'A 0.21lm 18O-GHz-fmax

6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications'. Tech. Dig. Int. Electron Device Mtg., San Francisco, CA, USA, 2000, pp. 741-744

SII-PFC: series inductance interval converters for single-stage power factor correction A. Lhzaro, A. Barrado, J. Pleite, R. Vazquez and E. Olias Compliance with EN 61000-3-2 Class-D for any load power range together with a low value and variation in the storage capacitor voltage are the main features of the proposed new family of single-stagepower factor correction converters (PFC). Introduction: Line current harmonics regulations such as the European Normative EN 61000-3-2 (identical to IEC 1000-3-2) open new possibilities for power supplies. It is now enough to present lower input current harmonics than the regulation limits. Therefore, designers are able to achieve compliance with these limits and a wellregulated output voltage with simpler and cheaper circuits. For these reasons, single-stage power factor correction converters (PFCs) are being taken into account. Inspection of prior work [ 1-51 provides some important conclusions. Two requirements are imposed on most single-stage PFCs. First, an adequate hold-up time performance; secondly, reduced size for the storage capacitor within commercial values (e450 V). The main advantages of the new family of converters, can be summarised as follows. Storage capacitor voltage: The value of this voltage can be selected even below the peak value of the line voltage (European range 264373 V). This aspect is particularly important since, in most cases, the value of voltage that optimises the size of the storage capacitor for a fixed hold-up time should be lower than the mentioned range. Among the different converters of the family, lower and higher values than the output voltage can be selected. Moreover, this family presents an inherent low variation in the storage capacitor voltage with respect to the load power range and with respect to the RMS value of line voltage. Input current: The second important advantage of this family is that input current contains harmonics lower than the EN 61000-3-2 Class-D limits for the whole range of load power. Therefore these converters are a quite robust solution. Experimental results will show how these goals have been achieved.

K. Ito and T. Toyonaka (Optical Device Center, OpNext Japan h e . , 216 Totstika-cho, Totsuka-hi, Yokohama 244-8567, Japan) H. Takahashi and T. Harada (Device Development Center, Hitachi Ltd., 6-16-3 Shinmachi, Ome-shi 198-8512, Japan) H. Chiba and S. Irikura (Advanced Technology Development Department, Hitachi ULSl Systems Co. Ltd., 6- 16-3 Shinmachi, Ome-shi, 198-8512, Japan) References 1

MIYAMOTO, Y., HAGIMOTO, K., ONHATA, M., KAGAWA, T., TSUZUKI, N., TSUNETSUGU, H., and NISHI, 1.: 'IO-Gbit/s strained MQW DFB-LD

0

transmitter module and superlattice APD receiver module using GaAs MESFET ICs', IEEE 1 Lightwave Technol., 1994, 12, pp. 332-342 2

TZENG, L.D., MIZUHAIIA, O., NGUYEN, T,V, OGAWA, K., WATANABE, I., MAKITA, K., TSUJI, M., and TAGUCHI, K.: 'A high-sensitivity APD

receivcr for 10-Gb/s system applications', IEEE Photonics Technol. Lett., 1996, 8, pp. 1229-1231

ELECTRONICS LETTERS 20th June 2002

Fig. 1 SII-B converter scheme and main functional features Discontinuous conduction mode (DCM) operation in both inductances; fast output voltage regulation; single control loop; secondary side energy storage in CI; series inductance intcrval: final common reset of LIZand LzI

Vol. 38 No. 13

65 1

Proposed topology: In this Letter the principle of operation as well as experimental results will be presented for the series inductance interval-boost converter (SII-B). The main functional features are summarised in Fig. 1.

During a portion of the line cycle, C, stores energy which is delivered to the output when input power is lower than the output power (Fig. 2u(iii)). Finally, the input current results are modulated by the duty cycle and the input voltage, as can be seen in Fig. 2a(ii).

Energy flow aizd liize frequency waveforms: The input of the power stage is a flyback converter with two output diodes. These diodes split the line energy. A part of this energy (trace 1 in Fig. 2a(iv)) is directly delivered to the output through Dsl (single processing energy). The other portion of the input energy is stored in the capacitor C I through the diode DAUX,The components LZ2,S2 and Dsz can be seen as a boost converter (this is the reason for the name SII-B). Complementary to the single processing energy, this boost converter feeds the output via DS2 (trace 2 in Fig. 2a(iv)) from the storage capacitor C1, mainly when input voltage is low. In Fig. 2a(i) it is shown how the duty cycle must vary with the line angle to keep the output voltage constant. The output voltage presents a fast dynamic response since the addition of the average currents through Dsl and Ds2 results are constant (see Fig. 2a(iv)).

Switching process: The different stages of a switching period could be summarised as follows (Fig. 2b):

* 1"

' 31

If7

I

C"Re"1

Stage 1: S1 and S2 are On. L22 is magnetised from VCl and L12 is magnetised from input voltage, VR~.CT. Stage 2: LZ2resets through DS2 to the output. During this stage the diode DAUXis reverse biased since the voltage in the transformer T2 is imposed by the conduction of DS2. Moreover, n2, the transformer turns ratio of T2 is < 1, (n2