Simulation of Quantum Current Oscillations in Trigate ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 5, MAY 2010

Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs Nima Dehdashti Akhavan, Aryan Afzalian, Member, IEEE, Chi-Woo Lee, Ran Yan, Isabelle Ferain, Pedram Razavi, Giorgos Fagas, and Jean-Pierre Colinge, Fellow, IEEE

Abstract—In this paper, we simulate quantum transport in trigate silicon-on-insulator (SOI) nanowire field-effect transistors using 3-D numerical simulations. The formation of 1-D subbands in SOI nanowire, which results in the oscillation of the current and transconductance characteristic at low temperatures, has been studied in detail. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased, thereby enabling the experimental evaluation of the subband energy spacing in nanowire structures (subband spectroscopy). Index Terms—Current oscillation, low temperature, multiplegate MOSFET, nanowire, numerical device modeling, 3-D simulation, 1-D quantum transport.

I. I NTRODUCTION

I

MPROVEMENTS in processing techniques have enabled the downscaling of semiconductor devices and fabrication of transistors with nanometer features. Further shrinking of the channel region in the classical bulk MOSFET will introduce new effects that pose challenges to device operation and enhance short-channel effects (SCEs), ON-current, and subthreshold slope degradation. In order to continue scaling, various device architectures have been proposed. Among these new devices, the multigate silicon nanowire transistor is particularly suited to overcome the scaling problems. Extensive theoretical and experimental investigations have been done by many groups and prove that the multigate field-effect transistor (MuGFET) exhibits excellent resistance to SCEs and hence offers better electrical characteristics than classical MOSFETs. In a MuGFET, scaling involves not only a reduction in channel length but also a reduction in semiconductor body thickness and width. Due to this reduction in body section, carriers are confined in the plane perpendicular to the channel, which leads to the formation of subbands inside the device. The effect of lateral confinement and related conductance quantization effects has extensively been studied. In low-dimensional devices, quantum confinement and subband splitting give rise to interesting phenomena. These effects can clearly be observed at low temperatures. At room temperature, these quantum effects tend to vanish due to ther-

Manuscript received August 26, 2009; revised February 1, 2010. Current version published April 21, 2010. This work was supported by the Science Foundation Ireland under Grant 05/IN/I888 and Grant 06/IN.1/I857. The review of this paper was arranged by Editor C. McAndrew. The authors are with the Tyndall National Institute, University College Cork, Cork, Ireland. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2044295

mal broadening of the energy distribution of the electrons. However, if both device dimensions and the drain voltage are small enough, these quantum characteristics can be observed at moderately low temperatures and even at room temperature. Different groups have fabricated multigate nanowire transistors and have reported the observation of oscillations in the drain current versus gate voltage at low temperatures, near room temperature, and at room temperature [1]–[6]. This effect is due to the filling of consecutive 1-D energy subbands by electrons as the gate voltage is increased. Singh et al. fabricated silicon gate-all-around nanowire transistor and investigated the effect of different physical parameters such as nanowire diameter and crystal orientation on current oscillations at low temperatures [7]. Similar work has also been done in the area of modeling carbon nanotube field-effect transistors (FETs) at low temperatures, but due to cylindrical confinement of the wave function in carbon nanotubes, such oscillations cannot be observed [8], [9]. In the case of silicon nanowire transistors, experimental observations have revealed a strong dependence of the drain current oscillations versus gate voltage on both the temperature and the applied drain voltage [3], [4], [10], [11]. Current oscillations can be observed only if the electron energy (both kinetic and thermal) is smaller than the subband energy spacing. The smaller the diameter of the nanowire, the higher the temperature and drain voltage at which drain current oscillations can be observed. From a theoretical point of view, as the gate voltage is increased, we expect to observe drain current oscillations in nanowire due to quantum mechanical effects caused by carrier confinement in the plane perpendicular to current flow. However, despite the several different approaches developed to study quantum transport in nanostructures [12]–[16], there is no report of investigating such quantum current oscillation due to quantization effects using numerical simulations. The only previous report on modeling such quantum current oscillations is a study that verifies the relation between the quantum effects at low temperatures and device parameters using a 1-D analytical quantum transport model assuming a MOSFET-like operation for the nanowire device [12]. Here, we perform extensive numerical modeling of the quantum transport in trigate nanowire transistors using a 3-D quantum simulator. The effect of drain/source bias on the electrical characteristics at different temperatures has been studied, and the results are compared with experimental data. Finally, we establish that the conditions for occurrence of oscillations are related to the energy separation between separated subbands ΔE.

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AKHAVAN et al.: SIMULATION OF QUANTUM CURRENT OSCILLATIONS IN TRIGATE SOI MOSFETS

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The outline of this paper is given as follows. In Section II, the simulation method used in this study is briefly described. The theory of the low-dimensional system at low temperatures is explained in Section III. The simulation results and discussion and the comparison with experiment data are then presented in Sections IV and V, respectively. II. N UMERICAL M ETHOD AND S IMULATION Different simulation methods have been developed to investigate electron transport in nanoscale devices, such as the Wigner function, the density matrix, and the nonequilibrium Green’s function (NEGF) [13]–[16]. Here, we adopt the NEGF approach where the quantum kinetics of the particles is governed by Green’s function equations. To describe the device and compute observable physical quantities, we need to solve the coupled set of quantum transport and electrostatic equations self-consistently. The governing NEGF equations in real space are −1 GR (r, E) = EI − H(r, E) − ΣR (r, E) G< (r, E) = GR (r, E)Σ< (r, E)GA (r, E) n(r) = − i G< (r, E)dE.

(1)

Here, GR and G< are the retarded and the lesser Green’s function, whose diagonal elements yield the density of states and electron density, respectively. GA is the complex conjugate of GR , and Σ< is the lesser self-energy matrix. The Hamiltonian matrix H includes the kinetic energy and the selfconsistent electrostatic potential of the 3-D structure, and ΣR is the retarded self-energy matrix of the contacts. The selfenergy matrix is computed from the surface Green’s function of isolated source and drain contacts [13] and [14]. Finally, n(r) is the 3-D electron charge concentration in the device that should satisfy Poisson’s equation subject to input voltages given as boundary conditions. A comprehensive development of the real-space NEGF in the effective mass approximation is described by Anantram et al. [13], and has been applied to 2-D MOSFET structures in the past years. After discretization, the 3-D device Hamiltonian takes the block-tridiagonal form schematically given in Fig. 1. The size of this matrix is (N x × N p) × (N x × N p), where N x and N p are the number of mesh points in the transport direction and that in a plane of confinement perpendicular to current flow, respectively. The matrix elements in Fig. 1 are defined as ⊗ = 2tx + 2ty + 2tz + USC tx,y,z =

2 2m∗x,y,z

∗ = 2ty ,

× = 2tz (2)

where tx , ty , and tz are the hopping parameters in the x-, y-, and z-directions, respectively. The complete definition of the different matrix elements can be found in [13]. In particular, USC in the diagonal elements incorporate the potential energy at each mesh point. To reduce the computation time associated with the integration part in (2), we have developed an in-

Fig. 1. Schematic of the 3-D effective mass Hamiltonian, discretized in the real space with dimensions of 4 × 4 × 4. The diagonal (⊗) and off-diagonal blocks (∗) represent tight-binding Hamiltonians in the cross section of the nanowire and tight-binding Hamiltonian couplings between adjacent cross sections in the nanowire are represented by (×), respectively. The explicit form is given by (2).

house program that parallelizes the NEGF equations in the energy space, and the parallelization approach is based on the message passing interface. Once computed from quantum transport equations, the electron density is fed back to Poisson’s equation to obtain the new electrostatic potential profile. This part is handled by the COMSOL Multiphysics software, which uses a finite-element method with irregular mesh to solve the electrostatics equation. Since the solution of the quantum transport and the electrostatic equation usually do not spontaneously converge, one has to use proper numerical strategies such as numerical damping or nonlinear Poisson equation to achieve convergence. The latter is used in our simulations. III. L OW-T EMPERATURE C HARACTERISTICS In this section, we will approach the low-temperature electrical characteristics of silicon nanowire transistors from a theoretical point of view. The theory of quantum transport in 1-D devices at low temperatures is reviewed in detail in [12], [15], and [17]. For the clarity of the subject in the following sections, we will briefly overview the band structure of a 1-D nanowire. In a nanowire structure, electrons are able to freely move in the direction of transport, while they are confined in the plane perpendicular to the transport direction. One can obtain the band structure of a 1-D nanowire by solving the Schrödinger equation by applying the method of separation of variables. Analytical derivation of energy levels for low-dimensional systems can be found in textbooks [18]. Doing so, the permitted energy levels for the electrons in a 1-D semiconductor can be written as 2 2 k 2m∗x x 2 2 ny nz π 2 2 = + 2 m∗y Ly m∗z Lz

E(k) = Eyz + Ex = Eyz + Eyz

(3) (4)

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Fig. 2. Band structure of the 1-D nanowire. For low VDS values, the energy range for current flow is constant, but ID increases in steps because the number of conducting channels increases with VGS . For high VDS values, the energy range for current flow again increases with VGS , but ID further increases because the number and portion of current-carrying modes also increases.

where E(k) gives the dispersion relationship of 1-D energy subbands, and Eyz is the minimum energy of a subband, resulting from the confinement in two directions. Fig. 2 shows the band structure of a typical 1-D structure. The energy versus k in each subband is plotted by adding the continuous Ex (kx ) values in the transport direction to the subband minima Eyz (3). Setting ny and nz equal to one, Eyz in (4) yields E(0), the bottom energy of the first subband in the silicon nanowire. As the gate voltage is increased, band bending pushes subbands down toward the Fermi level. As a result, the electron concentration increases, and more current flows through the device. At a finite temperature and voltage, the magnitude of the current is modulated by the Fermi window, which is defined as the difference between the Fermi function of the source and that of the drain, i.e., fS − fD . At a sufficiently low temperature and low VDS , the energy range for current transmission is small. Nevertheless, each time a subband passes the Fermi level, a corresponding jump can be observed in the current. After the subband minimum has passed the Fermi level, the current saturates to the value allowed by the occupied subbands. Any increase in the temperature or drain voltage always increases the current because the width of the Fermi function spreads out and a larger number of subbands contribute to the current flow. The transmission coefficient determines the participation of each subband in the current flow with respect to the applied gate potential. Every time a permitted subband with higher energy is available, a “jump” in the transmission curve is observed [11]. The positions of these jumps in the transmission curve are at the minimum energy of each subband. The total transmission coefficient is given by T (E) = T r [ΓL (E)Gr (E)ΓR (E)Ga (E)] .

(5)

Here, T r denotes the trace of a matrix, and Γ is the broadening function that determines the electron exchange rate between contacts and the device region. We should also note that, in a structure such as a nanowire in ballistic operation (i.e., in the absence of scattering), the ΓL and ΓR are nonzero only at the first and last sections of the device (i.e., at the source and drain). Fig. 3 shows the total transmission coefficient versus energy for a silicon nanowire with a 3 nm × 3 nm cross section with a 110 channel direction for different gate potential values. It can

Fig. 3. Total transmission coefficient versus energy for nanowire SOI FETs with trigate geometry at T = 77 K and VDS = 0.15 for different values of VGS . The Fermi level is set at Ef = 0. Each step in the figure corresponds to the bottom of a subband. It is clear that, as we increase the gate potential, the subbands are pushed from higher energy values to lower energy values toward the Fermi level and eventually cross the Fermi level. The energy spacing between the two lowest subbands is roughly 90 meV.

clearly be seen that the spacing between the first two steps in the transmission is approximately 90 meV, which corresponds to the energy spacing between the first and second subbands. This value is in agreement with the subband separation obtained by sp3 d5 tight binding calculation, as reported in [3] and [12]. In our simulations, the Fermi level is fixed at source contact. As the gate potential is increased, the transmission curve moves toward the Fermi level, which increases the current. Applying the Landauer formula, we can write an expression for the current based on the transmission and the Fermi distribution of electrons in the source and drain [13], [19], i.e., I(T, E, Ef ) =

q h

T (E, VDS )

× [fs (E − Ef S ) − fD (E − Ef D − VDS )] dE

(6)

where T is the total transmission coefficient, and fS (fD ) is the Fermi function at the source (drain). This equation states that the current flowing from the source to the drain is a function of the bias-dependent transmission and the difference of the Fermi functions between source and drain contacts for a given temperature and bias. According to (3), the subband separation is involved in the expression of the drain current via the transmission and Fermi functions. However, it is clear that, at a constant temperature, the currents carried by the different subbands can no longer be distinguished if VDS is increased above a certain level. When VDS is large enough, the width of fS − fD (i.e., the flux of injected electrons) increases, and electrons simultaneously travel from the source to the drain through several subbands. The resulting drain current is the mixture of currents due to different subbands involved in transport. In order to get a better understanding of the different terms in the Landauer formula, one can decompose the above equation into


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a product of terms that are a function of temperature or VDS only. By doing so, we obtain the following relationship: q df (E, T ) I(T, E, VDS ) = T (E, VDS ) ⊗ W (E, VDS ) ⊗ h dE (7a) =

qVDS T (E, VDS ) h

(7b)

where W is the finite voltage window defined as W (E) = Θ(E + VDS ) − Θ(E), the symbol ⊗ represents the convolution over energy, and Θ is the step function. The right-hand term of (7a) shows the energy averaging due to both the finite voltage and finite temperatures that intervene in the thermal broadening function. The detailed derivation of this decomposition can be found in [19]. If qVDS and kB T are small compared to the subband energy spacing, we can ignore the last term in the above equation and rewrite ID (VDS ) as follows: IDS

2q 2 VDS =M h

(8)

where M is the number of subbands that contribute to the current. This expression is consistent with a linear response to VDS for a fixed number of modes, and it implies that, for a given VDS , the drain current exhibits jumps as VGS allows more subbands to contribute. It is useful to define other device characteristics that will help us to identify the effect of subband separation more clearly. The transconductance is the variation of drain current with gate potential [19], i.e., d IDS (9) gm = d VGS VDS =cte.

Performing differentiation of the drain current with respect to VGS , allows one to magnify the oscillations due to subbands. As we stated before, T (E) reflects the energy distribution of subbands. As we increase VGS , the subbands are pushed down toward the Fermi level, and each time one subband crosses the Fermi level, an increase in drain current occurs, and hence, there appears an associated peak in transconductance. This can clearly be observed at low VDS values. The behavior of the transconductance completely changes at higher VDS values. If q × VDS is larger than the subband energy spacing, the Fermi window fS − fD becomes so wide that many subbands are occupied and contribute to the current together. As a result, their different contributions to the overall current cannot be distinguished any longer. IV. R ESULTS AND D ISCUSSION Up to now, we have discussed the theory of quantum transport in 1-D nanowires and reviewed the reported experimental results obtained at a low temperature and near room temperature for multigate nanowire transistors. Next, we will show that these observations and the relation between current oscillation and subband separation can be verified by 3-D numerical sim-

Fig. 4. Schematic of a trigate nanowire FET used in this paper. The red and blue areas are the oxide and silicon regions, respectively.

ulations. The structure of the simulated nanowire transistor is shown in Fig. 4. The device is the trigate FET with a cross section of 3 nm × 3 nm, a channel length of 10 nm, and a 5 nm-long source/drain extension. The gate oxide thickness is 1 nm, and the buried oxide is 5 nm thick. The device has an undoped channel with abrupt junction to heavily n-doped source/drain contacts. The back-gate bias is set to zero. For the gate contact, we have used Dirichlet boundary conditions equal to Θ = VGS , whereas we have used a Neumann boundary condition for all other boundaries. The channel is oriented along the 110 crystallographic direction. The values of the effective masses have been adopted from [20], where degeneracy for each valley has also been assumed. The validity of the effective mass approach for these device dimensions has been verified by different authors [20], [21]. The subband separation energy can be obtained from the transmission curve. As we can see in Fig. 3, the distance between two peaks is about 90 meV, and the transmission curve is shifted toward the Fermi level (left hand) as we increase the gate potential. In order to distinguish the current from individual subbands, the width of the Fermi window must not be significantly larger than 90 meV (i.e., must not be significantly larger than the energy between different subbands). The thermal energy is equal to 6.6 and 25.9 meV at 77 and 300 K, respectively. As a result, oscillations of the drain current due to the population of different subbands should be clearly visible at 77 K and progressively disappear as the temperature is increased. In addition, for these oscillations to be observed, the drain voltage, expressed in millivolts, must not be larger than the subband separation, expressed in millivolts, which is 90 meV. Thus, low-temperature current oscillations should be visible for VDS values lower than 90 mV but not for values larger than 100 mV. This tight relation between VDS and the temperature has previously been mentioned in (6) and (7). We should also mention that the subband separation changes as we increase the gate potential, and the value that we predict here corresponds to the largest subband separation.

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Fig. 5. (a) Numerical results for the ID –VGS characteristic at a low drain source potential of VDS = 15 mV. Clearly, at low temperatures, the width of the Fermi window is smaller than the subband energy spacing, so when each subband crosses the Fermi level, the current exhibits jumps. (b) Transconductance versus gate potential shows peaks at subband locations. As the temperature is increased, oscillations are smeared due to the thermal broadening of the Fermi window.

Fig. 6. Numerical results for (a) ID –VGS and (b) gm − VGS characteristics at a low temperature of T = 77 K and various VDS values. The observed oscillations here are comparable to those of Fig. 4. However, at higher VDS values, the width of the Fermi window increases, and the oscillations gradually disappear.

In Fig. 5, the temperature variation of the transconductance and drain current versus gate voltage is shown for a small drain voltage, i.e., VDS = 15 mV. At low temperatures, the drain current increases in steps with increasing VGS [Fig. 5(a)] as the total flux of electrons injected from the source to the drain is small, i.e., the width of the finite voltage window allows distinguishing individual subband contributions to the current according to (7a). This is also reflected in the small VDS and the low temperature oscillatory behavior of gm as the gate voltage is increased [Fig. 5(b)]. As indicated by arrows, the staircase shape of the drain current and the oscillations in transconductance gradually disappear as the temperature is increased toward room temperature due to the thermal broadening of the energy distribution of the electrons injected from the source to the drain. In Fig. 6, ID versus VGS and gm versus VGS have been plotted at liquid nitrogen temperature for various values

of VDS . At a low drain bias, distinct oscillations in the output characteristic are observed. However, at higher VDS values, the width of the finite voltage window increases, and when it becomes comparable to the subband spacing, the oscillations are suppressed. Overall, the gm (VGS ) curves in Figs. 5(b) and 6(b) clearly show that transconductance oscillations are smeared when the width of the Fermi window as determined by qVDS and kB T becomes comparable to the subband energy spacing (which is imposed by the last two terms at the right of (7a). However, we can still observe an overall oscillation of gm over a larger range of VG values due to discrete energy levels inside the device at room temperature because the finite voltage window is still small compared to the subband energy separation energy. The width of the Fermi window further increases for the larger values of VDS , which are comparable to the subband spacing so that no oscillations can be observed in the ID versus VGS and gm versus VGS curves, as shown


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Fig. 8. Electron concentration profile at (top) VGS = 0.3 V and (bottom) VGS = 0.6 V, which shows that when we have high current in the channel, the electrons are squeezed near the source/drain junction.

A detailed comparison with experiment data could be difficult due to the complex band structure and the existence of surface roughness scattering, nonuniformities along the channel, and variation of other parameters. However, we will give a qualitative comparison with the most recent experimental results. Recently, an analytical relation based on the top of the barrier model has been proposed in order to obtain the subband energy spacing. Based on the quantum transport theory at T = 0 K and a sufficiently low VDS value, using the proposed method, the energy spacing between subbands can be written as [12], [22]

√ 2m∗ q 2 gv 2m∗ q 4 gv2 + + qαG ΔVGS (10) ΔE = − πCΣ π 2 2 CΣ2

Fig. 7. (a) ID –VGS and (b) gm − VGS characteristics at high drain–source bias, i.e., VDS = 400 mV. In this limit, the width of the finite voltage window is much larger than the subband spacing so that there is no oscillation effect in either low- or high-temperature curves.

in Fig. 7. Finally, Fig. 8 shows the electron concentration profile in the middle of the channel for VGS = 0.3 V and VGS = 0.6 V, which implies that the electrons are squeezed near the source-and-drain junction when we have a peak in the gm (VGS ) curve.

where gv and m∗ are the valley degeneracy factor and the effective mass in the transport direction for the first subband, and αG is defined as the ratio of CG /CΣ , where CG is the gate capacitance, and CΣ is the sum of the gate, source, and drain capacitances. Finally, ΔVGS is the gate voltage spacing between the first two maxima in the transconductance curve. In order to perform a first-order comparison, we have used the same physical parameters as in [12]. Our numerical simulation shows that, for the given parameters, the energy spacing between subbands is approximately 90 meV, which is close to the value predicted by (10). From the experiment in [9], the oscillation can be observed up to 200 K for a low VDS value as we change the temperature and up to VDS = 0.9 V for T = 77 K as we change the drain bias, which is in broad agreement with our simulation [7], [23]. Furthermore, the distance between peaks in Fig. 6(b) at low temperatures is equal to ΔVGS = 0.5 V, which is close to value predicted in [3]. VI. C ONCLUSION

V. C OMPARISON W ITH P UBLISHED DATA In order to verify and discuss our results in more detail, we have compared our numerically obtained subband energy separation values, ΔVGS , and low-temperature output characteristics with recent analytical and experimental studies. There are some recent publications reporting low-temperature electrical characteristics of nanowire transistors [1]–[5]. Most of these results were obtained on nanowires with relatively large cross sections (T si > 5 nm).

We have used a 3-D device simulator to numerically study low-temperature quantum transport in nanowire silicon transistor. We have used the transmission curve and the ID (VGS ) and gm (VGS ) curves to study temperature and drain voltage effects. We have found that, at a low bias and a low temperature, the ID (VGS )S curve shows staircase-like current increases, and the gm (VGS ) curve exhibits oscillations. The positions of these peaks in the gm − VGS characteristic are associated with the energy spacing of different subbands in the nanowire structure. The energy spacing is simply the distance between steps in the

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transmission curve. As VDS is increased to values above the subband energy spacing, the steps in ID (VGS ) and oscillations in gm (VGS ) disappear. The same trend (disappearing of steps and oscillations) also occurs if the temperature is increased such that the thermal broadening becomes on the order of the subband spacing. We have also compared our results with recent experimental and theoretical studies. We have found out that the energy spacing and the distance between peaks in the ID –VGS curve match the experimental reports. These results suggest that the low-temperature characteristics could be used to study subbands in nanowire transistors.

R EFERENCES [1] X. Baie, J. P. Colinge, V. Bayot, and E. Grivei, “Quantum-wire effects in thin and narrow SOI MOSFETs,” in Proc. IEEE Int. SOI Conf., 1995, pp. 66–67. [2] S. C. Rustagi, N. Singh, Y. F. Lim, G. Zhang, S. Wang, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “Low-temperature transport characteristics and quantum-confinement effects in gate-all-around Si-nanowire N-MOSFET,” IEEE Electron Device Lett., vol. 28, no. 10, pp. 909–912, Oct. 2007. [3] K. H. Cho, S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo, D.-W. Kim, S. W. Hwang, D. Park, and B.-I. Ryu, “Observation of single electron tunneling and ballistic transport in twin silicon nanowire MOSFETs (TSNWFETs) fabricated by top-down CMOS process,” in IEDM Tech. Dig., 2006, pp. 290–293. [4] J. R. Colinge, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schrufer, K. Matthews, and P. Patruno, “Room-temperature low-dimensional effects in Pi-gate SOI MOSFETs,” IEEE Electron Device Lett., vol. 27, no. 9, pp. 775–777, Sep. 2006. [5] J. P. Colinge, X. Baie, V. Bayot, and E. Grivei, “A silicon-on-insulator quantum wire,” Solid State Electron., vol. 39, no. 1, pp. 49–51, Jan. 1996. [6] M. Kobayashi and T. Hiramoto, “Experimental study on quantum structure of silicon nano wire and its impact on nano wire MOSFET and singleelectron transistor,” in IEDM Tech. Dig., 2006, vol. 1/2, pp. 855–857. [7] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channelorientation and low temperature on device performance,” in IEDM Tech. Dig., 2006, pp. 294–297. [8] K. Natori, Y. Kimura, and T. Shimizu, “Characteristics of a carbon nanotube field-effect transistor analyzed as a ballistic nanowire field-effect transistor,” J. Appl. Phys., vol. 97, no. 3, p. 034 306, Feb. 2005. [9] J. C. Charlier and J. P. Issi, “Electronic structure and quantum transport in carbon nanotubes,” Appl. Phys. A, Mater. Sci. Process., vol. 67, no. 1, pp. 79–87, Jul. 1998. [10] J. P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, “Low-temperature electron mobility in trigate SOI MOSFETs,” IEEE Electron Device Lett., vol. 27, no. 2, pp. 120–122, Feb. 2006. [11] M. Je, S. Han, I. Kim, and H. Shin, “A silicon quantum wire transistor with one-dimensional subband effects,” Solid State Electron., vol. 44, no. 12, pp. 2207–2212, Dec. 2000. [12] R. Kim and M. S. Lundstrom, “Characteristic features of 1-D ballistic transport in nanowire MOSFETs,” IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 787–794, Nov. 2008. [13] M. P. Anantram, A. Svizhenko, and A. Martinez, “Two-dimensional quantum mechanical modeling of nanotransistors,” J. Appl. Phys., vol. 91, no. 4, p. 2343, 2002. [14] A. Schenk and W. Fichtner, “Quantum transport in two- and threedimensional nanoscale transistors: Coupled mode effects in the nonequilibrium Green’s function formalism,” J. Appl. Phys., vol. 100, no. 4, pp. 043 713-1–043 713-12, Aug. 2006. [15] J. Wang, E. Polizzi, and M. Lundstrom, “A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation,” J. Appl. Phys., vol. 96, no. 4, pp. 2192–2203, Aug. 2004. [16] D. Mamaluy, M. Sabathil, and P. Vogl, “Efficient method for the calculation of ballistic quantum transport,” J. Appl. Phys., vol. 93, no. 8, pp. 4628–4633, Apr. 2003.

[17] A. Martinez, M. Bescond, J. R. Barker et al., “A self-consistent full 3-D real-space NEGF simulator for studying nonperturbative effects in nanoMOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2213–2222, Sep. 2007. [18] C. A. C. J. P. Colinge, Physics of Semiconductor Devices. New York: Springer-Verlag, 2005. [19] P. F. Bagwell and T. P. Orlando, “Landauer conductance formula and its generalization to finite voltages,” Phys. Rev. B, Condens. Matter, vol. 40, no. 3, pp. 1456–1464, Jul. 1989. [20] J. Wang, A. Rahman, A. Ghosh, and M. Lundstrom, “On the validity of the parabolic effective-mass approximation for the I–V calculation of silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1589–1595, Jul. 2005. [21] M. Bescond, N. Cavassilas, and M. Lannoo, “Effective-mass approach for n-type semiconductor nanowire MOSFETs arbitrarily oriented,” Nanotechnology, vol. 18, no. 25, p. 255 201, 2007. [22] A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, “Theory of ballistic nanotransistors,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1853– 1864, Sep. 2003. [23] S. F. Hu, Y. C. Wu, C. L. Sung, C.-Y. Chang, and T.-Y. Huang, “A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire,” IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 93–97, Mar. 2004.

Nima Dehdashti Akhavan received the B.S. degree in electronic engineering and the M.S. degree in electronic engineering from Semnan University, Semnan, Iran, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree on device physics and quantum modeling of multigate SOI MOSFETs with the Tyndall National Institute, University College Cork, Cork, Ireland.

Aryan Afzalian (S’03–M’05) was born in Ottignies, Belgium, in 1977. He received the Electromechanical Engineer and Ph.D. degrees from the Université Catholique de Louvain, Louvain-la-Neuve, Belgium, in 2000 and 2006, respectively. He is currently a Postdoctoral Research Fellow with the Tyndall National Institute, University College Cork, Cork, Ireland, working on semiconductor physics and, in particular, on modeling quantum transport in nanoscale silicon devices such as SOI multigate nanowire transistors. His previous works include modeling, optimization, and characterization of SOI integrated optical sensors and analog circuits such as APS, optical communication receivers, and UV detectors, with an emphasis on physical modeling and the multidisciplinary approach. Dr. Afzalian is the recipient of the 2001 AILV price for his M.S. thesis work on SOI image sensors.

Chi-Woo Lee received the B.S. degree in physics from the University of Suwon, Hwaseong, Korea, in 2004 and the M.S. degree in electronic engineering from the University of Incheon, Incheon, Korea, in 2006. He is currently working toward the Ph.D. degree on the physics of multigate SOI MOSFETs with the Tyndall National Institute, University College Cork, Cork, Ireland. From 2004 and 2006, he was a Teaching and Research Assistant with the University of Incheon.


Ran Yan received the B.S. degree in electronic science and technology from Tsinghua University, Beijing, China, in 2006. She is currently working toward the Ph.D. degree in physics of multigate SOI MOSFETs with the Tyndall National Institute, University College Cork, Cork, Ireland. She was a Research Assistant in computer-aideddesign technologies with the Research Centre of Microelectronics Institute, Tsinghua University.

Isabelle Ferain received the M.Sc. degree in electrical engineering from both the Faculté Polytechnique de Mons, Mons, Belgium, and the Ecole Supérieure d’Electricité, France, Gif-sur-Yvette, France, in 2001 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2008. In 2001, she joined AMI Semiconductor (now ON Semiconductor), Oudenaarde, Belgium, where she was involved in SPC and line yield control. From 2004 to 2008, she was with IMEC, Leuven, Belgium, where she worked on the integration and electrical characterization of metal gate electrodes on fully depleted multiple-gate FETs (MuGFETs) on silicon on insulator. She is currently a Postdoctoral Researcher with the Tyndall National Institute, University College Cork, Cork, Ireland, working on the characterization of low-temperature directly bonded substrates and the fabrication of nanowires.

Pedram Razavi received the B.S. degree in electronic engineering from the Gilan University, Rasht, Iran, in 2004 and the M.Sc. degree in electronic engineering from Semnan University, Semnan, Iran, in 2008. He is currently working toward the Ph.D. degree on modeling and simulation of ultrascaled SOI multigate transistors with the Tyndall National Institute, University College Cork, Cork, Ireland.

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Giorgos Fagas was born in Greece in 1973. He received the B.Sc. degree in physics from the University of Ioannina, Ioannina, Greece, in 1996 and the Ph.D. degree in physics, specializing on computational condensed matter, from Lancaster University, Lancaster, U.K., in 2000. He was a Guest Scientist with the Max Planck Institute for the Physics of Complex Systems, Dresden, Germany, for two years. He was an Alexander von Humboldt Fellow with the University of Regensburg, Regensburg, Germany. In 2004, he joined the Tyndall National Institute, University College Cork, Cork, Ireland, where he is currently a Staff Researcher. He has been developing simulation tools that constitute part of the Tyndall National Institute’s IP portfolio on software, particularly the Transport in MEsoscopic Systems (TIMES) package. He has more than 30 publications and edited a reference book on molecular electronics. His expertise is in transport and quantum effects in nanomaterials and lowdimensional structures.

Jean-Pierre Colinge (M’86–SM’89–F’96) received the B.S. degree in philosophy, the B.S. degree in electrical engineering, and the Ph.D. degree in applied sciences from the Université Catholique de Louvain, Louvainla-Neuve, Belgium, in 1980, 1980, and 1984, respectively. He was with the Centre National d’Etudes des Télécommunications, Meylan, France; the HewlettPackard Laboratories, Palo Alto, CA; and IMEC, Leuven, Belgium, where he was involved in SOI technology for VLSI and special device applications. From 1991 to 1997, he was a Professor with the Université Catholique de Louvain, where he led a research team in the field of SOI technology for low-power, radiation-hard, high-temperature, and RF applications and reduceddimension devices (thin double-gate and quantum-wire MOSFETs). From 1997 to 2006, he was a Professor with the University of California, Davis, where he worked on advanced multigate SOI MOS devices. He is currently a Professor with the Tyndall National Institute, University College Cork, Cork, Ireland, where he is working on the modeling, fabrication, and characterization of advanced SOI MOS devices. He is the author of more than 300 scientific papers and four books in the field of SOI and two books on semiconductor device physics. Prof. Colinge has been a member of committees of several conferences, including the International Electron Devices Meeting and the International Conference on Solid State Devices and Materials, and was the General Chairman of the IEEE SOS/SOI Technology Conference in 1988.