Sliding-Mode-Control-Based Boost Converter for High ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015

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Sliding-Mode-Control-Based Boost Converter for High-Voltage–Low-Power Applications Antonio Leon-Masich, Student Member, IEEE, Hugo Valderrama-Blavi, Member, IEEE, Josep M. Bosque-Moncusí, Student Member, IEEE, Javier Maixé-Altés, Associate Member, IEEE, and Luis Martínez-Salamero, Member, IEEE Abstract—This paper presents the analysis and design of a very high-voltage-gain single-stage boost converter operating at the boundary between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The converter is supplied by a 12-V car battery and attains 1200 V with a voltage gain of 100. The use of a hysteretic comparator in the control loop precludes the risk of modulator saturation and facilitates the operation at the mentioned boundary. Sliding-mode control theory is applied to analyze the dynamic behavior of the switching regulator and to establish the system stability conditions. The performance of the converter is investigated using silicon carbide (SiC) devices for the power switch realization. LED-based efﬁcient lighting systems can be a promising application of the proposed system. Index Terms—High-voltage gain, hysteresis modulation, LED supplies, silicon carbide (SiC) devices, sliding-mode dynamics.

I. I NTRODUCTION

C

ONVERTERS operating with high-voltage gains are widely used in many industrial applications, some examples being high-intensity discharge lamps requiring several kilovolts at their start-up [1], front-edge stage circuits for renewable energy [2], [3], cold cathode fluorescent lamps, and telecommunication applications [4]. Voltage step-up converters can be isolated and nonisolated. The isolated converters, such as flyback, push–pull, forward, or tapped boost, can provide high output voltages at the expense of efficiency degradation provoked by the losses associated with the leakage inductance, which cause high-voltage stress, large switching losses, and serious electromagnetic interference problems [5]. These converters often require active or passive snubbers for recycling or dissipate leakage energy [6]. Moreover, using a transformer, although contributes to the voltage gain, increases the cost, volume, and losses. There are many options to achieve a high-voltage gain with nonisolated topologies, most of them being derived from a single-stage boost converter. It is worthy to remark that

Manuscript received September 3, 2013; revised February 16, 2014; accepted April 12, 2014. Date of publication May 29, 2014; date of current version December 19, 2014. This work was supported by the Spanish Ministry of Science and Education under Grant CSD2009-0046 and Grant DPI2012-31580. The authors are with the Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, 43007 Tarragona, Spain (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2014.2327004

the boost converter by itself is a poor candidate for highvoltage-gain applications because many factors can degrade its efficiency limiting also the converter power rating [7] and precluding the employ of high duty ratios that can saturate the pulsewidth modulator (PWM). Among the nonisolated topologies, high-voltage gain can be achieved by connecting several step-up converters in cascade [8]. The resulting topology can supply high output voltages with relatively high efficiency and a progressive reduction of the duty ratios. The main drawbacks are the stability [9], the complexity, and the high cost caused by interconnecting different dc–dc converters in cascade, as well as the need of synchronization in all the power switches to avoid beat frequencies. Another alternative is the employ of quadratic or cubic converters that can be derived from the cascade circuits by using a single driven transistor [10] at the expense of incorporating several additional diodes. At the same time, the single active switch must be designed to block the whole output voltage in the OFF-state and the entire input current in the ON-state. In order to avoid the extreme duty cycles of the converters without magnetic isolation, another option is using switchedcapacitor converters [11], wherein it is possible to increase the gain by introducing several stages, thus reducing the duty cycle and the devices’ stress. However, the current flowing through the devices increases in the switches’ turn-on impairing the efficiency due to the conduction loss increment. In this kind of converters, increasing the output voltage requires several switching capacitor stages, which also increases the overall cost and the complexity of the converter and reduces its reliability. An extension of Luo’s converters was reported in [12] by integrating various switched inductor stages [13], thus avoiding high duty cycles. However, the gain of the converter is not higher than that of quadratic or cubic converters, but the complexity of the circuit and its cost and volume increase. Other possibilities are converters with coupled inductors, where the switching devices have to block a smaller voltage so that devices with lower ON-resistance can be used, and the problem of the reverse recovery peak in the diode can be neglected. However, the coupled inductor needs a snubber to eliminate the voltage peaks generated by the leakage inductance, and this fact tends to increase the losses, cost, and volume of the converter [14]. Some efficiency improvement of these topologies combining coupled inductors with switched capacitors is found in [15] where the efficiency increment is obtained by mixing the single-stage boost converter with transformers at the expense of increasing the complexity of the converter and its control. The goal of this paper is to demonstrate that a highvoltage gain can be achieved in a single boost stage without

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transformers and to show that the resulting converter can be competitive in the field of LED-based lighting power supplies. The proposed converter requires duty cycles near unity; hence, a PWM approach is disregarded because of the risk of saturation for duty cycles bigger than 0.7. Instead, a hysteresis modulator with a variable width is employed to regulate the converter, which operates at the boundary between continuous conduction mode (CCM) and discontinuous conduction mode (DCM) in order to minimize the power losses. The highly nonlinear behavior introduced by the hysteretic comparator is tackled by means of the sliding-mode control theory, which provides an averaged dynamic model of the converter despite the variable switching frequency produced by the comparator. A subsequent linearization of this model allows the design of an appropriate compensating network. From the technological point of view, the extreme conditions of high-voltage operation are counteracted by the use of silicon carbide (SiC) power devices, which eventually results in good global efficiency. The design of a specific driver for a normally OFF SiC JFET used in the power switch implementation is also presented. The remainder of this paper is organized as follows. A brief review of the state of the art of sliding-mode control in power converters, together with the boost converter analysis under slidingmode operation, is presented in Section II. The design of the converter with an associated driver for a normally OFF SiC JFET is given in Section III. The converter operation at the DCM– CCM boundary with high gain is discussed in Section IV. Experimental measurements in the converter supplying a LED spot and resistive loads with SiC devices are reported in Section V. Finally, conclusions are presented in Section VI.

II. S LIDING -M ODE C ONTROL Our goal is to design a single boost converter with a high dc gain (around 100) for lighting applications. For this reason, the converter will have to operate in the DCM–CCM boundary to reduce device recovery losses and improve the overall efficiency. In addition, it will employ a hysteretic modulator in the control loop to work with duty cycles near the unity without the risk of modulator saturation. Furthermore, the converter should be controlled through the inductor current since the current dynamic behavior with respect to the control variations is of minimum-phase type. When dealing with a hysteretic modulator in a feedback controlled system, there are three possible methods to tackle the analysis, i.e., describing function, Tsypkin’s method, and sliding-mode control. The first two methods are performed in the frequency domain and exhibit complementary properties. While the describing function is an analytical approach giving enough insight on the influence of the different parameters in the system self-oscillation, its prediction of limit cycles is inaccurate. On the contrary, Tsypkin’s method is an accurate numerical procedure requiring some complex computations that cannot give sufficient information on the role of the different parameters in the system performance. In a clear-cut contrast, sliding-mode control is a time-domain analytical method that provides not only a good insight but also an accurate prediction

Fig. 1. (a) Boost converter with parasitic elements. (b) ON-state. (c) OFF-state.

of the dynamical behavior of hysteresis-based feedback controlled systems such as self-oscillating power converters [17]. Power converters are variable structure systems whose associated sliding-mode control theory is the natural way to regulate them. This is due to the fact that input signals for switching devices are continuous functions of the converter state, and the resulting dynamic models are described by differential equations with discontinuous right-hand sides. In this context, sliding modes can be induced with state trajectories over the surfaces in the system state that establish the discontinuity of the right-hand sides of the differential equations [18]. Moreover, since the production of chattering is intrinsic to the nature of switching power converters, first-order sliding-mode controllers [19]–[21] are preferred to high-order sliding-mode controllers [22], which, in turn, are increasingly used in the regulation of electrical drives [23]–[25]. The circuit description of the converter is depicted in Fig. 1(a), where parasitic resistances in the reactive components, together with an ON-resistance for the transistor, and a voltage source for the diode are included in order to study the influence of the conduction losses in the converter performance. In the DCM–CCM border, the converter has two structural changes within a switching period, i.e., ON-state (see Fig. 1(b)) and OFF-state (see Fig. 1(c)), and therefore, it can be represented by means of two linear vector differential equations x(t) ˙ = A1 x(t) + B1 x(t) ˙ = A2 x(t) + B2

f or f or

u = 1 (ON−state) u = 0 (OFF−state)

(1) (2)

where x(t) is the state vector corresponding to the state variables of the power stage x(t) = [iL , vC ]T .

(3)

LEON-MASICH et al.: SLIDING-MODE BOOST CONVERTER FOR HIGH-VOLTAGE–LOW-POWER APPLICATIONS

Matrices A1 , A2 , B1 , and B2 are given, respectively, by −rL −rON V S 0 L A1 = B1 = L (4) 1 0 − (Ro +rC )C 0 r VS −vD rC 1 C ·R − LL − (Ror+r − − )L L (R +r )L C o C L B2 = A2 = . Ro 1 0 − (R +r (R +r )C )C o

C

o

C

(5) The control technique applied to the converter requires the use of a switching surface s(x) to induce sliding motions in the converter by forcing the input current to track a slow varying signal k(t) s(x) = iL − k(t)

In order to find the equilibrium point of the resulting sliding dynamics, we will decompose k(t) in two terms, namely, a positive constant K and a superposed time-varying component ˆ k(t). We will first assume a switching surface of the type S(x) = iL − K, which will result in an equilibrium point X ∗ ˆ will be of constant coordinates. The influence of the term k(t) predicted next in a closed-loop model of the converter dynamics after linearization around X ∗ by assuming that kˆ K. The resulting equivalent control for S(x) = iL − K and the corresponding ideal sliding dynamics are given by (12)–(14), respectively, as follows: ueq =

(6)

1 2

Ro K·rC ·Ro Ro +rC + vC Ro +rC + vD Ro rC ·Ro ·K Ro +rC + vC Ro +rC + vD

−VS + rL · K + −K · rON +

iL = K

t (IREF − io (λ)) · d λ = Im (t).

(7)

−∞

IREF is the output current constant reference, iO (t) is the output current, and Im (t) is the average input current. Introducing the invariance conditions [18] s(x) = 0 and ds(x)/dt = 0 in (1)–(6) yields the equivalent control ueq (t), which is bounded by both maximum and minimum values of u(t)

Therefore, the coordinates of the equilibrium point X ∗ = are given by (15) and (16). (See (16) at the bottom of the page.) IL∗ = K.

(15)

Assuming now that k(t) is time varying, the corresponding equivalent control will be given by

(8)

dk(t) k(t)·rC ·Ro Ro dt −VS +rL ·k(t)+ Ro +rC +vC Ro +rC +vD . o ·k(t) o −k(t)·rON + rCR·R +vC RoR+r +vD o +rC C

(17)

Therefore, the ideal sliding dynamics can be expressed as (18) and (19) as follows:

Moreover, a switching law of the type u(t) = 0

if

s(x) > 0

(9)

u(t) = 1

if

s(x) < 0

(10)

will induce a sliding regime on the switching surface ensuring the sliding-mode existence conditions because s(x)

(14)

[IL∗ VC∗ ]

ueq = 0 < ueq (t) < 1.

(12) (13)

Ro d vC vC = K · (1 − ueq ) − . dt C(Ro + rC ) C(Ro + rC )

where k(t) is given by k(t) =

231

ds(x) < 0. dt

iL (t) = k(t).

(18)

Linearizing (19), shown at the bottom of the page, around the equilibrium point X ∗ = [IL∗ VC∗ ] leads to the following expression: ˆ d vˆC ˆ + b · vˆC + c · d k(t) + d · VˆS = a · k(t) dt dt

(11)

(20)

VC∗

=

2 +(−6·r 2 2 2 2 4·K((−rL −rON )·K +VS )Ro3 +[(rC ON −4·rL )rC +rON )K +((2·vD +4·VS )·rC −2·vD ·rON )·K +vD ]·Ro 2·Ro 2 (−v +K ·r 2 −2·rC (−vC +K ·rON )−((rON +rC )·K +vD )·Ro +rC D ON ) + 2·Ro 1 + [((rON −rC )·K −vD )·Ro −vD ·rC +K ·rON ·rC ] (16) 2·Ro

f (x) =

Ro · k(t) − vC d vC = − dt C(Ro + rC )

−dk(t) dt

rC VS −vD k(t) + − L1 + (Ro +r v Ro · k(t) + C L C )L ·Ro rC k(t) − L1 − (Ro +r vC − vLD · C · (Ro + rC ) − (RroC+r C )L C )L

+ − rLL − rON L

rC ·Ro (Ro +rC )L

(19)

232


Fig. 4.

Fig. 2.

Boost converter with hysteretic control of the input current.

Power stage scheme.

and the characteristic equation of the system will be given by

ki · c ki · a 2 −b + =0 (27) s +s Ro Ro that will correspond to a stable system provided that the following condition is satisfied: 2 R o · VS 0 < ki < . (28) L K

Fig. 3.

Dynamic model of the switching regulator depicted in Fig. 2.

where coefficients a, b, c, and d are given by (21)–(24), respectively, for the case of no losses for the sake of simplicity

VS ∂f (x)

1 (21) a= = dk x∗ C Ro · K

∂f (x)

2 b= (22) =− dvC x∗ Ro · C

K L ∂f (x)

=− (23) c= dvy y= dK(t) ,x∗ C R o · VS dt

∂f (x)

K 1 d= = − . dVS x∗ C R o · VS

(24)

Fig. 2 illustrates the block diagram of the boost converter controlled through the switching surface S(x). It can be observed that the ideal comparator required by the sliding-mode control theory has been implemented by a hysteretic comparator based on a flip-flop that activates the switch when the inductor current is zero and turns off the MOSFET/JFET when the inductor current reaches 2Im . This is equivalent to force the average input current Im to take the appropriated value in order to fulfill the output requirements. Fig. 3 illustrates the closed-loop dynamic model of the switching regulator depicted in Fig. 2 where the expression of H(s) is derived from (20) by assuming that VˆS = 0. Hence, H(s) =

a+c·s vˆC (s) . = ˆ s−b k(s)

(25)

The system loop gain can be expressed as T (s) = H(s) ·

1 ki ki · c s + (a/c) = · · Ro s Ro s · (s − b)

(26)

Therefore, ki can be found using classical Bode techniques in (26) or by pole assignment in (27). III. C ONVERTER I MPLEMENTATION A. Power Stage Figs. 4 and 5 illustrate the circuit scheme of power stage and sliding-mode controller, respectively. With the aim of achieving a single-stage boost converter with the highest efficiency, the converter has been implemented with SiC devices. These devices are increasingly replacing Si components in the design of power converters due to their advantageous thermal and electrical characteristics, which make them capable to work at higher voltages and frequencies with lower losses than their Si counterparts [26]–[30]. In our case, the power diode is a SiC Schottky noncommercial device that has been specifically fabricated for our application by the National Center for Research in microelectronics under the series name ALS11. The power transistor is the normally OFF JFET SJEP12R063 that has required the design of a specific driver as it is described below in this section. The input series inductor of 70 μH has been realized with 11 wires of 0.07 mm2 by making 37 turns around the Kool Mμ 773244-A7 core, which has a relative permeability value of 90. It has to be pointed out that the use of 11 wires instead of 1 intends to reduce the skin effect when the switching frequency of the converter increases beyond 40 kHz. The output capacitor is of ceramic type with a capacity of 8 μF and an equivalent series resistance of 8 mΩ and a breaking voltage of 1.3 kV. The input current sensor is made of a surface mount device resistance of 100 mΩ and 5 W, whereas the output current sensor is an E24 resistor of 10 Ω and 0.25 W. Signals −Ie and Iout are proportional to inductor current iL and output current io , respectively.


Fig. 5.

233

Control implementation schematic circuit.

B. Control Stage Fig. 5 shows the two main blocks of the sliding-mode controller, namely, integrator of the output current error and hysteretic comparator. The integrator has been implemented with a circuit based on LF347 operational amplifier, whereas the hysteretic circuit employs two LM319 comparators with a response time of 80 ns, and a JKMC14027 flip-flop with a bandwidth of 13 MHz. The inputs of the hysteretic comparator are k(t) and Ie , which are respectively given by the output of the integrator and the output of an inverting amplifier based on LF347. The output of the hysteretic comparator is a digital signal Q that activates the driver to turn on or turn off the power transistor. The transistor turn-on corresponds to the high level of Q, which is the result of a zero input current, whereas the turn-off is produced by the low level of Q, which is obtained when k(t) is bigger than 2Im . C. Driver Implementation The driving circuit of the normally OFF JFET has to provide a negative voltage to turn off the JFET and a positive voltage to turn it on. Although normally ON JFET SiC devices and drivers are quite common, normally OFF JFETs and MOSFETs are less available. The ON JFET is a majority carrier device that typically has normally ON characteristics requiring a negative bias applied to the gate pinchoff channel, the pinchoff voltage level being determined by the design of the channel [31]. The OFF JFET has complementary characteristics, which implies that different drivers for each type of SiC JFET are needed. In Fig. 6, the basic circuit differences between normally OFF and normally ON JFET drivers are shown. The resulting driver prototype employed in our case for the SJEP12R063 normally OFF JFET is depicted in Fig. 7. The driver is composed by a simple push–pull output driver, a series gate resistance RS and a parallel connection of a capacitor C, diode D1 and resistance RP , and a diode D2 . The output of the parallel combination is directly connected to the JFET. The resulting driver prototype is illustrated in Fig. 8. It has to be pointed out that signal Q in Fig. 7 is the output of the

Fig. 6.

Typical JFET driver. (a) n-on. (b) n-off.

Fig. 7.

Implementation of the driver prototype circuit.

Fig. 8.

Driver prototype.

hysteretic comparator previously described. It can be observed that the driver is realized by two bipolar transistors, i.e., an n-p-n transistor (ZTX 653) with a Vbr of 100 V and a collector current of 2 A and a p-n-p transistor (ZTX 753) with a Vbr of 100 V and a collector current of −2 A.

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The RS resistor has been realized by means six E24 resistors of 6.8 Ω in parallel, whereas the RP resistor has been implemented by four E24 resistors of 640 Ω. Diodes D1 and D2 are of Schottky type (SD103-A) of 40 V and 15 A. Finally, capacitor C has been implemented by a ceramic capacitor of 470 nF and 16 V. IV. C ONVERTER O PERATION A. DCM–CCM Boundary Operation Switching losses can be minimized if the turn-off of the bipolar diode occurs at zero current, which imposes DCM operation. However, preserving in DCM the value of the CCM input average current to satisfy the load requirements requires current peaks much higher, thus increasing the RMS value of the current in all devices, and therefore, the conduction losses of the transistor and diode. The deeper the DCM operation is, the higher the current stress is and therefore the higher the conduction losses are. Consequently, the DCM–CCM boundary appears as the working zone that combines the lowest conduction losses with minimum switching losses by keeping the diode turned off at zero current. To calculate the averaged input current Im , the only data required is the switching period TS because assuming a high duty cycle D, such that 0.99 < D < 1, at the DCM–CCM boundary, we obtain Im ≈

VS VS · D · TS ≈ · TS 2·L 2·L

(29)

Im =

Po η · VS2 · TS ⇒ Po = η · VS 2·L

(30)

where Po is the output power, and η is the converter efficiency. Neglecting the efficiency η effect, the input current Im and the output power PO are both proportional to the switching period TS and can be controlled by adjusting the value of TS . It can be observed that, for a constant value of the switching period, the converter behaves like a loss-free resistor [32] because the input current Im is also proportional to the supply voltage VS . B. High-Gain Analysis Disregarding the voltage drop of the diode vd , because this device is only conducting in a negligible OFF interval, the following dc gain is obtained: Vo = VS Ro (1 − D)2 +

Ro (1 − D) D(1−D)·Ro ·rC + rON_EFF Ro +rC

rON_EFF = rON + RSENSE1 .

dMAX =

+ rL

(31) (32)

Fig. 9.

DC gain of the boost converter for different output loads. TABLE I P OWER S WITCHES

Fig. 9 shows the graphical representation of the dc gain as a function of the duty cycle taking values between 0.980 and 1 for different resistive output loads. The rON value of the JFET has been obtained from the corresponding data sheet. It can be observed that the ideal gain 1/(1 − D) constitutes the upper bound of the family of curves representing (31). It can be observed in Fig. 9 that the dc gain increases with the value of the resistive load, and it can be deduced that the maximum gain corresponds to the maximum value of the duty cycle given by (33), shown at the bottom of the page. From (31) and (33), it can be concluded that very high values of dc gain require extreme values of the duty cycle in the region 0.93 < D < 0.9925. These values can be supplied by the hysteresis comparator without a risk of modulator saturation. V. E XPERIMENTAL R ESULTS Table I shows the characteristics of the semiconductor devices described in Section III in terms of blocking voltage for both the transistor and diode. As regards the power transistor, the values of ON-resistance, threshold voltage Vth , gate voltage Vg , gate charge Qg , and gate current Ig are also depicted. Information about forward current, on voltage drop, and total capacitance charge QC of the diode is also given. The experimental prototype has been supplied with three different voltages (i.e., 9, 12, and 14 V), and for each input voltage, different loads have been tested (i.e., 10, 20, 30, 40, 50, and 60 kΩ). The measured parasitic resistances are rL , namely, 140 mΩ < rL < 155 mΩ for a range of switching frequency between 20 and 40 kHz, and rC = 8 mΩ. Control parameter ki is 102.

√ Ro2 +2 · Ro · rC − 2 · (Ro +2 · rC ) · Ro · 12 · rL + 12 · rON_EFF +rC · Ro + 12 · rC · (rL +rON_EFF ) Ro · (Ro +2 · rC )

(33)


235

Fig. 12.

LED-based spotlight and boost converter with SiC devices.

Fig. 13.

Converter waveforms for a 320-LED load.

Fig. 10. Efficiency (continuous line) and switching frequency (discontinuous line).

Fig. 11.

Converter waveforms for a resistive load of 60 kΩ.

A. SiC Diode and SiC JFET The efficiency curves and the resulting switching frequency are depicted in Fig. 10. It can be observed that, as the output voltage increases, the switching frequency decreases. In addition, it has to be pointed out that below 1000 V in the output voltage, the dominant losses are of switching type, the conduction losses being preponderant beyond the mentioned value. Therefore, the converter exhibits a higher efficiency value for the lowest input voltage in all the output voltage range up to 1000 V. As illustrated in Fig. 11, the output voltage reaches 1.2 kVdc (CH.3) from a 12-Vdc (CH.1) input supply in the case of a resistive load of 60 kΩ. The input current (CH.2) exhibits a switching frequency of 23 kHz in the DCM–CCM boundary. The average value of the current flowing through the output load (CH.4) is 20 mA approximately. The SiC-based converter has been also loaded with a LED spot consisting of 320 LEDs connected in series as it is illustrated in the picture shown in Fig. 12. The corresponding

steady-state results are illustrated in Fig. 13, where it can be seen that the output voltage reaches 956 V (CH.3) for an input voltage of 12 V (CH.1). This voltage corresponds to the voltage drop produced by the circulation of an output current of 21.6 mA (CH.4) through the 320 LEDs. B. Driver’s Results Figs. 14–16 corroborate the correct behavior of the driver designed in Section IV by showing the turn-on and turn-off of the normally OFF JFET. Fig. 14 shows the OFF-state of the JFET with an IGS = 0. Next, the JFET is first activated with a gate current peak of 600 mA; hence, IGS reaches its final value of approximately 10 mA after a short transient. Hence, according to the data sheet, the estimated value of rON is 60 mΩ. The value of the current peak (600 mA) can be observed in detail in Fig. 15. Finally, the turn-off transient is illustrated in Fig. 16. It is shown in the three figures that the gate 1voltage is 3.3 V in the ON-state and −15 V in the OFF-state. VI. C ONCLUSION The design of a very high-voltage-gain single-stage boost converter has been investigated. A voltage gain around 100 has been obtained with duty cycles near 1 without risk of saturation

236


The system operates at the boundary of CCM and DCM to make compatible a high output load and a high duty cycle operation with minimum losses. The experimental results are in good agreement with the theoretical predictions and show the expected variation of the switching frequency with the coordinates of the equilibrium point. The performance of the converter supplying a LED-based spotlight has been also studied and shows promising results for future lighting applications. The converter has been implemented by means of a normally OFF JFET and a Schottky diode, which has been specifically fabricated for the application. The use of SiC devices has allowed to yield 1200 V with a dc gain of 100 and an efficiency value of 83% operating at 24 kHz. R EFERENCES Fig. 14.

Start-up transient of SiC JFET device.

Fig. 15.

Peak current in the start-up transient of SiC JFET.

Fig. 16.

Turn-off transient of SiC JFET device.

due to the use of a hysteretic modulator. The converter has been controlled through the inductor current whose reference is given by the integral of the output current error. The dynamic behavior of the system has been studied by means of the slidingmode control theory to establish the stability conditions.

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Antonio Leon-Masich (S’11) was born in Lleida, Spain, in 1986. He received the B.S. and M.S. degrees in electronics engineering in 2009 and 2011, respectively, from the Universitat Rovira i Virgili, Tarragona, Spain, where he is currently working toward the Ph.D. degree. Since 2009, he has been a member of the Automatic Control and Industrial Electronics Research Group (GAEI), Universitat Rovira i Virgili. His research interests are high-gain and highvoltage converters for electronic ballasts using silicon carbide devices.

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Hugo Valderrama-Blavi (S’98–M’01) received the Ingeniero and Ph.D. degrees from the Universitat Politècnica de Catalunya, Barcelona, Spain, in 1995 and 2001, respectively. He is currently an Associate Professor with the Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, Tarragona, Spain. During the academic year 2001–2002, he was a Visiting Scholar with the Laboratoire d’Analyse et d’Architecture des Systémes, Centre National de la Recherche Scientifique, Toulouse, France. His current research interests are power electronics, renewable energy sources, silicon carbide devices, and nonlinear control.

Josep M. Bosque-Moncusí (S’10) received the Enginyer Tècnic Industrial en Electrònica Industrial degree and the Enginyer en Electrònica Master’s degree in 2005 and 2009, respectively, from the Universitat Rovira i Virgili (URV), Tarragona, Spain, where he is currently working toward the Ph.D. degree. Since 2004, he has been a Research Technician with the Automatic Control and Industrial Electronics Research Group (GAEI), URV. His research interests are power electronics and renewable energy.

Javier Maixé-Altés (S’93–A’00) received the Ingeniero de Telecomunicación and Ph.D. degrees from the Universitat Politècnica de Catalunya, Barcelona, Spain, in 1979 and 2000, respectively. From 1981 to 1992, he was an Assistant Professor with the Escuela Universitaria de Ingeniería Técnica de Tarragona, Tarragona, Spain. Since 1992, he has been with the Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Escuela Técnica Superior de Ingeniería, Universitat Rovira i Virgili, Tarragona, Spain, where he is currently an Associate Professor. His research interests are in the field of power electronics for automotive applications, resonant converters, and electrical drives.

Luis Martínez-Salamero (M’85) received the Ingeniero de Telecomunicación and Doctorate degrees from the Universitat Politècnica de Catalunya, Barcelona, Spain, in 1978 and 1984, respectively. From 1978 to 1992, he taught courses on circuit theory, analog electronics, and power processing at the Escuela Técnica Superior de Ingeniería de Telecomunicación de Barcelona, Barcelona. During the academic year 1992–1993, he was a Visiting Professor with the Center for Solid-State Power Conditioning and Control, Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA. He is currently a Full Professor with the Universitat Rovira i Virgili, Tarragona, Spain. During the academic years 2003–2004 and 2010–2011, he was a Visiting Scholar with the Laboratoire d’Analyse et d’Architecture des Systémes, National Centre for Scientific Research (LAAS-CNRS), Toulouse, France. Prof. Martínez-Salamero was the President of the IEEE Spanish Joint Chapter of the IEEE Power Electronics and IEEE Industrial Electronics Societies in 2005–2008. He was a Distinguished Lecturer of the IEEE Circuits and Systems Society in 2001–2002.