Soft switching DC/DC converter with five resonant tanks ... - IEEE Xplore

IET Power Electronics Research Article

Soft switching DC/DC converter with five resonant tanks for medium voltage applications

ISSN 1755-4535 Received on 28th November 2014 Revised on 27th March 2015 Accepted on 8th April 2015 doi: 10.1049/iet-pel.2014.0920 www.ietdl.org

Bor-Ren Lin ✉, Kuan-Hao Chen Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan ✉ E-mail: [email protected]

Abstract: A zero-voltage switching (ZVS) converter with five resonant circuits with shared switches is presented to achieve the functions of less switch counts, low switching losses and low current stress of passive components at low-voltage side. For medium input voltage case, four split capacitors and four active switches with Vin/2 voltage stress are adopted at highvoltage side. Two balance capacitors are used to automatically balance input capacitor voltages in every switching cycle. Five resonant circuits are adopted in the proposed converter to share load current and reduce the current stress of passive components. On the basis of the circuit characteristics of resonant converter, power switches are turned on at ZVS from zero to full load. Rectifier diodes can be turned off at zero-current switching if the switching frequency is less than the series resonant frequency. Hence, the reverse recovery losses on the rectifier diodes are improved. Experimental verifications with a 1.92 kW prototype are provided to demonstrate the effectiveness of the proposed converter.

1

Introduction

High-frequency link DC/DC converters based on three-level pulse-width modulation scheme have been proposed and developed in [1, 2] to reduce the voltage stress of switches at half of input voltage for industry power supply units. To eliminate the switching noise and electromagnetic interference caused by hard switching, soft switching three-level DC/DC converters have been presented in [3–5]. Thus, the switching losses of switches are reduced and the electromagnetic interference is also improved. However, there are two main drawbacks in conventional soft switching three-level converters. First, the achievement of zero-voltage switching (ZVS) of lagging-leg switches is very difficult especially at light load condition. The second disadvantage is high circulating current loss on the primary side during the freewheeling interval. To improve and extend the ZVS range of lagging-leg switches and reduce the circulating current losses, additional passive (such as inductors) or active components added on the primary or secondary side have been presented in [6–10]. Although the external inductor can extend the ZVS range of lagging-leg switches, the duty cycle losses of switches is also increased. The effective duty cycle is reduced such that the turns ratio of isolated transformer is decreased. The lower turns ratio will increase the voltage stress of rectifier diodes on the secondary side and the conduction losses of switches on the primary side. Passive components including diodes and clamped capacitor added on the secondary side can generate a positive rectified voltage during the freewheeling interval to reduce the primary side current to zero. Hence, the circulating current loss can be improved. However, the power converters with more additional power components will reduce the circuit reliability. Resonant converters [11–16] such as ‘LLC’ converters have drawn much attention because of its essential advantages of high conversion efficiency and high power density. All the possible modes of operation such as the continuous and discontinuous cases of the series resonant converter have been discussed in [15] to derive the voltage conversion ratio of series converter. To avoid the study of a very complex amount of equations and modes to derive the conversion ratio of resonant converter, frequency modulation (FM) scheme is proposed in [16] to regulate output voltage. The very simple and useful approach to a complex problem proposed by Steigerwald [16] is just an approximation and it is just a simplified model of a

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complex operation. If the switching frequency is close to the series resonant frequency, the ZVS turn-on of all switches is achieved and the circulating current on the primary side can be minimised. If the switching frequency is less than the series resonant frequency, the ZVS operation can be realised and the rectifier diodes on the secondary side are turned off under zero-current switching (ZCS). Hence, ‘LLC’ converters are better to work at series resonant frequency at normal input voltage case in order to achieve high circuit efficiency and low circulating current loss. A new parallel DC/DC converter is presented for medium-voltage and high-load current applications. The proposed converter has five resonant circuits with the shared active switches to achieve ZVS turn-on for all switches and low-circulating current losses. Five resonant converters are used in the proposed converter to increase the output power with less current rating of resonant components. Four switches connected in series are used in the proposed converter. On the basis of the proper gating signals of switches, the voltage stress of switches is reduced to half of the input voltage. The balanced capacitors are connected in series between the AC sides of two half-bridge legs in order to automatically balance input split capacitor voltages. For each resonant circuit, the variable FM is used to regulate the output voltage. Since the input impedance of each resonant circuit is an inductive load at switching frequency, switches can be turned on at ZVS. If the switching frequency is equal to the series resonant frequency, rectifier diodes can be turned off at ZCS and the circulating current loss is minimised. Thus, the switching losses and conduction losses of power switches are reduced and the reverse recovery problem of the rectifier diodes is improved. Finally, experiments are presented for a 1.92 kW prototype circuit converting 750–800 V input to an output voltage 24 V/80 A for industry power supplies or battery chargers.

2 2.1

Proposed converter and operational principle Conventional resonant circuit configurations

The conventional ‘LLC’ resonant converter with half-bridge circuit is illustrated in Fig. 1a. The series resonant tank is connected between the centre point of half-bridge circuit and ground point. Similarly, the other ‘LLC’ resonant converter is shown in Fig. 1b IET Power Electron., 2015, Vol. 8, Iss. 10, pp. 1864–1874 & The Institution of Engineering and Technology 2015

Fig. 1 Circuit configuration of LLC resonant converter a Half-bridge resonant circuit with low-voltage side connection b Half-bridge resonant circuit with high-voltage side connection c Half-bridge resonant circuit with split capacitors d Proposed half-bridge circuit with three resonant tanks

with the resonant tank connected between the centre point of half-bridge circuit and high-voltage side. Fig. 1c shows another half-bridge resonant converter with split capacitors Cr1 and Cr2. The primary current is flowing through capacitors Cr1 and Cr2. Thus, the current stress of resonant capacitors in Fig. 1c is less

than that of resonant capacitor in Figs. 1a and b. To increase the power rating at half-bridge resonant converter, the proposed converter combined above three resonant circuits with the shared switches is presented in Fig. 1d. Three resonant tanks have the same circuit characteristics to provide medium power to output

Fig. 2 Circuit configuration of the proposed converter for medium input voltage and medium output power

IET Power Electron., 2015, Vol. 8, Iss. 10, pp. 1864–1874 & The Institution of Engineering and Technology 2015

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load. Normally, a single-phase power factor corrector is adopted in the front stage to provide input voltage of the proposed converter at Vin = 380–400 V. Thus, power factor and line current harmonics at AC utility side can meet the demand of IEC61000-3-2 limit. 2.2

Proposed circuit configuration

For DC traction systems or three-phase power factor corrector converters, the input voltage of DC/DC converter can be higher than 750 V. Therefore the proposed converter in Fig. 1d should be modified to reduce the voltage stress of switches. Fig. 2 shows the circuit topology of the proposed converter for medium input voltage and high-load current applications. The circuit components at high-voltage side include input voltage Vin, four active switches S1–S4 with their body diodes and parallel capacitors Coss1–Coss4, eight resonant capacitors Cr1–Cr8, five series resonant inductors Lr1–Lr4 and five transformers. Five centre-tapped rectifiers are connected in parallel at low-voltage side. The components at low-voltage side include ten rectifier diodes D1–D10 and one output filter capacitor Co. In the proposed converter, there are five resonant circuits to share load current. Thus, the proposed converter can provide more power to output load compared with the conventional half-bridge ‘LLC’ resonant converter. The first, second and fourth resonant circuits are based on the half-bridge topology with split capacitors. The third and fifth resonant circuits are based on half-bridge topology with resonant tank connected to high-voltage side and ground point, respectively. S1 (S2) and S3 (S4) have the same gate voltage waveforms with 0.5 duty cycle. However, S1 (S3) and S2 (S4) operate complementarily with a short dead time to avoid short circuit. The components S1–S4, Cr1–Cr4 and Cr6–Cr7 establish a switched capacitor circuit [17]. Thus, the input capacitor voltages are balanced, vCr1 + vCr2 = vCr3 + vCr4 = vCr6 + vCr7 = Vin /2. FM scheme is used to generate the gating voltages of S1–S4 and to control output voltage at the desired voltage level. 2.3

Operation analysis

In the proposed converter, FM is used to control input impedance of ‘LLC’ resonant tanks. Therefore the output voltage Vo can be controlled at the desired voltage level. To simplify the circuit analysis, the following assumptions are presumed. Five transformers T1–T5 have the same magnetising inductances Lm1 = Lm2 = Lm3 = Lm4 = Lm5 = Lm and same turns ratio n = np/ns1 = np/

ns2. Power metal oxide semiconductor field effect transistors (MOSFETs) S1–S4 have the same output capacitances Coss1 = Coss2 = Coss3 = Coss4 = Coss. Average voltage across Cr1 and Cr2 is equal to Vin/2. Similarly, voltage across Cr3 and Cr4 is also equal to Vin/2. Resonant capacitances are Cr5 = Cr8 = 2Cr1 = 2Cr2 = 2Cr3 = 2Cr4 = 2Cr6 = 2Cr7 = Cr. Resonant inductances are identical Lr1 = Lr2 = Lr3 = Lr4 = Lr5 = Lr. If the switching frequency fsw is less (or greater) than the series resonant frequency fr, there are six (or four) operating modes of the proposed converter in a switching cycle. Fig. 3 shows the main voltage and current waveforms of the proposed converter under fsw < fr. Figs. 4 and 5 show the corresponding equivalent circuits for each operation mode. Before time t0, power MOSFETs S1–S4 and rectifier diodes D2, D4, D6, D8 and D10 are all off. Coss1 and Coss3 are discharged and Coss2 and Coss4 are charged. Mode 1 [t0−t1]: Coss1 and Coss3 are discharged to zero voltage at time t0. Inductor currents iLr1 − iLr5 are all negative at t0. Thus, the anti-parallel diodes of S1 and S3 are conducting at t0. S1 and S3 can be turned on at this moment under ZVS. The drain–source voltages of S2 and S4 equal vCr1 + vCr2 and vCr3 + vCr4 , respectively. The capacitor voltage vCr6 + vCr7 = vCr1 + vCr2 . On the other hand, the capacitor voltage vCr6 + vCr7 = vCr3 + vCr4 in mode 4. Therefore it can be seen that vCr1 + vCr2 = vCr3 + vCr4 = vCr6 + vCr7 = Vin /2 in steady state. In each resonant circuit, the primary side current iLr is greater than the magnetising current iLm so that the rectifier diodes D1, D3, D5, D7 and D9 are conducting. The magnetising voltages vLm1 − vLm5 are positive and the magnetising currents iLm1 − iLm5 increase in this mode. Lr1, Cr1 and Cr2 are resonants in circuit 1, Lr2, Cr3 and Cr4 are resonants in circuit 2, Lr3 and Cr5 are resonants in circuit 3, Lr4, Cr6 and Cr7 are resonants in circuit 4 and Lr5 and Cr8 are resonants in circuit 5. Energy is transferred from input voltage Vin to output load Ro in this mode. Mode 2 [t1−t2]: Mode 2 begins at time t1 when the magnetising currents are equal to the primary side currents. Hence, diodes D1– D10 are all turned off. In this mode, Lr1, Lm1, Cr1 and Cr2 are resonants in circuit 1, Lr2, Lm2, Cr3 and Cr4 are resonants in circuit 2, Lr3, Lm3 and Cr5 are resonants in circuit 3, Lr4, Lm4, Cr6 and Cr7 are resonants in circuit 4 and Lr5, Lm5 and Cr8 are resonants in circuit 5. Mode 3 [t2−t3]: Mode 3 begins at time t2 when active switches S1 and S3 are turned off. Diodes D2, D4, D6, D8 and D10 are conducting in this mode. The magnetising voltages vLm1 − vLm5 are negative and the magnetising currents iLm1 − iLm5 are decreasing. Since the

Fig. 3 Key waveforms of the proposed converter

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Fig. 4 Operation modes 1–3 of the proposed converter in a switching cycle a Mode 1 b Mode 2 c Mode 3


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Fig. 5 Operation modes 4–6 of the proposed converter in a switching cycle a Mode 4 b Mode 5 c Mode 6

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Fig. 6 Converter voltage gain G(fs) and the desired voltage gain Gd at different frequency ratios fs/fr

inductor currents iLr1 − iLr5 are all positive at t2, Coss1 and Coss3 are charged and Coss2 and Coss4 are discharged. If the energy stored in Lr1–Lr5 at t2 is greater than the energy stored in Coss1–Coss4, then Coss2 and Coss4 can be discharged to zero voltage at time t3. Mode 4 [t3−t4]: Mode 4 begins at t3 when capacitors Coss2 and Coss4 are discharged to zero voltage. Since the inductor currents iLr1 − iLr5 are all positive at t3, the anti-parallel diodes of S2 and S4 are

conducting. Thus, S2 and S4 can be turned on at this moment to realise ZVS. Since diodes D2, D4, D6, D8 and D10 are conducting so that the magnetising currents iLm1 − iLm5 decrease. The drain– source voltages of S1 and S3 equalvCr1 + vCr2 and vCr3 + vCr4 , respectively. The capacitor voltage vCr6 + vCr7 = vCr3 + vCr4 . In this mode, Lr1, Cr1 and Cr2 are resonants in circuit 1, Lr2, Cr3 and Cr4 are resonants in circuit 2, Lr3 and Cr5 are resonants in circuit 3, Lr4, Cr6 and Cr7 are resonants in circuit 4 and Lr5 and Cr8 are resonants in circuit 5. Power is transferred from input voltage Vin to output load Ro in this mode. Mode 5 [t4−t5]: Mode 4 begins at time t4 when the magnetising currents iLm1 − iLm5 are equal to the primary side currentsiLr1 − iLr5 . Diodes D1–D10 are turned off. In mode 5, Lr1, Lm1, Cr1 and Cr2 are resonants in circuit 1, Lr2, Lm2, Cr3 and Cr4 are resonants in circuit 2, Lr3, Lm3 and Cr5 are resonants in circuit 3, Lr4, Lm4, Cr6 and Cr7 are resonants in circuit 4 and Lr5, Lm5 and Cr8 are resonants in circuit 5. Mode 6 [t5−T + t0]: Mode 6 begins at time t5 when active switches S2 and S4 are turned off. Diodes D1, D3, D5, D7 and D9 are conducting so that the magnetising voltages vLm1 − vLm5 are positive and the magnetising currents iLm1 − iLm5 are increasing. Since the inductor currents iLr1 − iLr5 are all negative at t5, Coss1 and Coss3 are discharged and Coss2 and Coss4 are charged. If the energy stored in Lr1–Lr5 at t5 is greater than the energy stored in Coss1–Coss4, then Coss1 and Coss3 can be discharged to zero voltage. Then, the operating modes of the proposed converter in a switching period are completed.

Fig. 7 Measured gate voltage waveforms of S1–S4 at a Vin = 750 V and 25% load b Vin = 750 V and 100% load c Vin = 800 V and 25% load d Vin = 800 V and 100% load


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Fig. 8 Measured results of gate voltage and drain voltage of active switches a S1 and S2 at 25% load with Vin = 750 V b S1 and S2 at 25% load with Vin = 800 V c S3 and S4 at 25% load with Vin = 750 V d S3 and S4 at 25% load with Vin = 800 V

3

Converter performance analysis

The proposed converter includes five resonant circuits. Power transferred from input voltage to output load through five resonant circuits is related to the switching frequency. Each resonant circuit has the same circuit characteristics to supply one-fifth of rated power to output load. If the switching frequency is greater than the series resonant frequency, the proposed converter has four operation modes in each switching cycle. However, there are six operation modes in each switching cycle if the switching frequency is less than the series resonant frequency. To avoid the study of a very complex amount of equations and modes to derive the conversion ratio of resonant converter, FM scheme is adopted to regulate output voltage. The input voltage of the resonant circuit is a square wave voltage. If the bandwidth of the resonant circuit is much less than the switching frequency, the harmonics of the input square wave voltage can be neglected at the output of the resonant circuit. The duty ratio of S1–S4 is 0.5 so that the input voltage to the resonant circuit is a square waveform. Since five resonant circuits have the same circuit components and parameters, only resonant circuit 3 is discussed to derive the system AC voltage gain. The secondary side current io3 is a quasi-sinusoidal current. If inductor current iLr3 . iLm3 , then rectifier diode D5 is conducting and vLm3 = nVo . On the other hand, vLm3 = −nVo and

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rectifier diode D6 is conducting when iLr3 , iLm3 . The capacitor charge or discharge time in modes 3 and 6 and the time intervals in modes 2 and 5 are much less than the time intervals of series resonant circuit by Lr3 and Cr3 in modes 1 and 4. Therefore the magnetising inductor voltage vLm3 approximates a quasi-square waveform

vLm3 =

4nVo sin (2pm fs t − um ) mp m=1, 3, 5, ...

(1)

where θm is the phase angle of mth harmonic frequency. The peak fundamental magnetising inductor voltage is equal to vˆ Lm3 , f = 4nVo /(p). Since the average output value of the resonant circuit 3 is equal to one-fifth of load current, the peak value of the transformer secondary winding current is expressed as îT3, sec = pIo /10

(2)

Thus, the load resistance Ro reflected to the transformer primary side IET Power Electron., 2015, Vol. 8, Iss. 10, pp. 1864–1874 & The Institution of Engineering and Technology 2015

Fig. 9 load

Measured results of the resonant inductor currents iLr1 − iLr5 at full

a Vin = 750 V b Vin = 800 V

is given as Rac, 1 = Rac, 2 = Rac, 3 = Rac, 4 = Rac, 5 = Rac =

vˆ Lm3 , f

îT1, sec /n

=

40n2 R p2 o

(3)

The resonant circuit is excited by an effectively sinusoidal input voltage and drives the effective resistive load Rac. The input impedance Zin of the series resonant circuit is related to the switching frequency Zin ( fs ) =

Rac (j2p fs Lm ) 1 + j2p fs Lr + Rac + j2p fs Lm j2p fs Cr

(4)

FM scheme is used to control the AC voltage gain of the proposed converter. According to the different switching frequencies, the voltage gain of the resonant circuit can be derived as Rac (j2p fs Lm )/Rac + j2p fs Lm Zin ( fs ) 1 = 2 [1 + k(1 − fr2 /fs2 )] + 1/Q2 ( fs / fr − fr / fs )2

|G( fs )| =


Fig. 10 Measured capacitor voltages at full load

(5)

a vCr1 b vCr1 c vCr1 d vCr1

− vCr8 at − vCr8 at + vCr2 , + vCr2 ,

Vin = 750 V Vin = 800 V vCr3 + vCr4 and vCr6 + vCr7 at Vin = 750 V vCr3 + vCr4 and vCr6 + vCr7 at Vin = 800 V

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obtained in (9) nmin ≥

4

Vin, max 4(1 + k)(Vo + Vf )

(9)

Experimental verification

A design example and experimental verification of the proposed converter are provided in this section. A laboratory prototype with 1.92 kW rated power was constructed to demonstrate the performance and verify the effectiveness of the proposed converter. The output voltage Vo = 24 V and full load current Io, rated = 80 A. The input voltage range Vin = 750–800 V. The selected series resonant frequency fr is 100 kHz. The selected inductance ratio Lm/Lr = 1/k = 7. Step 1: Turns ratio of T1–T5: In the prototype circuit, the desired minimum voltage gain is designed to be unity at series resonant frequency. From (6), the theoretical turns ratio of T1–T5 is obtained as n=

np Gd, min Vin, max 1 × 800 = 8.06 = = 4(24 + 0.8) ns 4(Vo + Vf )

(10)

The actual primary and secondary turns used in the prototype circuit are np = 40 turns and ns = 5 turns and the actual turns ratio of T1–T5 is n = 8. Step 2: The desired voltage gain of the proposed converter: On the basis of the input and output voltage specifications, the desired minimum and maximum voltage gains of the proposed converter are

Fig. 11 Measured the output currents of five resonant circuits at full load under

Gd, min =

4(Vo + Vf )n 4 × (24 + 0.8) × 8 = 0.992 = Vin, max 800

(11)

Gd, max =

4(Vo + Vf )n 4 × (24 + 0.8) × 8 = 1.058 = Vin, min 750

(12)

a Vin = 750 V b Vin = 800 V

where k = Lr/Lm, Q = Rac / Lr /Cr , fr = 1/(2p Lr Cr ) and fs is the switching frequency. On the basis of the input and output voltage specifications, the desired voltage gain Gd of the proposed converter is given as Gd =

4n(Vo + Vf ) Vin

(6)

where Vf is the voltage drop on diodes D1–D10. If the input and output voltages are given, the operating switching frequency can be obtained by Gd = G( fs). The voltage gain of the proposed converter at no-load condition (Q = ∞) and fs = ∞ can be illustrated as |G( fs )|NL, fs =1 = 1/(1 + k)

(7)

If the desired minimum voltage gain Gd,min of the proposed converter at maximum input voltage case is greater than the voltage gain at no-load condition in (7), then the output voltage of the proposed converter can be regulated Gd, min =

4n(Vo + Vf ) 1 . Vin, max (1 + k)

(8)

On the basis of (8), the minimum turns ratio of transformers T1–T5 is

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Step 3: Q value at full load: The AC voltage gain against frequency ratio fs/fr with k = 1/7 is shown in Fig. 6. In (11) and (12), the desired minimum and maximum voltage gains are 0.992 and 1.058, respectively. In Fig. 6, the maximum Q at full load should be nmin = 7.056. Thus, the output voltage of the proposed converter at no-load condition can be regulated. Step 7: Power semiconductors: The input maximum voltage is 800 V. The voltage stress of S1–S4 is equal to Vin/2 = 400 V. Thus, MOSFETs IRFP460 with 500 V voltage rating and 20 A current rating are used for power switches S1–S4. The output voltage is 24 V and load current 80 A. The average diode current is equal to 80 A/10 = 8 A. 20CPQ150 with 150 V voltage rating and 20 A current rating are used for rectifier diodes D1–D10 in the prototype circuit. On the basis of a laboratory prototype with the circuit parameters derived in the previous section, experimental verification is provided to demonstrate the effectiveness of the proposed converter. Fig. 7 gives the test results of gate voltage waveforms of S1–S4 under different input voltage and load conditions. S1 and S3 have the same voltage waveforms and S2 and S4 have the identical voltage signals. At the same load condition such as 100% load, the switching frequency of active switches under Vin = 750 V is less than the switching frequency under Vin = 800 V. Under the same IET Power Electron., 2015, Vol. 8, Iss. 10, pp. 1864–1874 & The Institution of Engineering and Technology 2015

input voltage, the switching frequency of active switches at full load is less than the switching frequency at light load. Fig. 8 shows the measured gate voltage and drain voltage of S1–S4 at light load and different input voltages. Before switches S1–S4 are turned on, the drain voltage is decreased to zero. Thus, S1–S4 are turned on under ZVS from 25% load. The measured inductor currents iLr1 − iLr5 at full load and different input voltage conditions are illustrated in Fig. 9. Five resonant inductor currents iLr1 − iLr5 are balanced each other. The measured resonant capacitor voltages vC r1 − vCr8 at full load and different input voltage conditions are shown in Figs. 10a and b. The average capacitor voltages vC r1 − vCr8 are balanced and equal to Vin/4. Figs. 10c and d give the measured capacitor voltages of vCr1 + vCr2 , vCr3 + vC and vCr6 + vCr7 at full load and different r4 input voltages. It is clear that these three voltages are balanced, vCr1 + vCr2 = vCr3 + vCr4 = vCr6 + vCr7 . Fig. 11 gives the measured output currents io1–io5 at full load and different input voltages. It is clear that five output currents io1–io5 are balanced each other. The curves of switching frequency of the proposed converter at different loads are shown in Fig. 12a. The circuit efficiencies of the proposed converter and the conventional parallel three-level converter under the same voltage and power conditions are shown in Fig. 12b. It can be seen that the proposed converter has better circuit efficiency at light load. Conventional parallel three-level converter has low duty ratio at light load. Thus, there are high circulating losses during the freewheeling interval.

5

Conclusion

This paper presents a new ZVS converter with low-voltage stress of power MOSFETs for medium-voltage applications. Five resonant circuits with the same power switches are adopted at the primary

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side. Each resonant circuit delivers one-fifth of load power to output side such that the switch counts are reduced and the current stress of passive components and transformer windings are reduced. Two half-bridge circuit legs with four split capacitors are adopted so that the voltage stress of power MOSFETs are clamped at half of input voltage. Two capacitors Cr6 and Cr7 are adopted to balance input capacitor voltages. Compared with the conventional parallel three-level converter, the proposed converter has less power MOSFETs counts. FM scheme is adopted to derive the AC voltage conversion ratio. The main limitation of the proposed converter is too many passive components for low or medium power applications. Finally, experiments are described to verify the effectiveness of the converter.

6

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