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Jul 13, 2013 - Abstract: A new soft switching resonant converter is presented in this study to ... The resonant converter is adopted in each half-bridge circuit.
www.ietdl.org Published in IET Power Electronics Received on 14th March 2013 Revised on 13th July 2013 Accepted on 13th August 2013 doi: 10.1049/iet-pel.2013.0181

ISSN 1755-4535

Soft switching resonant converter with flying capacitor and two series half-bridge legs Bor-Ren Lin, Chih-Chieh Chen Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: A new soft switching resonant converter is presented in this study to reduce the switching losses on power metal oxide semiconductor field effect transistors (MOSFETs) and overcome the reverse recovery losses on rectifier diodes. Two half-bridge legs connected in series and two split capacitors are adopted to limit the voltage stress of each MOSFET at half-input voltage and to reduce the current rating of transformer windings and passive components at output side. A flying capacitor is connected between two half-bridge legs in order to automatically balance two input capacitor voltages. Therefore MOSFETs with low-voltage stress can be used at high-input voltage applications. The resonant converter is adopted in each half-bridge circuit to reduce the switching losses of active devices. Finally, experiments based on a laboratory prototype are provided to verify the circuit performance.

1

Introduction

High-power converters have been used for many industry applications [1–3]. For three-phase AC/DC power conversion systems, three-phase 380 V (or 480 V) AC/DC converter with power factor correction is generally used in the front stage to provide a stable DC bus voltage and a DC/DC converter is adopted in the second stage to provide low output voltage and high-load current. In the front stage, the DC bus voltage may be equal or higher than 800 V. Power switches with high-voltage stress will result in high cost and poor efficiency. Thus, it is difficult to select suitable power switches in the DC/DC converter. To use low-voltage stress power switches in high-input voltage DC converters, three-level circuit topologies [4–6] have been proposed in the second stage DC/DC converters. Based on the added neutral-point clamped diodes, the voltage stress of the power switches is clamped at half of the input voltage. However, two input split capacitor voltages may be unbalanced. A flying capacitor [3, 7] is added in the conventional three-level DC/DC converter to automatically balance two input capacitor voltages. Soft switching three-level DC/DC converters [8–14] have been presented to reduce the voltage stress of power switches at half of the input voltage and to turn on the active switches under zero voltage switching (ZVS). These control schemes are based on duty cycle control to regulate output voltage. However, the ZVS condition of the power switches is related to the load condition and input voltage. In [14], asymmetric pulse-width modulation three-level converter with four circuit modules was proposed to share the load current and reduce the current rating of passive components at the secondary side for high-load current applications. However, it is difficult to operate the soft switching turn on under a IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

wide load range. The drawbacks of the circuit topology in [14] are the unbalanced voltage stress and unbalanced average current on the rectifier diodes, too many power components in the circuit and two input capacitor voltage unbalance problems. The reverse recovery losses of the rectifier diodes at the output side are the other main drawbacks of three-level converters. Resonant converters [15–20] have been presented with the advantages of high conversion efficiency and high power density. If the operating switching frequency is less than the series resonant frequency, all the power switches can be turned on under ZVS and the diodes can be turned off under zero current switching (ZCS) under the wide ranges of input voltage and load variations. Thus, the switching losses of the active switches are improved and the reverse recovery losses of the diodes are overcome. In [21], a three-level DC/DC converter with four resonant circuits and two centre-tapped rectifiers is presented for high load current applications. The drawbacks of this circuit are too many circuit components to share the load current and input voltage balancing problem. To overcome the drawbacks in [14, 21], this paper presents a new resonant converter for high input-voltage and high-load current applications. There are two DC/DC sub-circuits connected in series at the primary side in order to share the load power and reduce the voltage stress of the active switches at half of the input voltage. To balance the two input capacitor voltages, one flying capacitor is connected between the AC terminals of the two half-bridge legs. In each circuit, a series resonant converter is adopted to turn on all the active switches at ZVS and turn off the rectifier diodes at ZCS under a wide range of load power and input voltage. Thus, the switching losses of the power semiconductors are reduced. Compared with the three-level 811

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www.ietdl.org converters in [14, 21] at the same power level, the proposed converter has less power components and the input capacitor voltage balancing problem is improved across the flying capacitor. Finally, experiments based on a laboratory prototype were provided to verify the performance of the proposed converter.

2

Circuit configuration

The circuit configuration of the proposed converter for three-phase switching mode power converter is shown in Fig. 1. The front stage of the proposed converter is a three-phase AC/DC converter with power factor correction (PFC) function to reduce line current harmonics. The second stage is a DC/DC converter with low-voltage stress metal oxide semiconductor field effect transistors (MOSFETs). The adopted DC/DC converter includes two LLC (Lm, Lr, Cr) circuits to share the load current and reduce the current rating of the passive components. The first LLC circuit consists of S1, S2, Cr1, Lr1, T1, D1, D2 and Co. The second LLC circuit includes S3, S4, Cr2, Lr2, T2, D3, D4 and Co. Co is the output capacitance. Cin1 and Cin2 form a capacitive divider to split the input voltage. Cr1 and Cr2 are the series resonant capacitances. Lr1 and Lr2 are the series resonant inductances. Lm1 and Lm2 are the magnetising inductances of the transformers T1 and T2, respectively. D1–D4 are the rectifier diodes and T1 and T2 are the isolated transformers. The primary sides of two circuits are connected in series. Thus, the voltage stress of each MOSFET is limited at Vin/2. Active switches S1 and S3 are turned on/off at the same time. In the same manner, S2 and S4 have the same pulse-width modulation (PWM) signals. To balance the two input capacitor voltages, one flying capacitor Cf is placed between terminals b and c. When the active switches S1 and S3 are turned on and S2 and S4 are turned off, the flying capacitor voltage vCf = vCin1. On the other hand, vCf = vCin2 if S2 and S4 are turned on. Since each active switch has the same duty cycle in a switching period, the flying capacitor voltage can be obtained as vCf = vCin1 = vCin2 = Vin/2. Thus, two capacitor voltages vCin1 and vCin2 are automatically balanced in a switching cycle because of the added flying capacitor Cf. The frequency modulation scheme with 0.5 duty cycle is used to control the output voltage Vo against the load current variation. If the operated switching frequency is lower than the series resonant frequency (by the series resonant inductance and series resonant capacitance), active switches S1–S4 can be turned on at ZVS and the rectifier diodes D1–D4 are turned off at ZCS. Thus, the switching losses of the active switches are reduced and the reverse recovery problem of the fast recovery diodes is improved.

Fig. 1 Circuit configuration of the proposed converter 812 & The Institution of Engineering and Technology 2014

3

Principles of operation

In this section, the circuit operations are discussed with the following assumptions to simplify the system analysis: † Transformers T1 and T2 are identical with the same turns ratio n = np/ns1 = np/ns2 and same magnetising inductances Lm1 = Lm2 = Lm. † S1–S4 have the same output capacitances CS1 = CS2 = CS3 = CS4 = CS. † Cin1 = Cin2, Cr1 = Cr2 = Cr and Lr1 = Lr2 = Lr. Fig. 2 gives the key waveforms of the proposed converter during a switching cycle. Based on the on/off states of S1– S4 and D1–D4, there are six operation modes in the proposed converter. Fig. 3 shows the corresponding equivalent circuits for these operation modes. Before time t0, all the switches are in the off state. The inductor current iLr1 is positive and iLr2 is negative. Thus, CS1 and CS3 are discharged and CS2 and CS4 are charged. Since iLr1 < iLm1 and iLr2 > iLm2, diodes D2 and D3 are conducting. Mode 1 [t0 ≤ t < t1]: At time t0, CS1 and CS3 are discharged to zero voltage and the anti-parallel diodes of S1 and S3 are conducting. Thus, S1 and S3 can be turned on under ZVS. Since iLr1 < iLm1 and iLr2 > iLm2, diodes D2 and D3 are conducting. The magnetising voltages vLm1 = −nVo and vLm2 = nVo. Therefore the magnetising current iLm1 decreases and iLm2 increases in this mode. Lr1 and Cr1 in circuit 1 are resonant with the applied voltage nVo − vCr1(t0). In the same manner, Lr2 and Cr2 in circuit 2 are resonant with the applied voltage Vin/2 − nVo − vCr2(t0). The inductor currents iLr1 and iLr2 and capacitor voltages vCr1 and vCr2 are expressed as     nVo − vCr1 t0 sin vr t − t0 iLr1 (t) = Z  r   + iLr1 t0 cos vr t − t0

(1)

Fig. 2 Key waveforms of the proposed converter IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

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Fig. 3 Operation modes of the proposed converter during one switching cycle a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6

    Vin /2 − nVo − vCr2 t0 iLr2 (t) = sin vr t − t0 Z   r   + iLr2 t0 cos vr t − t0

(2)

     vCr1 (t) = nVo − nVo − vCr1 t0 cos vr t − t0     + iLr1 t0 Zr sin vr t − t0

(3)

   vCr2 (t) = Vin /2 − nVo − Vin /2 − nVo − vCr2 t0       × cos vr t − t0 + iLr2 t0 Zr sin vr t − t0

iLr2 and capacitor voltages vCr1 and vCr2 are obtained as

(4)

  where vr = 1/ Lr Cr and Zr = Lr /Cr . The inductor current iLr1 decreases and iLr2 increases in this mode. The flying capacitor voltage vCf equals vCin1 in this mode. This mode ends at time t1 when iLm1 = iLr1 and iLm2 = iLr2. Then, the diodes D1–D4 are in the off state. Mode 2 [t1 ≤ t < t2 ]: At t1, the inductor currents are equal to the magnetising currents, that is, iLr1 = iLm1 and iLr2 = iLm2. Diodes D1–D4 are all off. S1 and S3 are still conducting. Cr1, Lr1 and Lm1 in circuit 1 and Cr2, Lr2 and Lm2 in circuit 2 are resonant. The inductor currents iLr1 and IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

      vCr1 t1 sin vp t − t1 + iLr1 t1 iLr1 (t) = − Zp   × cos vp t − t1

(5)

    Vin /2 − vCr2 t1 sin vp t − t1 iLr2 (t) = Zp     + iLr2 t1 cos vp t − t1

(6)

    vCr1 (t) = vCr1 t1 cos vp t − t1     + iLr1 t1 Zp sin vp t − t1

(7)

     vCr2 (t) = Vin /2 − Vin /2 − vCr2 t1 cos vp t − t1     + iLr2 t1 Zp sin vp t − t1 (8)         Lr + Lm /Cr . where vp = 1/ Lr + Lm Cr and Zp = 813

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www.ietdl.org Mode 3 [t2 ≤ t < t3]: S1 and S3 are turned off at time t2. The rising slope of the drain-to-source voltage of S1 is limited by CS1 and CS2. Thus, switch S1 is turned off under ZVS. In the same manner, S3 is also turned off under ZVS. Since iLr1(t2) is negative and iLr2(t2) is positive, CS1 and CS3 are charged and CS2 and CS4 are discharged in this mode. Diodes D1 and D4 are conducting in this mode so that the magnetising voltages vLm1 = nVo and vLm2 = − nVo. The magnetising current iLm1 increases and iLm2 decreases in this mode. If the energy stored in Lr1 and Lr2 is greater than the energy stored in CS1–CS4, then CS2 and CS4 can be discharged to zero voltage. Mode 4 [t3 ≤ t < t4]: At time t3, CS2 and CS4 are discharged to zero voltage and the anti-parallel diodes of S2 and S4 are conducting [since iLr1(t3) < 0 and iLr2(t3) > 0]. Thus, S2 and S4 can be turned on at this moment under ZVS. Diodes D1 and D4 are conducting in this mode such that vLm1 = nVo and vLm2 = − nVo. Lr1 and Cr1 are resonant in circuit 1 and Lr2 and Cr2 are resonant in circuit 2. iLr1, iLr2, vCr1 and vCr2 are expressed as     Vin /2 − nVo − vCr1 t3 sin vr t − t3 iLr1 (t) = Zr     + iLr1 t3 cos vr t − t3     nVo − vCr2 t3 iLr2 (t) = sin vr t − t3 Zr     + iLr2 t3 cos vr t − t3    vCr1 (t) = Vin /2 − nVo − Vin /2 − nVo − vCr1 t3       × cos vr t − t3 + iLr1 t3 Zr sin vr t − t3    vCr2 (t) = nVo − nVo − vCr2 t3       × cos vr t − t3 + iLr2 t3 Zr sin vr t − t3

(9)

(10)

(11)

(12)

(13)

System analysis and design example

The fundamental harmonic approach is adopted to analyse the circuits 1 and 2. The fundamental switching frequency is used to obtain the system transfer function of each circuit and all the harmonics of the switching frequency are neglected in the following discussion. Circuits 1 and 2 have the same circuit components and circuit configuration. However, the PWM signals of each circuit are interleaved by one-half switching period and each circuit supplies one half of load power. Therefore only circuit 1 is discussed in the following. Since the duty ratio of S1–S4 is 0.5, the AC terminal voltages vab and vcd are the square waveforms between 0 and Vin/2. The components Cin1, S1, S2, Cr1, Lr1, Lm1, D1, D2 and Co form the standard LLC resonant circuit. Based on the Fourier series analysis, the input voltage vab is given as V    Vin Vin  in + sin 2pfs t + sin 2pnfs t 4 p n p n=3, 5...

(14)

(15)

(16)

(17)

= vab,dc + vab,f + vab,h where vab,dc, vab,f and vab,h are the DC component, fundamental frequency component and harmonic components of vab, respectively. The secondary side of the resonant converter is driven by a quasi-sinusoidal current. If iLr1 > iLm1, D1 conducts and vLm1 = nVo. On the other hand, vLm1 = − nVo if iLr1 < iLm1 and D2 conducts. The transformer primary voltage vLm1 can be considered as a quasi-square waveform. The peak voltage of vLm1 at the fundamental frequency is expressed as vˆ Lm1, f = 4nVo /p. The average output current of each centre-tapped rectifier is equal to Io/2 and the peak value of the diode currents is given as ˆiD1 = ˆiD2 = pIo /4. The load resistance reflected to the primary side of transformer T1 is given as Rac, T 1 =   vˆ Lm1, f / ˆiD1 /n = 16n2 Ro /p2 . Therefore the resonant tank shown in Fig. 4 is excited by an effectively sinusoidal input voltage Vab, f and drives the effective AC resistive road Rac,T1. From Fig. 4, the AC voltage gain of the resonant tank at fundamental frequency can be derived in the following equation |Gac (f )| =

Mode 6 [t5 ≤ t < Ts + t0]: At t5, S2 and S4 are turned off. Diodes D2 and D3 are conducting and the magnetising voltages vLm1 = − nVo and vLm2 = nVo. Since iLr1(t5) > 0 and 814 & The Institution of Engineering and Technology 2014

4

vab =

The inductor current iLr1 increases and iLr2 decreases in this mode. Mode 5 [t4 ≤ t < t5]: At t5, iLm1 = iLr1 and iLm2 = iLr2 such that D1–D4 are all off. Components Cr1, Lr1 and Lm1 in circuit 1 are resonant. In the same manner, Cr2, Lr2 and Lm2 are resonant in circuit 2. iLr1, iLr2, vCr1 and vCr2 are given as     Vin /2 − vCr1 t4 iLr1 (t) = sin vp t − t4 Zp     + iLr1 t4 cos vp t − t4       v t iLr2 (t) = − Cr2 4 sin vp t − t4 + iLr2 t4 Zp   × cos vp t − t4      vCr1 (t) = Vin /2 − Vin /2 − vCr1 t4 cos vp t − t4     + iLr1 t4 Zp sin vp t − t4     vCr2 (t) = vCr2 t4 cos vp t − t4     + iLr2 t4 Zp sin vp t − t4

iLr2(t5) < 0, CS1 and CS3 are discharged and CS2 and CS4 are charged in this mode. If the energy stored in Lr1 and Lr2 is greater than the energy stored in CS1–CS4, then CS1 and CS3 can be discharged to zero voltage. At Ts + t0, vCS1 = vCS3 = 0. Then, the anti-parallel diodes of S1 and S3 are conducting. Then, the operations of the proposed converter in a switching period are completed.

VLm1, f Vab, f

1 =       2        2 1+k 1− fr2 / fs2 +Q2 fs / fr − fr / fs (18)   where Q = Lr1 /Cr1 /Rac, T 1 , fr = 1/2p Lr1 Cr1 , k = Lr1/Lm1 and fs is the switching frequency. The AC voltage gain at no-load condition (Q = 0) and fs = ∞ case is given as |Gac (f )|Q=0, fs =1 ≃ 1/(1 + k). If the minimum DC voltage gain of the proposed converter is greater than |Gac (f )|Q=0, fs =1 , then the output voltage of the proposed IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

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Fig. 4 AC resonant tank by Cr1, Lr1 and T1 related to fundamental switching frequency

converter can be regulated from no-load to full-load condition

Gdc,

min

=

n Vo + Vf Vin, max /4

. |Gac (f )|Q=0, fs =1 =

1 (19) (1 + k)

where Vf is the voltage drop on D1–D4. The proposed converter was implemented by a laboratory prototype with the following specifications: Vin = 750 V– 800 V, Vo = 24 V, Po = 960 W and series resonant frequency fr = 120 kHz. Transformers T1 and T2 were implemented using TDK EER-42 magnetic core with Ae = 194 mm2. The primary and secondary winding turns of T1 and T2 are 24 turns and 3 turns, respectively. The minimum and maximum voltage gains of LLC circuits 1 and 2 are obtained as

Gdc, min =

4n Vo + Vf Vin, max

=

Fig. 6 Measured waveforms of the gate voltages vS1, full load and Vin = 800 V case

gs–vS4, gs

at

1/8 and Q = 0.3. The AC voltage gain of the proposed converter at no load condition (Q = 0) is given as |Gac (f )|Q=0, fs =1 ≃ 1/(1 + k) = 1/(1 + 1/8) = 0.889 , Gdc, min

(23)

Therefore the output voltage of the proposed converter at no load can be regulated. The series resonant inductances, the magnetising inductances and the resonant capacitances are

4 × (24/3) × (24 + 0.8) ≃1 800 (20)

Gdc, max =

4n Vo + Vf Vin, min

=

4 × (24/3) × (24 + 0.8) = 1.06 750 (21)

The AC equivalent resistances of T1 and T2 at full load are obtained as Rac,T 1 = Rac,T 2 = 16 × (24/3)2 × (24/40)/3.14162 ≃ 62.25 V

(22)

From (18), the inductance ratio of Lr1 and Lm1 and quality factor Q at full load condition are selected as k = Lr1/Lm1=

Fig. 5 Measured waveforms of the gate voltages vS1, full load and Vin = 750 V case IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

gs–vS4, gs

Fig. 7 Experimental results of gate voltage, drain voltage and drain current of switch S1 at at

a Vin = 750 V and 5% load b Vin = 750 V and full load 815

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www.ietdl.org obtained in the following equations Lr1 = Lr2 =

QRac, T 1 0.3 × 62.25 = ≃ 25 mH 2pfr 2p × 120 × 103

Lm1 = Lm2 = Lr1 /k = Cr1 = Cr2 = =

25 mH ≃ 200 mH 1/8

(24) (25)

1 4p2 Lr1 fr2

proposed converter. The input capacitances Cin1 and Cin2 are 680 nF/450 V, the flying capacitance Cf is 0.68 μF/630 V and the output capacitance Co is 3000 μF/100 V. The constant output voltage is demanded in the DC/DC converter. Thus, a resistor-based voltage divider, a voltage controller (TL431), an optocoupler (PC817) and a variable frequency control IC are used to control the output voltage.

5 1

 2 ≃ 70 nF 4p2 × 25 × 10−6 × 120 × 103

(26)

The voltage stresses of active switches S1–S4 are expressed as vS1, max = Vin, max /2 = 400 V

Experimental results

A laboratory prototype with the circuit parameters derived in the previous section was tested to verify the performance of the proposed converter. The measured gate voltages of

(27)

The MOSFETs IRFP460 with 500 V voltage and 20 A current stresses are adopted for power switches S1–S4 in the proposed circuit. The voltage stress and average current of the rectifier diodes D1–D4 are obtained as

vD1,stress = 2 Vo + Vf = 2 × (24 + 0.8) = 49.6 V iD1,av = Io, max /4 = 40/4 = 10 A

(28) (29)

The fast recovery diodes 30CPQ150 with 150 V voltage, 30 A current stresses and 0.8 V voltage drop are used in the

Fig. 8 Experimental results of gate voltage, drain voltage and drain current of switch S1 at a Vin = 800 V and 5% load b Vin = 800 V and full load 816 & The Institution of Engineering and Technology 2014

Fig. 9 Measured waveforms of the two input capacitor voltages and flying capacitor voltage at full load a Vin = 750 V b Vin = 800 V c Dynamic response with Io variation between 10 and 40 A IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

www.ietdl.org S1–S4 at full load with input voltage Vin = 750 V and 800 V cases are given in Figs. 5 and 6, respectively. Figs. 7 and 8 show the experimental results of gate voltage, drain voltage and drain current of switch S1 at 5 and 100% loads with Vin = 750 V and Vin = 800 V case, respectively. Before switch S1 is turned on, the drain current is negative to discharge the drain-to-source capacitor. Thus, switch S1 can be turned on at ZVS when the drain voltage is decreased to zero voltage. In the same manner, S2–S4 are also turned on at ZVS. The measured waveforms of the two input capacitor voltages and flying capacitor voltage at full load and input Vin = 750 V and Vin = 800 V are given in Figs. 9a and b. Fig. 9c shows the measured input capacitor voltages and flying capacitor voltage under the load variations between 10 and 40 A. It is clear from Fig. 9 that the two input capacitor voltages and the flying capacitor voltage are balanced. Fig. 10 gives the measured waveforms of switch currents iS3 and iS4, inductor current iLr2 and flying capacitor current iCf at full load and nominal input voltage Vin = 800 V. The measured waveforms of gate voltage vS1, gs and inductor currents iLr1 and iLr2 at full load and nominal input voltage Vin = 800 V are illustrated in Fig. 11. Two inductor currents are balanced with the phase shift of one-half of the switching period. Fig. 12 shows the measured waveforms of gate voltage vS1, gs and two resonant capacitor voltages vCr1 and vCr2 at full load and nominal input voltage Vin = 800 V. Fig. 13 gives the

Fig. 12 Measured waveforms of gate voltage vS1, gs and resonant capacitor voltages vCr1 and vCr2 at full load and nominal input voltage Vin = 800 V

Fig. 13 Measured waveforms of output diode currents iD1–iD4 at full load and nominal input voltage Vin = 800 V

Fig. 10 Measured waveforms of switch currents iS3 and iS4, inductor current iLr2 and flying capacitor current iCf at full load and nominal input voltage Vin = 800 V

Fig. 14 Measured efficiencies of the proposed converter at different load conditions

measured waveforms of the diode currents at full load. The diode currents are almost balanced. Fig. 14 illustrates the measured circuit efficiencies of the proposed converter at different load conditions.

6 Fig. 11 Measured waveforms of gate voltage vS1, gs and inductor currents iLr1 and iLr2 at full load and nominal input voltage Vin = 800 V IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181

Conclusion

This paper presents a new resonant converter for high-input voltage applications. The features of the proposed converter 817

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www.ietdl.org are low-voltage stress of MOSFETs, ZVS turn on for all active switches, no reverse recovery loss on the rectifier diodes and low-current rating of the transformer windings. One flying capacitor is adopted to automatically balance two input capacitor voltages. Two resonant converters are used to reduce the voltage stress of each MOSFET and to share the load current. Therefore the proposed converter is suitable for high-input voltage and high-load current applications. In each resonant converter, variable frequency control is used to regulate the output voltage at the desired voltage level. Since the operating switching frequency is less than the series resonant frequency, the MOSFETs can be turned on at ZVS and the rectifier diodes are turned off at ZCS. Thus, the switching loss of the active switches is reduced and the reverse recovery loss of the rectifier diodes is overcome. The proposed converter can be applied for a battery charger with high-input voltage, industry switching mode power supplies with wide range of single-phase AC voltage 180 V–550 Vrms (or three-phase AC voltage 340 V– 550 Vrms) and DC traction power system. Finally, experiments are provided to verify the effectiveness of the proposed converter.

7

Acknowledgment

This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224-022MY3.

8

References

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IET Power Electron., 2014, Vol. 7, Iss. 4, pp. 811–818 doi: 10.1049/iet-pel.2013.0181