An Exercise of ET/UTBB SOI CMOS Modeling and Simulation with BSIM-IMG Qiang (Brian) Chen1, Xinghua Zhong1, Yanjun Wu1, Nengyong Zhu1, Wei Huang1, Darsen Lu2, Chenming Hu2, Bich-Yen Nguyen3, and Olivier Faynot4 1Accelicon Technologies Inc., Cupertino CA, USA, 2University of California, Berkeley CA, USA, 3Soitec, France, 4CEA-LETI, France Email:
[email protected], Tel: (408) 725-7176 Abstract – This paper presents an exploratory application of BSIM-IMG (May/2011-release) to ET/UTBB SOI MOSFET modeling and circuit simulations. Compliance with fundamental compact model requirements and physical scalability with respect to technology parameters in BSIM-IMG are analyzed. BSIM-IMG model parameters are extracted on a 20nm technology. Simulation results are presented both for conventional benchmark and ET/UTBB SOI specific circuits.
INTRODUCTION The extremely-thin/ultra-thin body and buried oxide (ET/UTBB) SOI technology remains a viable option for 20nm node and beyond for its performance advantages over the bulk technology and easier integration than non-planar technologies [1]. Compact models developed for general SOI MOSFET structures have been tried for ET/UTBB SOI device modeling [ 2 , 3 ]. It has been shown [ 4 ] that the industry standard model of BSIMSOI is capable of fitting DC and AC measurement data of ET/UTBB devices and adequate for circuit simulations, whereas its physicality for undoped channels needs improvement. More recently, dedicated models are being developed [1, 5 , 6 , 7 ], and model standardization is being carried out at CMC [8]. The BSIM Independent-Multi-Gate (IMG) model, the sole confirmed model candidate at CMC as of writing (May, 2011), is explored in this paper for practical modeling and simulation applications.
RESULTS AND DISCUSSIONS BSIM-IMG uses the surface-potential based approach as opposed to the conventional threshold voltage based methodology to meet next-generation compact model requirements [8], such as model symmetry around Vds=0V and continuity of high-order derivatives in particular. Select benchmark tests [9,10] are carried out on BSIM-IMG. The model’s drain-source symmetry is sustained when the gate current module is turned on (Figure 1). The temperature independent slope ratio test shows proper convergence in the weak inversion region towards the asymptotic value of 1.297 (Figure 2). The ‘tree-top’ test result, where gm/Id is simulated, shows a nearly constant value in the weak inversion region (Figure 3), which is consistent with the gate capacitance behavior (Figure 4). The single-tone harmonic balance simulation result shows a slope of three for the third harmonic as expected from the drain-source symmetry and continuity of high-order derivatives (Figure 5).
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Physical scalability of BSIM-IMG is considered through long-channel device behavior for technological parameter ranges where full depletion occurs. Specifically, the body doping level is varied from 1020m-3 to 1024m-3, silicon thickness from 3nm to 15nm, the top gate EOT from 0.8nm to 20nm, the back gate EOT from 14nm to 30nm, and the back gate doping level from 1020m-3 to 1024m-3 (in both N and P types). Constant-current based threshold voltage (Vt) is evaluated at ICON=1nA. Simulation results indicate that the long-channel Vt increases as TSi is reduced (Figure 6), which is explained by steeper vertical potential profile and larger voltage drop across the front gate oxide [ 11]. Vt simulations for various NBody correctly show increase of Vt with NBody in the higher doping regime, which is analogous to that in bulk MOSFETs (Figure 7). In the undoped/lightly doped regime, simulations properly reflect the diminishing impact of NBody on Vt, which eliminates the random dopant fluctuation effect and results in improved matching properties. The back gate bias dependence indicates that back gate depletion and impact of the back gate doping type and level have not been implemented yet in the latest BSIM-IMG release (Figure 8). As the front gate EOT increases, Vt increases in accordance with the conventional dependence seen in bulk transistors (Figure 9). As the back gate EOT decreases, Vt itself increases (Figure 10), which is explained by the same mechanism for the Vt vs. TSi dependence. In addition, its sensitivity to the back gate bias increases as well, resulting from a stronger back gate control. BSIM-IMG models have been extracted on MBP® for a 20nm ET/UTBB SOI technology by fitting both DC and AC data at different temperatures across a typical modeling transistor array of geometries. Satisfying fitting accuracy has been achieved. Using HSPICE® , the resulting models are used for simulations with great efficiency of various circuits, such as SRAM bit cell SNM characterization and flip-flop setup time/hold time characterization. A 51-stage RO simulation result, obtained with appropriate model modifications to protect technology IP, is shown in Figure 11 for stage delay vs. dynamic power correlation. A four-transistor Schmitt trigger that cleverly exploits the back gate in ET/UTBB devices [12] is simulated successfully (Figure 12). In conclusion, BSIM-IMG models have been extracted for a 20nm ET/UTBB SOI technology with satisfying fitting accuracy, and used for efficient circuit simulations with HSPICE® . Areas for improvement have been suggested.
ACKNOWLEDGMENTS The authors gratefully acknowledge excellent support from Synopsys® for HSPICE® Verilog-A and RF simulations.
REFERENCES [1] O. Faynot, et. al., ‘Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond,’ IEDM, 2010, pp. 50-53. [2] BSIMSOI, http://www-device.eecs.berkeley.edu/~bsimsoi/ [3] M. Miura-Mattausch, et. al., ‘HiSIM-SOI: Complete surfacepotential-based model valid for all SOI-structure types,’ IEEE SOI Conf., Oct. 2010, pp. 1-4. [4] Q. Chen, et. al., ‘Assessment of ETSOI MOSFET modeling with BSIMSOI,’ CSTIC, 2011.
Figure 1 Modified symmetry test simulation result with IGMOD on
[5] D. Lu, et. al., ‘A Multi-Gate CMOS compact model - BSIM-MG,’ IWCM, Jan. 2010. [6] J. G. Fossum, UFDG User’s Guide, Gainesville, FL: 2007. [7] G. Dessai, et. al., ‘Compact charge model for independent-gate asymmetric DGFET,’ IEEE T-ED, vol.57, no.9, pp. 2106-2115, 2010. [8] Compact Model Council, http://www.geia.org/CMC-Introduction [9] X. Li., et. al., ‘Benchmark tests for MOSFET compact models with application to the PSP Model,’ IEEE T-ED, vol. 56, no. 2, pp. 243251, Feb. 2009. [10] C. C. McAndrew, ‘Validation of MOSFET model source–drain symmetry,’ IEEE T-ED, vol. 53, no. 9, pp. 2202–2206, Sept. 2006. [11] Q. Chen, et. al., ‘A comparative study of threshold voltage variations in symmetric and asymmetric undoped double-gate MOSFETs,’ IEEE SOI Conf., 2002, pp. 30-31. [12] T. Cakici, et. al., ‘A low power four transistor Schmitt trigger for asymmetric double gate fully depleted SOI devices,’ IEEE SOI Conf., 2003, pp. 21-22.
Figure 2 Slope ratio test result (ΔV=1mV)
Figure 3 Tree-top test simulation result
Figure 4 Normalized total gate capacitance dependence
Figure 5 Single tone (100MHz) harmonic balance simulation result
Figure 6 Linear Vt dependence on silicon thickness
Figure 7 Linear Vt dependence on body doping level
Figure 8 Linear Vt dependence on back gate bias
Figure 9 Linear Vt dependence on the front gate EOT
Figure 10 Linear Vt dependence on the back gate EOT
Figure 11 Stage delay vs. dynamic current in a 51-stage RO simulation
Figure 12 Transient transfer characteristics of simulated 4T-ST
