Special Issue on Advanced Modeling of Power Devices ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

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Special Issue on Advanced Modeling of Power Devices and Their Applications

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HIS special issue is devoted to the research and development activities in the modeling field of power devices, the correlation of modeling approaches to the physics of power devices, and, in particular, on emerging models of advanced power devices for power circuit applications. The importance of accurate design of circuits containing power devices is increasing due to the necessity of realizing efficient usage of electrical energy for applications in various supply voltage ranges. High-voltage (HV) MOSFETs are utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at various bias conditions. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently, many investigations are also intensively undertaken for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications, e.g., beyond 10 kV. A good understanding of power device operation under such extremely high bias conditions requires a broad physical analysis and, consequently, leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing effective resistivity of power devices makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested. Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of communication easily occurs in the high-voltage research and development community, although the basic physics and tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of research and development activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices, including novel bipolar, thyristor, and diode structures. Models for active and passive components integrated in advanced Silicon, as well as new material technologies, statistical modeling, and mixed-mode simulation are also of special interest. The cover figure by Ohashi and Omura gives a visual overview of the covered targets in this special issue. This Special Issue on the Advanced Modeling of Power Devices and Their Applications includes a total number of 24 rigorously reviewed papers, including 8 invited papers. It starts with an invited review paper by Ohashi and Omura titled “Role of Simulation Technology for the Process in Power Devices and Their Applications,” providing an overview of many kinds

Digital Object Identifier 10.1109/TED.2012.2235933

of power devices fabricated for different applications with different materials. Afterward, the issue is ordered according to the bias range of applications from higher voltages to rather low voltages, namely, in terms of device structures from IGBT to HV MOSFET. The second invited paper is titled “Analytical Modeling of IGBTs: Challenges and Solutions” by Baliga, describing the physics and functionality of IGBT structures applicable up to very high voltage operation. The third invited paper titled “Application of Electrical Circuit Simulations in Hybrid Vehicle Development” by Ueta et al. focuses on IGBT modeling for vehicle applications. The fourth invited paper titled “Limiting Factors of the Safe Operating Area for Power Devices” by Schulze et al. describes the effect of the high voltages applied on power devices and their safety operation. Three regular papers focusing on IGBT properties follow. The paper titled “Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclampled Inductive Switching” by Breglio et al. describes the expected failures that occur during switching. Then, the paper titled “HISIM-IGBT: A Compact Si-IGBT Model for Power Electronic Circuit Design” by Miyake et al. describes a consistently potential based compact model of IGBTs for circuit simulation. The succeeding paper by Navarro et al. titled “A Sequential Model Parameter Extraction Technique for Physics-Based IGBT Compact Models” develops and applies an efficient parameter extraction sequence for different IGBT models. The fifth invited paper by Ortiz et al. titled “Modeling of Soft-Switching Losses of PT and NPT IGBTs in High-Power High-Efficiency Dual-Active-Bridge DC/DC Converters” describes a model simulating the switching loss for real circuit applications. Two regular papers about circuit applications follow. In the paper titled “Layout Role in Failure Physics of IGBTs Under Overloading Clamped Inductive Turnoff” by Perpina et al., the important role of layout is analyzed and described. The paper by Takao and Ohashi titled “Accurate Power Circuit Loss Estimation Method for Power Converters with Si-IGBT and SiC-Diode Hybrid Pair” proposes a novel power loss estimation method. The succeeding five papers are introducing new types of power devices based on large band-gap materials different from Silicon. Among them, the first three papers are applying SiC, whereas the last two are applying GaN. The sixth invited paper titled “Physical Models for SiC and Their Application to the Device Simulations of SiC Insulated-Gate Bipolar Transistors” by Hatakeyama et al. proposes models based on the material properties applicable for device simulation. Two regular papers about SiC follow. The paper titled “Modeling of SiC IGBT Turn-Off Behavior Valid for Over 5-kV Circuit Simulation” by Miyake et al. proposes a SPICE simulation model for SiC

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IGBTs. The paper titled “Behavioral Approach to SiC-MergedDiode Electrothermal Model Generation” by Napieralski et al. proposes a method to merge the electrical and thermal effects. The seventh invited paper titled “A Compact Physical AlGaN/GaN HFET Model” by Trew et al. proposes a compact model of heterostructure GaN FETs for circuit simulations, including the band structural features. A regular paper titled “GaN Power Transistor Modeling for High Speed Converter Circuit Design” by Nakajima et al. also aims at a similar goal. The conventional Silicon HV MOSFETs cover a wide range of operation bias conditions. Different from the conventional application range of MOSFETs, HV MOSFETs require specific additional modeling approaches, which are discussed by an invited paper and eight regular papers. The eighth invited paper titled “The Second Generation of HISIM-HV Compact Models for High-Voltage MOSFETs” by Mattausch et al. addresses a consistent quasi-2-D modeling approach of the HV MOSFET. The regular paper by Wang et al. is titled “An Accurate and Robust Compact Model for High-Voltage MOS IC Simulation” also proposes another compact model based on a different approach. The succeeding regular paper titled “Measurement and Compact Modeling of 1/f Noise in HVMOSFETs” by Mavredakis focuses on 1/f noise modeling for rather conventional HV MOSFET structures. Then, the regular paper titled “A Physics-Based Analytical 1/f Noise Model for RESURF LDMOS Transistors” by Mahmud et al. proposes a 1/f noise model specific for a more complicated structure of HV MOSFETs. Afterward, the regular paper by Iizuka et al. titled “Modeling of the Impurity-Gradient Effect in High-Voltage Laterally-Diffused MOSFETs” models the specific effects caused by the doping gradient present in the conventional LDMOS structure of HV MOSFETs. The regular paper titled “TCAD Simulation of Worst-Case-Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors” by Reggiani et al. investigates the unavoidable thermal effects of

the HV MOSFETs. The regular paper titled “Electro-Thermal Simulation of Self-Heating in DMOS Transistors up to Thermal Runaway” by Pfost et al. focuses also on the electrothermal coupling of HV MOSFETs. The next regular paper by Koh and Iizuka titled “Parameter Extraction and Comparison of Self-Heating Model for Power MOSFETs Based on Transient Current” gives a model parameter extraction based estimation of the electrothermal coupling. The final paper of this special issue titled “Modeling and Simulation Methodology for SOA Aware Circuit Design in DC and Pulsed-Mode Operation of HV MOSFETs” by Khandelwal et al. describes important design issues for circuits containing HV MOSFETs. The editors would like to sincerely thank the reviewers evaluating the submitted papers for this special T RANSACTIONS ON E LECTRON D EVICES issue, who carefully and rigorously reviewed each manuscript and the subsequent revised versions under a very tight schedule. The editors would also like to thank the paper authors for their cooperation in submitting their revised manuscripts in a shorter-than-normal time frame and for documenting important research results so that these research results are timely available to the wider communities of researchers and users in the field of power devices. The editors further express their thankfulness and great appreciation for the supporting work of J. A. Marsh from the Electron Devices Society publications office. The editors enjoyed putting together this special issue, and they hope that the readers will enjoy it, too.

M ITIKO M IURA -M ATTAUSCH, Guest Editor NARAIN D. A RORA, Guest Editor E HRENFRIED S EEBACHER, Guest Editor S AMAR K. S AHA, Guest Editor

Mitiko Miura-Mattausch (M’95–F’07) from 1981 to 1984, she was with the Max Planck Institute for Solid-State Physics, Stuttgart, Germany, as a Researcher, working on nonlinear phenomena in solid-state materials. From 1984 to 1996, he with Corporate Research and Development, Siemens AG in Munich, Germany, working on hot-electron problems in MOSFETs, ultrahigh-speed bipolar transistors and analytical modeling of deep submicrometer MOSFETs for circuit simulation. Since 1996, she has been leading the Ultrascaled Device Laboratory, Hiroshima University, Japan, and focuses on advanced MOSFET features under RF operation experimentally and theoretically. She is currently a Professor with the Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University. She has supervised more than 20 Ph.D. theses. She is the author of more than 300 papers in peer-reviewed international journals and conferences, and three technical books.


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Narain D. Arora received the Ph.D. degree from the Indian Institute of Technology, Delhi, India. He has over 30 years of industry experience, doing research in the field semiconductor process and device design, simulation, modeling, and characterization, including parasitic (interconnect) modeling and extraction. From 1967 to 1979, he was a Senior Scientific Officer with the Armament Research and Development Establishment and Solid State Physics Laboratory, Defense R&D Labs, Delhi. In 1983, he was a Postdoctoral Fellow with the University of Waterloo, Waterloo, ON, Canada, and a Visiting Professor with North Carolina State University, Raleigh. From 1983 to 1996, he held several engineering and management positions with the Semiconductor Division, Digital Equipment Corporation. From 1996 to 2002, he served as a Vice President and a Chief Scientist with Simplex Solutions Inc. From 2002 to 2007, he was the Vice President of Research and Development with Cadence Design Systems. He is currently the Senior Vice President of Design Technology with Silterra Malaysia, Sdn. Bhd., Kulim, Malaysia. He has given many invited talks. He is a holder of five U.S. patents. He is the author of over 60 journal papers and the book MOSFET Modeling for VLSI Circuit Simulation: Theory and Practice (Springer-Verlag, 1993). The book was translated into Chinese language in 1999. The 1993 edition was reprinted in 2007 by World Scientific Publications and is being digitized to become an eBook, published on SpringerLink online platform. Dr. Arora is a Distinguished Lecturer of IEEE Electron Devices Society and the founding chair (1998–2004) of IEEE Compact Modeling Technical Committee. He was a Guest Editor for the 2006 special issues of IEEE T RANSACTIONS ON E LECTRON D EVICES S OCIETY on device modeling. He was a recipient of two best paper awards.

Ehrenfried Seebacher received the M.Sc. degree in physics with Graz University of Technology, Graz, Austria, in 1993. From 1994 to 1998, he has been working with the Department of Research and Development, Austriamicrosystems, on compact modeling of CMOS, BiCMOS, and HV CMOS processes. Since 1999, he has been a Section Manager of a group responsible for compact modeling, process characterization, physical verification, and design for manufacturability. He is currently a Manager with the Department of Process Research and Development, Austriamicrosystems AG, Unterpremstätten, Austria, and a Project Leader of technology and product development kit projects. He is the author or coauthor of more than 30 papers. His research interests include are compact modeling of MOS, bipolar transistors, and passive elements mixed-mode circuits and specialized electrooptical system on-chip solutions.

Samar K. Saha received the Ph.D. degree in physics from Gauhati University, Guwahati, India, and the M.S degree in engineering management from Stanford University, Stanford, CA. Since 1981, Dr. Saha has worked in various positions for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, and Silterra. He has also worked as a faculty member in the electrical engineering departments at Southern Illinois University at Carbondale, Carbondale; Auburn University, Auburn, AL; University of Nevada at Las Vegas, Las Vegas; and the University of Colorado at Colorado Springs, Colorado Springs. He is currently the Director of Compact Modeling with SuVolta, Inc., Los Gatos, CA, and an Adjunct Professor with the Department of Electrical Engineering, Santa Clara University, Santa Clara. He is the author of more than 80 research papers and the holder of seven U.S. patents and one European patent. His research interests include nanoscale device and process architecture, technology computer-aided design (TCAD), compact modeling, and TCAD and R&D management. Dr. Saha is the Vice President of IEEE Electron Devices Society (EDS) Publications, the Editor-in-Chief of QuestEDS, an elected member of the EDS Board of Governors, and a member of IEEE Conference Publications Committee. He is the Chair of EDS George Smith and Paul Rappaport awards. He has served as the Head Guest Editor for the IEEE T RANSACTIONS ON E LECTRON D EVICES Special Issues on “Advanced Compact Models and 45-nm Modeling Challenges” and “Compact Interconnect Models for Giga Scale Integration.” He was the Editor for Region-5&6 EDS Newsletter, the Chair of EDS Compact Modeling Technical Committee, the Chair of EDS North America West Subcommittee for Regions/Chapters, and the Chair of EDS Santa Clara Valley chapter.