Statistics of Grain Boundaries in Polysilicon - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007. Statistics of Grain Boundaries in Polysilicon. Hiroshi Watanabe. Abstract—A ...
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007

Statistics of Grain Boundaries in Polysilicon Hiroshi Watanabe

Abstract—A nanometer-scale variation of grain boundary locations in gate polysilicon is investigated in detail based on the assumption that the arrangement of grain boundaries obeys Poisson distribution. The statistics of grain boundaries described here reveals a relation between nanoscopic location and the arrangement of grain boundaries, which implies fluctuation in transistor characteristics of 45-nm and beyond MOSFETs. Index Terms—Entropy, fluctuation, grain boundary, MOS devices, Poisson distribution, polysilicon, SRAM, statistics. Fig. 1.

I. INTRODUCTION

F

OR SEVERAL decades, electrical properties of polycrystalline silicon (polysilicon) have been the focus of increasing attention in the field of integrated circuit technology since its application area is quite wide [1]–[5], encompassing thinfilm transistors (TFTs) [6]–[9], solar cells, devices fabricated on polysilicon [10]–[12], etc. Two principal models are proposed in the literature. One is the carrier-trapping model of carrier conductivity [1], [3]. In this model, there are many trapping states that originated from the silicon dangling bond [4] at the grain surface. The trapped charge at the trapping states makes a local potential barrier through which carriers are transmitted by thermionic emission or tunneling [3]. Kimura et al. [8] and Yamaguchi [9] independently investigated the location dependence of this local potential in TFT, finding that the location dependence is less significant in terms of current–voltage characteristics, whereas a grain boundary in the channel causes the drain–current to be greatly degraded compared with the case without grain boundary. The other is the dopant segregation model, in which phosphorus and arsenic atoms doped in polysilicon segregate to the grain boundaries [2]. In this case, there are some amounts of ionic charges that are opposite in sign with the trapped charges at the grain surface. According to Jackson et al. [4], the surface trap density at the grain boundary NIT is nearly 1E12 cm−2 , which is equivalent to 1E18 cm−3 . This value is much smaller than the donor ion + concentration ND in the gate polysilicon, which is typically −3 1E20 cm . In the gate polysilicon, the influence of NIT therefore becomes negligible; then, a local potential drop due to the segregated ions appears at the grain boundary, instead of the local potential barrier. This local potential drop may increase gate-induced drain leakage (GIDL) and drain-induced barrier lowering (DIBL) if the grain boundary is located at the drainedge side of the gate polysilicon. If the grain boundary is away from the drain-edge side, then GIDL and DIBL may not be Manuscript received May 4, 2006; revised October 3, 2006. The review of this paper was arranged by Editor Y. Chen. The author is with the Advanced LSI Technology Laboratory, Corporate Research and Development Center, Toshiba Corporation, Yokohama 235-8522, Japan (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2006.887212

Relation between grain-boundary fluctuation and dopant fluctuation.

increased so much. Accordingly, these intrinsic leakages may exhibit bit-to-bit dispersion due to the fact that the locations of the grain boundaries are different in different transistors. On the other hand, random dopant fluctuation [13] might be predominant even in the gate of single-crystal silicon. Then, we have to consider the random dopant fluctuation as well as the grain boundary fluctuation in the gate polysilicon. In this case, the doping ions would be distributed around the grain boundary; then, the random dopant fluctuation is probably influenced by the grain-boundary location and not completely at random, as shown in Fig. 1. This strongly suggests that the location of the grain boundary has a significant impact on the bit-to-bit dispersion. In this paper, a location dependence of grain boundaries on the leakage current of scaled MOSFETs is clearly shown. Poisson distribution deduces a nanometer-scale variation in the arrangement of grain boundaries. As a result, we explain a relation between peaks shown in terms of the frequency distribution of the gate leakage current and the arrangement of grain boundaries. It is also found that nanoscopic variation of this arrangement causes the dispersion of threshold voltage VT . Since the drain-to-gate leakage current (DGLC) is affected by grain boundaries, a negative relation between the dispersions of VT and drain–current ID is deduced. In Sections II and III, we describe the origin of the fluctuation and statistics of a grain boundary, respectively. In Section IV, we describe the simulation results. Sections V and VI are devoted to the discussion and the conclusion, respectively. II. ORIGIN OF FLUCTUATIONS IN GATE CURRENT The barrier height for electron tunneling through the gate oxide is lowered due to the local potential drop at the grain boundary, as previously mentioned. The polysilicon depletion layer is also narrower due to the higher concentration at the grain boundary, which further lowers the barrier height. Consequently, the gate current due to direct tunneling concentrates at the grain boundaries, which probably results in the location dependence of the gate current due to the grain boundary. In order to investigate this hypothesis, we calculate the direct

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Fig. 4. Comparison of calculation results and measurements of gate current density. Fig. 2.

Cross-sectional view defining grain boundaries.

Fig. 5. Position dependence of ∆j , which is a component of a fluctuation vector when j = 1, 2, . . . ,10 and LG = 30 nm and TOX = 1.3 nm. Fig. 3. Cross-sectional view of the nMOSFET with grain boundaries used in the present simulation. The first and mth sites belong to the SDE region.

tunneling currents through the gate oxide of nMOSFETs with no grain boundary and with a grain boundary in the n+ gate polysilicon. Fig. 2 is a schematic diagram showing the grain whose width is denoted by WGR and the grain boundary whose width is denoted by WGB in the n+ gate polysilicon. Fig. 3 is a schematic diagram of the cross-sectional view of the nMOSFET used in the present calculation, in which Y j is the width of the source–drain extension (SDE) region, Xj is the depth of the SDE region, and the integer m is defined as gate length LG divided by WGB . Assume that WGB is 3 nm, m = 10 corresponds to LG = 30 nm, m = 15 corresponds to LG = 45 nm, etc. The first and the mth sites belong to the SDE overlap region, while the second and the (m − 1)th sites partially belong to the SDE overlap region. Details of the calculation method of the direct tunneling have already been published in [15]. In Fig. 4, we compare the measured gate leakage current and the calculated direct tunneling current through the gate oxide in an nMOSFET and a pMOSFET. In this calculation, we have used the value for oxide thickness that is determined from the transmission-electronmicroscopy images of the measured samples. Although a quite good agreement is obtained, the impact of grain boundary might disappear because it may be in several percent, which is too small to be seen in the semilog plot. Then, in Fig. 5, we plot the calculated tunnel-current difference from the nograin-boundary case ∆j against the normalized position of the grain boundary in the n+ gate polysilicon j/m, where ∆j is derived by subtracting the calculated tunnel current without

Fig. 6. Electric field dependence of ∆j . Since Y j is fixed, ∆j in a smaller LG is more enhanced by the grain boundary at the SDE region.

grain boundary from that with a grain boundary at the jth site, and LG = 30 nm and WGB = 3 nm. When the gate voltage VG is 1 V, the gate current increases are nearly 11% at the SDE regions (j = 1 and m), while the gate current increases are nearly 3% at the center of the channel (j = 2, 3, . . . , m − 1). In the SDE overlap, the electrons tunnel from the diffusion layer to the polysilicon, while they tunnel from the inversion layer to the polysilicon out of the SDE overlap. This may cause the location dependence of ∆j . The discrepancies between the cases of the SDE grain boundary and the center grain boundary are shown in Fig. 6. Smaller LG increases the discrepancy, which indicates that the location dependence is enhanced with the scaling. Next, let us consider a case of OFF-state, e.g., VG is less than VT and the drain voltage VD is 0.03 V in an nMOSFET of LG = 30 nm and TOX = 0.8 nm, as shown in Fig. 7. The upper depicts the electron current flow in the case of no grain boundary, and the lower depicts it in the case that a grain boundary is located

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Fig. 9. Arrangements of grain boundaries in the gate. The arrangement states described in (a) are taken into account, and the arrangements states described in (b) are excluded. The reason that the grain boundaries are assumed to be located separately among the sites is that the two grain boundaries occupying nearestneighbor sites are regarded as a grain boundary with a width of = 2WGB , as seen in (b).

Fig. 7. Electron current flow distribution in the substrate with or without a grain boundary at the drain edge. The DGLC occurs at the drain edge due to the grain boundary, as shown on the lower part. The arrows in the gate have been omitted to make the figures transparent.

the band-gap narrowing that assumes complete ionization and is quite workable in the device simulation, we developed a phenomenological method to self-consistently calculate both incomplete ionization and band-gap narrowing [14]–[16]. If one neglected the band-gap narrowing, one would underestimate the density of the excess electrons at the grain boundary and might overlook the aforementioned drain-to-gate current because the electron density is equivalent to the distance between EF and EC in the energy-band diagram. This calculation method is therefore necessary for studying location dependence due to the conduction-band lowering at the grain boundary. III. STATISTICS OF GRAIN BOUNDARIES

Fig. 8. Relation between band-gap narrowing and local potential due to grain boundary.

at the drain edge. The drain-edge grain boundary causes the drain-to-gate current to occur, which may be due to the excess electrons at the grain boundary. The barrier lowering due to the grain boundary is equivalent to the conduction-band lowering that is composed mainly of the band-gap narrowing and a local potential drop due to excess electrons and segregated dopants at the grain boundary, as shown in Fig. 8. The conduction-band edge and the valenceband edge are modulated by the local potential drop, as depicted by the dashed line. The conduction-band edge is further lowered by the band-gap narrowing for electrons, whereas the valence-band edge is partially recovered by the band-gap narrowing for holes, as depicted by the bulk line. However, the calculation of the band-gap narrowing in a degenerate semiconductor (e.g., n+ gate polysilicon) is a complicated problem because the incomplete ionization of dopants and the band-gap narrowing are mutually affected [14]–[16]. The bandgap narrowing is based on the scattering theory, whereas the ionization problem is a bound state problem. Appending a module for incomplete ionization to Schenk’s formula [17] for

In general, we have two approaches to deduce the fluctuation due to the location dependence of grain boundaries, namely 1) a method using random numbers that correspond to the arrangements of grain boundaries in the gate polysilicon and 2) a method to statistically deduce the fluctuation of arrangements. In this paper, we produce a statistical method using Poisson distribution and compare the results obtained using random numbers. First, in order to study the statistics of grain boundary, we quantify the fluctuation in the gate current. Assuming that WGB is a constant, there can be m (= LG /WGB ) sites that n grain boundaries can occupy, as shown in Fig. 3. Here, we assume that WGB is 3 nm and that the SDE overlap Y j is 4.5 nm in order to clearly deduce the location dependence. We denote the tunnel-current difference from the no-grain-boundary case by ∆r (r = 1, 2, . . . , m) when there is a grain boundary at the rth site. As previously mentioned, Fig. 5 shows that the calculated ∆r is larger in the SDE region than in the channel region. Considering all the arrangements in which any two sites are separate for WGB not to be doubled, as shown in Fig. 9(a), we may obtain the frequency distribution of the gate current. However, since the number of these arrangements is too large, we may try to sample the arrangements using the random

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Fig. 10. Frequency distribution with regard to increase in gate current per bit that is obtained by (θm,n , ∆) when WGR  = 100 nm, LG = 30 nm, TOX = 1.3 nm, and VG = 1 V.

number method. This yields a frequency diagram, as shown in Fig. 10(a), in which there is a confusing structure with many peaks. It is then difficult to deduce meaningful information from this diagram. Next, describing an average of WGR by WGR , Poisson distribution is given by 1 Pn (LG , WGR ) = n!



LG WGR 

n



LG exp − WGR 

 (1)

which gives the probability that we have n grain boundaries in a gate whose length is LG . Since Poisson distribution generally describes random and rare events, WGR  has to be much larger than LG . In other words, the present technique is valid for deep submicrometer devices (LG  0.1 µm) since WGR  is typically about 100 nm in the conventional fabrication process of gate polysilicon. We subsequently define g(m, n) as the number of cases in which n grain boundaries are arranged among m sites, excluding cases in which nearest-neighbor sites are occupied by two grain boundaries, as shown in Fig. 9(b). If we set a site with a grain boundary to “1” and another site with no grain boundary to “0,” then we can write the arrangement of grain boundaries by a vector θm,n , e.g., θm,n = (. . . , 0, 1, 0, 0, 1, . . .). We can also define a vector ∆ = (∆1 , ∆2 , . . . , ∆m ). Here, a scalar product (θm,n , ∆) is a projection of the tunnel-current difference from the no-grain-boundary case to the arrangement θm,n . Let us consider the case of m = 3. If n = 0, then we have g(3, 0) = 1 and θ3,0 = (0, 0, 0), resulting in the tunnel-current difference obtained by (θ3,0 , ∆) = 0∆1 + 0∆2 + 0∆3 = 0. If n = 1, then we have g(3, 1) = 3 and θ3,1 = (1, 0, 0), (0, 1, 0), and (0, 0, 1), resulting in tunnel-current differences of ∆1 , ∆2 , and ∆3 , respectively. If n = 2, then we have g(3, 2) = 1 and θ3,2 = (1, 0, 1), resulting in a tunnel-current difference of ∆1 + ∆3 . The number of bits associated with (θm,n , ∆) is calculated by multiplying the number of all the considered bits and the probability of θm,n , i.e., P (θm,n ) =

Pn (LG , WGR ) . g(m, n)

(2)

We can thus regulate the frequency distribution of the tunnelcurrent difference, as shown in Fig. 10(b). This analysis requires fewer data (∆1 , ∆2 , . . . , ∆m ) to deduce the frequency distribution compared with the random number approach, which substantially reduces the computational time.

Fig. 11. WGR  dependence of the frequency distribution when LG = 30 nm, TOX = 1.3 nm, and VG = 1 V.

Finally, we have to produce an indicator for evaluating the intensity of fluctuation from the frequency distribution diagram regulated with Poisson distribution. We can thus define the entropy for the fluctuation due to the grain boundaries as    S = kB log W∆ = kB log (∆, θr ) × P (θr ) (3) r

where W∆ indicates the number of microscopic states. In the summation of this equation, P (θ) indicates the peak height in the frequency of (∆, θ). The scalar product indicates the value corresponding to the peak. The higher peak indicated by P (θ) and the larger values indicated by (∆, θ) result in larger entropy, i.e., intense fluctuation. In other words, we have to decrease P (θ) and (∆, θ), that is, to reduce the entropy, in order to decrease the product dispersion. IV. RESULTS The confused structure shown in Fig. 10(a) is turned into the transparent structure of peaks shown in Fig. 10(b), taking into account Poisson distribution. When VG = 1 V, there are four peaks at ∆ = 3%, 6%, 11%, and 14%. The 3% and 11% peaks are ascribed to the grain boundaries in the channel region and in the SDE region, respectively, as shown in Fig. 5. The 6% peak is composed of two grain boundaries in the channel region since ∆ = 6% = 3% + 3%. The 14% peak is composed of the first grain boundary in the SDE region and the second grain boundary in the channel region since ∆ = 14% = 11% + 3%. Fig. 11 shows that these peaks become lower as WGR  increases, which means that the fabrication process for gate polysilicon

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Fig. 12. TOX dependence of the frequency distribution when LG = 30 nm, WGR  = 100 nm, and VG = 1 V. Fig. 15.

Fig. 13. LG dependence of the frequency distribution when WGR  = 100 nm, TOX = 1.3 nm, and VG = 1 V.

Variation of VT and ID,Leak .

Fig. 16. Cumulative frequency of ∆VT , which is defined as the difference measured from “no grain boundary.” The fluctuations in ∆VT are enhanced as WGR  is decreased. This is consistent with Fig. 11.

Fig. 14. VG dependence of the frequency distribution when LG = 30 nm, WGR  = 100 nm, TOX = 1.3 nm, and VG = 1 V.

should be optimized to enlarge WGR . Fig. 12 shows that the values for these peaks become larger as TOX is decreased, while the highest peak is decreased from 18% to 14%. The product of this peak and the corresponding value are then increased since 14% × 3% − 18% × 2% is positive. This indicates that the decrease of TOX enlarges the entropy. Fig. 13 shows that these peaks become higher and then the entropy increases as LG is decreased. Similarly, the entropy increases as VG is increased, as shown in Fig. 14. These results suggest that the scaling of MOSFETs enlarges the entropy and then enhances the fluctuation due to grain boundaries. On the other hand, Fig. 15 shows that the fluctuation of grain boundaries causes the dispersions of VT with ∆VT ≤ 14 mV and of drain leak ID,Leak , with ∆ID,Leak being a few nanoamperes. In Fig. 16, the dispersions of ∆VT > 0, ∆VT ∼ = −a few millivolts, and ∆VT ∼ = −10 mV are attributable to grain boundaries between the center of channel and SDE, near the center of channel, and at the drain-edge, respectively. In Fig. 17, the dispersions of ∆ID,Leak ≈ 1 nA, ∆ID,Leak ≈ −0.5 nA, and ∆ID,Leak ≈

Fig. 17. Cumulative frequency of ∆ID,Leak , which is defined as the difference measured from “no grain boundary.” The fluctuations in ∆ID,Leak are enhanced as WGR  is decreased. This is consistent with Fig. 11.

−1 nA are attributable to the grain boundary at the drain edge, near the center, and between the center and SDE, respectively. For example, the drain-edge dispersion corresponds to ∆VT ≈ −10 mV and ∆ID,Leak ≈ 1 nA. The dispersion due to the grain boundary near the center corresponds to ∆VT ≈ −a few millivolts and ∆ID,Leak ≈ −0.5 nA. The dispersion due to the grain boundary between the center and SDE corresponds to ∆VT > 0 and ∆ID,Leak ≈ −1 nA. Consequently, we have a negative linear relation between the dispersions of VT and ID , which is deduced by Poisson distribution, as shown in Fig. 18. Conversely, the result obtained using the random number method is apart from the line that indicates the negative

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phosphorus nuclei is much greater in the quasi-atom than in the phosphorus atom. Therefore, we can regard that the donor impurity is electrically active. VI. CONCLUSION

Fig. 18. Relation between IOFF and VT . The crosses correspond to the arrangement vector (θm,n ) and depict data before regulation by the Poisson distribution. The dotted circles depict the data of the dominant contribution deduced by the Poisson distribution.

Fig. 19. Scheme of quasi-atom model composed of five silicon atoms and one phosphorus atom.

linear relation, as depicted by the crosses. Figs. 16 and 17 also show that the fluctuation is enhanced as WGR  is decreased, which is similar to Fig. 11. V. DISCUSSION More fundamentally, the distribution of grains and grain boundaries should be addressed in two dimensions (the transistor length and the transistor width). The present limitation to the length dimension might then appear invalid. However, the location dependence discussed here is caused from the difference in the impact between the SDE region and the center of channel, whereas the grain boundary location along the width dimension can hardly affect on the leakage current. Of course, it is worth noting that the present analysis is more valid for devices with narrower gate, e.g., SRAM. Although we have regarded that the donor impurity atoms are electrically active at the grain boundary in this paper, one might think that the donor atoms are electrically inactive since all five bonds of the dopant atoms are saturated [18]. In order to discuss this problem, let us consider a quasi-atom model that is composed of five silicon atoms and a phosphorus atom surrounded by these silicon atoms, as shown in Fig. 19. Each silicon atom has four bonds, and one of the bonds is used to bind the silicon atom to the phosphorus atom. Two of the three remaining bonds are used to bind the silicon atom with two other silicon atoms. The other bond gives a peripheral electron in a large quasi-atom composed of five silicon atoms and one phosphorus atom. As a result, a nonsaturated bond is left in the quasi-atom, which behaves as a dopant and then feeds the remaining peripheral electron with lower ionization energy because the distance between the peripheral electron and the

It is shown that the arrangement vectors and the Poisson distribution analysis of grain boundaries deduces a clear frequency distribution of gate leakage current. We relate the peaks in the frequency distribution to nanoscopic variation in the arrangement of grain boundaries and show that the drain-togate leakage current modulated by grain boundaries causes dispersion in ID of a few nanoamperes and dispersion in VT of a few ten millivolts for LG = 30 nm, even though there is no fluctuation of impurities. This grain-boundary fluctuation is therefore essential to the VT of a narrow-gate-width device such as SRAM. It is also found that the scaling of MOSFET enlarges the dispersions of VT and ID . In addition, the analysis based on the Poisson distribution reveals a negative linear relation between the dispersions of ID and VT . A way of suppressing these fluctuations is to optimize the fabrication process so as to increase the average grain size. ACKNOWLEDGMENT The author would like to thank Dr. K. Matsuzawa and S. Toriyama for the useful discussions. R EFERENCES [1] J. Y. W. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl. Phys., vol. 46, no. 12, pp. 5247–5254, Dec. 1975. [2] M. Mandurah, K. C. Saraswat, and C. R. Helms, “Dopant segregation in polycrystalline silicon,” J. Appl. Phys., vol. 51, no. 11, pp. 5755–5763, Nov. 1980. [3] K. C. Saraswat, “Physical and electrical properties of polycrystalline silicon thin films,” in Grain Boundaries in Semiconductors, G. E. Pike, C. Seager, and H. Leamy, Eds. New York: Elsevier, 1982, pp. 261–274. [4] W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, “Density of gap states of silicon grain boundaries determined by optical absorption,” Appl. Phys. Lett., vol. 43, no. 2, pp. 195–197, 1983. [5] J. D. Lee, B. C. Shim, H. S. Uh, and B.-G. Park, “Surface morphology and I–V characteristics of single-crystal, polycrystalline, and amorphous silicon FEA’s,” IEEE Electron Device Lett., vol. 20, no. 5, pp. 215–218, May 1999. [6] M. Valdinoci et al., “Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions,” Solid State Electron., vol. 41, no. 9, pp. 1363–1369, Sep. 1997. [7] P. Migliorato, S. W. B. Tam, O. K. B. Lui, T. M. Brown, and M. J. Quinn, “Device physics and modeling of poly-Si TFTs,” in Proc. SID Dig., 1997, pp. 171–175. [8] M. Kimura, S. Inoue, and T. Shimoda, “Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location,” J. Appl. Phys., vol. 89, no. 1, pp. 596–600, Jan. 2001. [9] K. Yamaguchi, “Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size,” J. Appl. Phys., vol. 89, no. 1, pp. 590–595, Jan. 2001. [10] S. S. Bhattacharya, S. K. Banerjee, B.-Y. Nguyen, and P. J. Tobin, “Temperature dependence of the anomalous leakage current in polysilicon-on-insulator MOSFETs,” IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 221–227, Feb. 1994. [11] H. Lim, “Influence of polysilicon deposition conditions on the characteristics of oxide-nitride-oxide memory capacitors,” J. Korean Phys. Soc., vol. 33, no. 4, pp. 501–506, 1998. [12] A. C. K. Chan et al., “SOI Flash memory scaling limit and design consideration based on 2-D analytical modeling,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2054–2060, Dec. 2004.

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[13] S. Toriyama, K. Matsuzawa, and N. Sano, “Gate tunneling fluctuations associated with random dopant effects,” in Proc. SISPAD, 2005, pp. 23–26. [14] H. Watanabe, K. Matsuzawa, and S. Takagi, “Scaling effects on gate leakage current,” IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1779–1784, Aug. 2003. [15] H. Watanabe and S. Takagi, “Effect of incomplete ionization of impurities in polysilicon gate and band gap narrowing on direct tunneling gate leakage current,” J. Appl. Phys., vol. 90, no. 3, pp. 1600–1607, Aug. 2001. [16] H. Watanabe, “Depletion layer of gate poly-Si,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2265–2271, Oct. 2005. [17] A. Schenk, “Finite-temperature full random-phase approximation model of band gap narrowing for silicon device simulation,” J. Appl. Phys., vol. 84, no. 7, pp. 3684–3695, Oct. 1998. [18] W. E. Spear and P. G. Le Comber, “Electronic properties of substitutionally doped amorphous Si and Ge,” Philos. Mag., vol. 33, no. 6, p. 935, 1976.

Hiroshi Watanabe was born in Gunnma, Japan. He received the B.Sc., M.Sc., and Ph.D. degrees from the University of Tsukuba, Ibaraki, Japan, in 1989, 1991, and 1994, respectively, all in physics. He joined the Ultralarge Scaled Integration (ULSI) Laboratory, Research and Development Center, Toshiba Corporation, Kawasaki, Japan, in 1994. Since 1999, he has been a Research Scientist with Advanced LSI Technology Laboratory, Corporate Research and Development Center, Toshiba Corporation, Yokohama, Japan. He has studied quantumstatistical mechanics, quantum spin systems, device physics, and device modeling. His current research interest is to formulate high precise physical models for tunneling phenomena and its related physics in nano and decanano devices, and then to develop high precise device-circuit simulator for further scaled non-volatile memory cells and integrated novel functional devices. Dr. Watanabe is a member of IEEE TRANSACTIONS ON ELECTRON DEVICES Golden List and a member of the Japan Society of Applied Physics.