Sub-60mV/dec Subthreshold Slope in Junctionless Nanowire ...

Sub-60mV/dec Subthreshold Slope in Junctionless Nanowire Transistors N. Dehdashti, C.-W. Lee, A.Kranti, R. Yan, I. Ferain, R. Yu, P. Razavi, JP Colinge Tyndall National Institute University College Cork, Ireland

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OUTLINE

• Junctionless transistor • Conduction mechanisms • Drain electric field • Subthreshold slope measurements • Simulations • Conclusions 2

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Anantomy of Junctionless Transistor Gate

A

Source

Source

Source

3

P+ PolySi Gate

Drain

N+ Silicon

B

C

Drain

N+ PolySi Gate

Drain

P+ Silicon

A: 3D view of a junctionless transistor B: cross section of an N-channel device C: cross section of a P-channel device www.tyndall.ie

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TEM Cross section

BOX

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OUTLINE


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Electrostatic Pinchoff The cross section must be small enough for channel region to be depleted on carriers: Electrostatic Pinchoff Source

Gate

Drain tsi Wsi

6

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Increasing Gate Voltage

Below VTH

Higher VG

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Slightly above VTH

Depletion gone

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OUTLINE


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Increasing Drain Voltage

VD=50mV

VD=400mV

10

VD=200mV

VD=600mV

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Drain electric field

The high-field region is in the drain, not in the channel region

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OUTLINE


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Subthreshold slope

IM; W=50nm

-4 -5

10

-7

10

Vbg=0

10

-8

10

Vsd=3.00V Vsd=3.25V Vsd=3.50V Vsd=3.75V Vsd=4.00V Vsd=4.25V Vsd=4.50V Vsd=4.75V Vsd=5.00V

-8

10

-9

10 10

-10

10

-11

10

-12

-9

10

-10

10

Vsd=1.50V Vsd=1.75V Vsd=2.00V Vsd=2.25V Vsd=2.50V Vsd=2.75V Vsd=3.00V

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10

-12

10

-13

10

-14

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Gate Voltage (V)

”Regular” inversionmode trigate FET 13

Vth=-1.5V

10

-7

Drain Current (A)

Drain Current (A)

10

Waf 3;C1; 83

-6

JL; W=50nm

-6

10

10

-3.0

-2.5

-2.0

-1.5

-1.0

Gate Voltage (V)

Junctionless trigate FET

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”Regular” inversion-mode trigate FET

-6

Drain Current (A)

10

VD=4V -8

10

VDS=3.0V~5.0V

-10

10

Step=0.5V -12

10

-14

10

0.0

0.4

0.8

1.2

1.6

Gate Voltage (V) 14

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Junctionless trigate FET

Drain Current (A)

-6

10

-8

10

VD=1.75V VDS=1.5V~2.25V

-10

Step=0.25V

10

-12

10

-14

10

-3.0

-2.5

-2.0

-1.5

-1.0

Gate Voltage (V) 15

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OUTLINE


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Device simulation (ATLAS)

Lgate

Drain

Gate

Wsi

Source

tsi A-A’ BOX 17

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Electric field VDS=2.2V, VGS=VTH-200mV W=20nm Tsi=5nm, Tox=10nm, L=200nm

Electric field (V/cm)

Electric field

Junctionless Inversion-mode

6

2.0x10

6

1.5x10

6

1.0x10

Drain

Source

5

5.0x10

0.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Cutline from source to drain (µm) 18

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Impact Ionization Rate Gate

Gate

Drain

Drain

Inversion-mode Na=2e18: Impact ionization is in the channel region

Junctionless Nd=1e19: Impact ionization is in the drain

Impact gen rate_ VDS=2.2V, VGS=0V, 20x5nm_L200 19

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Electron Temperature VDS=2.2V, VGS=VTH-200mV

Electron Temperature (K)

3

8.0

x10

Junctionless Inversion-mode ( M − 1) = ∫ α Te ( x) dx

6.0

4.0

2.0 Source 0.0 0.0

0.1

Drain 0.2

0.3

Distance along 20

0.4

0.5 0.6 x-direction (µm)

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Impact Ionization Rate

2.0 x10

Junctionless Inversion-mode

-1

-3

Impact Ioniczaton Gerneration Rate (s cm )

VDS=2.2V, VGS=VTH-200mV 26

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1.5

( M − 1) = ∫ α Te ( x) dx

1.0

0.5

0.0 0.0

Drain 0.2 0.3 0.4 0.5 Distance along x-direction (µm) Source 0.1

0.6

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Conclusions

• Peak electric field is in the drain itself • Wider high-field region accelerates electrons to higher impact ionization rates • Bandgap narrowing in highly doped silicon 70 to 150 meV for ND=1e19-5e19 cm-3 • Sub-60mV slope observed at VDS=1.75V instead of 4V in regular device 22

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