Synchronization Phenomena in Microgrids with Capacitive Coupling

IEEE TRANSACTIONS ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. XXX, NO. XX, XX 2015

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Synchronization Phenomena in Microgrids with Capacitive Coupling Kuntal Mandal, Member, IEEE, and Soumitro Banerjee, Fellow, IEEE

Abstract—Multiple converters connected to a microgrid must have the same clock frequency, else interaction among the frequencies may cause beating noise. But the frequency equalization is difficult to achieve in practice. We show that the nonlinearity present in all power electronic systems offers an interesting possibility: the clocks may synchronize spontaneously if appropriate coupling exists among the converters. We further show that if the control circuits of the converters receive their power supply from the intermediate bus of the microgrid, the small ripple voltage across the intermediate bus capacitor can cause minute changes in the frequencies of the clocks—which may result in synchronization of the converters. The desirable periodic synchronization is achieved over specific ranges of the intermediate bus capacitance that depend on the frequency ratios of the converters in the uncoupled state. Index Terms—cascaded dc-dc switching converters, microgrids, mutual coupling, synchronization.

I. I NTRODUCTION ISTRIBUTED Power System (DPS) approach has been widely adopted for many applications such as telecommunications, computing equipments and microgrids [1] for its higher efficiency, better reliability, higher power density, better standardization and ease of packaging and maintenance. One typical DPS structure is called intermediate bus architecture, where the output of a regulated or fixed duty-ratio dc-dc converter provides the input to multiple non-isolated Point-ofLoad converters. Studies on modeling, stability analysis [2]– [5], and bifurcation analysis [6]–[9] of such cascaded converter systems have been reported. When multiple dc-dc converters are running in an interconnected fashion, there is a risk of developing beating noise at a frequency that is the difference of the switching frequencies of the individual converters and is very difficult to filter out. To avoid this problem, frequency synchronization of the different converters, similar to the practice in a centralized power system, is recommended by most system designers [10], [11]. However, as power systems move to DPS, multiple power modules—often sourced from different manufacturers—are used in a power board. Thus, different switching frequencies usually exist in such a system. Over the last decade, there have been extensive work on frequency synchronization of dc-dc converters in DPS, which

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Manuscript received XX XXXX; revised XX XXXX K. Mandal and S. Banerjee are with the Indian Institute of Science Education and Research Kolkata, Mohanpur Campus – 741246, India. e-mail: [email protected], [email protected] c 2014 IEEE. Personal use of this material is permitted. Copyright ⃝ However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to [email protected].

have recommended the use of converters, microcontrollers, and digital signal processors from the same manufacturer, which can then be synchronized using a ‘synch pin’ [12], [13]. In this paper, we propose an alternative method of frequency synchronization of the converters using the knowledge of nonlinear dynamics. In the nonlinear science literature, it is well known that when nonlinear oscillators have some mutual coupling, they may synchronize spontaneously [14]–[18]. Recently such synchronization has been achieved in the context of ac microgrids [19]. There have been elaborate studies on various types of synchronization (in-phase, anti-phase, lag, and generalized synchronization), and the conditions under which they occur. The question is, can we use that knowledge productively to induce synchronization in converters connected to dc microgrids? When two or more converters are interconnected in a “system”, each converter along with its control circuit acts as an oscillator. The studies on synchronization in nonlinear systems indicates that if appropriate couping is established among the converters, they may also synchronize to operate at a single frequency. We show that if the control circuits (including the clock generators) derive their power supply from the intermediate bus, it establishes appropriate coupling between the oscillators that can induce synchrony. The voltage across the intermediate bus capacitor has a dc value and a ripple, and this ripple can affect the frequencies of the converters. Under certain conditions this mutual coupling establishes frequency synchronization of all the converters. We illustrate this phenomenon using a simple system comprising two buck converters connected in cascade under voltage-mode control. Our investigation shows that the phenomenon is of a general nature, applicable to systems with any number of converters and different types of controllers. The paper is organized as follows. In Section II, we describe the system and present its mathematical model. Unlike earlier studies on the dynamics of dc-dc converters, in this work we include the clock generator in the system model. The mismatch between the oscillators can be of two types: (a) there can be difference in the initial conditions, due to which the converters may start off in different phases, and (b) the frequencies of the individual converters may be different, due to the small differences in parameter values of the R and C elements used in the clock generators. In Section III, we first consider the situation where the initial frequencies and phases are different. Then we consider the situation where the frequencies are the same but the initial phases are different. In Section IV we explore the parameter space to identify the region where a “desirable” (i.e., period-1) form of synchronized behavior


S1 Vin

L1

S2

iL1

+ −

D1 Q

C1

S FF1

Vref1

t

vramp1

vcon1

D2 C2 Q

VU2 VL2

Kp1 ,Ki1

S FF2

+-

+-

VU1 VL1

B. The Control Circuits iL2

+ v - o1

CLK1

R

L2

+ v - o2

R2

CLK2

R

Vref2

+-

+vramp2

2

t

vcon2

Kp2 ,Ki2

Fig. 1. Closed-loop circuit of cascaded buck converters. Power supply of the control circuits is obtained from the intermediate bus voltage vo1 across C1 .

occurs. In Section V we explore the bifurcation behavior if the external parameters (the input voltage and load) are varied when such a system is running in synchronized mode. Finally in Section VI we conclude.

A vital component of the control circuit is the clock generator, which is generally realized by a 555 timer [20] in analog controllers. A simplified functional block diagram of the 555 timer used as an astable multivibrator is shown in Fig. 2(a). It consists of two voltage comparators (comp1 and comp2), one R-S flip-flop, a discharge transistor TR, a resistive (R) voltage divider and an output buffer. With the addition of an external capacitor CT and two external resistors (RA , RB ), the 555 timer can be configured to produce periodic ramp waveform. The capacitor CT is periodically charged and discharged between the trigger level VL= vo1 /3 and the threshold level VH = 2vo1 /3 (Fig. 2(b)). By the choice of RA , RB , and CT , the lengths of the charging and discharging times and the clock period are set. Using a level shifter (−6 V), the ramp voltage is set as vramp = vCT − 6. Therefore, when the bus voltage is constant (12 V), lower and upper thresholds of the ramps are VL1 = VL2 = −2.0 V, VU1 = VU2 = 2.0 V respectively.

II. S YSTEM D ESCRIPTION A. Operational Principle of the Power-Stage Fig. 1 shows two buck converters connected in cascade. All the converters are controlled by pulse-width modulation (PWM) scheme, in which the control voltage vcon is compared with a ramp signal vramp to generate a pulse-width modulated signal that drives the switch S. The PWM output is “HIGH” when vcon is greater than vramp , and is “LOW” otherwise. In order to obtain zero steady-state errors for both the outputs, proportional-integral (PI) compensators are used. For the first converter, the control voltage is derived from the voltage feedback loop as ∫ vcon1 = Kp1 (Vref1 − vo1 ) + Ki1 (Vref1 − vo1 )dt where, the proportional and integral gains are denoted by Kp1 and Ki1 respectively, vo1 is the voltage of the intermediate bus. The ramp signal for the first converter is given by ( ) t vramp1 = VL1 + (VU1 − VL1 ) mod 1 Ts where, VL1 and VU1 are the lower and upper threshold voltages of the ramp, and Ts is the switching period. vo1 R

RA

CLK + -comp1 R Q

VH R

RB VL CT

_ comp2 SQ + - TR

Fig. 3. Waveforms (left) and power spectra (right) of the intermediate bus voltage (a) when the clock frequencies are the same, and (b) when they are slightly different. The timers are fed from a constant voltage supply.

Fig 3 illustrates the problem that this paper seeks to address. If the two timers of the system have identical values of RA , RB and CT , and are fed from a constant voltage supply, they generate the same frequency. In that situation the system operates in period-1 as shown in Fig 3(a) and there is only one frequency component. This situation is very difficult to achieve in practice. On the other hand, if the clock circuit parameters are slightly different, the two clock frequencies would also be different. In that situation the waveforms show beat phenomenon (Fig 3(b)). The frequency spectra (second column) show a few low-frequency components in addition to the fundamental frequency. If the vo1 has a small ripple component related to the dynamics of the connected converters, these time-lengths would vary slightly. This establishes a coupling between the converters and their controllers. C. Mathematical Modeling

R (a)

(b)

Fig. 2. (a) Astable multivibrator circuit built around a 555 timer, (b) Typical waveforms. The CLK and vramp signals are generated by this chip.

Each buck converter consists of a switch Si and a diode Di , for i = 1, 2. When the converters are operating in continuous conduction mode (CCM), diode Di is always in a complementary state to switch Si . In discontinuous conduction mode (DCM) there is an interval when both switch Si and diode Di are off.


TABLE I S WITCH COMBINATIONS AND SUBSYSTEM NUMBER IN CCM AND IN DCM

u4 0 0 0 0 0 . . 1

u3 0 0 0 0 1 . . 1

u2 0 0 1 1 0 . . 1

u1 0 1 0 1 0 . . 1

Mk M0 M1 M2 M3 M4 . . M15

u4 0 0 1 1 0 0 1 1

u3 0 1 0 1 0 1 0 1

u2 0 0 0 0 1 1 1 1

u1 0 0 0 0 0 0 0 0

i L1 0 0 0 0 0 0 0 0

Mk M16 M17 M18 M19 M20 M21 M22 M23

The power stage of the system (Fig. 1) can be described by the following differential equations 1 diL1 = [−vo1 + u1 Vin ] , dt L1 diL2 1 = [u2 vo1 − vo2 ] , dt L2

dvo1 1 = [iL − u2 iL2 ] , dt C1 [ 1 ] dvo2 1 vo2 = iL2 − . dt C2 R2

where u1 = 1 and u2 = 1 if the switches S1 and S2 are ON (u1 = 0 and u2 = 0 if S1 and S2 are OFF). The state equations related to the integrators of the controllers are dρ1 dρ2 = Ki1 [Vref1 − vo1 ], = Ki2 [Vref2 − vo2 ]. dt dt The state equations of the capacitors in the two 555 timers are given by [ ( ) ] dvCT1 1 vo1 − vCT1 vCT1 = (1 − u3 ) − u3 dt CT1 (R + RB1 ) RB1 [ ( A1 ) ] dvCT2 1 vo1 − vCT2 vC = (1 − u4 ) − u4 T2 dt CT2 (RA2 + RB2 ) RB2 where u3 = 1 and u4 = 1 when the transistors TR1 , TR2 of the 555 timers are ON (i.e., the capacitors are discharging). Depending on the operating conditions there are different switch combinations (also called subsystems Mk ) given by the appropriate choice of binary command signals u (Table I). Due to the four switches in the system, 24 different linear differential equations or subsystems are possible in CCM. In DCM, when inductor current of the first stage is zero (iL1 = 0), the number of subsystem increases by eight (Table I).

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state operation mode when both the timers are in phase. However, many other operation modes are possible under different operating conditions when the timers may not be in phase. The state-space model of each subsystem within a switching cycle is given by Mk : x˙ = Ak x + Bk u [ ]⊤ where, x = iL1 vo1 ρ1 vCT1 iL2 vo2 ρ2 vCT2 , u = [ ]⊤ Vin Vref1 Vref2 , superscript ⊤ denotes transpose. The subsystems Mk are defined in Table I and those appearing in a typical cycle are illustrated in Fig. 4. The switching instants at which the transitions between subsystems occur can be determined by the following switching conditions: h1 : vcon1 − vramp1 = 0,

h2 : vcon2 − vramp2 = 0,

h3 : vCT1 − (2/3)vo1 = 0, h5 : vCT1 − (1/3)vo1 = 0,

h4 : vCT2 − (2/3)vo1 = 0, h6 : vCT2 − (1/3)vo1 = 0.

When the converters are operating in DCM the switching conditions are given by: h7 : iL1 = 0,

h8 : iL2 = 0.

Once the steady-state behaviors are available, stability analysis can be done by Filippov’s method [21], [22] due to its switching nature. TABLE II S PECIFICATIONS OF THE CONVERTER AND VALUES OF THE PARAMETERS FOR POWER - STAGE AND CONTROLLERS

Specifications Input voltage Bus voltage Output voltage Output Power Switching frequency Parameter Inductors Capacitor Output Resistor Voltage References Proportional gains Integral gains

Value Vin = 24 V vo1 = 12 V±5% vo2 = 5 V±1% Po2 = 5 W fs = 10 kHz

Value L1 = 0.7 mH, L2 = 1.5 mH C2 = 50 µF R2 = 5 Ω Vref1 = 12 V, Vref2 = 5 V Kp1 = Kp2 = 3 Ki1 = Ki2 = 1000 s−1

D. Design of the Converter

Fig. 4. Typical waveforms of the control voltages in the first and the second stage at steady-state when the charging and discharging of the timer capacitors happen at the same time. (Color online.)

As shown in Fig. 4 a switching cycle in CCM comprises four subsystems (M3 −M1 −M0 −M12 ) for a typical steady-

The specifications and the design values of the power-stage and controllers are given in Table-II based on the design method given in [23], [24]. The ripple current in the second stage is within ±20% of the rated current. In this work the frequency is set at a relatively low value than what is used in the industry, to avoid switching noise, as the phenomenon itself is not dependent on the choice of frequency. III. S YNCHRONIZATION U NDER C APACITIVE C OUPLING The ripple voltage across the intermediate bus is dependent on the value of the capacitor C1 : With the increase of the


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Fig. 5. Phase space plots, sampled data points, waveforms, and frequency spectra are shown for different values of capacitive coupling (i.e., C1 ) with non-identical timers (f1 /f2 ≈ 1.02): (a) C1 = 24 µF, (b) C1 = 30 µF, (c) C1 = 80 µF, (d) C1 = 100 µF. First column: Orbit in the (vo1 , vo2 ) plane. Second column: sampled data plot – maximum of vo1 , and vo2 at that time in each cycle. Third column: Blue line - vramp1 (t), black line - vramp2 (t) Fourth column: Blue line – spectrum of intermediate bus voltage vo1 , black line – spectrum of vo2 . (Color online.)

E IGENVALUES WITH

C1 Orbit 80 stable period-1 30 stable period-1 24.2 stable period-1 24.1 unstable period-1

TABLE III C1 (µF ) CORRESPONDING TO Fig. 5.

VARIATION OF

Subsystem Sequence Eigenvalues M3 −M1 −M0 −M8 −M2 −M6 −M21 −0.0453, 0.3889±0.7412j (≃ 0.8370), 0.9744, 0.9651, 0.9249, 0, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 −0.7356, 0.3478±0.7863j (≃ 0.8598), 0.9525±0.0220j, 0.9765, 0, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 −0.9969, 0.3332±0.7922j (≃ 0.8594), 0.9376±0.0105j, 0.9763, 0, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 −1.0031, 0.3329±0.7922j (≃ 0.8593), 0.9371±0.0094j, 0.9763, 0, 0

value of C1 the ripple voltage decreases. So the extent of the coupling can be varied by varying the value of this capacitor. A. Non-Identical Timers First we consider the practical situation where the parameters in the timer circuits are non-identical, by setting the timer 1 and timer 2 parameter values as RA1 = 11 KΩ, RB1 = 1.7 KΩ, CT 1 = 10 nF (f1 ≈ 10 kHz) RA2 = 9 KΩ, RB2 = 2.7 KΩ, CT 2 = 10.2 nF (f1 ≈ 9.8 kHz) respectively. In this case, not only the frequencies of the timers are different but also the rising and falling slopes of the ramps are slightly different. In addition, the initial phases are also different. Our observation is that the system locks into a period-1 synchronized behavior for a range of the coupling parameter, and instability sets in for the values of coupling outside this range. This is illustrated for two situations f1 /f2 > 1 (Fig. 5) and for f1 /f2 < 1 (Fig. 6). As the coupling parameter is successively increased, the phase difference between the ramp voltages reduces, but phase synchronization never occurs. In Fig. 5(b) and (c) we see that the system synchronizes and works in a desirable period-1 mode for C1 = 30 µF and C1 = 80 µF. But when the coupling parameter is reduced to C1 = 24 µF, a period-2 subharmonic sets in. On the other hand, when the coupling parameter is increased to C1 = 100 µF (Fig. 5(d)), a slow oscillation exists in the waveforms and the behavior is quasiperiodic. At C1 = 24 µF (Fig. 5(a)), the system is frequency synchronized, but operates in period-2 (first and second columns). It is also clear from the phase space plot that the ripple of the intermediate bus is around ±10%. The spectral peak of the bus

voltage shows (fourth column) two frequency components— one half the other—due to the period doubled dynamics. The calculation of the eigenvalues (Table III) shows that, as C1 is decreased, an eigenvalue moves out of the unit circle through negative real axis, causing a period-doubling bifurcation. At C1 = 30 µF (Fig. 5(b)) and C1 = 80 µF (Fig. 5(c)), the system exhibits period-1 synchronized orbit and now the ripple in the bus voltage is within the specified value ±5%. Though the frequency is synchronized, the phase of the ramp voltages are not. Finally at C1 = 100 µF (Fig. 5(d)), the system behaves quasi-periodically and low frequency components (see the inset in the frequency spectrum) appear in the spectra. The ripple in the bus voltage is within the specified value. Now keeping all other timer parameters fixed, the capacitor of the timer 2 is set CT 2 = 9.9 nF (f1 ≈ 10.1 kHz), so that f1 /f2 ≈ 0.99. In this case also period-1 frequency synchronization is found to occur over a certain range of the coupling parameter. For low values of C1 , high periodic orbits develop, and for high values quasiperiodicity develops. A noticable feature is that in this case the orbits show antiphase synchronization. At a low value of the coupling parameter C1 , high periodic (period-9) behavior is observed at C1 = 32 µF (Fig. 6(a)). The spectra contain the corresponding frequency components. As the coupling is increased to C1 = 40 µF (Fig. 6(b)), the system shows synchronized behavior but in almost anti-phase synchronization (second column). The ripple of the intermediate bus voltage is more than the specified value ±5%. With further increment of the coupling parameter (C1 = 80 µF), the ripple voltage of the bus reduces to within the specified limit and the magnitude of the spectral peak reduces significantly


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Fig. 6. Phase space plots, sampled data points, waveforms, and frequency spectra are shown for different values of capacitive coupling (i.e., C1 ) with non-identical timers (f1 /f2 ≈ 0.99): (a) C1 = 32 µF, (b) C1 = 40 µF, (c) C1 = 80 µF, (d) C1 = 100 µF. (Color online.) E IGENVALUES WITH

C1 Orbit 80 stable period-1 40 stable period-1

TABLE IV C1 (µF ) CORRESPONDING TO Fig. 6.

VARIATION OF

Subsystem Sequence Eigenvalues M1 −M9 −M3 −M2 −M6 −M4 −M18 −0.7065, 0.4205 ± 0.7272j (≃ 0.8400), 0.8145, 0.9747, 0.9698, 0, 0 M1 −M9 −M8 −M2 −M6 −M4 −M18 −0.2772, 0.4288 ± 0.7946j (≃ 0.9029), 0.7041, 0.9653, 0.9767, 0, 0

Fig. 7. The phase space plots, sampled data points, waveforms and frequency spectra are shown for increasing values of C1 with identical timer parameters (f1 /f2 ≈ 1): (a) C1 = 40 µF, (b) C1 = 40 µF, (c) C1 = 200 µF, (d) C1 = 200 µF. (Color online.) E IGENVALUES WITH

C1 200 200 40 40

Orbit stable period-1 stable period-1 stable period-1 stable period-1

TABLE V C1 (µF ) CORRESPONDING TO Fig. 7.

VARIATION OF

Subsystem Sequence Eigenvalues M3 −M1 −M0 −M8 −M2 −M6 −M21 0.4091 ± 0.7387j (≃ 0.8444), 0.9702 ± 0.0025j, 0.9754, 0.4702, 0, 0 M3 −M1 −M0 −M12 −M19 0.4072 ± 0.7331j (≃ 0.8386), 0.9740, 0.9677, 0.4603, 0.2483, 0, 0 M1 −M9 −M8 −M2 −M6 −M4 −M21 −0.5368, 0.3554 ± 0.7523j (≃ 0.8320), 0.9750, 0.9647, 0.8613, 0, 0 M3 −M1 −M0 −M12 −M19 −0.6613, 0.3834 ± 0.7150j (≃ 0.8113), 0.9684, 0.9742, 0.2409, 0, 0

(Fig. 6(c)). The phase difference of the ramp voltages remains the same. The calculated eigenvalues are also given in Table IV which shows that all the eigenvalues are within the unit circle. Finally at C1 = 100 µF (Fig. 6(c)), quasi-periodic orbit develops which introduces low frequency components in the waveforms (see the inset in the frequency spectrum). B. Identical Timers Now we consider the situation where the frequencies of the two 555 timers are identical (i.e., fixed RA = 11 KΩ, RB = 1.7 KΩ and CT = 10 nF), and the system starts from different initial conditions. Such a situation may arise when all the converters use the output of a single clock, and this

clock, in turn, takes its power supply from the intermediate bus. Our observation is that the two converters tend to phasesynchronize over a range of the coupling parameter, and instability may set in for too low a coupling. Fig. 7 shows the results for increasing values of the coupling parameter, while Fig. 8 shows it for decreasing values of the coupling parameter. In Figs. 7, we see that two different stable period-1 orbits are possible for the same parameter setting depending on the initial condition. In Fig. 7(a) and (c), not only the frequencies of the clocks are synchronized, but the phases are also synchronized. In Fig. 7(b) and (d), the frequencies of the clocks are synchronized, but with a phase difference. For a higher


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Fig. 8. The phase space plots, sampled data points, waveforms and frequency spectra are shown for decreasing values of C1 with identical timer parameters (f1 /f2 ≈ 1): (a) C1 = 30 µF, (b) C1 = 26 µF, (c) C1 = 24 µF. (Color online.) E IGENVALUES WITH

C1 Orbit 30 stable period-1 26.46 stable period-1 26.45 unstable period-1

TABLE VI C1 (µF ) CORRESPONDING TO Fig. 8.

VARIATION OF

Subsystem Sequence Eigenvalues M3 −M1 −M0 −M8 −M2 −M6 −M21 −0.8394, 0.3436 ± 0.7473j (≃0.8225), 0.9748, 0.9646, 0.8081, 0, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 −0.9997, 0.3387 ± 0.7439j (≃0.8174), 0.7789, 0.9747, 0.9646, 0, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 −1.0003, 0.3387 ± 0.7439j (≃0.8174), 0.7789, 0.9747, 0.9646, 0, 0

value of C1 = 200 µF (Fig. 7(c) and (d)), the ripple voltage of the bus is reduced, the magnitude of the spectral peak (fourth column) also reduces significantly. The computed eigenvalues are given in Table V which indicate stability of the orbits. Fig. 7 also shows that, as the coupling parameter increases, the frequency of the clocks slightly increases. Thus, the EMI filter should not be tuned to a single frequency, and has to be so designed that it can filter out this small range of frequencies. Now we consider decreasing values of the coupling parameter for the situation where the frequencies are the same but the initial phases are different. Starting with a low value of coupling, at C1 = 30 µF (Fig. 8(a)), the system exhibits period1 synchronized orbit but the ripple in the bus voltage is more than the specified ±5% limit (first column). At C1 = 26 µF (Fig. 8(b)), the system is frequency synchronized, but operates in period-2 (first and second columns). The calculated eigenvalues (Table VI) show that at C1 = 26.45 µF, the stable period-1 orbit is unstable and a stable period-2 orbit is created. When C1 is decreased to 24 µF (Fig. 8(c)), the system shows chaotic behavior (first and second columns). The ramp voltages are also chaotic, but are still in synchronism (third column). There is a large spread in the frequency spectra (fourth column).

IV. T HE PARAMETER RANGE FOR DESIRABLE SYNCHRONIZATION

From the above results it is clear that, if the two converters have different operating frequencies to start with, a desirable form of synchronization (giving stable period-1 orbit) is obtained only for a certain range of the coupling parameter C1 . Therefore, one may be interested to know the range in which the capacitive coupling can synchronize the two timers. We find that this is dependent on the starting frequency ratio f1 /f2 . To study this effect, we vary this ratio by varying the capacitor of the timer 2 (CT 2 ), keeping all the timer parameters fixed. With the variation of this frequency ratio (f1 fixed and f2 varying) the system is synchronized within a range of the coupling parameter C1 . Fig. 9 shows this range in the parameter space, with the frequency ratio in the x-axis and the coupling parameter in the y-axis. It shows a region where the period-1 frequency synchronization occurs; in the other areas one observes quasi-periodic, high-periodic, coexistence of different behaviors and chaotic behavior depending on the capacitor value. The range of the coupling parameter for effective synchronization reduces as one moves away from the value f1 /f2 ≈ 1. We find that at f1 /f2 ≈ 1 (Fig. 7), the range of synchronized zone is maximum. However, in this state the phases are also in synchronism. Thus the on- and off-times of the two converters overlap and so the total harmonic distortion (THD) is higher. When f1 /f2 ≥ 1 (Fig. 5), the range of synchronized zone is reduced and within this zone there is a small phase lag. When f1 /f2 ≤ 1 (Fig. 6), the range of synchronized zone is small, but within this range the phase lag is significant, and so the THD is lower. V. T HE BIFURCATION ANALYSIS

Fig. 9. Synchronized period-1 boundaries in the frequency ratio—coupling capacitor parameter space. (Color online.)

After achieving the synchronized period-1 behavior, one would be interested to see what happens if the external parameters (input voltage and load resistance) are varied when the system is running with a fixed coupling capacitor.


TABLE VII E IGENVALUES WITH VARIATION OF Vin (V) CORRESPONDING

Vin Orbit 22.69 unstable period-1 22.70 stable period-1 31.94 stable period-1 31.95 unstable period-1

Fig. 10(a).

Subsystem Sequence Eigenvalues M3 −M1 −M9 −M8 −M2 −M6 −0.303 ± 1.148j (≃1.187), 0.392 ± 0.694j, 0.930, 0.970, 0.975, 0 M3 −M1 −M9 −M8 −M2 −M6 −M21 0.393 ± 0.790j (≃0.882), 0.955 ± 0.013j, −0.155, 0.976, 0, 0 M3 −M1 −M0 −M8 −M18 −M21 −0.9994, 0.3910 ± 0.7167j, 0.9719, 0.9692, −0.0766, 0, 0 M3 −M1 −M0 −M8 −M18 −M21 −1.000, 0.3911 ± 0.7167j, 0.9719, 0.9692, −0.0766, 0, 0 TABLE VIII E IGENVALUES WITH VARIATION OF R2 (Ω) CORRESPONDING

R2 Orbit 4.61 unstable period-1 4.62 stable period-1

TO

7

TO

Fig. 11(a).

Subsystem Sequence Eigenvalues M3 −M1 −M0 −M8 −M2 −M6 −0.3932±1.135j (≃1.20), 0.384±0.682j, 0.9648±0.0076j, 0.9767, 0 M3 −M1 −M0 −M8 −M2 −M6 −M21 0.3691 ± 0.7677j (≃0.852), 0.971 ± 0.0168j, −0.3203, 0.9775, 0, 0

Fig. 10. Bifurcation diagrams with the variation of the input voltage Vin at C1 = 50 µF: (a) studied system (f1 /f2 ≈ 1.02), (b) ideal system. Other parameters are given in Table II-D.

We illustrate this with the bifurcation diagrams by varying Vin (Fig. 10) and R2 (Fig. 11). To facilitate comparison with the “ideal” case where the two clocks have fixed frequency (10 kHz) and ideal ramp (VL1 = VL2 = −2.0 V, VU1 = VU2 = 2.0 V), we present (Fig. 10(b) and Fig. 11(b)) showing these cases. Fig. 10(a) shows a stable operating range (22.70 V – 31.94 V) of the input voltage. The calculated eigenvalues (Table VII) shows that the instabilities for the lower and upper values are caused by border-collision and period-doubling respectively. The range of stable operation in the synchronized system is smaller than that of the ideal system (12.8 V – 25.77 V). With the increasing value of the Vin , the ideal system bifurcates for a smaller value of Vin (at 26.83 V as shown in Fig. 10(b), the eigenvalues are −3.3456, 0.3871 ± 0.7392j, 0.9699, 0.9668, 0) than the synchronized system (around 31.95 V). The period-2 orbit starts at Vin = 25.77 V and is stable up to Vin = 34.85 V (the eigenvalues for period2 orbit are −0.9594, −0.4564 ± 0.5633j (≃0.7250), 0.9416, 0.94, 0). Then the system develops chaos at Vin = 34.86 V through border-collision (the calculated eigenvalues for period2 orbit are −3.0298, −0.4289 ± 0.5734j , 0.9415, 0.9355, 0). Similarly, keeping Vin = 24 V fixed, if the load resistance is varied, Fig. 11(a) shows that a stable period-1 behavior is obtained over the range (4.62 Ω−9.55 Ω) in the synchronized system while a relatively larger range (3.18 Ω − 6.91 Ω) is obtained in the ideal system as shown in Fig. 11(b). From the Table VIII, it is seen that at R2 = 4.61 Ω, a pair of eigenvalues jump from inside the unit circle indicating the occurrence of a border-collision bifurcation.

Fig. 11. Bifurcation diagrams with the variation of the load resistance R2 at Vin = 24 V, C1 = 50 µF: (a) studied system (f1 /f2 ≈ 1.02), (b) ideal system.

With the decreasing values of R2 , for ideal system, the period-1 orbit is stable up to R2 = 3.18 Ω (eigenvalues are −0.0403 ± 0.9941j (≃0.9949), 0.3212 ± 0.6843j, 0.9685, 0.9733). For higher values of R2 , the period-1 orbit is stable up to R2 = 6.91 Ω (the eigenvalues are −0.1020, 0.3821 ± 0.7864j (≃0.8743), 0.9697 ± 0.0012j, 0). Then one of the eigenvalues of the period-1 orbit jumps outside of the unit circle from the inside and a period-2 orbit (inset of Fig. 11(b)) is born due to border-collision (the calculated eigenvalues of period-1 at R2 = 6.92 Ω are −1.5984, 0.3994 ± 0.7816j, 0.9696, 0.9676, 0). VI. C ONCLUSION In interconnected power converter configuration in a microgrid, all the converters should have the same clock frequency. In this paper, we have proposed a natural way of achieving this, by constructively utilizing the nonlinearity inherent in power converters. Such microgrids are normally used in remote locations in the production and consumption of renewable energy, where access to the power grid may not be available. We show that synchronization among the converters connected to a microgrid can be obtained if all the control circuits derive their power supply from the intermediate bus naturally present in such a system, instead of investing in constant-voltage supplies to power the control units. Under this condition, even when the frequencies of the clocks of two converters are slightly different, frequency synchronization can be achieved with proper choice of coupling. In such a situation the capacitor connected to the intermediate bus acts as the coupling parameter, as the magnitude of the


voltage ripple depends on it. We show that a desirable form of synchronization (where all the clocks work in synchronized periodic manner) can be achieved only for a certain range of the coupling parameter. For higher values the system loses synchrony and for lower values high-periodic, quasi-periodic, or chaotic behavior may develop. This range, in turn, depends on the frequency ratio of the uncoupled converters. As the frequency ratio moves away from unity, the useful range of the coupling parameter is reduced. Even though the total harmonic distortion (THD) increases for lower values of the coupling capacitor, synchronization is desirable so that filters in the downstream converters can be properly designed. In terms of THD, the desirable condition in a microgrid is where the frequencies of the clocks are synchronized, but they operate with a phase difference. This is a condition naturally reached in capacitive coupling, when the frequency of the first converter is lower than that of the second converter. If the converters are controlled by fixed-frequency clocks, the converters are stable for a certain range of the external parameters like input voltage and load. When the converters are controlled by clocks synchronized in the above way, this range of the external parameters for stable operation is somewhat less. This range should be taken into account when designing the system. For different values of the coupling parameter, the frequency at which the clocks synchronize may vary slightly. Therefore the filter should not be designed for a single frequency and should be designed to block a range of frequencies. R EFERENCES [1] A. Kwasinski, “Quantitative evaluation of dc microgrids availability: Effects of system architecture and converter topology design choices,” IEEE Transactions on Power Electronics, vol. 26, no. 3, pp. 835–768, March 2011. [2] S. Abe, H. Nakagawa, M. Hirokawa, T. Zaitsu, and T. Ninomiya, “System stability of full-regulated bus converter in distributed power system.” Berlin, Germany: Twenty-Seventh International Telecommunications Conference, 2005. INTELEC ’05, September 2005. [3] X. Yang, H. Zhang, and X. Ma, “Modeling and stability analysis of cascade buck converters with N power stages,” Mathematics and Computers in Simulation, vol. 80, pp. 533–546, September 2009. [4] W. Chen, X. Ruan, H. Yan, and C. K. Tse, “DC/DC conversion systems consisting of multiple converter modules: Stability, control and experimental verifications,” IEEE Transactions on Power Electronics, vol. 24, no. 6, pp. 1463–1474, June 2009. [5] X. Zhang, X. Ruan, and C. K. Tse, “Impedance-based local stability criterion for dc distributed power systems,” IEEE Transactions on Circuits and Systems–I, vol. 62, no. 3, pp. 916–925, March 2015. [6] H. Zhang, X.-P. Yang, X.-K. Ma, and F. Zheng, “Theoretical and experimental investigation of bidirectional hopf bifurcations in cascade dc-dc buck converters,” Mathematics and Computers in Simulation, vol. 82, pp. 540–557, 2011. [7] A. El Aroudi, D. Giaouris, L. Martinez-Salamero, and S. Banerjee, “Bifurcation behavior in switching converters driving other downstream converters in dc distributed power systems applications.” Marrakech, Morocco: MEDYNA 2013 : 1st Euro-Mediterranean Conference on Structural Dynamics and Vibroacoustics, 23-25 April 2013. [8] X. Xiong, C. K. Tse, and X. Ruan, “Smooth and non-smooth bifurcations in multi-structure multi-operating-mode hybrid power systems,” International Journal on Bifurcation and Chaos, vol. 23, no. 5, pp. 1–12, May 2013. [9] ——, “Bifurcation analysis of standalone photovoltaic-battery hybrid power system,” IEEE Transactions on Circuits and Systems–I, vol. 60, no. 5, pp. 1354–1365, May 2013.

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[10] “Adjust or synchronize LM2586/88 switching frequency,” Texas Instruments, Tech. Rep. AN-1082, April 2013. [11] R. Ambatipudi, “Simple techniques minimize cross-coupling in distributed power systems,” National Semiconductor Corporation, Tech. Rep., 2011. [12] S. Galati and M. Merisio, “Challenges and applicative solutions for nipol converters in intermediate bus architecture,” STMicroelectronics Power Supplement, Tech. Rep., August 2006. [13] Synchronization of Power Converters, Synchronization Application Notes, NetPower, Advanced Power Solutions, April 2007. [14] A. Balanov, N. Janson, D. Postnov, and O. Sosnovtseva, Synchronization: From Simple to Complex. Springer, 2008. [15] A. Pikovsky, M. Resenblum, and J. Kurths, Synchronization: An Universal Concept in Nonlinear Sciences. Cambridge University Press, Cambridge, U.K., 2001. [16] G. Katriel, “Synchronization of oscillators coupled through an environment,” Physica D: Nonlinear Phenomena, vol. 237, no. 22, pp. 2933– 2944, November 2008. [17] M.-F. Danca, “Synchronization of switch dynamical systems,” International Journal of Bifurcation and Chaos, vol. 12, no. 8, pp. 1813–1826, 2002. [18] J. Zhaoa, D. J. Hill, and T. Liu, “Synchronization of complex dynamical networks with switching topology: A switched system point of view,” Automatica, vol. 45, pp. 2502–2511, September 2009. [19] B. B. Johnson, S. V. Dhople, A. O. Hamadeh, and P. T. Krein, “Synchronization of nonlinear oscillators in an LTI electrical power network,” IEEE Transactions on Circuits and Systems–I, vol. 61, no. 3, pp. 834–844, March 2014. [20] 555 Timer, National Semiconductor, July 2006. [21] K. Mandal, C. Chakraborty, A. Abusorrah, M. M. Al-Hindawi, Y. AlTurki, and S. Banerjee, “An automated algorithm for stability analysis of hybrid dynamical systems,” The European Physical Journal Special Topics, vol. 222, pp. 757–768, July 2013. [22] K. Mandal, S. Banerjee, and C. Chakraborty, “A new algorithm for small-signal analysis of dc-dc converters,” IEEE Transactions on Industrial Informatics, vol. 10, no. 1, pp. 628–636, February 2014. [23] Selection of Architecture for Systems using Bus Converters and POL Converters, Design Note 023, Ericsson Power Modules, July 2010. [24] M. Barry, “Design issues in regulated and unregulated intermediate bus converters.” Applied Power Electronics Conference and Exposition, 2004. Kuntal Mandal (S’11-M’13) received the B.E. degree in electrical engineering from the Jalpaiguri Government Engineering College, North Bengal University, West Bengal, India, in 2003 and the M.E. degree in control system engineering from Jadavpur University, Kolkata, India, in 2006. Then he served as a lecturer in the Electrical Engineering Department of Future Institute of Engineering & Management, Kolkata, India. In 2013, he received the Ph.D. degree from the Department of Electrical Engineering, Indian Institute of Technology Kharagpur, India. His research interests include stability analysis and nonlinear dynamics of complex power electronic circuits and its control. Soumitro Banerjee (M’91-SM’03-F’14) (born 1960) did his B.E. from the Bengal Engineering College (Calcutta University) in 1981, M.Tech. from IIT Delhi in 1983, and Ph.D. from the same Institute in 1987. He was in the faculty of the Indian Institute of Technology Kharagpur, since 1986, and has moved to the Indian Institute of Science Education and Research Kolkata, in 2009. Dr. Banerjee’s areas of interest are the nonlinear dynamics of power electronic circuits and systems, and bifurcation theory for nonsmooth systems. He has published three books: “Nonlinear Phenomena in Power Electronics” (Ed: Banerjee and Verghese, IEEE Press, 2001), “Dynamics for Engineers” (Wiley, London, 2005), and “Wind Electrical Systems” (Oxford University Press, New Delhi, 2005). Dr. Banerjee served as Associate Editor of the IEEE Transactions on Circuits & Systems II (2003-05), and as Associate Editor of the IEEE Transactions on Circuits & Systems – I (2006-2007). He is a recipient of the S. S. Bhatnagar Prize (2003). He is a Fellow of the Indian Academy of Sciences, the Indian National Academy of Engineering, the Indian National Science Academy, and the Third World Academy of Sciences.