Synthesizing Interacting Finite State Machines - Semantic Scholar

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Synthesizing Interacting Finite State Machines. Adnan Aziz1. Felice Balarin2. Robert K. Brayton1. Alberto Sangiovanni-Vincentelli1. Email:fadnan,felice,brayton ...
Synthesizing Interacting Finite State Machines Adnan Aziz1

Felice Balarin2 Robert K. Brayton1 Alberto Sangiovanni-Vincentelli1 Email:fadnan,felice,brayton,[email protected] 1. VLSI CAD Group – Dept. of EECS, University of California at Berkeley 2. Cadence Berkeley Laboratories

Abstract We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems.

1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages.

of the entire system. This can be at the logic level (i.e. the input is a netlist of gates and latches) or the state transition graph level. Designs invariably consist of a set of interacting components. Natural questions related to such systems are what is the optimal choice of a component, and automatically deriving a component so as to satisfy given properties. Previous work in the VLSI design automation community related to optimizing interacting state machines has tended to be ad hoc and incomplete. The constructions and proofs offered are often extremely cumbersome. Relevant papers include [16, 8, 11, 18, 19, 20]. One attempt at formal synthesis framework based on trace and automata theory is given in [9]. However, the central theorem relating flexibility in a sub-circuit to the specification and the environment is incorrect; we give the correct formulation. There is a large body of theoretical work related to the existence of efficient decision procedures for deciding logics

In particular logic synthesis, the science of optimizing designs (for various measures such as area, speed, or power) specified at the gate level, has shifted to the forefront of CAD research. Another area rapidly gaining importance

of programs [21, 13, 7, 15]. [13, 7] take logical specifications and construct programs satisfying them. [21] uses a game theoretic formulation to show that the set of moves for a controller is an !-regular set. [15] gives an elegant

is design verification, the study of systematic methods for formally proving the correctness of designs. Logic synthesis algorithms originally targeted the optimization of PLA implementations; this was followed by

characterization of realizability. Typically, the synthesis process has two stages: first, the set of all possible implementations is characterized (which is the topic of this paper), and then one is chosen according

research in synthesizing more general multi-level logic implementations. Currently, the central thrust in logic synthesis is sequential synthesis, i.e. the automatic optimization

to some optimality criteria. Using the sequential calculus S1S as our basic tool we show in section 3.1 that the set of all implementations can always be captured by a single finite-state automaton, which can be generated au-

 Supported by SRC Grant 95-DC-324A

tomatically. However, in practise such an automaton may be prohibitively large to construct. One approach to alleviate this problem is to define easier to handle automata which capture only a subset of possible implementations. We pursue this approach in section 3.2. The rest of this paper is structured as follows: x 2 reviews the basic definitions and salient results. In x 3 we apply these results to synthesizing and optimizing finite state machine networks; specifically, we derive sources of flexibility that can be exploited by synthesis. We also address the issue of hardware realizability. In section x 4 we describe extensions of our approach to synthesizing systems which incorporate fairness constraints and timed systems. The analysis in this paper is of a theoretical nature. In particular, the complexity of the exact procedures described can be exponential, or even doubly exponential. From a theoretical point of view, the complexity is inherent; this simply reinforces the need for approximations and heuristics.

2 Definitions and Basic Results 2.1 Finite State Automata and Machines Given a finite set Σ (the alphabet), the set Σ is the set of all finite sequences over Σ, i.e. all maps f : f0; 1; 2; : ::; n ? 1g ! Σ. A -language over Σ is a subset of Σ. Given

X 2 Σ, j X j denotes the cardinality of X .

The set Σ! is the set of all infinite sequences over Σ, i.e. all maps f : ! ! Σ, where ! = f0; 1; 2; : ::g is the set of natural numbers. An !-language over Σ is a subset of Σ! .

Notation: Lower case variables will take values from alphabets; upper case variables will be sequence valued. Definition 1 A finite state automaton (FA) is a 5-tuple (Σ; S; s0 ; T; A) where Σ is a finite set called the alphabet, S is a finite set of states, s0 2 S is the initial state,

T  S  Σ  S is the transition relation, and A  S is the set of accepting states. The automaton is said to be deterministic (variously a DFA) if (8s)(8x) [ j ft : (s; x; t) 2 T gj  1 ]; otherwise it is said to be non-deterministic (variously an NFA). A string X 2 Σ is accepted by the FA if there exists

a sequence of states 0 1 : : :n such that n = j x j +1, = s0 , n 2 A, and (8i) [(i ; Xi ; i+1 ) 2 T ]. The language of the automaton is the set of strings accepted by it; this language is said to be -regular if it is the language

0

accepted by some automaton. Definition 2 A Buchi automaton (BA) is a 5-tuple (Σ; S; s0 ; T; B ) where Σ is a finite set called the alpha-

S is a finite set of states, s0 2 S is the initial state, T  S  Σ  S is the transition relation, and B  S are

bet,

the accepting states. The automaton is said to be deterministic if the following holds, else it is said to be non-deterministic.

8s)(8x) [ j ft : (s; x; t) 2 T g j 1 ];

(

A string x 2 Σ! is accepted by the BA if there exists a sequence of states 0 1 : : : such that 0 = s0 , and

8i) [(i ; xi; i+1) 2 T ], and inf () \ B 6= , where

(

inf () is the infinitary set of , i.e. the set of states that occur infinitely often in . The language of the automaton is the set of strings accepted by it; a language is said to

be !-regular if it is the language accepted by some Buchi automaton.

Definition 3 A finite state machine M is a 5-tuple (S; s0 ; I; O; T ) where S is a finite set of states, s0 2 S is the initial state, I is a finite set of inputs, O is a finite set of outputs, and T  S  I  O  S is the transition relation. M is deterministic if

8s) (8i) (8o) j ft : (s; i; o; t) 2 T g j  1

(

M is said to be complete

if

8s) (8i) (9o) (9t) [(s; i; o; t) 2 T ]

(

M is said to be an implementation if it is complete and

8s) (8i) j f(t; o) : (s; i; o; t) 2 T g j  1

(

M is said to be Moore if 8s; i; o1; o2; t s; i; o1 ; t) 2 T ^ (s; i; o2; t) 2 T ! o1 = o2

(

otherwise it is said to be Mealy. Given an input sequence i = (i1 i2    in ), and output sequence o = (o1 o2    on), a corresponding run is a sequence of states  = (s0 s1    sn ) such that

8k) [(sk ; ik+1; ok+1; sk+1) 2 T ].

is an element of C . Similarly the language of a finite state machine with fairness is defined to be the language of the corresponding Buchi automaton.

(

Composition of finite state machines is defined in the usual way. In composing interacting FSMs, (sometimes

Remark: Our definition of deterministic finite state machine has been referred to as “pseudo non-deterministic”

referred to as a network of FSM’s) some inputs of each machine may be the outputs of each machine, whereas some inputs may be external; also, not all outputs need be external. The entire systems is itself a finite state ma-

The notion of a run readily generalizes to infinite sequences.

(PNDFSM) in the past [20]. The term deterministic was reserved for what we refer to as implementable. A related notion is that of incompletely specified finite state machines (ISFSM), where given a state s and an input i, either (9!o; t) [(s; i; o; t) 2 T ] or (8o; t) [(s; i; o; t) 2 T ].

Definition 4 The

M

=

-language

identified with an FSM (S; r; I; O; T ), denoted by LM and referred to as

the behavior of M , is the set of sequences (i; o) 2 (I  O) such that there exists a run in M corresponding to (i; o).

Remark: Clearly the behavior LM is a -regular language ([10, 17]) on the alphabet I  O. The automa-

ton AM defining the language is simply the FSM itself – the states of AM are the states S , initial states of AM are the states r, the transition relation of the automaton is f(s; (i; o); t) : (s; i; o; t) 2 T g, and all states are accepting. Note that the behavior of a deterministic machine is defined by a deterministic finite automaton. Definition 5 Given a language L

 (ΣI  ΣO ) , a finite

state machine M on input ΣI , output ΣO is said to be compatible with L if LM  L; M is said to be a realization of L if it is compatible with L and is an implementation. A language is said to be realizable if there exists a realization of it; similarly an FSM is realizable if its language is realizable. Definition 6 A finite state machine with Buchi fairness is a tuple (M; C ) where M is an FSM, and C is a subset of the

states of M . Given F = (M; C ), an FSM with fairness F is said to be deterministic (complete) if M is deterministic (complete). The notion of a corresponding run over infinite input/output sequences is defined analogously to that for ordinary FSMs; a run  is fair if the infinitary set of states

chine on the product state space, referred to as the product machine [14]; transitions take place synchronously, i.e. in “lock-step”. When the component machines are Mealy and derived from hardware, composition can lead to combinational cycles, and the product may have undesired oscillatory behaviors [5]. These problems can be circumvented by using Moore machines; we will come back to this phenomenon in section 3.3.

2.2 The Sequential Calculus S1S The logic S1S is a formalism for describing properties of sequences. It was shown by Buchi in [4] to be decidable. As such it provides an powerful mechanism for analyzing and manipulating sequential systems – the full power of logic (conjunction, negation, universal and existential quantification, etc) is available. Definition 7 The logic S1S (second order theory of one successor) is a second order logic [17]. For-

mulae are derived from the alphabet f0; S; =;