implementation of the median-based filter used for noise reduction from images. The filter involves two procedures: an impulse detection algorithm and the noise ...
The Evaluation of Image Noise Reduction Filter Implementation with the Blackfin Microcomputer Andrei STEFAN, B.Sc., Sorin ZOICAN, Ph.D. POLITEHNICA University of Bucharest Bucharest, ROMANIA Abstract—This paper evaluates the possibility of the real time implementation of the median-based filter used for noise reduction from images. The filter involves two procedures: an impulse detection algorithm and the noise filtering. Both the impulse detection and the noise filtering procedures are applied through several iterations for better performance [2]. The real time implementation is based on the Blackfin digital signal microcomputer from Analog Devices [5]. The paper is organized as follows: a brief description of the filtering algorithm, the micro signal architecture (MSA), the proposed approach for real time implementation and conclusion.
flag which indicate the good pixels (the pixels that has been modified will be marked as good), M ij( n −1) is the median
Index Terms—Image enhancement, impulse detection, median filter, micro signal architecture, real time.
value in the current window computed only for the corrupted pixels with g ij( n −1) set to 0 and yij(n ) represents the
I.
3x3 pixels) at iteration (n-1), f ij(n ) is flag which marks the corrupted pixels in the image at the iteration n (that is, the flag value is set to 1 if the current pixel xij( n −1) has a large value compared with the median value mij( n −1) ), xij(n ) is the current pixel at the iteration n, g ij( n −1) represents another
filtered image. The function median(W ) returns the median value of the array W. The image processing has two phases: the first one is the noise detection and the second one is the filtering. For each image pixel the following computation are performed [2],[3]:
THE FILTERING ALGORITHM
Image processing is an important application of twodimensional (2D) signal processing. Because of the developments of fast, low-cost, and power-efficient embedded signal processors for real-time processing, digital image processing is widely used in portable consumer electronics such as digital cameras and picture phones. A digital image (or picture) is visual information received, represented, processed, stored, or transmitted by digital systems. With advancements in microelectronics, digital image processing is widely used for applications such as enhancement, compression, and recognition [1]. The general idea behind the filter is to average a pixel using other pixel values from its neighborhood, but simultaneously to take care of important image structures such as edges. The main concern of the proposed filter is to distinguish between local variations due to noise and due to image structure. The filtering algorithm chosen to evaluate the possibility of a real time implementation is described by the relations (1) to (6) in witch the following notations have defined [2]: mij( n −1) represents the median value of the
A. The noise detection phase
1. Compute the median value for the current pixel neighborhoods:
m ij( n −1) = median(Wij( n −1) ) 2. Compute a matrix flag F = [ f ij ] with
f ij( n )
f ij( n −1)
, | x ij( n −1) − mijn −1 |< T
=
(2)
else 1 , The threshold T is defined according with the noise ratio, n r , as follows T = a + b.n r with a = 65, b = −50 [2]. 3. Modify the current pixel as follows: x ij( n ) =
pixels in the window Wij( n −1) (the size of this window is
c 978-1-4244-6363-3/10/$26.00 2010 IEEE
(1)
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m ij( n −1)
,
f ij( n −1) ≠ f ij( n )
,
f ij( n −1)
(3) x ij( n −1)
=
f ij( n )
The Blackfin BF533 processor includes system peripherals and also has a direct memory access (DMA) controller that effectively transfers data between external devices/memories and the internal memories without processor intervention. Blackfin processors provide L1 cache memory for quick accessing of both data and instructions. These features make the Blackfin processors suitable to replace other high-end DSP processors and microcontrollers. In the following sections, we further introduce the core architecture and its system peripherals [5], [7].
The first phase is performed progressively in N d = 3 iterations and it produce the matrix F = [ ( Nd )
G = [ g ij(0) ] = [ f ij
(N ) f ij d ]
. The matrix
] is used at beginning of the second
phase. This phase is performed N f iterations until all the (N f )
values g ij
will be 0.
B. The noise filtering phase
4. Compute the median value M ij( n −1) for the good pixels M ij( n −1) = median(Wij( n −1) | g ij( n −1) = 0)
III.
(4)
This median value is computed using the modified pixels xij(n ) from noise detection phase.
The Blackfin processor family includes dual-core processors, such as the ADSP-BF561 processor. In addition to other features, dual-core processors add a new dimension to application development. Each dual-core Blackfin processor has two Blackfin cores, A and B, each with its own internal L1 memory. There is a common internal memory shared between the two cores, and both cores share access to external memory. Each core functions independently: they have their own reset address, Event Vector Table, instruction and data caches, and so on. On reset, core A starts running from its reset address, while core B is disabled. Core B starts running when it is enabled by core A. When core B starts running, it starts running its own application, from its own reset address. Having one application per core the full potential of the dual-core Blackfin processor is exploiting. Effectively, two singlecore applications are building independently, and run in parallel on the processor. The shared memory areas, both internal and external, are each sub-divided into three areas a section dedicated to core A, a section dedicated to core B, and a shared section. It is left up to the developer to arrange for shared, serialized access to the shared areas from each of the cores. One of the most execution time consuming in median filtering is the sorting procedure. The sorting algorithms are simple from a mathematical point of view; they can be time consuming to perform on DSPs due to their non-linear computational complexity and the presence of many control operations in their execution. In our implementation we have chosen the merge sort algorithm for sorting the values in the current window. We discuss the cycle counts of this algorithm on the Blackfin processor, and show how to reduce the cycle count. In addition we look at methods to accelerate the sorting of data that is wider than the register width of the processor. Since most of the operations in sort algorithms are of the control type, a processor compute unit with a deep pipeline will stall whenever it encounters a conditional operation such as a jump, a branch in a loop structure, etc. However, we can say that we consume about yN log 2 N cycles, where N is the number of the values to
5. Compute the output pixel yij(n ) : y ij( n ) =
M ij( n −1)
,
g ij( n −1) = 1 (5)
y ij( n −1)
,
else
6. Update the matrix G: g ij( n ) =
g ij( n −1)
,
y ij( n ) = y ij( n −1)
,
y ij( n )
(6) 0
7. Repeat the steps 4 to 6 until
=
M ij( n −1)
∑g
(N f ) ij
= 0.
i, j
The parameter N f is proportional with noise ratio. Our experiments indicate that it is between 5 and 10. From relations (1) to (6) we can observe the necessarily computations and will evaluate the computational effort to implement the image processing algorithm. II.
THE REAL TIME IMPLEMENTATION APPROACH
THE BLACKFIN MICROCOMPUTER
The Blackfin digital signal microcomputer is based on a unified architecture named Micro Signal Architecture. The Micro Signal Architecture (MSA) is designed to achieve high-speed digital signal performance and best power efficiency. This architecture combines the best capabilities of microcontroller and DSP processor into a single programming model [4]. The main advantage of the MSA is the integrated feature that combines multimedia processing, communication, and user interface on a single, easy-toprogram platform. The Blackfin core combines dual multiply-accumulate (MAC) engines, an orthogonal reduce instruction-set computer (RISC)-like instruction set, single instruction, multiple data (SIMD) programming capabilities, and multimedia processing features into a unified architecture.
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be sorted and the factor y depends on the particular processor architecture, software code, algorithm flow, etc. used to execute the algorithm. The cycles required to implement the merge sort algorithm is with the factor about 63 log 2 9 ≈ 200 cycles or 234 nanoseconds. Other techniques may reduce the number of processor cycles. One of them is the vector search instruction [6]. The vector search instruction is used in a loop to locate a maximum or minimum element in an array of 16-bit packed data. A condition code GE (greater or equal) or LE (less or equal) will be set in the instruction in order to compute the maximum or the minimum value of the vector. Two values are tested at a time. The vector search instruction compares two 16-bit, signed half-words to values stored in the registers of the Blackfin microcontroller. Then, it conditionally updates each register with minimum or maximum of these values. Also, destination pointers are updated, based on the comparison, to indicate the position of minimum and maximum in the vector. The sorting procedure may be completed in about half of the above mentioned execution time, if the vector search instruction is used. On the other hand, two successive input frames may be processed in the two cores of the processor, as illustrated in the figure 1. In figure 1 T is the frame rate and Tc represents the computation time for the current frame. Each core in the Blackfin processor has its own interrupts system. The input frames are acquired from a serial port (SPORT0) that generates a common interrupt for both cores (indicated in the figure 1 as IRQ_core_A and IRQ_core_B). Each core implements the image processing algorithm in its own main program (denoted as Main_core_A and Main_core_B) if an appropriate flag (flag_A or flag_B) is set to 1. These flags are set in the interrupt service routines for core A or core B. The main programs process the odd or the even input frames only. A necessarily functioning condition is Tc < 2T .
b)
c) Figure 1. The image processing flowchart a) general concept b) flow chart in core A c) flowchart in core B IV.
THE MAIN RESULTS
The above presented algorithm was implemented on the Blackfin BF561 microcomputer in order to evaluate the perceptual quality of the restored image and the possibility that the image processing to be performed in real time. The original image, noised image, new filter filtered image and median filtered image are illustrated in the figure 2. The original image was corrupted with salt and pepper impulsive noise (20% to 40% of pixels was corrupted). In figure 2 is evaluating the perceptual quality of the image processing filter from [2] comparing with the standard median filter. The new filter has better performance but consumes more execution time. The new median filter has better performance (as perceptual quality) than the classical median filter. A large number of simulations were been conducted with various images. For all the images the new median filter performs better (the noise was near completely eliminated). The execution time is illustrated in the figure 3. The number of iteration is N d = 3 (for impulse detector) and
N f = 5 (for noise filtering) . The value of
N f is an
average value because it is dependant of noise rate.
a)
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Figure 3. Execution time and frame rate for the new median filter The paper focuses on the possibility to implement the new median filter in real time (as is discussed in the section III. We can observe that for reasonable noise rate and medium image size the image processing can be performed in real time (that is more than 15 frames per seconds) using the Blackfin processor. This is possible using the switching buffers technique illustrated in figure 1 and the programming technique illustrated in section III.
Impulsive noise rate = 20%
V.
CONCLUSION
This paper investigates if the image restoring algorithms can be implemented in real time and good perceptual quality. A robust image de-noising algorithm presented in [2] was chosen for evaluation. A key feature in such algorithms is the sorting procedure that was efficiently implemented. A dual core Blackfin microcomputer was involved in the implementation and the software organization of the frame processing was presented. Both methods have lead to the possibility of a real time implementation. VI.
REFERENCES
[1] A. Bovik, Handbook of Image & Video Processing, 1st Ed. New York: Academic, 2000. [2] Z. Wang and D. Zhang, ‘‘Progressive switching median filter for the removal of impulse noise from highly corrupted images,’’ IEEE Trans. Circuits Syst. II, vol. 46, no. 1, pp. 78---80, Jan. 1999. [3] H.-L. Eng and K.-K. Ma, ‘‘Noise adaptive soft switching median filter,’’ IEEE Trans. Image Process., vol. 10, no. 2, pp. 242---251, Feb. 2001. [4] Analog Devices, ADSP BF5xx Blackfin Processor Hardware Reference, 2009 [5] Analog Devices, Blackfin Processor Programming Reference, 2008 [6] Analog Devices, Visual DSP++ 5.0 C/C++ Compiler and Library Manual for Blackfin Processors, 2008 [7] Analog Dev, Visual DSP++ 5.0 Users Guide, 2007
Impulsive noise rate = 40% Figure 2 The image processing results
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