The science and technology of magnetoresistive tunneling ... - CiteSeerX

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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, MARCH 2002

The Science and Technology of Magnetoresistive Tunneling Memory Brad N. Engel, Nicholas D. Rizzo, Jason Janesky, Jon M. Slaughter, Renu Dave, Mark DeHerrera, Mark Durlam, Member, IEEE, and Saied Tehrani, Senior Member, IEEE

Abstract—Rapid advances in portable communication and computing systems are creating an increasing demand for nonvolatile random access memory that is both high-density and highspeed. Existing solid-state technologies are unable to provide all of the needed attributes in a single memory solution. Therefore, a number of different memories are currently being used to achieve the multiple functionality requirements, often compromising performance and adding cost to the system. A new technology, magnetoresistive random access memory (MRAM) based on magnetoresistive tunneling, has the potential to replace these memories in various systems with a single, universal solution. The key attributes of MRAM are nonvolatility, high-speed operation and unlimited read and write endurance. This technology is enabled by the ability to deposit high-quality, nanometer scale tunneling barriers that display enhanced magnetoresistive response. In this article we describe several fundamental technical and scientific aspects of MRAM with emphasis on recent accomplishments that enabled our successful demonstration of a 256-kb memory chip. Index Terms—Magnetic film memories, magnetic tunnel junction, magnetoresistive device, magnetoresistive random access memory (MRAM), micromagnetic switching, MRAM integration, random access memories (RAMs).

I. INTRODUCTION ITH the widespread adoption of portable digital electronics and wireless communication devices, the increasing demand for solid-state memories continues unabated. Currently, there are number of technologies being mass produced or aggressively pursued in research laboratories to address a variety of memory applications. In this article, we present a summary of our recent progress on a new technology, magnetoresistive random access memory (MRAM), based on integration of magnetic tunnel junction (MTJ) material and complimentary metal oxide semiconductor (CMOS) circuits. MRAM has the potential to be competitive with all existing semiconductor memories and, through its unique properties, provide new functionalities. The key attributes of MRAM technology are nonvolatility combined with high-speed operation and effectively unlimited read-write endurance. Table I shows the features of MRAM compared to several other major memory technologies. Each of the existing technologies provides particular functional advantages, but with some significant shortcomings as well. As such, none are suitable as a

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Manuscript received February 7, 2002; revised February 26, 2002. This work was supported in part by the U.S. Defense Advanced Research Projects Agency Grant MDA 972-96-3-0016. The authors are with Motorola Labs, Physical Sciences Research Laboratories, and Motorola Semiconductor Product Sector, Embedded Memory Center, Tempe, AZ 85284 USA. Publisher Item Identifier S 1536-125X(02)04587-8.

TABLE I COMPARISON OF MRAM EXPECTED FEATURES WITH OTHER MEMORY TECHNOLOGIES. BOLD TYPE INDICATES AN UNDESIRABLE ATTRIBUTE

“universal memory” that would provide desirable performance for all of the most important memory attributes. As can be seen in the table, MRAM possesses the nonvolatility, endurance, speed, and density necessary to function as a universal memory for a host of applications. Some of the key challenges to successful implementation of this technology are controlling the resistance uniformity, switching behavior of magnetic bits, and integration of MTJ with CMOS [1] and [2]. In this paper, we describe some of the unique aspects of the magnetic material, how the memory operates, and summarize our recent accomplishments that enabled the successful demonstration of a 256-kb memory chip with read and program address access times of 35 ns [3]. II. MEMORY CELL STRUCTURE The principle of operation of an MTJ-based MRAM bit cell relies on generating localized magnetic fields from intersecting current lines to store digital information in a free magnetic layer and using the tunneling magnetoresistance (TMR) phenomenon to read the bit state. Fig. 1 shows our preferred architecture, in which each memory cell is composed of a single transistor and an MTJ element. The line below the MTJ, designated the digit line, is electrically isolated, while the line above the MTJ device, designated the bit line, is in direct contact with the MTJ. The bit line is, therefore, used for both reading and writing. Significant progress over the past several years has been made on MTJ structures and processes that exhibit a large TMR effect [4] and [5]. The majority of experimental work has focused on Ni, Fe, Co, and their alloys as magnetic electrodes and aluminum oxide as the tunnel barrier. The magnetoresistance ratio

1536-125X/02$17.00 © 2002 IEEE

ENGEL et al.: SCIENCE OF MAGNETORESISTIVE TUNNELING MEMORY

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Fig. 1. MRAM cross-point architecture with bits between orthogonal conductors and each cell defined by one MTJ and one transistor. Top lines, in contact with the top electrodes of the bits, provide hard-axis field, while bottom lines are isolated and provide easy-axis field. Turning on transistor provides a current path so that the corresponding bit state can be sensed.

is defined as the ratio of the resistance difference to the lowresistance value and is typically in the 30–50% range for highquality material. The basic MTJ stack is composed of multiple layers of nanometer and subnanometer-scaled thickness. The structure includes a minimum of two magnetic layers separated by a thin dielectric tunnel barrier and a mechanism to pin the magnetic moment of one of the layers in a fixed direction. The direction of the moment of the free magnetic layer is used for the information storage. The resistance of the memory bit is either low or high depending on the relative moment orientation, parallel or anti-parallel, of the free layer with respect to the fixed layer. This approach requires only the free layer magnetic moment to be switched for a write operation, while the other layer is magnetically fixed. The fixed layer must be able to hold its magnetic direction during exposure to fields that are large enough to switch the free layer. Mechanisms to maintain a fixed magnetic direction include pinning by an adjacent antiferromagnetic layer or use of a high-coercivity material. An MTJ material stack for MRAM typically has several additional layers for controlling the magnetic properties of the bit. An MRAM cell with such a material stack is shown in Fig. 2. This example uses an additional multilayer structure to improve the fixed layer performance. The Ru layer provides very strong antiferromagnetic coupling between the fixed layer and pinned layer, creating a three-layer synthetic antiferromagnet (SAF) that results in a magnetically rigid system to help control magnetic coupling to the free layer. The magnetic moment of the pinned layer is exchange biased by an antiferromagnetic pinning layer material, such as IrMn or PtMn, to prevent the SAF from responding to the magnetic fields used for write operations. In addition to the MTJ stack, the memory cell shown in Fig. 2 has a single transistor and various electrodes and current carrying lines. The line above the MTJ stack, referred to as the bit line, is in direct contact with the MTJ, and is used for both reading and writing. The line below the MTJ, referred to as the digit line, is electrically isolated and is oriented perpendicular to the bit line. Switching is accomplished by passing currents through the orthogonal digit and bit lines to create a sufficiently large magnetic field to reverse the moment of the free layer. To

Fig. 2. A 1-MTJ, 1-transistor MRAM cell. The magnetoresistive signal is the result of electrons that tunnel through the thin AlO insulating layer between the magnetic fixed and free layers. The top electrode connects many bits while the bottom electrode makes contact to the isolation transistor in the CMOS below.

read the bit, the isolation transistor is turned on so that a sense current can flow perpendicularly through the MTJ stack. For submicron patterned MTJ devices to have a resistance that is suitable for MRAM, the tunnel barrier thickness must be on the order of 1.5 nm or less. In addition to being pinhole free and very smooth, the AlO tunneling barrier must be extremely uniform over a wafer. Since the resistance of the junction is exponentially dependent on thickness, small variations in the AlO thickness result in large variations in the resistance [6]. The uniformity and absolute values of the resistance, in addition to the MR values of the cells are important parameters for the read operation, since in our preferred architecture the cell signal, which depends on cell resistance and MR, is compared with a nearby reference cell during read operation. Obtaining good uniformity over large wafer sizes is challenging due to the exponential dependence of the resistance on barrier thickness. However, we have achieved 1- resistance uniformity of 6% and MR uniformity of 2% over 200 mm % wafers. The fully patterned bits have average k / m . The metal and resistance-area product RA layers were formed by sputter deposition and an RF-produced oxygen plasma was used to oxidize a thin Al layer to form the AlO tunnel barrier. This uniformity is achieved through a deposition process with a 1- thickness uniformity of 0.5%. The magnetic electrodes are alloys of Ni, Fe, and Co. III. BIT PROGRAMMING Information is stored in an MRAM array by selectively switching the magnetic moment direction of individual bits. Programming is accomplished by passing currents through selected conductive lines of the cross point architecture, thereby generating a sufficient localized magnetic field only at the

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Fig. 4. Hysteresis loop measured for a patterned bit under increasing H . As H increases, E is reduced and the easy-axis switching field is reduced accordingly. Fig. 3. Schematic of energy barrier E that separates state 0 from state 1 in MRAM cell. (a) In zero magnetic field, E is maximum. (b) For nonzero H or H , E is reduced but finite. (c) For nonzero H and H , E is reduced to 0 and the cell is programmed.

single bit in the intersection. The bit state is programmed to a one or zero, depending on the polarity of the current that generates the magnetic field along the bit’s easy direction. All other bits are exposed only to fields from a single line (1/2 selected bits), or no lines, and are not programmed or disturbed. The programming operation relies on the magnetic field to reduce the energy barrier to magnetization reversal of the free layer. The bit of the MTJ memory cell is generally elongated in shape, so that a magnetic shape anisotropy creates an energy to magnetization reversal, the energy barrier being barrier can be critical for the nonvolatility of the cell. The size of reduced through the application of a magnetic field along the easy-axis (parallel to the long axis of the cell) or hard-axis directions (transverse to the hard-axis of the cell). As shown is a maximum with no field applied. schematically in Fig. 3, ) or hard-axis fields ( ) applied With easy-axis ( is reduced but still finite. This case corresponds separately, to the 1/2-selected bits that are only exposed to fields from one is reduced line. With both easy and hard-axis fields applied, to zero and the bit located at the intersection of the current carrying lines is programmed. The easy-axis field direction determines the written bit state depending on the current polarity. The hard-axis field, however, can be unidirectional, since its only function is to symmetrically reduce the energy barrier to allow the intersecting easy-axis line to program the bit. In Fig. 4 we show quasistatic hysteresis loops of a typical MTJ cell, which demonstrates the is maximum effect of applied field on . With so the easy-axis switching field is also a maximum. As increases, decreases and the switching field decreases accordingly. The easy-axis switching field can be plotted versus the applied hard-axis field in what is known as an astroid curve. The resulting curve defines the switching threshold for programming such that field combinations below this threshold will not

Fig. 5. Easy-axis switching field versus hard-axis applied field. Squares are the average switching astroid measured for 0:6 1:2 m bits with applied fields swept quasistatically. Circles are measurements on the same bit size with the applied field pulsed with a 20 ns duration.

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be written and conversely fields above the threshold will program the bits. In Fig. 5, we show the switching astroid measured m b size. for a Due to process and material variations, an array of memory cells will have a distribution of switching fields with a width . Therefore, to program all of the bits with the same current, the applied field needs to be larger than the mean switching field by several . In addition, the applied field must be kept below a maximum value, otherwise the 1/2-selected nonvolatile bit states may be disturbed during programming. Thus, there is an operating point window for programming fields; inside this window all the bits can be programmed without errors or disturbs. A schematic of the operating point window superposed on the switching astroid is shown in Fig. 6. To maximize this window, it is critical to minimize the switching distribution


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Fig. 7. Theoretical switching astroids of patterned elliptical bits compared to the ideal Stoner–Wohlfarth (SW) coherent rotation model. The points are from micromagnetic simulations of two different bit widths (0.6 and 0.26 m) at aspect ratio 2. Fig. 6. Schematic representation of MRAM program operating point window superimposed on an astroid curve. The cross-hatched regions represent the switching field distribution for an array at the unselected and 1/2-selected fields.

width. In addition, the window can be further expanded by increasing the field separation between the unselected and 1/2-selected mean switching fields. Improving the hard-axis response of the bits, i.e., the steepness of the switching astroid, will allow the use of a higher unselected switching fields and, therefore, increase the separation of the distributions at a given current. This hard-axis response depends in detail on the reversal mode, which in turn is a function of free layer material, bit shape and size. The most ideal response that can be expected is that of coherent rotation of an ellipsoidal particle first studied by Stoner and Wohlfarth [7]. However, due to the planer geometry of real patterned bits, the magnetic behavior does not generally follow this ideal rotation mode, and a nucleation-propagation reversal mechanism results. Fig. 7 is a plot of theoretical astroid curves for two different bit sizes generated from micromagnetic simulations compared with the ideal coherent rotation model. It is evident from these simulations that reducing the dimension causes the reversal mode to become more coherent and approach the ideal behavior. Quasistatic experimental measurements are shown in Fig. 8 as a plot the switching astroid for three bits sizes compared with the ideal coherent rotation model. In confirmation of the predicted trend, as the bit width is scaled to smaller dimensions, the hard-axis response improves. Hence, scaling MRAM to smaller dimensions allows increased separation of the unselected and 1/2-selected bits, and, therefore, improves selectability. Understanding and control of the micromagnetic behavior of MTJ elements is essential for minimizing the switching distribution and improving hard-axis response [8] and [9]. The switching field is mainly governed by the magnetic shape anisotropy that arises from the element boundaries. Hence, bit size, shape, and aspect ratio all play roles in controlling the micromagnetic arrangement and, therefore, the switching

Fig. 8. Measured quasistatic switching astroids versus bit scaling. Dashed curve is predicted behavior for idealized Stoner–Wohlfarth coherently rotating particle. Values normalized to the switching field at zero hard-axis bias.

behavior [10] and [14]. In addition, bit-to-bit magnetic interactions in high-density arrays can further influence switching distributions [11]. While the quasistatic switching properties of the bits are critical to characterize and understand, the high-speed switching properties of the bits are most relevant to device performance in a high frequency memory. We have also measured the switching performance of our bits down to nanosecond time scales. Returning to Fig. 5, the high-speed switching astroid is shown where the easy and hard-axis fields were applied with pulse duns. There is good agreement in the general rations of shape of the astroid curve with that measured quasistatically, indicating the switching behavior does not change significantly in pulsed operation. In order to minimize switching distributions and to ensure reliable, repeatable programming, the bits must change state

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Fig. 9. Voltage versus time for a bit undergoing thermally activated magnetization reversal. The four panels show the accumulation of multiple transitions combining to form an emergent continuous switching probability.

with a single mode, which is equivalent to having a single energy barrier for magnetization reversal. We have verified that our bits possess a single energy barrier by measuring their thermally activated magnetization reversal [12]. In thermal activaleads to a probability tion theory, a finite energy barrier ( ), where the of not switching in time of characteristic reversal time is given by the Arrhenius–Néel law ( /kT), and is the minimum thermal reversal atns). Our experiment consisted of applying tempt time ( a reverse field to a bit to reduce the switching energy barrier to a low, but nonzero value. The bit will then reverse at a later random time due to thermal activation. By measuring the TMR response, we record a time trace on an oscilloscope of the bit reversing from the high resistance state to the low resistance state. By averaging multiple transitions, the probability of not reversing versus time is derived. In Fig. 9, the voltage versus time is shown for a bit undergoing a thermally activated reversal from the high to the low state. The four panels show the accumulation of multiple transitions combining to form an emergent continuous switching probability. In Fig. 10, we see the result of averaging 256 such transitions. The dotted line is a fit of an exponential function to the data, indicating that we have excellent agreement with single energy barrier statistics. We have also used our high-speed capabilities to verify the switching reliability for a large number of write cycles. The reliability test consisted of exposing the bit to a pulsed switching and pulse duration current of magnitude greater than ns. The reversals were counted to verify that the bit switched

Fig. 10. Voltage versus time for the average of 256 reversals that were random in time due to thermal activation. The dotted line is a fit to an exponential function, which is expected for thermal activation over a single energy barrier.

every time. In addition, every cycles, the bit was switched quasistatically to measure the critical device parameters such as , and switching field . resistance , magnetoresistance The bit reversed every time with no significant change in the critical device parameters to greater than 10 write cycles. The approximate lifetime for FLASH memory is a much more lim-


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V. SUMMARY

Fig. 11.

Architecture of magnetic tunnel junction integration with CMOS.

ited write cycles. These results, therefore, demonstrate the robust program endurance of MRAM that enables its potential use as a universal memory. IV. INTEGRATION AND CIRCUIT DEMONSTRATION The MRAM module, encompassing both program lines and patterned MTJ layer, is inserted in the back-end-of-line (BEOL) interconnect using four additional lithography steps. Typical bit cell architecture is based on a minimum sized active transistor as the isolation device in conjunction with an MTJ element to define the MRAM bit as shown in Fig. 11. The source and isolation are shared between neighboring cells to minimize cell area. Our 256 kb circuit was fabricated using a 0.6- m CMOS process with five layers of metal and two layers of polysilicon, with a bit , where is one-half cell size of 7.2 m , corresponding to the metal pitch. We have successfully integrated MTJ devices with CMOS transistors without any threshold shift or performance degradation to the underlying CMOS [13]. Likewise, the performance characteristics of the MTJ devices were also unchanged by the integration. The 256-kb memory demonstration has a 16-kb 16 organization, allowing parallel read of 16 bits. Each bit is selected for reading by addressing a bit line column that connects to the top terminals of a column of bits, including a reference column; a word line row is selected that activates all the transistor gates of the selected row of bits. The target bit and the associated reference bit are selected and then compared through the sense circuitry. A reference voltage equal to the midpoint voltage between the minimum and maximum resistance states of the bit is generated for the reference columns using a self-calibrating reference bias voltage generator. This allows a midpoint current to be generated for the reference side of the differential current conveyor to compare the current through the target cell to the corresponding cell in the reference column and determine the resistance state of the target cell. The current conveyor’s differential operation is unaffected by internal offset voltage and consumes only 120 A at 65 MHz. Our fully fabricated one-tran3.2 sistor/one-MTJ (1T/1MTJ) 256-kb MRAM, is 3.9 mm mm in area. The access time of 35 ns and cycle time of 35 ns at 3.0 V uses 8.2 mA of current during read operation, consuming 24 mW [3].

In this paper we have presented our progress on the main building blocks and key issues in the development of MTJbased MRAM. We have developed MTJ material for use in MRAM applications with a suitable resistance-area product of 200 to 1000 k - m and MR values above 40%. Controlling repeatability and reproducibility of bit switching characteristics is critical for writing individual bits within an array without disturbing neighboring bits. We have demonstrated that conventional lithography and patterning of submicron structures can produce single energy barrier magnetic reversal behavior in MRAM elements. Switching repeatability, as well as hard-axis selectability, is achieved by control of bit shape and aspect ratio. MTJ memory cells were inserted into the back end of a 0.6- m CMOS process. The 256-kb MRAM circuits, based on a single-MTJ, single-transistor architecture, were fabricated and tested to show 35 ns access and cycle times. This performance is very encouraging for a 0.6- m technology, and will improve significantly at smaller lithography dimensions. These results show that MRAM is a unique high-speed, nonvolatile memory with the potential to become a universal memory for a variety of applications. REFERENCES [1] W. J. Gallagher, S. S. P. Parkin, Y. Lu, X. P. Bian, A. Marley, R. A. Altman, S. A. Rishton, K. P. Roche, C. Jahnes, T. M. Shaw, and G. Xiao, “Microstructured magnetic tunnel junctions,” J. Appl. Phys., vol. 81, pp. 3741–3746, 1997. [2] S. Tehrani, J. M. Slaughter, E. Chen, M. Durlam, J. Shi, and M. DeHerrera, “Progress and outlook for MRAM technology,” IEEE Trans. Magn., pt. 1, vol. 35, pp. 2814–2819, Sept. 2000. [3] P. K. Naji, M. Durlam, S. Tehrani, J. Calder, and M. F. DeHerrera, “A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM,” in Proc. IEEE ISSCC Dig. Tech. Papers, vol. 44, Feb. 2001, pp. 122–123. [4] T. Miyazaki and N. Tezuka, “Giant magnetic tunneling effect in Fe/Al O /Fe junction,” J. Magn. Magn. Mater., vol. 139, p. L231, 1995. [5] S. S. P. Parkin, K. P. Roche, M. G. Samant, P. M. Rice, R. B. Beyers, and R. E. Scheuerlein, “Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory,” J. Appl. Phys., vol. 85, p. 3741, 1999. [6] E. Y. Chen, R. Whig, J. M. Slaughter, D. Cronk, J. Goggin, G. Steiner, and S. Tehrani, “Comparison of oxidation methods for magnetic tunnel junction material,” J. Appl. Phys., vol. 87, pp. 6061–6063, 2000. [7] R. O’Handley, Modern Magnetic Materials: Principles and Applications. New York: Wiley, 1999. [8] J. Shi, T. Zhu, M. Durlam, E. Chen, S. Tehrani, Y. F. Zheng, and J.-G. Zhu, “End domain states and magnetization reversal in submicron magnetic structures,” IEEE Trans. Magn., pt. 1, vol. 34, p. 997, July 1998. [9] J. Shi, S. Tehrani, T. Zhu, Y. F. Zheng, and J. G. Zhu, “Magnetization vortices and anomalous switching in patterned NiFeCo submicron arrays,” Appl. Phys. Lett., vol. 74, pp. 2525–2527, 1999. [10] J. Shi, S. Tehrani, and M. Scheinfein, “Geometry dependence of magnetization vortices in patterned submicron NiFe elements,” Appl. Phys. Lett., vol. 76, pp. 2588–2590, 2000. [11] J. Janesky, N. D. Rizzo, L. Savtchenko, B. Engel, J. M. Slaughter, and S. Tehrani, “Magnetostatic interactions between submicrometer patterned magnetic elements,” IEEE Trans. Mag., pt. 1, vol. 37, p. 2052, July 2001. [12] N. D. Rizzo, M. DeHerrera, J. Janesky, B. N. Engel, J. M. Slaughter, and S. Tehrani, “Thermally activated magnetization in submicron magnetic structures for MRAM,” Appl. Phys. Lett., vol. 80, pp. 2335–2337, 2002. [13] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski, and K. Kyler, “Nonvolatile RAM based on magnetic tunnel junction elements,” in Proc. IEEE ISSCC Dig. Tech. Papers, vol. 43, Feb. 2000, p. 128. [14] J. Shi and S. Tehrani, “Edge pinned states in patterned submicron ultra-thin film magnetic structures,” Appl. Phys. Lett., vol. 77, pp. 1692–1694, 2000.

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Brad N. Engel received the B.S. and Ph.D. degrees in physics from the University of Florida, Gainesville, in 1981 and 1988, respectively, specializing in ultra-low temperature quantum fluids. He worked on the research faculty at the Optical Sciences Center, University of Arizona, Tucson, concentrating on artificially structured magnetic thin-film growth and behavior. In 1995, he joined Storage Technology Corporation as the Lead Engineer for the research and development of a GMR spin-valve recording head for tape applications. In 1999, he moved to Motorola Labs, Tempe, AZ, where he is currently the Manager of the Spintronics Device Physics group in the Physical Sciences Research Lab.

Nicholas D. Rizzo received the B.S. degree in physics from the University of Virginia, Charlottesville, in 1991 and the Ph.D. degree in physics from Yale University, New Haven, CT, in 1997 for his research on the effect of ferromagnetic inclusions in superconducting wires. Following graduation, he was a National Research Council Postdoctoral Fellow at the National Institute of Standards and Technology, Boulder, CO, where he focused on the high-speed switching and thermal stability of magnetic disk media. In 1999, he joined Motorola Labs, Tempe, AZ, where he is currently a Principal Staff Scientist in the Spintronics Device Physics group working on MRAM.

Jason Janesky received the B.S. degree in engineering physics from the University of Arizona, Tucson, in 1994 and the M.S. degree in solid state physics from Oregon State University, Corvallis, in 1998, where he worked on nuclear magnetic resonance of electroluminescent phosphor candidates for LCD displays. In 1999, he joined Motorola Labs, Tempe, AZ, where he is currently a Magnetics Characterization Engineer in the Spintronics Device Physics group.

Jon M. Slaughter received the Ph.D. degree in physics from Michigan State University, East Lansing, in 1988 for research on the structure and galvanomagnetic properties of magnetic multilayers. From 1988 to 1996, he was a Researcher at the Optical Sciences Center, University of Arizona, Tucson. In 1996, he joined Motorola Labs, Tempe, AZ, to work on magnetic material for magnetic random access memory (MRAM). Currently, he is the Manager of magnetic materials research in Motorola Labs, Physical Sciences Research Laboratories.

Renu Dave received the B.S. degree in metallurgical engineering from Punjab Engineering College, Punjab, India, in 1994 and the M.S. degree in material science from the University of Wisconsin, Milwaukee, in 1996, where she worked on sputter deposited nanolaminate films. In 1996, she joined Motorola Labs, Tempe, AZ, where she is currently a Material Development Engineer in the magnetic random access memory (MRAM) group.

Mark DeHerrera received the B.S.E. degree in electrical engineering, from Arizona State University, Tempe, AZ, in 1997, where he is working toward the M.S. degree in electrical engineering. In 1997, he joined Motorola, Tempe, AZ, where he is currently a Device Engineer working on magnetic random access memory (MRAM) testing and characterization in the Embedded Memory Center. Mr. DeHerrera received the Distinguished Senior award from the Electrical Engineering Department, Arizona State University.

Mark Durlam (S’79–MA’83–M’97) received the M.E.E.E. degree from Utah State University, Logan, in 1987. In 1992, he joined Motorola Labs, Tempe, AZ, where he worked on implanted MESFET’s and PHEMT devices at the Compound Semiconductor facility. Currently, he is a Senior Staff Engineer working on magnetic random access memory (MRAM) devices in Motorola’s Embedded Memory Center.

Saied Tehrani (S’82–M’85–SM’92) received the B.S. degree from the University of North Carolina, Charlotte, in 1981 and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982 and 1985, respectively. In 1985, he joined Motorola, Tempe, AZ, and was involved in the device and process research and development of heterojunction devices for high-efficiency and low-power applications and its transfer into production for wireless applications. He started working on the magnetic random access memory (MRAM) in 1995. Currently, he is the Director of MRAM technology at the Motorola Embedded Memory Center.